DAC5675A www.ti.com SBAS334C – NOVEMBER 2004 – REVISED MARCH 2005 14-Bit, 400MSPS Digital-to-Analog Converter FEATURES • • • • • • • • • 400MSPS Update Rate LVDS-Compatible Input Interface Spurious-Free Dynamic Range (SFDR) to Nyquist: – 69dBc at 70MHz IF, 400MSPS W-CDMA Adjacent Channel Power Ratio (ACPR): – 73dBc at 30.72MHz IF, 122.88MSPS – 71dBc at 61.44MHz IF, 245.76MSPS Differential Scalable Current Sink Outputs: 2mA to 20mA On-Chip 1.2V Reference Single 3.3V Supply Operation Power Dissipation: 660mW at fCLK = 400MSPS, fOUT = 20MHz Package: 48-Pin HTQFP PowerPad™, TJA = 28.8°C/W APPLICATIONS • • • • Cellular Base Transceiver Station Transmit Channel: – CDMA: WCDMA, CDMA2000, IS-95 – TDMA: GSM, IS-136, EDGE/GPRS – Supports Single-Carrier and Multicarrier Applications Test and Measurement: Arbitrary Waveform Generation Direct Digital Synthesis (DDS) Cable Modem Headend DESCRIPTION The DAC5675A is a 14-bit resolution high-speed digital-to-analog converter. The DAC5675A is designed for high-speed digital data transmission in wired and wireless communication systems, high-frequency direct-digital synthesis (DDS), and waveform reconstruction in test and measurement applications. The DAC5675A has excellent spurious-free dynamic range (SFDR) at high intermediate frequencies, which makes the DAC5675A well-suited for multicarrier transmission in TDMA- and CDMA-based cellular base transceiver stations (BTSs). The DAC5675A operates from a single-supply voltage of 3.3V. Power dissipation is 660mW at fCLK = 400MSPS, fOUT = 70MHz. The DAC5675A provides a nominal full-scale differential current output of 20mA, supporting both single-ended and differential applications. The output current can be directly fed to the load with no additional external output buffer required. The output is referred to the analog supply voltage AVDD. The DAC5675A comprises a low-voltage differential signaling (LVDS) interface for high-speed digital data input. LVDS features a low differential voltage swing with a low constant power consumption across frequency, allowing for high-speed data transmission with low noise levels; that is, with low electromagnetic interference (EMI). LVDS is typically implemented in low-voltage digital CMOS processes, making it the ideal technology for high-speed interfacing between the DAC5675A and high-speed low-voltage CMOS ASICs or FPGAs. The DAC5675A current-sink-array architecture supports update rates of up to 400MSPS. On-chip edge-triggered input latches provide for minimum setup and hold times, thereby relaxing interface timing. The DAC5675A has been specifically designed for a differential transformer-coupled output with a 50Ω doublyterminated load. With the 20mA full-scale output current, both a 4:1 impedance ratio (resulting in an output power of 4dBm) and 1:1 impedance ratio transformer (–2dBm) are supported. The last configuration is preferred for optimum performance at high output frequencies and update rates. The outputs are terminated to AVDD and have voltage compliance ranges from AVDD – 1 to AVDD + 0.3V. An accurate on-chip 1.2V temperature-compensated bandgap reference and control amplifier allows the user to adjust this output current from 20mA down to 2mA. This provides 20dB gain range control capabilities. Alternatively, an external reference voltage may be applied. The DAC5675A features a SLEEP mode, which reduces the standby power to approximately 18mW. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPad is a trademark of Texas Instruments. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2005, Texas Instruments Incorporated DAC5675A www.ti.com SBAS334C – NOVEMBER 2004 – REVISED MARCH 2005 The DAC5675A is available in a 48-pin HTQFP thermally-enhanced PowerPad package. This package increases thermal efficiency in a standard size IC package. The device is characterized for operation over the industrial temperature range of –40°C to +85°C. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) DAC5675A UNIT AVDD (2) –0.3 to +3.6 V (3) –0.3 to +3.6 V AVDD to DVDD –3.6 to +3.6 V –0.3 to +0.5 V CLK, CLKC(2) –0.3 to AVDD + 0.3 V Digital input D[13:0]A, D[13:0]B(3), SLEEP –0.3 to DVDD + 0.3 V IOUT1, IOUT2(2) –1.0 to AVDD + 0.3 V EXTIO, BIAS(2) –1.0 to AVDD + 0.3 V Peak input current (any input) 20 mA Peak total input current (all inputs) -30 mA Operating free-air temperature range, TA –40 to +85 °C Storage temperature range –65 to +150 °C +260 °C Supply voltage range DVDD Voltage between AGND and DGND Lead temperature 1,6mm (1/16in) from the case for 10s (1) (2) (3) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure outside of absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Measured with respect to AGND. Measured with respect to DGND. ORDERING INFORMATION (1) (1) 2 PRODUCT PACKAGELEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING DAC5675A 48-HTQFP PHP –40°C to +85°C DAC5675A ORDERING NUMBER TRANSPORT MEDIA, QUANTITY DAC5675AIPHP Tray, 250 DAC5675AIPHPR Tray, 1000 For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet. DAC5675A www.ti.com SBAS334C – NOVEMBER 2004 – REVISED MARCH 2005 Functional Block Diagram SLEEP DAC5675A Bandgap Reference 1.2V EXTIO BIASJ Current Source Array Output Current Switches Decoder DAC Latch + Drivers Control Amp 14 D[13:0]A LVDS Input Interface D[13:0]B Input Latches 14 CLK Clock Distribution CLKC AVDD (4x) AGND(4x) DVDD(2x) DGND(2x) 3 DAC5675A www.ti.com SBAS334C – NOVEMBER 2004 – REVISED MARCH 2005 DC ELECTRICAL CHARACTERISTICS Over operating free-air temperature range. Typical values at +25°C, AVDD = 3.3V, DVDD = 3.3V, IO(FS) = 20mA, unless otherwise noted. DAC5675A PARAMETER TEST CONDITIONS Resolution MIN TYP MAX 14 UNIT Bit DC Accuracy (1) INL Integral nonlinearity DNL Differential nonlinearity TMIN to TMAX Monotonicity –4 ±1.5 4 LSB –2 ±0.6 2 LSB 2 20 mA AVDD– 1 AVDD +0.3 Monotonic 12b Level Analog Output IO(FS) Full-scale output current Output compliance range AVDD = 3.15V to 3.45V, IO(FS) = 20mA Offset error 0.01 Gain error V %FSR Without internal reference –10 5 10 %FSR With internal reference –10 2.5 10 %FSR Output resistance Output capacitance 300 kΩ 5 pF Reference Output V(EXTIO) Reference voltage Reference output 1.17 current (2) 1.23 1.29 100 V nA Reference Input V(EXTIO) Input reference voltage 0.6 Input resistance 1.2 1.25 V 1 MΩ Small-signal bandwidth 1.4 MHz Input capacitance 100 pF 12 ppm of FSR/°C ±50 ppm/°C Temperature Coefficients Offset drift ∆ V(EXTIO) Reference voltage drift Power Supply AVDD Analog supply voltage 3.15 3.3 3.6 V DVDD Digital supply voltage 3.15 3.3 3.6 V current (3) I(AVDD) Analog supply I(DVDD) Digital supply current (3) PD Power dissipation PD Power dissipation APSRR Analog and digital powersupply rejection ratio DPSRR (1) (2) (3) 4 115 mA 85 mA Sleep mode 18 mW AVDD = 3.3V, DVDD = 3.3V 660 900 mW –0.5 ±0.1 0.5 %FSR/V –0.5 ±0.1 0.5 %FSR/V AVDD = 3.15V to 3.45V Measured differential at IOUT1 and IOUT2; 25Ω to AVDD. Use an external buffer amplifier with high impedance input to drive any external load. Measured at fCLK = 400MSPS and fOUT = 70MHz. DAC5675A www.ti.com SBAS334C – NOVEMBER 2004 – REVISED MARCH 2005 AC ELECTRICAL CHARACTERISTICS Over operating free-air temperature range. Typical values at +25°C, AVDD = 3.3V, DVDD = 3.3V, IO(FS) = 20mA, differential transformer-coupled output, 50Ω doubly-terminated load, unless otherwise noted. DAC5675A PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 400 MSPS Analog Output fCLK Output update rate ts(DAC) Output setting time to 0.1% tPD Output propagation delay tr(IOUT) Output rise time, 10% to 90% tf(IOUT) Output fall time, 90% to 10% Output noise (1) Transition: code x2000 to x23FF 12 ns 1 ns 300 ps 300 ps IOUTFS = 20mA 55 pA/√Hz IOUTFS = 2mA 30 pA/√Hz fCLK = 100MSPS, fOUT = 19.9MHz 73 dBc fCLK = 160MSPS, fOUT = 41MHz 72 dBc fCLK = 200MSPS, fOUT = 70MHz 68 dBc fCLK = 400MSPS, fOUT = 20.1MHz 72 dBc fCLK = 400MSPS, fOUT = 70MHz 71 dBc fCLK = 400MSPS, fOUT = 140MHz 58 dBc fCLK = 100MSPS, fOUT = 19.9MHz 73 dBc fCLK = 160MSPS, fOUT = 41MHz 73 dBc fCLK = 200MSPS, fOUT = 70MHz 70 dBc fCLK = 400MSPS, fOUT = 20.1MHz 73 dBc fCLK = 400MSPS, fOUT = 70MHz 74 dBc fCLK = 400MSPS, fOUT = 140MHz 60 dBc fCLK = 100MSPS, fOUT = 19.9MHz 88 dBc fCLK = 160MSPS, fOUT = 41MHz 87 dBc fCLK = 200MSPS, fOUT = 70MHz 82 dBc fCLK = 400MSPS, fOUT = 20.1MHz 87 dBc AC Linearity THD SFDR SFDR ACPR Total harmonic distortion Spurious-free dynamic range to Nyquist Spurious-free dynamic range within a window, 5MHz span Adjacent channel power ratio WCDMA with 3.84MHz BW, 5MHz channel spacing Two-tone intermodulation to Nyquist (each tone at -6dBfs) IMD (1) (2) (3) (4) Four-tone intermodulation, 15MHz span, missing center tone (each tone at -16dBfs) fCLK = 400MSPS, fOUT = 70MHz 82 dBc fCLK = 400MSPS, fOUT = 140MHz 75 dBc fCLK = 122.88MSPS, IF = 30.72MHz (2) 73 dB 61.44MHz (3) 71 dB fCLK = 399.32MSPS, IF = 153.36MHz (4) 65 dB fCLK = 400MSPS, fOUT1 = 70MHz, fOUT2 = 71MHz 73 dBc fCLK = 400MSPS, fOUT1 = 140MHz, fOUT2 = 141MHz 62 dBc fCLK = 156MSPS, fOUT = 15.6, 15.8, 16.2, 16.4MHz 82 dBc fCLK = 400MSPS, fOUT = 68.1, 69.3, 71.2, 72MHz 74 dBc fCLK = 245.76MSPS, IF = Noise averaged up to 400MHz when operating at 400MSPS. See Figure 9. See Figure 10. See Figure 12 5 DAC5675A www.ti.com SBAS334C – NOVEMBER 2004 – REVISED MARCH 2005 DIGITAL SPECIFICATIONS Over operating free-air temperature range. Typical values at +25°C, AVDD = 3.3V, DVDD = 3.3V, unless otherwise noted. DAC5675A PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LVDS Interface: nodes D[13:0]A, D[13:0]B VITH+ Positive-going differential input voltage threshold VITH- Negative-going differential input voltage threshold ZT Internal termination impedance CI Input capacitance See LVDS min/max threshold voltages table 90 100 mV -100 mV 110 132 2 Ω pF CMOS Interface (SLEEP): VIH High-level input voltage VIL Low-level input voltage 2 IIH High-level input current –100 IIL Low-level input current –10 3.3 0 Input capacitance V 0.8 V 100 µA 10 µA 2 pF Clock Interface (CLK, CLKC): |CLKCLKC| VCM Clock differential input voltage 0.4 Clock duty cycle 40 Common-mode voltage range 2 ±20% 0.8 VPP 60 % V Input resistance Node CLK, CLKC 670 Ω Input capacitance Node CLK, CLKC 2 pF Input resistance Differential 1.3 kΩ Input capacitance Differential 1 pF Timing tSU Input setup time tH Input hold time tDD Digital delay time (DAC latency) 6 1.5 ns 0 ns 3 clk DAC5675A www.ti.com SBAS334C – NOVEMBER 2004 – REVISED MARCH 2005 Timing Information D[13:0]A Valid Data D[13:0]B tH tSU tDD CLK 50% 50% CLKC tPD tS(DAC) 0.1% DAC Output IOUT1/IOUT2 50% 90% 10% 0.1% tr(IOUT) Figure 1. Timing Diagram ELECTRICAL CHARACTERISTICS (1) Over operating free-air temperature range, AVDD = 3.3V, DVDD = 3.3V, IO(FS) = 20mA, unless otherwise noted. APPLIED VOLTAGES RESULTING DIFFERENTIAL INPUT VOLTAGE RESULTING COMMON-MODE INPUT VOLTAGE VA,B [mV] VCOM [V] LOGICAL BIT BINARY EQUIVALENT VA [V] VB [V] 1.25 1.15 100 1.2 1 1.15 1.25 –100 1.2 0 2.4 2.3 100 2.35 1 2.3 2.4 –100 2.35 0 (1) 0.1 0 100 0.05 1 0 0.1 –100 0.05 0 1.5 0.9 600 1.2 1 0.9 1.5 –600 1.2 0 2.4 1.8 600 2.1 1 1.8 2.4 –600 2.1 0 0.6 0 600 0.3 1 0 0.6 –600 0.3 0 COMMENT Operation with minimum differential voltage (±100mV) applied to the complementary inputs versus common-mode range Operation with maximum differential voltage (±600mV) applied to the complementary inputs versus common-mode range Specifications subject to change. DVDD DAC5675A VA 1.4V VB 1V VA, B VA, B 0.4V 0V − 0.4V VCOM = VA + VB VA Logical Bit Equivalent 2 VB DGND 1 0 Figure 2. LVDS Timing Test Circuit and Input Test Levels 7 DAC5675A www.ti.com SBAS334C – NOVEMBER 2004 – REVISED MARCH 2005 D13A 1 D13B 2 D12A 3 D12B 4 D11A 5 EXTIO BIASJ NC SLEEP 45 AGND AVDD 46 AVDD AGND 47 IOUT2 AGND 48 IOUT1 AVDD DEVICE INFORMATION 44 43 42 41 40 39 38 37 36 D0B 35 D0A Thermal Pad(1) 34 D1B 33 D1A 32 D2B DAC5675A (Top View) DAC5675 31 D2A 27 D4A D8A 11 26 D5B D8B 12 25 D5A Note (1): Thermal pad size: 4,5mm x 4,5mm (min), 5,5mm x 5,5mm (max) 13 14 15 16 17 18 19 20 21 22 23 24 D6B D9B 10 D6A 28 D4B CLK 9 CLCK D9A AVDD 29 D3A AGND 8 DVDD D10B DGND 30 D3B DGND 7 DVDD D10A D7B 6 D7A D11B Table 1. TERMINAL FUNCTIONS TERMINAL 8 NAME NO. I/O DESCRIPTION AGND 19, 41, 46, 47 I Analog negative supply voltage (ground); pin 47 internally connected to PowerPAD. AVDD 20, 42, 45, 48 I Analog positive supply voltage. BIASJ 39 O Full-scale output current bias. CLK 22 I External clock input. CLKC 21 I Complementary external clock input. D[13:0]A 1, 3, 5, 7, 9, 11, 13, 23, 25, 27, 29, 31, 33, 35 I LVDS positive input, data bits 0 through 13. D13A is most significant data bit (MSB). D0A is least significant data bit (MSB). D[13:0]B 2, 4, 6, 8, 10, 12, 14, 24, 26, 28, 30, 32, 34, 36 I LVDS negative input, data bits 0 through 13. D13B is most significant data bit (MSB). D0B is least significant data bit (MSB). DGND 16, 18 I Digital negative supply voltage (ground). NC 38 -— DVDD 15, 17 I EXTIO 40 I/O Internal reference output or external reference input. Requires a 0.1µF decoupling capacitor to AGND when used as reference output. IOUT1 43 O DAC current output. Full-scale when all input bits are set to '0'. Connect reference side of DAC load resistors to AVDD. IOUT2 44 O DAC complementary current output. Full-scale when all input bits are set to '1'. Connect reference side of DAC load resistors to AVDD. SLEEP 37 I Asynchronous hardware power down input. Active high. Internal pulldown. Not connected in chip. Can be high or low. Digital positive supply voltage. DAC5675A www.ti.com SBAS334C – NOVEMBER 2004 – REVISED MARCH 2005 TYPICAL CHARACTERISTICS DIFFERENTIAL NON-LINEARITY (DNL) vs INPUT CODE INTEGRAL NON-LINEARITY (INL) vs INPUT CODE 1.5 1.0 0.8 1.0 0.6 0.5 INL (LSB) DNL (LSB) 0.4 0.2 0 −0.2 0 −0.5 −0.4 −0.6 −1.0 −0.8 −1.5 −1.0 0 2000 4000 6000 8000 10000 12000 14000 16000 0 4000 2000 6000 Input Code Figure 3. Figure 4. TWO-TONE IMD (POWER) vs FREQUENCY 0 −30 −40 Two−Tone IMD3 (dBc) −20 Power (dBFS) TWO-TONE IMD3 vs FREQUENCY f1 = 69.5MHz, −6dBFS f2 = 70.5MHz, −6dBFS IMD3 = 77.41dBc VCC = VAA = 3.3V fCLK = 200MHz −10 −50 −60 −70 −80 −90 −100 67 65 69 71 73 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 60 75 f 2 − f1 = 1MHz (−6dBFS each) VCC = VAA = 3.3V f CLK = 200MHz 5 15 25 35 Frequency (MHz) 65 75 85 SINGLE-TONE SPECTRUM POWER vs FREQUENCY SPURIOUS-FREE DYNAMIC RANGE vs FREQUENCY 86 −40 −50 40.06MHz VCC = VAA = 3.3V fCLK = 400MHz −3dBFS 82 SFDR (dBFS) −30 78 74 −6dBFS 70 0dBFS 66 62 60.25MHz −70 90 VCC = VAA = 3.3V f CLK = 400MHz f OUT = 20.1MHz, 0dBFS SFDR = 74.75dBc −20 Power (dBFS) 55 Figure 6. 20.1MHz −60 45 Center Frequency (MHz) Figure 5. 0 −10 8000 10000 12000 14000 16000 Input Code 58 −80 54 −90 50 0 20 40 60 80 100 120 140 Frequency (MHz) Figure 7. 160 180 200 10 20 30 40 50 60 70 80 90 100 110 120 Output Frequency (MHz) Figure 8. 9 DAC5675A www.ti.com SBAS334C – NOVEMBER 2004 – REVISED MARCH 2005 TYPICAL CHARACTERISTICS (continued) SPURIOUS-FREE DYNAMIC RANGE vs FREQUENCY 90 86 78 74 −6dBFS 70 VCC = VAA = 3.3V fCLK = 122.88MHz fCENTER = 30.72MHz ACLR = 72.29dB −35 Power (dBm/30kHz) SFDR (dBFS) −25 VCC = VAA = 3.3V fCLK = 200MHz −3dBFS 82 W-CDMA TM1 SINGLE CARRIER POWER vs FREQUENCY 0dBFS 66 62 −45 −55 −65 −75 −85 58 −95 54 −105 −115 50 10 20 30 40 50 60 70 80 90 18 100 110 120 23 28 Output Frequency (MHz) −30 Figure 10. W-CDMA TM1 DUAL CARRIER POWER vs FREQUENCY W-CDMA TM1 SINGLE CARRIER ACLR vs OUTPUT FREQUENCY V CC = V AA = 3.3V fCENTER = 92.16MHz VCC = VAA = 3.3V fCLK = 399.36MHz Single Channel 78 ACLR = 65dBc 76 74 −60 −70 −80 72 70 68 66 −90 64 −100 62 60 87.2 92.2 Frequency Figure 11. 10 43 80 f CLK = 368.64MHz −50 −110 82.2 38 Figure 9. ACLR (dBc) Power (dBm/30kHz) −40 33 Frequency 97.2 10.2 10 30 50 70 90 110 Output Frequency (MHz) Figure 12. 130 150 DAC5675A www.ti.com SBAS334C – NOVEMBER 2004 – REVISED MARCH 2005 APPLICATION INFORMATION Detailed Description Figure 13 shows a simplified block diagram of the current steering DAC5675A. The DAC5675A consists of a segmented array of NPN-transistor current sinks, capable of delivering a full-scale output current up to 20mA. Differential current switches direct the current of each current sink to either one of the complementary output nodes IOUT1 or IOUT2. The complementary current output enables differential operation, canceling out common-mode noise sources (digital feed-through, on-chip and PCB noise), dc offsets, and even-order distortion components, and doubling signal output power. The full-scale output current is set using an external resistor (RBIAS) in combination with an on-chip bandgap voltage reference source (1.2V) and control amplifier. The current (IBIAS) through resistor RBIAS is mirrored internally to provide a full-scale output current equal to 16 times IBIAS. The full-scale current is adjustable from 20mA down to 2mA by using the appropriate bias resistor value. SLEEP 3.3V (AVDD) DAC5675A Bandgap Reference 1.2V 50Ω IOUT Output 1:1 EXTIO Current Source Array BIASJ CEXT 0.1µF Output Current Switches Control Amp RBIAS 1kΩ IOUT 50Ω RLOAD 50Ω 3.3V (AVDD) 14 D[13:0]A LVDS Input Interface D[13:0]B Input Latches Decoder 14 DAC Latch + Drivers 3.3V (AVDD) CLK 1:4 Clock Input 100Ω RT 200Ω Clock Distribution CLKC AVDD(4x) AGND(4x) DVDD(2x) DGND(2x) Figure 13. Application Schematic 11 DAC5675A www.ti.com SBAS334C – NOVEMBER 2004 – REVISED MARCH 2005 APPLICATION INFORMATION (continued) Digital Inputs The DAC5675A uses a low voltage differential signaling (LVDS) bus input interface. The LVDS features a low differential voltage swing with low constant power consumption (≈4mA per complementary data input) across frequency. The differential characteristic of LVDS allows for high-speed data transmission with low electromagnetic interference (EMI) levels. The LVDS input minimum and maximum input threshold table lists the LVDS input levels. Figure 14 shows the equivalent complementary digital input interface for the DAC5675A, valid for pins D[13:0]A and D[13:0]B. Note that the LVDS interface features internal 110Ω resistors for proper termination. Figure 2 shows the LVDS input timing measurement circuit and waveforms. A common-mode level of 1.2V and a differential input swing of 0.8VPP is applied to the inputs. Figure 15 shows a schematic of the equivalent CMOS/TTL-compatible digital inputs of the DAC5675A, valid for the SLEEP pin. DVDD DAC5675A DAC5675A D[13..0]A 110Ω Termination Resistor Internal Digital IN D[13..0]B D[13..0]A D[13..0]B Internal Digital In DGND Figure 14. LVDS Digital Equivalent Input DVDD DAC5675A Internal Digital In Digital Input DGND Figure 15. CMOS/TTL Digital Equivalent Input Clock Input The DAC5675A features differential, LVPECL compatible clock inputs (CLK, CLKC). Figure 16 shows the equivalent schematic of the clock input buffer. The internal biasing resistors set the input common-mode voltage to approximately 2V, while the input resistance is typically 670Ω. A variety of clock sources can be ac-coupled to the device, including a sine wave source (see Figure 17). 12 DAC5675A www.ti.com SBAS334C – NOVEMBER 2004 – REVISED MARCH 2005 APPLICATION INFORMATION (continued) AVDD DAC5675A R1 1kΩ R1 1kΩ Internal Clock CLK CLKC R2 2kΩ R2 2kΩ AGND Figure 16. Clock Equivalent Input Optional, may be bypassed for sine wave input. Swing Limitation CAC 0.1µF 1:4 CLK RT 200Ω DAC5675A CLKC Termination Resistor Figure 17. Driving the DAC5675A with a Single-Ended Clock Source Using a Transformer To obtain best ac performance the DAC5675A clock input should be driven with a differential LVPECL or sine wave source as shown in Figure 18 and Figure 19. Here, the potential of VTT should be set to the termination voltage required by the driver along with the proper termination resistors (RT). The DAC5675A clock input can also be driven single-ended; this is shown in Figure 20. 13 DAC5675A www.ti.com SBAS334C – NOVEMBER 2004 – REVISED MARCH 2005 APPLICATION INFORMATION (continued) CAC 0.01µF ECL/PECL Gate CLK Single−Ended ECL or (LV)PECL Source CAC 0.01µF DAC5675A CLKC RT 50Ω RT 50Ω VTT Figure 18. Driving the DAC5675A with a Single-Ended ECL/PECL Clock Source CAC 0.01µF Differential + ECL or (LV)PECL Source − RT 50Ω CLK CAC 0.01µF DAC5675A CLKC RT 50Ω VTT Figure 19. Driving the DAC5675A with a Differential ECL/PECL Clock Source TTL/CMOS Source CLK R OPT 22Ω DAC5675A CLKC 0.01µF Node CLKC Internally biased to AVDD/2 Figure 20. Driving the DAC5675A with a Single-Ended TTL/CMOS Clock Source 14 DAC5675A www.ti.com SBAS334C – NOVEMBER 2004 – REVISED MARCH 2005 APPLICATION INFORMATION (continued) Supply Inputs The DAC5675A comprises separate analog and digital supplies, that is, AVDD and DVDD, respectively. These supply inputs can be set independently from 3.6V down to 3.15V. DAC Transfer Function The DAC5675A has a current sink output. The current flow through IOUT1 and IOUT2 is controlled by D[13:0]A and D[13:0]B. For ease of use, we denote D[13:0] as the logical bit equivalent of D[13:0]A and its complement D[13:0]B. The DAC5675A supports straight binary coding with D13 being the MSB and D0 the LSB. Full-scale current flows through IOUT2 when all D[13:0] inputs are set high and through IOUT1 when all D[13:0] inputs are set low. The relationship between IOUT1 and IOUT2 can be expressed asEquation 1: IOUT1 IO (FS)IOUT2 (1) IO(FS) is the full-scale output current sink (2mA to 20mA). Since the output stage is a current sink, the current can only flow from AVDD through the load resistors RL into the IOUT1 and IOUT2 pins. The output current flow in each pin driving a resistive load can be expressed as shown in Figure 21, as well as in Equation 2 and Equation 3. DAC5675A D[13:0] = 0 IOUT1 IOUT2 D[13:0] = 1 − VOUT2 0mA RL VOUT1 − + RL 3.3V AVDD + 20mA Figure 21. Relationship Between D[13:0], IOUT1 and IOUT2 IO (FS) 16383CODE 16384 IO (FS) CODE IOUT2 16384 IOUT1 (2) (3) where CODE is the decimal representation of the DAC input word. This would translate into single-ended voltages at IOUT1 and IOUT2, as shown in Equation 4 and Equation 5: VOUT1 AVDD IOUT1 RL (4) VOUT2 AVDD IOUT2 RL (5) Assuming that D[13:0] = 1 and the RL is 50Ω, the differential voltage between pins IOUT1 and IOUT2 can be expressed as shown in Equation 6 through Equation 8: VOUT1 3.3V 0mA 50 3.3V (6) VOUT2 AVDD 20mA 50 2.3V (7) VDIFF VOUT1 VOUT2 1V (8) If D[13:0] = 0, then IOUT2 = 0mA and IOUT1 = 20mA and the differential voltage VDIFF = –1V. The output currents and voltages in IOUT1 and IOUT2 are complementary. The voltage, when measured differentially, will be doubled compared to measuring each output individually. Care must be taken not to exceed the compliance voltages at the IOUT1 and IOUT2 pins in order to keep signal distortion low. 15 DAC5675A www.ti.com SBAS334C – NOVEMBER 2004 – REVISED MARCH 2005 APPLICATION INFORMATION (continued) Reference Operation The DAC5675A has a bandgap reference and control amplifier for biasing the full-scale output current. The full-scale output current is set by applying an external resistor RBIAS. The bias current IBIAS through resistor RBIAS is defined by the on-chip bandgap reference voltage and control amplifier. The full-scale output current equals 16 times this bias current. The full-scale output current IO(FS) is thus expressed as Equation 9: 16 V EXTIO I O(FS) 16 I BIAS RBIAS (9) where VEXTIO is the voltage at terminal EXTIO. The bandgap reference voltage delivers a stable voltage of 1.2V. This reference can be overridden by applying an external voltage to terminal EXTIO. The bandgap reference can additionally be used for external reference operation. In such a case, an external buffer amplifier with high impedance input should be selected in order to limit the bandgap load current to less than 100nA. The capacitor CEXT may be omitted. Terminal EXTIO serves as either an input or output node. The full-scale output current is adjustable from 20mA down to 2mA by varying resistor RBIAS. Analog Current Outputs Figure 22 shows a simplified schematic of the current sink array output with corresponding switches. Differential NPN switches direct the current of each individual NPN current sink to either the positive output node IOUT1 or its complementary negative output node IOUT2. D[13:0] controls the S(N)C current switches and D[13:0] controls the S(N) current switches, as explained in the previous DAC Transfer Function section (see Figure 21). The output impedance is determined by the stack of the current sinks and differential switches, and is > 300kΩ in parallel with an output capacitance of 5pF. The external output resistors are referred to the positive supply AVDD. 3.3V AVDD RLOAD RLOAD IOUT1 IOUT2 DAC5675A S(1) S(1)C S(2) S(2)C S(N) S(N)C Current Sink Array AGND Figure 22. Equivalent Analog Current Output The DAC5675A can easily be configured to drive a doubly-terminated 50Ω cable using a properly selected transformer. Figure 23 and Figure 24 show the 1:1 and 4:1 impedance ratio configuration, respectively. These configurations provide maximum rejection of common-mode noise sources and even-order distortion components, thereby doubling the power of the DAC to the output. The center tap on the primary side of the transformer is terminated to AVDD, enabling a dc current flow for both IOUT1 and IOUT2. Note that the ac performance of the DAC5675A is optimum and specified using a 1:1 differential transformer-coupled output. 16 DAC5675A www.ti.com SBAS334C – NOVEMBER 2004 – REVISED MARCH 2005 APPLICATION INFORMATION (continued) 3.3V AVDD DAC5675A 50Ω 1:1 IOUT1 RLOAD 50Ω 100Ω IOUT2 50Ω 3.3V AVDD Figure 23. Driving a Doubly-Terminated 50Ω Cable Using a 1:1 Impedance Ratio Transformer 3.3V AVDD DAC5675A 100Ω 4:1 IOUT1 RLOAD 50Ω IOUT2 15Ω 100Ω 3.3V AVDD Figure 24. Driving a Doubly-Terminated 50Ω Cable Using a 4:1 Impedance Ratio Transformer Figure 25(a) shows the typical differential output configuration with two external matched resistor loads. The nominal resistor load of 25Ω gives a differential output swing of 1VPP (0.5–VPP single-ended) when applying a 20mA full-scale output current. The output impedance of the DAC5675A slightly depends on the output voltage at nodes IOUT1 and IOUT2. Consequently, for optimum dc-integral nonlinearity, the configuration of Figure 25(b) should be chosen. In this current/voltage (I-V) configuration, terminal IOUT1 is kept at AVDD by the inverting operational amplifier. The complementary output should be connected to AVDD to provide a dc-current path for the current sources switched to IOUT1. The amplifier maximum output swing and the full-scale output current of the DAC determine the value of the feedback resistor (RFB). The capacitor (CFB) filters the steep edges of the DAC5675A current output, thereby reducing the operational amplifier slew-rate requirements. In this configuration, the op amp should operate at a supply voltage higher than the resistor output reference voltage AVDD as a result of its positive and negative output swing around AVDD. Node IOUT1 should be selected if a single-ended unipolar output is desired. 17 DAC5675A www.ti.com SBAS334C – NOVEMBER 2004 – REVISED MARCH 2005 APPLICATION INFORMATION (continued) (a) (b) 3.3V AVDD DAC5675A CFB IOUT1 VOUT1 IOUT2 VOUT2 25Ω 3.3V AVDD 200Ω (RFB) DAC5675A 25Ω IOUT1 VOUT IOUT2 Optional, for single− ended output referred to AVDD 3.3V AVDD Figure 25. Output Configurations Sleep Mode The DAC5675A features a power-down mode that turns off the output current and reduces the supply current to approximately 6mA. The power-down mode is activated by applying a logic level 1 to the SLEEP pin pulled down internally. Definitions Definitions of Specifications and Terminology Gain error is defined as the percentage error in the ratio between the measured full-scale output current and the value of 16 x V(EXTIO)/RBIAS. A V(EXTIO) of 1.25V is used to measure the gain error with an external reference voltage applied. With an internal reference, this error includes the deviation of V(EXTIO) (internal bandgap reference voltage) from the typical value of 1.25V. Offset error is defined as the percentage error in the ratio of the differential output current (IOUT1–IOUT2) and the half of the full-scale output current for input code 8192. THD is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental output signal. SNR is the ratio of the rms value of the fundamental output signal to the rms sum of all other spectral components below the Nyquist frequency, including noise, but excluding the first six harmonics and dc. SINAD is the ratio of the rms value of the fundamental output signal to the rms sum of all other spectral components below the Nyquist frequency, including noise and harmonics, but excluding dc. ACPR or adjacent channel power ratio is defined for a 3.84Mcps 3GPP W-CDMA input signal measured in a 3.84MHz bandwidth at a 5MHz offset from the carrier with a 12dB peak-to-average ratio. APSSR or analog power supply ratio is the percentage variation of full-scale output current versus a 5% variation of the analog power supply AVDD from the nominal. This is a dc measurement. DPSSR or digital power supply ratio is the percentage variation of full-scale output current versus a 5% variation of the digital power supply DVDD from the nominal. This is a dc measurement. 18 PACKAGE OPTION ADDENDUM www.ti.com 21-May-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) DAC5675AIPHP ACTIVE HTQFP PHP 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DAC5675AIPHPG4 ACTIVE HTQFP PHP 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DAC5675AIPHPR ACTIVE HTQFP PHP 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DAC5675AIPHPRG4 ACTIVE HTQFP PHP 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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OTHER QUALIFIED VERSIONS OF DAC5675A : Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 21-May-2010 • Space: DAC5675A-SP NOTE: Qualified Version Definitions: • Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device DAC5675AIPHPR Package Package Pins Type Drawing HTQFP PHP 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 9.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 9.6 1.5 12.0 16.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC5675AIPHPR HTQFP PHP 48 1000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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