144 pin SO-DIMM SDRAM Modules HYS64V16200GDL HYS64V32220GDL 128MB & 256 MB PC100 / PC133 • 144 Pin Eight Byte Small Outline Dual-In-Line Synchronous DRAM Modules for PC100 and PC133 notebook applications • One bank 16M x 64 (128MByte) and two banks 32M x 64 (256 MByte) non-parity module organisation • Performance: -7 -7.5 -8 PC133 2-2-2 PC133 3-3-3 PC100 2-2-2 Units fCK Clock frequency (max.) 133 133 100 MHz tAC Clock access time 5.4 5.4 6 ns • Single +3.3V(± 0.3V ) power supply • Programmable CAS Latency, Burst Length and Wrap Sequence (Sequential & Interleave) • Auto Refresh (CBR) and Self Refresh • Decoupling capacitors mounted on substrate • All inputs, outputs are LVTTL compatible • Serial Presence Detect with E2PROM • 256Mbit SDRAM low power components in TSOP54 packages with 16M x 16 organisation • 8192 refresh cycles every 64 ms • Gold contact pad, JEDEC MO-190 outline dimensions • This module family is fully compliant with the latest INTEL SO-DIMM layout and electrical specifications • All PC133 modules are fully backward compatible to PC100-222 operation • Importante Notice: These SO-DIMM modules are based on 256Mbit SDRAM technology and can be used in applications only, where 256Mbit addressing is supported. INFINEON Technologies 1 9.01 HYS64V16200GDL/HYS64V32220GDL 144 pin SO-DIMM SDRAM Modules This INFINEON modules are industry standard 144 pin 8-byte Synchronous DRAM (SDRAM) Small Outline Dual In-line Memory Modules (SO-DIMM) which are organised as x64 high speed memory arrays designed for use in non-parity applications. These SO-DIMMs use 256Mbit SDRAMs in TSOPII packages. Decoupling capacitors are mounted on the board. The DIMMs use serial presence detects implemented via a serial E2PROM using the two pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All INFINEON 144-pin SO-DIMMs provide a high performance, flexible 8-byte interface in a 67,6 mm long footprint. Product Spectrum: Speed HYS64V16200GDL-7 HYS64V16200GDL-7.5 HYS64V16200GDL-8 HYS64V32220GDL-7 HYS64V32220GDL-7.5 32M x 64 HYS64V32220GDL-8 16M x 64 SDRAMs used PC133-222 PC133-333 4 16Mx16 PC100-222 PC133-222 PC133-333 8 16Mx16 PC100-222 RowAddr. Bank Select 13 BA0, BA1 Column Refresh Addr. Period 8k 9 7,8 µs Note: All partnumbers end with a place code, designating the die revision. Example: HYS64V32220GDL-8-C2, indicating Rev.C2 dies are used for SDRAM components. Card Dimensions: Organisation 16M x 64 32M x 64 PCB-Board INTEL Rev. 1.0/1.2 L x H x T [mm] 67.60 x 25.40 x 3.80 67.60 x 31.75 x 3.80 Pin Names A0-A12 Address Inputs DQMB0 -DQMB7 Data Mask BA0,BA1 Bank Selects CS0, CS1 *) Chip Select DQ0 - DQ63 Data Input/Output Vcc Power (+3.3 Volt) RAS Row Address Strobe Vss Ground CAS Column Address Strobe SCL Clock for Presence Detect WE Read / Write Input SDA Serial Data Out for Presence Detect CKE0, CKE1 Clock Enable N.C. No Connection CLK0, CLK1 *) Clock Input *) CS1 and CKE1 on two bank modules only INFINEON Technologies 2 9.01 HYS64V16200GDL/HYS64V32220GDL 144 pin SO-DIMM SDRAM Modules Pin Configuration Front Side PIN # Back Side PIN # Front Side PIN # Back Side PIN # 1 VSS 2 VSS 73 NC 74 3 DQ0 4 DQ32 75 Vss 76 CLK1 Vss 5 DQ1 6 DQ33 77 NC 78 NC 7 DQ2 8 DQ34 79 NC 80 NC 9 DQ3 10 DQ35 81 Vcc 82 Vcc 11 VCC 12 Vcc 83 DQ16 84 DQ48 13 DQ4 14 DQ36 85 DQ17 86 DQ49 15 DQ5 16 DQ37 87 DQ18 88 DQ50 17 DQ6 18 DQ38 89 DQ19 90 DQ51 19 DQ7 20 DQ39 91 Vss 92 Vss 21 Vss 22 Vss 93 DQ20 94 DQ52 23 DQMB0 24 DQMB4 95 DQ21 96 DQ53 25 DQMB1 26 DQMB5 97 DQ22 98 DQ54 27 Vcc 28 Vcc 99 DQ23 100 DQ55 29 A0 30 A3 101 Vcc 102 Vcc 31 A1 32 A4 103 A6 104 A7 33 A2 34 A5 105 A8 106 BA0 35 Vss 36 Vss 107 Vss 108 Vss 37 DQ8 38 DQ40 109 A9 110 BA1 39 DQ9 40 DQ41 111 A10 112 A11 41 DQ10 42 DQ42 113 Vcc 114 Vcc 43 DQ11 44 DQ43 115 DQMB2 116 DQMB6 45 Vcc 46 Vcc 117 DQMB3 118 DQMB7 47 DQ12 48 DQ44 119 Vss 120 Vss 49 DQ13 50 DQ45 121 DQ24 122 DQ56 51 DQ14 52 DQ46 123 DQ25 124 DQ57 53 DQ15 54 DQ47 125 DQ26 126 DQ58 55 Vss 56 Vss 127 DQ27 128 DQ59 57 NC 58 NC 129 Vcc 130 Vcc 59 NC 60 NC 131 DQ28 132 DQ60 61 CLK0 62 CKE0 133 DQ29 134 DQ61 63 Vcc 64 Vcc 135 DQ30 136 DQ62 65 RAS 66 CAS 137 DQ31 138 DQ63 67 WE 68 CKE1 139 Vss 140 Vss 69 CS0 70 A12 141 SDA 142 SCL 71 CS1 72 N.C 143 Vcc 144 Vcc INFINEON Technologies 3 9.01 HYS64V16200GDL/HYS64V32220GDL 144 pin SO-DIMM SDRAM Modules WE CS0 WE CS LDQM DQ0-DQ7 DQMB0 DQ0-DQ7 DQMB1 DQ8-DQ15 DQMB4 DQ32-DQ39 DQMB5 DQ40-DQ47 UDQM DQ8-DQ15 D0 WE CS LDQM DQ0-DQ7 DQMB2 DQ16-DQ23 DQMB3 DQ24-DQ31 DQMB6 DQ48-DQ55 DQMB7 DQ56-DQ63 UDQM DQ8-DQ15 D1 A0-A12, BA0, BA1 D0-D3 VC C D0-D3 D0-D3 RAS D0-D3 CAS D0-D3 CKE0 D0-D3 CLK0 4 SDRAM UDQM DQ8-DQ15 D2 WE CS LDQM DQ0-DQ7 UDQM DQ8-DQ15 D3 E 2 PROM (256 word x 8 Bit) C 1 -C 4 VSS WE CS LDQM DQ0-DQ7 SA0 SA1 SA2 SCL SDA Note: All resistors are 10 Ω CLK1 10 pF SPB04133_256Mb Block Diagram for one bank 16M x 64 (128MByte) SDRAM SO- DIMM - Module INFINEON Technologies 4 9.01 HYS64V16200GDL/HYS64V32220GDL 144 pin SO-DIMM SDRAM Modules WE CS0 CS1 DQMB0 DQ0-DQ7 DQMB1 DQ8-DQ15 DQMB2 DQ16-DQ23 DQMB3 DQ24-DQ31 CS WE LDQM DQ0-DQ7 CS WE LDQM DQ0-DQ7 UDQM DQ8-DQ15 D0 UDQM DQ8-DQ15 D4 CS WE LDQM DQ0-DQ7 CS WE LDQM DQ0-DQ7 UDQM DQ8-DQ15 D1 UDQM DQ8-DQ15 D5 A0-A12, BA0, BA1 D0-D7 VC C D0-D7 DQMB4 DQ32-DQ39 DQMB5 DQ40-DQ47 DQMB6 DQ48-DQ55 DQMB7 DQ56-DQ63 D0-D7 RAS D0-D7 CAS D0-D7 CKE0 D0-D3 CKE1 D4-D7 CLK0 D0-D3 CLK1 D4-D7 CS WE LDQM DQ0-DQ7 UDQM DQ8-DQ15 D2 UDQM DQ8-DQ15 D6 CS WE LDQM DQ0-DQ7 CS WE LDQM DQ0-DQ7 UDQM DQ8-DQ15 D3 UDQM DQ8-DQ15 D7 E 2 PROM (256 word x 8 Bit) C VS S CS WE LDQM DQ0-DQ7 SA0 SA1 SA2 SCL SDA Note: All resistors are 10 Ω SPB04134_256M Block Diagram for two bank 32M x 64 (256MByte) SDRAM SO- DIMM - Module INFINEON Technologies 5 9.01 HYS64V16200GDL/HYS64V32220GDL 144 pin SO-DIMM SDRAM Modules Absolute Maximum Ratings Parameter Symbol Limit Values min. max. Unit Input / Output voltage relative to VSS VIN, VOUT – 1.0 4.6 V Power supply voltage on VDD VDD – 1.0 4.6 V Storage temperature range T STG -55 +150 oC Power dissipation (per SDRAM component) PD – 1 W Data out current (short circuit) IOS – 50 mA Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. Functional operation should be restricted to recommended operation conditions. Exposure to higher than recommended voltage for extended periods of time affect device reliability DC Characteristics TA = 0 to 70 oC; VSS = 0 V; VDD = 3.3 V ± 0.3 V Parameter Symbol Limit Values min. max. Unit Input high voltage VIH 2.0 Vcc+0.3 Input low voltage VIL – 0.5 0.8 V V Output high voltage (I OUT = – 4.0 mA) VOH 2.4 – V Output low voltage (IOUT = 4.0 mA) VOL – 0.4 V Input leakage current, any input (0 V < VIN < 3.6 V, all other inputs = 0 V) I I(L) – 20 20 mA Output leakage current (DQ is disabled, 0 V < VOUT < VDD) I O(L) – 20 20 mA Capacitance TA = 0 to 70 oC; VDD = 3.3 V ± 0.3 V, f = 1 MHz Parameter Symbol Limit Values Unit 16M x 64 max. 32M x 64 max. Input capacitance (A0 to A11, BA0, BA1) CI1 28 52 pF Input capacitance (RAS, CAS, WE, CKE0) CI2 25 46 pF Input Capacitance (CLK0, CLK1) CI3 35 35 pF Input capacitance (CS0) CI4 25 30 pF Input capacitance (DQMB0-DQMB7) CI5 10 15 pF Input / Output capacitance (DQ0-DQ63) CIO 12 18 pF Input Capacitance (SCL,SA0-2) Csc 8 8 pF Input/Output Capacitance Csd 10 10 pF INFINEON Technologies 6 9.01 HYS64V16200GDL/HYS64V32220GDL 144 pin SO-DIMM SDRAM Modules Operating Currents per memory bank (TA = 0 to 70 oC; VSS = 0 V; VDD = 3.3 V ± 0.3 V) (Recommended Operating Conditions unless otherwise noted) Parameter & Test Condition Symb. -7/-7.5 -8 ICC1 920 680 Note OPERATING CURRENT trc=trcmin., All banks operated in random access, all banks operated in ping-pong manner PRECHARGE STANDBY CURRENT in Power Down Mode CS =VIH (min.), CKE<=Vil(max) tck = min. ICC2P PRECHARGE STANDBY CURRENT in Non-Power Down Mode CS = VIH (min.), CKE>=Vih(min) tck = min. ICC2N 160 NO OPERATING CURRENT CKE>=VIH(min.) ICC3N 200 tck = min., CS = VIH(min), active state ( max. 4 banks) CKE<=VIL(max.) ICC3P BURST OPERATING CURRENT tck = min., Read command cycling ICC4 AUTO REFRESH CURRENT tck = min., Auto Refresh command cycling ICC5 SELF REFRESH CURRENT Self Refresh Mode, CKE=0.2V, tck = infinity. ICC6 8 mA 1 120 mA 1 180 mA 1 mA 1 mA 1,2 mA 1 mA 1 40 600 mA 1, 2 400 960 880 7.2 Notes: 1. These parameters depend on the cycle rate. These values are measured at 133 MHz for -7 & -7.5 and at 100 MHz for -8 modules. Input signals are changed once during tck. 2. These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3 and BL=4 is assumed and the data-out current is excluded. INFINEON Technologies 7 9.01 HYS64V16200GDL/HYS64V32220GDL 144 pin SO-DIMM SDRAM Modules AC Characteristics 1)2) (TA = 0 to 70 oC; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns) Symbol Parameter Unit Limit Values -7 PC133-222 -7.5 PC133-333 -8 PC100-222 min. max. min. max. min. max. CAS Latency = 3 tCK CAS Latency = 2 7.5 7.5 – – 7.5 10 – – 10 10 – – CAS Latency = 3 tCK CAS Latency = 2 – – 133 133 – – 133 100 – – 100 100 Access Time from Clock CAS Latency = 3 tAC CAS Latency = 2 – – 5.4 5.4 – – 5.4 6 – – 6 6 ns ns – 2.5 – 3 – ns Clock and Access Time Clock Cycle Time ns ns Clock Frequency MHz MHz 2, 3 Clock High Pulse Width tCH 2.5 Clock Low Pulse Width tCL 2.5 – 2.5 – 3 – ns Transition time tT 0.3 1.2 0.3 1.2 0.5 2 ns Input Setup Time tIS 1.5 – 1.5 – 2 – ns 4 Input Hold Time tIH 0.8 – 0.8 – 1 – ns 4 Power Down Mode Entry time tSB Setup and Hold Paramters – 1 – 1 – 1 CLK 4 Power Down Mode Exit Setup Time tPDE 1 – 1 – 1 – CLK 4 tRSC 2 – 2 – 2 – CLK Row to Column Delay Time tRCD 15 – 20 – 20 – ns 5 Row Precharge Time tRP 15 – 20 – 20 – ns 5 Row Active Time tRAS 42 100k 45 100k 50 100k ns 5 Row Cycle Time tRC Mode Register Set-up time Common Parameters 60 – 67 – 70 – ns 5 Activate(a) to Activate(b) Command tRRD period 14 – 15 – 16 – ns 5 CAS(a) to CAS(b) Command period tCCD 1 – 1 – 1 – CLK INFINEON Technologies 8 9.01 HYS64V16200GDL/HYS64V32220GDL 144 pin SO-DIMM SDRAM Modules Parameter Symbol Unit Limit Values -7 PC133-222 -7.5 PC133-333 -8 PC100-222 min. max. min. max. min. max. Refresh Cycle Refresh Period (4096 cycles) tREF – 64 – 64 – 64 ms Self Refresh Exit Time tSREX 1 – 1 – 1 – CLK 6 Data Out Hold Time tOH 3 – 3 – 3 – ns Data Out to Low Impedance Time tLZ 0 – 0 – 0 – ns Data Out to High Impedance Time tHZ 3 7 3 7 3 8 ns DQM Data Out Disable Latency tDQZ – 2 – 2 – 2 CLK Data Input to Precharge (write recovery) tWR 2 – 2 – 2 – CLK DQM Write Mask Latency tDQW 0 – 0 – 0 – CLK Read Cycle 7 Write Cycle INFINEON Technologies 9 9.01 HYS64V16200GDL/HYS64V32220GDL 144 pin SO-DIMM SDRAM Modules Notes: 1. All AC characteristics shown are for SDRAM components. An initial pause of 100 µ s is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 2. AC timing tests have Vil = 0.4 V and Vih = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between Vih and V il. All AC measurements assume tT =1ns with the AC output load circuit shownSpecified tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0 V. . t CH 2.4 V 0.4 V 1.4 V CLOCK t CL t IS tT t IH 1.4 V INPUT tAC t LZ tAC t OH I/O OUTPUT 1.4 V 50 pF t HZ Measurement conditions for tac and toh IO.vsd 3. If clock rising time is longer than 1ns, a time (tT -0.5) ns has to be added to this parameter. 4. If tT is longer than 1ns, a time (tT -1) ns has to be added to this parameter. 5. Any time that the refresh Period has been exceeded, a minimum of two Auto (CRB) Refresh commands must be given to “wake-up“ the device. 6. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 7. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels. Serial Presence Detects: A serial presence detect storage device - E2PROM - is assembled onto the module. Information about the module configuration, speed, etc. is written into the E 2PROM device during module production using a serial presence detect protocol ( I2C synchronous 2-wire bus) INFINEON Technologies 10 9.01 HYS64V16200GDL/HYS64V32220GDL 144 pin SO-DIMM SDRAM Modules SPD-Table HYS64V16200GDL: Byte# Description SPD Entry Value Hex 16Mx64 16Mx64 16Mx64 -7 -7.5 -8 128 80 256 SDRAM 08 04 0 Number of SPD bytes 1 2 Total bytes in Serial PD Memory Type 3 4 Number of Row Addresses Number of Column Addresses 13 9 0D 09 5 6 Number of DIMM Banks Module Data Width 1 64 01 40 7 8 Module Data Width (cont’d) Module Interface Levels 0 LVTTL 00 01 9 SDRAM Cycle Time at CL=3 10 SDRAM Access time from Clock at CL=3 11 Dimm Config (Error Det/Corr.) 12 13 Refresh Rate/Type SDRAM width, Primary 14 15 Error Checking SDRAM data width Minimum clock delay for back-to-back random column address 16 17 7.5 / 10.0 ns 75 75 5.4 / 6.0 ns 54 54 A0 60 none 00 Self-Refresh, 7.8 µs x16 82 10 n/a tccd = 1 CLK 00 01 Burst Length supported Number of SDRAM banks 1, 2, 4 & 8 2 0F 04 18 19 Supported CAS Latencies CS Latencies 2, & 3 CS latency = 0 06 01 20 21 WE Latencies SDRAM DIMM module attributes Write latency = 0 unbuffered 01 00 22 23 SDRAM Device Attributes :General SDRAM Cycle Time at CL = 2 Vcc tol +/- 10% 7.5 / 10 ns 75 A0 24 25 SDRAM Access Time from Clock at CL=2 SDRAM Cycle Time at CL = 1 5.4 / 6.0 ns not supported 54 00 60 FF 26 27 SDRAM Access Time from Clock at CL=1 Minimum Row Precharge Time not supported 20 ns 00 0F FF 14 28 29 Minimum Row Active to Row Active delay Minimum RAS to CAS delay 15 / 16 ns 20 ns 0E 0F 0F 30 31 Minimum Ras pulse width Module Bank Density (per bank) 42 / 45 / 60 ns 128MB 2A 2D 20 32 32 33 SDRAM input setup time SDRAM input hold time 1.5 / 2 ns 0.8 / 1 ns 15 08 15 08 20 10 34 35 SDRAM data input setup time SDRAM data input hold time 1.5 / 2 ns 0.8 / 1 ns 15 08 15 08 20 10 36-61 62 Superset information SPD Revision 0E 00 Revision 1.2 63 Checksum for bytes 0 - 62 64-125 Manufactures’s information FF 12 F4 39 126 127 Frequency Specification Details 64 87 128+ Unused storage locations FF INFINEON Technologies 11 10 14 9C 9.01 HYS64V16200GDL/HYS64V32220GDL 144 pin SO-DIMM SDRAM Modules SPD-Table HYS64V32220GDL: Byte# Description SPD Entry Value Hex 32Mx64 32Mx64 32Mx64 -7 -7.5 -8 128 80 256 SDRAM 08 04 0 Number of SPD bytes 1 2 Total bytes in Serial PD Memory Type 3 4 Number of Row Addresses Number of Column Addresses 13 9 0D 09 5 6 Number of DIMM Banks Module Data Width 2 64 02 40 7 8 Module Data Width (cont’d) Module Interface Levels 0 LVTTL 00 01 9 SDRAM Cycle Time at CL=3 10 SDRAM Access time from Clock at CL=3 11 Dimm Config (Error Det/Corr.) 12 13 Refresh Rate/Type SDRAM width, Primary 14 15 Error Checking SDRAM data width Minimum clock delay for back-to-back random column address 16 17 7.5 / 10.0 ns 75 75 5.4 / 6.0 ns 54 54 A0 60 none 00 Self-Refresh, 7.8 µs x16 82 10 n/a tccd = 1 CLK 00 01 Burst Length supported Number of SDRAM banks 1, 2, 4 & 8 2 0F 04 18 19 Supported CAS Latencies CS Latencies 2, & 3 CS latency = 0 06 01 20 21 WE Latencies SDRAM DIMM module attributes Write latency = 0 unbuffered 01 00 22 23 SDRAM Device Attributes :General SDRAM Cycle Time at CL = 2 Vcc tol +/- 10% 7.5 / 10 ns 75 A0 24 25 SDRAM Access Time from Clock at CL=2 SDRAM Cycle Time at CL = 1 5.4 / 6.0 ns not supported 54 00 60 FF 26 27 SDRAM Access Time from Clock at CL=1 Minimum Row Precharge Time not supported 20 ns 00 0F FF 14 28 29 Minimum Row Active to Row Active delay Minimum RAS to CAS delay 15 / 16 ns 20 ns 0E 0F 0F 30 31 Minimum Ras pulse width Module Bank Density (per bank) 42 / 45 / 60 ns 128MB 2A 2D 20 32 32 33 SDRAM input setup time SDRAM input hold time 1.5 / 2 ns 0.8 / 1 ns 15 08 15 08 20 10 34 35 SDRAM data input setup time SDRAM data input hold time 1.5 / 2 ns 0.8 / 1 ns 15 08 15 08 20 10 36-61 62 Superset information SPD Revision 0E 00 Revision 1.2 63 Checksum for bytes 0 - 62 64-125 Manufactures’s information FF 12 F5 1E 126 127 Frequency Specification Details 64 C7 128+ Unused storage locations FF INFINEON Technologies 12 10 14 81 9.01 HYS64V16200GDL/HYS64V32220GDL 144 pin SO-DIMM SDRAM Modules Package Outlines 128 MByte SO-DIMM Module package (JEDEC MO-190) (144 pin, dual read-out, single in-line memory module) 67,6 ± 0.15 3.8 max. 25.4 ± 0.13 63,6 3.3 1 23.2 59 61 32.8 143 1 ± 0.1 2.6 4.6 2 1.5 1.8 60 62 144 20 6 4 3.7 4 Detail of Contacts 0.6 0.2 -0.15 0.25 2.55 Detail of Chamfer 0.2 -0.15 0.8 L-DIM-144-10 note: all tolerances are in accordance with the JEDEC standard INFINEON Technologies 13 9.01 HYS64V16200GDL/HYS64V32220GDL 144 pin SO-DIMM SDRAM Modules 256 MByte SO-DIMM Module package (JEDEC MO-190) (144 pin, dual read-out, single in-line memory module) 67.6 ± 0.15 3.8 max. 31.75 ± 0.13 63.6 3.3 1 23.2 59 61 32.8 143 1± 0.1 2.5 24.5 4.6 2 1.5 1.8 60 62 144 20 6 4 3.7 4 0.25 0.2 -0.15 Detail of Chamfer 2.55 Detail of Contacts 0.6 0.2 -0.15 0.8 L-DIM-144-9 note: all tolerances are in accordance with the JEDEC standard INFINEON Technologies 14 9.01 HYS64V16200GDL/HYS64V32220GDL 144 pin SO-DIMM SDRAM Modules Change List 6.99 19.1.2000 19.7.2000 24.7.2000 25.7.2000 5.9.2000 24.11.2000 15.12.2000 5.3.2001 9.07.2001 6.09.2001 INFINEON Technologies First and preliminary version, -8A only -7.5 and -8 speed sorts added CKE1 added to the block diagram GDL versions added for 256Mbit S17-C2 with 1.5mA ICC6 per component -8A speed sort removed backward compatibility for “C2” base modules clarifed ICC6 changed from 6mA to 6.8 mA per memory bank after the component datasheet for 256M S17 changed from 1.5 to 1.7 mA ICC2PS changed from 16 to 8 mA ICC6 changed from 6.8 to 7.2 mA (Request from Axel Hahn and Uwe Fritsch) Component datasheet unchanged at ICC6=1.7mA Preliminary Capacitance Values added All reference to older versions based on 256M S20 removed ICC currents, where wrong and have been corrected according to the latest 256M S17 datasheet HYS64V16200GL-7/-7.5 and -8 added HYS64V1632220GDL-7 added SCR : Absolute Maximum Ratings Table added 15 9.01 HYS64V16200GDL/HYS64V32220GDL 144 pin SO-DIMM SDRAM Modules INFINEON Technologies 16 9.01