CY62177DV30 MoBL® 32-Mbit (2M x 16) Static RAM Features reduces power consumption. The device can also be put into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE1HIGH or CE2 LOW), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE1 LOW, CE2 HIGH and WE LOW). • Very high speed: 55 ns and 70 ns • Wide voltage range: 2.20V–3.60V • Ultra-low active power — Typical active current: 2 mA @ f = 1 MHz — Typical active current: 15 mA @ f = fmax Writing to the device is accomplished by taking Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A20). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A20). • Ultra low standby power • Easy memory expansion with CE1, CE2 and OE features • Automatic power-down when deselected • CMOS for optimum speed/power • Packages offered in a 48-ball FBGA Reading from the device is accomplished by taking Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table for a complete description of read and write modes. Functional Description[1] The CY62177DV30 is a high-performance CMOS static RAM organized as 2M words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones.The device also has an automatic power-down feature that significantly Logic Block Diagram 2048K × 16 RAM Array SENSE AMPS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA-IN DRIVERS I/O0–I/O7 I/O8–I/O15 COLUMN DECODER A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 BHE WE OE CE2 CE1 BLE Power-down Circuit Note: 1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05633 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 14, 2006 [+] Feedback CY62177DV30 MoBL® Pin Configuration[2] FBGA Top View 1 2 3 4 5 6 BLE OE A0 A1 A2 CE2 A I/O8 BHE A3 A4 CE1 I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 I/O3 Vcc D VCC I/O12 DNU A16 I/O4 Vss E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 A19 A12 A13 WE I/O7 G A18 A8 A9 A10 A11 A20 H Product Portfolio Power Dissipation Operating ICC(mA) VCC Range (V) Product CY62177DV30L Min. Typ.[3] 2.20 3.0 f = 1 MHz Max. Speed (ns) Typ.[3] 3.60 55 2 Max. Max. Typ.[3] Max. 4 15 30 5 60 12 25 15 30 5 50 12 25 70 CY62177DV30LL 55 70 2 Standby ISB2(µA) f = fmax Typ.[3] 4 Notes: 2. DNU pins have to be left floating or tied to Vss to ensure proper application. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C. Document #: 38-05633 Rev. *C Page 2 of 11 [+] Feedback CY62177DV30 MoBL® Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................ –65°C to + 150°C Ambient Temperature with Power Applied............................................ –55°C to + 125°C Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .....................................................>200 mA Operating Range Supply Voltage to Ground Potential .......–0.3V to VCC + 0.3V DC Voltage Applied to Outputs in High Z State[4, 5] .................................–0.3V to VCC + 0.3V DC Input Voltage[4, 5] .............................–0.3V to VCC + 0.3V Device Range CY62177DV30L Ambient Temperature Industrial –40°C to +85°C CY62177DV30LL VCC[6] 2.20V to 3.60V Electrical Characteristics Over the Operating Range CY62177DV30-55 Parameter Description Test Conditions Min. Typ.[3] Max. CY62177DV30-70 Min. Typ.[3] Max. Unit VOH Output HIGH Voltage VOL Output LOW Voltage VIH Input HIGH Voltage VCC = 2.2V to 2.7V 1.8 VCC +0.3V 1.8 VCC= 2.7V to 3.6V 2.2 VCC +0.3V 2.2 VCC +0.3V V VIL Input LOW Voltage VCC = 2.2V to 2.7V VCC= 2.7V to 3.6V –0.3 0.6 –0.3 0.6 V -0.3 0.8 -0.3 0.8 V IIX Input Leakage Current GND < VI < VCC –1 +1 –1 +1 µA IOZ Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 –1 +1 µA ICC VCC Operating Supply Current f = fMAX = 1/tRC Automatic CE Power-Down Current—CMOS Inputs CE1 > VCC−0.2V, CE2 < 0.2V, L VIN > VCC–0.2V, VIN < 0.2V) LL f = fMAX (Address and Data Only), f = 0 (OE, WE, BHE and BLE), VCC=3.60V Automatic CE Power-Down Current—CMOS Inputs CE1 > VCC − 0.2V, CE2 < 0.2V, L VIN > VCC – 0.2V or VIN < 0.2V, LL f = 0, VCC = 3.60V ISB1 ISB2 IOH = –0.1 mA VCC = 2.20V 2.0 IOH = –1.0 mA VCC = 2.70V 2.4 IOL = 0.1 mA VCC = 2.20V IOL = 2.1mA VCC = 2.70V f = 1 MHz VCC = VCCmax IOUT = 0 mA CMOS levels 2.0 V 2.4 V 0.4 0.4 0.4 V 0.4 V VCC +0.3V V 15 30 12 25 mA 2 4 2 4 mA µA 5 100 5 100 5 100 5 100 5 60 5 60 5 50 5 50 µA Notes: 4. VIL(min.) = –2.0V for pulse durations less than 20 ns. 5. VIH(Max) = VCC + 0.75V for pulse durations less than 20 ns. 6. Full Device AC operation requires linear VCC ramp from 0 to VCC(min) > 500 µs. Document #: 38-05633 Rev. *C Page 3 of 11 [+] Feedback CY62177DV30 MoBL® Capacitance[7, 8] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. TA = 25°C, f = 1 MHz, VCC = VCC(typ) Unit 12 pF 12 pF Thermal Resistance[7] Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions BGA Unit 55 °C/W 16 °C/W Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board AC Test Loads and Waveforms R1 VCC OUTPUT VCC 10% GND Rise Time = 1 V/ns R2 50 pF INCLUDING JIG AND SCOPE ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT V Parameters 2.5V (2.2V to 2.7V) 3.0V (2.7V to 3.6V) Unit R1 16667 1103 Ω R2 15385 1554 Ω RTH 8000 645 Ω VTH 1.20 1.75 V Data Retention Characteristics (Over the Operating Range) Parameter Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR[7] Chip Deselect to Data Retention Time tR[9] Operation Recovery Time Conditions Min. Typ.[3] Max. Unit L 30 µA LL 25 1.5 VCC= 1.5V CE1 > VCC−0.2V, CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V V 0 ns tRC ns Notes: 7. Tested initially and after any design or process changes that may affect these parameters. 8. This applies for all packages. 9. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs. Document #: 38-05633 Rev. *C Page 4 of 11 [+] Feedback CY62177DV30 MoBL® Data Retention Waveform[10, 11] VCC, min. tCDR VCC DATA RETENTION MODE VDR > 1.5V VCC, min. tR CE or BHE.BLE Switching Characteristics Over the Operating Range[11, 12] 55 ns Parameter Description Min. 70 ns Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 55 70 ns tDOE OE LOW to Data Valid 25 35 ns tLZOE tHZOE 55 55 OE LOW to LOW Z[13] OE HIGH to High Z[13, 14] Z[13] CE LOW to Low tHZCE CE HIGH to High Z[13, 14] tPU CE LOW HIGH to Power-Up tPD CE HIGH to Power-Down tDBE BLE/BHE LOW to Data Valid tLZBE BLE/BHE LOW to Low Z[13] WRITE BLE/BHE HIGH to HIGH 10 70 10 ns 25 10 20 0 0 55 10 ns ns 70 ns 70 ns 5 20 ns ns 25 55 ns ns 5 20 Z[13, 14] ns 10 5 tLZCE tHZBE 70 ns 25 ns CYCLE[15] tWC Write Cycle Time 55 70 ns tSCE CE LOW to Write End 40 60 ns tAW Address Set-Up to Write End 40 60 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns tPWE WE Pulse Width 40 45 ns tBW BLE/BHE LOW to Write End 40 60 ns tSD Data Set-Up to Write End 25 30 ns tHD Data Hold from Write End 0 tHZWE WE LOW to High-Z[13, 14] tLZWE WE HIGH to Low-Z[13] 0 20 10 ns 25 10 ns ns Notes: 10. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE. 11. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section. 13. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 15. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 38-05633 Rev. *C Page 5 of 11 [+] Feedback CY62177DV30 MoBL® Switching Waveforms Read Cycle 1 (Address Transition Controlled)[16, 17] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Read Cycle 2 (OE Controlled)[11, 17, 18] ADDRESS tRC CE tPD tHZCE tACE BHE/BLE tLZBE tDBE tHZBE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPU 50% 50% ICC ISB Notes: 16. The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL. 17. WE is HIGH for read cycle. 18. Address valid prior to or coincident with CE, BHE, BLE transition LOW. Document #: 38-05633 Rev. *C Page 6 of 11 [+] Feedback CY62177DV30 MoBL® Switching Waveforms (continued) Write Cycle 1 (WE Controlled)[11, 15, 19, 20, 21] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD VALID DATA See Note 21 tHZOE Write Cycle 2 (CE Controlled)[11, 15, 19, 20, 21] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD VALID DATA See Note 21 t HZOE Notes: 19. Data I/O is high impedance if OE = VIH. 20. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high-impedance state. 21. During this period, the I/Os are in output state and input signals should not be applied. Document #: 38-05633 Rev. *C Page 7 of 11 [+] Feedback CY62177DV30 MoBL® Switching Waveforms (continued) Write Cycle 3 (WE Controlled, OE LOW)[11, 20, 21] tWC ADDRESS tSCE CE tBW BHE/BLE tAW tHA tSA tPWE WE tHD tSD DATA I/O See Note 21 VALID DATA tLZWE tHZWE Write Cycle 4 (BHE/BLE Controlled, OE LOW)[11, 20, 21] tWC ADDRESS CE tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tSD DATA I/O See Note 21 Document #: 38-05633 Rev. *C tHD VALID DATA Page 8 of 11 [+] Feedback CY62177DV30 MoBL® Truth Table CE1 CE2 WE OE BHE BLE H X X X X X X L X X X X X X X H L H H L L L L H H L H L H H L L H H L H L Inputs/Outputs Mode Power High Z Deselect/Power-Down Standby (ISB) X High Z Deselect/Power-Down Standby (ISB) H High Z Deselect/Power-Down Standby (ISB) Data Out (I/O0–I/O15) Read Active (ICC) L Data Out (I/O0–I/O7); High Z (I/O8–I/O15) Read Active (ICC) L H High Z (I/O0–I/O7); Data Out (I/O8–I/O15) Read Active (ICC) H L H High Z Output Disabled Active (ICC) H H H L High Z Output Disabled Active (ICC) H H H L L High Z Output Disabled Active (ICC) L H L X L L Data In (I/O0–I/O15) Write Active (ICC) L H L X H L Data In (I/O0–I/O7); High Z (I/O8–I/O15) Write Active (ICC) L H L X L H High Z (I/O0–I/O7); Data In (I/O8–I/O15) Write Active (ICC) Ordering Information Speed (ns) 55 Ordering Code CY62177DV30L-55BAI Package Diagram Package Type 51-85191 48-ball FBGA (8 mm × 9.5mm × 1.2 mm) Operating Range Industrial CY62177DV30LL-55BAI CY62177DV30LL-55BAXI 70 CY62177DV30L-70BAI Document #: 38-05633 Rev. *C 48-ball FBGA (8 mm × 9.5mm × 1.2 mm) (Pb-free) 51-85191 48-ball FBGA (8 mm × 9.5mm × 1.2 mm) Industrial Page 9 of 11 [+] Feedback CY62177DV30 MoBL® Package Diagram 48 FBGA (8 x 9.5 x 1.2 MM) (51-85191) BOTTOM VIEW A1 CORNER TOP VIEW Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 2 3 4 5 6 6 5 4 3 2 1 C C E F D E 2.625 D 0.75 A B 5.25 A B 9.50±0.10 9.50±0.10 1 G F G H H A 1.875 A B 0.75 8.00±0.10 B 8.00±0.10 0.15(4X) 0.15 C 0.21±0.05 0.65 MAX. 0.25 C 3.75 51-85191-** 1.20 MAX 0.26 MAX. SEATING PLANE C DESIGNED BY UNLESS OTHERWISE SPECIFIED DATE ALL DIMENSIONS ARE IN MILLIMETERS STANDARD TOLERANCES ON: DECIMALS .XX -+ .XXX .XXXX -+ + - DRAWN ANGLES + - DATE HTN CHK BY DATE APPROVED BY DATE APPROVED BY DATE TITLE MATERIAL FINISH AINS INFORMATION WHICH IS THE PROPRIETARY PROPERTY OF CYPRESS COMPANY. THIS DRAWING IS ENCE AND ITS CONTENTS MAY NOT BE DISCLOSED WITHOUT WRITTEN CONSENT OF CYPRESS COMPANY. CYPRESS Company Confidential 06/25/03 SIZE A SCALE 48 FBGA (8x9.5x1.2MM) PACKAGE OUTLINE PART NO. BA48J 1: 1 DWG NO 51-85191 SHEET MoBL is a registered trademark and More Battery Life is a trademarks of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders Document #: 38-05633 Rev. *C Page 10 of 11 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY62177DV30 MoBL® Document History Page Document Title:CY62177DV30 MoBL® 32-Mbit (2M x 16) Static RAM Document #: 38-05633 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 251075 See ECN AJU New Data Sheet *A 330363 See ECN AJU Changed title of data sheet from CYM62177DV30 to CY62177DV30 Added second chip enable (CE2) Added footnote #12 on page 5 *B 400960 See ECN NXR Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed ISB1 from 60 and 40 µA to 100 µA for the L and LL versions for both the 55 and the 70 ns speed bins respectively. *C 469187 See ECN NXR Converted from Preliminary to Final Changed the ISB2(Max) from 40 µA to 50 µA for LL version of both 45 ns and 55 ns speed bins Changed the ICCDR(Max) from 20 µA to 25 µA for LL version Updated the Ordeing Information table Document #: 38-05633 Rev. *C Page 11 of 11 [+] Feedback