ISSI IS24C256A 128k-bit/ 256k-bit 2-wire serial cmos eeprom Datasheet

ISSI
IS24C128A
IS24C256A
128K-bit/ 256K-bit
2-WIRE SERIAL CMOS EEPROM
FEATURES
• Two-Wire Serial Interface, I2CTM compatible
–Bi-directional data transfer protocol
• Wide Voltage Operation
–Vcc = 1.8V to 5.5V
• 400 KHz (2.5V) and 1 MHz (5.0V) compatibility
• Low Power CMOS Technology
–Active Current less than 3 mA (2.5V)
–Standby Current less than 20 µA (2.5V)
• Hardware Data Protection
–Write Protect Pin
• Sequential Read Feature
• Filtered Inputs for Noise Suppression
• Self time write cycle with auto clear
–5 ms @ 2.5V
• Organization:
–16Kx8 (256 pages of 64 bytes)
–32Kx8 (512 pages of 64 bytes)
• 64 Byte Page Write Buffer
• High Reliability
–Endurance: 1,000,000 Cycles
–Data Retention: 40 Years
• Industrial and Automotive temperature ranges
• 8-pin PDIP, 8-pin (JEDEC) SOIC, and 8-pin
(EIAJ) SOIC packages
• Lead-free available
®
ADVANCED INFORMATION
JULY 2006
DESCRIPTION
The IS24C128A/256A is an electrically erasable PROM
device that uses the standard 2-wire interface for
communications. The IS24C128A is 128K-bit (16Kx8)
and the IS24C256A is 256K-bit (32Kx8). These
EEPROM are offered in a wide operating voltage range
of 1.8V to 5.5V to be compatible with most application
voltages. ISSI designed the IS24C128A/256A to be an
efficient 2-wire EEPROM solution. The devices are
packaged in 8-pin PDIP, 8-pin (JEDEC) SOIC, and 8pin (EIAJ) SOIC.
The IS24C128A/256A maintains compatibility with the
popular 2-wire bus protocol, so it is easy to design into
applications implementing this bus type. The simple
bus consists of the Serial Clock wire (SCL) and the
Serial Data wire (SDA). Using the bus, a Master device
such as a microcontroller is usually connected to one
or more Slave devices such as the IS24C128A/256A.
The bit stream over the SDA line includes a series of
bytes, which identifies a particular Slave device, an
instruction, an address within that Slave device, and a
series of data, if appropriate. The IS24C128A/256A has
a Write Protect pin (WP) to allow blocking of any write
instruction transmitted over the bus.
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCED INFORMATION Rev. 00B
06/27/06
1
IS24C128A
IS24C256A
ISSI
®
FUNCTIONAL BLOCK DIAGRAM
HIGH VOLTAGE
GENERATOR,
TIMING & CONTROL
Vcc
SCL
CONTROL
LOGIC
WP
SLAVE ADDRESS
REGISTER &
COMPARATOR
A0
X
DECODER
SDA
EEPROM
ARRAY
WORD ADDRESS
COUNTER
A1
Y
DECODER
A2
ACK
GND
nMOS
2
Clock
DI/O
>
DATA
REGISTER
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCED INFORMATION Rev. 00B
06/27/06
IS24C128A
IS24C256A
ISSI
®
PIN CONFIGURATION
8-Pin DIP and SOIC
A0
1
8
VCC
A1
2
7
WP
A2
3
6
SCL
GND
4
5
SDA
PIN DESCRIPTIONS
A0-A2
SDA
SCL
WP
Vcc
NC
GND
Address Inputs
Serial Address/Data I/O
Serial Clock Input
Write Protect Input
Power Supply
No Connect
Ground
SCL
A0, A1, A2
This input clock pin is used to synchronize the data transfer
to and from the device.
The A0, A1, and A2 are the device address inputs that are
hardwired or left not connected for hardware compatibility
with the IS24C32A/64A. When pins are hardwired, as many
as eight 256K devices may be addressed on a single bus
system. When the pins are not hardwired, the default values
of A0, A1, and A2 are zero.
SDA
The SDA is a Bi-directional pin used to transfer addresses
and data into and out of the device. The SDA pin is an open
drain output and can be wire Or'ed with other open drain or
open collector outputs. The SDA bus requires a pullup
resistor to Vcc.
WP
WP is the Write Protect pin. If the WP pin is tied to Vcc
the entire array becomes Write Protected (Read only).
When WP is tied to GND or left floating, normal read/write
operations are allowed to the device.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCED INFORMATION Rev. 00B
06/27/06
3
IS24C128A
IS24C256A
ISSI
DEVICE OPERATION
The IS24C128A/256A features a serial communication and
supports a bi-directional 2-wire bus transmission protocol
called I2CTM.
2-WIRE BUS
The two-wire bus is defined as a Serial Data line (SDA), and
a Serial Clock line (SCL). The protocol defines any device
that sends data onto the SDA bus as a transmitter, and the
receiving devices as receivers. The bus is controlled by
Master device which generates the SCL, controls the bus
access and generates the Stop and Start conditions. The
IS24C128A/256A is the Slave device on the bus.
The Bus Protocol:
– Data transfer may be initiated only when the bus is not
busy
– During a data transfer, the SDA line must remain stable
whenever the SCL line is high. Any changes in the data
line while the SCL line is high will be interpreted as a
Start or Stop condition.
The state of the SDA line represents valid data after a Start
condition. The SDA line must be stable for the duration of
the High period of the clock signal. The data on the SDA
line may be changed during the Low period of the clock
signal. There is one clock pulse per bit of data. Each data
transfer is initiated with a Start condition and terminated
with a Stop condition.
Start Condition
The Start condition precedes all commands to the device
and is defined as a High to Low transition of SDA when
SCL is High. The IS24C128A/256A monitors the SDA and
SCL lines and will not respond until the Start condition is
met.
Stop Condition
The Stop condition is defined as a Low to High transition of
SDA when SCL is High. All operations must end with a Stop
condition.
Acknowledge (ACK)
After a successful data transfer, each receiving device is
required to generate an ACK. The Acknowledging device
pulls down the SDA line.
Reset
The IS24C128A/256A contains a reset function in case
the 2-wire bus transmission is accidentally interrupted
(eg. a power loss), or needs to be terminated mid-stream.
The reset is caused when the Master device creates a
Start condition. To do this, it may be necessary for the
Master device to monitor the SDA line while cycling the
4
®
SCL up to nine times. (For each clock signal transition to
High, the Master checks for a High level on SDA.)
Standby Mode
Power consumption is reduced in standby mode. The
IS24C128A/256A will enter standby mode: a) At Power-up,
and remain in it until SCL or SDA toggles; b) Following the
Stop signal if no write operation is initiated; or c) Following
any internal write operation
DEVICE ADDRESSING
The Master begins a transmission by sending a Start
condition. The Master then sends the address of the
particular Slave devices it is requesting. The Slave device
(Fig. 5) address is 8 bits.
The four most significant bits of the Slave device address
are fixed as 1010 for the IS24C128A/256A.
This device has three address bits (A2, A1, and A0),
which allows up to eight IS24C128A/256A devices to
share the 2-wire bus. Upon receiving the Slave address,
the device compares the three address bits with the
hardwired A2, A1, and A0 input pins to determine if it is
the appropriate Slave.
The last bit of the Slave address specifies whether a Read
or Write operation is to be performed. When this bit is set
to 1, a Read operation is selected, and when set to 0, a
Write operation is selected.
After the Master transmits the Start condition and Slave
address byte (Fig. 5), the appropriate 2-wire Slave (eg.
IS24C128A/256A) will respond with ACK on the SDA
line. The Slave will pull down the SDA on the ninth clock
cycle, signaling that it received the eight bits of data.
The selected IS24C128A/256A then prepares for a Read
or Write operation by monitoring the bus.
WRITE OPERATION
Byte Write
In the Byte Write mode, the Master device sends the Start
condition and the Slave address information (with the R/W
set to Zero) to the Slave device. After the Slave generates
an ACK, the Master sends the two byte address that are to
be written into the address pointer of the IS24C128A/
256A. After receiving another ACK from the Slave, the
Master device transmits the data byte to be written into the
address memory location. The IS24C128A/256A
acknowledges once more and the Master generates the
Stop condition, at which time the device begins its internal
programming cycle. While this internal cycle is in progress,
the device will not respond to any request from the Master
device.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCED INFORMATION Rev. 00B
06/27/06
IS24C128A
IS24C256A
Page Write
The IS24C128A/256A is capable of 64-byte Page-Write
operation. A Page-Write is initiated in the same manner as a
Byte Write, but instead of terminating the internal Write cycle
after the first data word is transferred, the Master device can
transmit up to 63 more bytes. After the receipt of each data
word, the IS24C128A/256A responds immediately with an
ACK on SDA line, and the six lower order data word address
bits are internally incremented by one, while the higher order
bits of the data word address remain constant. If a byte
address is incremented from the last byte of a page, it
returns to the first byte of that page. If the Master device
should transmit more than 64 words prior to issuing the Stop
condition, the address counter will “roll over,” and the previously
written data will be overwritten. Once all 64 bytes are
received and the Stop condition has been sent by the Master,
the internal programming cycle begins. At this point, all
received data is written to the IS24C128A/256A in a single
Write cycle. All inputs are disabled until completion of the
internal Write cycle.
Acknowledge (ACK) Polling
The disabling of the inputs can be used to take advantage
of the typical Write cycle time. Once the Stop condition
is issued to indicate the end of the host's Write operation,
the IS24C128A/256A initiates the internal Write cycle. ACK
polling can be initiated immediately. This involves issuing
the Start condition followed by the Slave address for a
Write operation. If the IS24C128A/256A is still busy with the
Write operation, no ACK will be returned. If the IS24C128A/
256A has completed the Write operation, an ACK will be
returned and the host can then proceed with the next Read
or Write operation.
READ OPERATION
Read operations are initiated in the same manner as Write
operations, except that the (R/W) bit of the Slave address
is set to “1”. There are three Read operation options:
current address read, random address read, and sequential
read.
ISSI
®
should generate a Stop condition so the IS24C128A/256A
discontinues transmission. If 'n' is the last byte of the
memory, the data from location '0' will be transmitted. (Refer
to Figure 8. Current Address Read Diagram.)
Random Address Read
Selective Read operations allow the Master device to select
at random any memory location for a Read operation. The
Master device first performs a 'dummy' Write operation by
sending the Start condition, Slave address and word address
of the location it wishes to read. After the IS24C128A/256A
acknowledges the word address, the Master device resends
the Start condition and the Slave address, this time with the
R/W bit set to one. The IS24C128A/256A then responds
with its ACK and sends the data requested. The Master
device does not send an ACK but will generate a Stop
condition. (Refer to Figure 9. Random Address Read
Diagram.)
Sequential Read
Sequential Reads can be initiated as either a Current
Address Read or Random Address Read. After the
IS24C128A/256A sends the initial byte sequence, the
Master device now responds with an ACK indicating it
requires additional data from the IS24C128A/256A. The
IS24C128A/256A continues to output data for each ACK
received. The Master device terminates the sequential
Read operation by pulling SDA High (no ACK) indicating the
last data word to be read, followed by a Stop condition.
The data output is sequential, with the data from address n
followed by the data from address n+1, ... etc. The address
counter increments by one automatically, allowing the
entire memory contents to be serially read during sequential
Read operation. When the memory address boundary of
16383 or 32767 (depending on the device) is reached, the
address counter “rolls over” to address 0, and the IS24C128A/
256A continues to output data for each ACK received.
(Refer to Figure 10. Sequential Read Operation Starting with
a Random Address Read Diagram.)
Current Address Read
The IS24C128A/256A contains an internal address counter
which maintains the address of the last byte accessed,
incremented by one. For example, if the previous operation
is either a Read or Write operation addressed to the
address location n, the internal address counter would
increment to address location n+1. When the IS24C128A/
256A receives the Slave Device Addressing Byte with a
Read operation (R/W bit set to “1”), it will respond an ACK
and transmit the 8-bit data word stored at address location
n+1. The Master should not acknowledge the transfer but
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCED INFORMATION Rev. 00B
06/27/06
5
IS24C128A
IS24C256A
ISSI
®
Figure 1. Typical System Bus Configuration
Vcc
SDA
SCL
Master
Transmitter/
Receiver
IS24C128A/256A
Figure 2. Output Acknowledge
SCL from
Master
1
8
9
Data Output
from
Transmitter
tAA
Data Output
from
Receiver
tAA
ACK
STOP
Condition
SCL
START
Condition
Figure 3. Start and Stop Conditions
SDA
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCED INFORMATION Rev. 00B
06/27/06
IS24C128A
IS24C256A
ISSI
®
Figure 4. Data Validity Protocol
Data Change
SCL
Data Stable
Data Stable
SDA
Figure 5. Slave Address
BIT
7
6
5
4
3
2
1
0
1
0
1
0
A2
A1
A0
R/W
Figure 6. Byte Write
SDA
Bus
Activity
S
T
A
R
T
Device
Address
M
S
B
W
R
I
T
E
S
T
O
P
Data
Word Address
Word Address
A
A
A
C * t
C
C
K
K
K
L
M
S
* = Don't care bit
S
B
B
= Don't care bit for IS24C128A
R/W
A
C
K
t
Figure 7. Page Write
SDA
Bus
Activity
S
T
A
R
T
Device
Address
M
S
B
W
R
I
T
E
Word Address (n) Word Address (n)
A
A
A
C
C * t
C
K
K
K
L
S
B
R/W
Data (n)
Data (n+63)
A
C
K
A
C
K
* = Don't care bit
t = Don't care bit for IS24C128A
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ADVANCED INFORMATION Rev. 00B
06/27/06
Data (n+1)
A
C
K
S
T
O
P
7
IS24C128A
IS24C256A
ISSI
®
Figure 8. Current Address Read
S
T
A
R
T
R
E
A
D
Device
Address
SDA
Bus
Activity
S
T
O
P
Data
A
C
K
M
S
B
L
S
B
N
O
A
C
K
R/W
Figure 9. Random Address Read
S
T
A
R
T
Device
Address
W
R
I
T
E
SDA
Bus
Activity
Word
Address (n)
A
C *
K
M
S
B
Word
Address (n)
A
C
K
t
S
T
A
R
T
Device
Address
R
E
A
D
Data n
A
C
K
A
C
K
L
S
B
R/W
S
T
O
P
N
O
* = Don't care bit
t = Don't care bit for IS24C128A
DUMMY WRITE
A
C
K
Figure 10. Sequential Read
Device
Address
SDA
Bus
Activity
R
E
A
D
Data Byte n
A
C
K
Data Byte n+1
A
C
K
Data Byte n+2
A
C
K
S
T
O
P
Data Byte n+X
A
C
K
N
O
R/W
8
A
C
K
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCED INFORMATION Rev. 00B
06/27/06
IS24C128A
IS24C256A
ISSI
®
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VS
VP
TBIAS
TSTG
IOUT
Parameter
Supply Voltage
Voltage on Any Pin
Temperature Under Bias
Storage Temperature
Output Current
Value
–0.5 to +6.5
–0.5 to Vcc +0.5
–55 to +125
–65 to +150
5
Unit
V
V
°C
°C
mA
Notes:
1. Stresses violating the conditions listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only. Functional operation of the
device outside these conditions or those indicated in the operational sections of this
specification is not implied. Exposure to these conditions for extended periods may affect
reliability.
OPERATING RANGE (IS24C128A/256A-2)
Range
Industrial
Ambient Temperature
–40°C to +85°C
VCC
1.8V to 5.5V
Note: ISSI offers Industrial grade for Commercial application (0oC to +70oC).
OPERATING RANGE (IS24C128A/256A-3)
Range
Automotive
Ambient Temperature
–40°C to +125°C
VCC
2.5V to 5.5V
CAPACITANCE(1,2)
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Conditions
VIN = 0V
VOUT = 0V
Max.
6
8
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCED INFORMATION Rev. 00B
06/27/06
9
IS24C128A
IS24C256A
ISSI
®
DC ELECTRICAL CHARACTERISTICS
Industrial (TA = -40oC to +85oC), Automotive (TA = -40oC to +125oC)
Symbol
VOL1
VOL2
VIH
V IL
I LI
ILO
Parameter
Output Low Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
Test Conditions
VCC = 1.8V, IOL = 0.15 mA
VCC = 2.5V, IOL = 2.1 mA
Min.
Max.
—
0.2
—
0.4
VCC X 0.7 VCC + 0.5
–1.0
VCC X 0.3
—
3
—
3
VIN = VCC max.
Unit
V
V
V
V
µA
µA
Notes: VIL min and VIH max are reference only and are not tested.
POWER SUPPLY CHARACTERISTICS
Industrial (TA = -40oC to +85oC), Automotive (TA = -40oC to +125oC)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
ICC1
Vcc Operating Current
Read at 400 KHz (Vcc = 2.5V)
—
3.0
mA
ICC2
ISB1
Vcc Operating Current
Write at 400 KHz (Vcc = 2.5V)
—
3.0
mA
Standby Current
Vcc = 1.8V
—
15
µA
ISB2
Standby Current
Vcc = 2.5V
—
20
µA
ISB3
Standby Current
Vcc = 5.0V
—
25
µA
AC ELECTRICAL CHARACTERISTICS
Industrial (TA = -40oC to +85oC)
1.8V ≤ Vcc < 2.5V
Symbol
fSCL
T
tLow
tHigh
tBUF
tSU:STA
tSU:STO
tHD:STA
tHD:STO
tSU:DAT
tHD:DAT
tSU:WP
tHD:WP
tDH
tAA
tR
tF
tWR
Parameter
SCL Clock Frequency
Noise Suppression Time(1)
Clock Low Period
Clock High Period
Bus Free Time Before New Transmission(1)
Start Condition Setup Time
Stop Condition Setup Time
Start Condition Hold Time
Stop Condition Hold Time
Data In Setup Time
Data In Hold Time
WP pin Setup Time
WP pin Hold Time
Data Out Hold Time
(SCL Low to SDA Data Out Change)
Clock to Output (SCL Low to SDA Data Out Valid)
SCL and SDA Rise Time(1)
SCL and SDA Fall Time(1)
Write Cycle Time
Min.
0
—
4.7
4
4.7
4
4
4
4
100
0
4
4.7
100
Max.
100
100
—
—
—
—
—
—
—
—
—
—
—
—
100
—
—
—
3500
1000
300
10
2.5V ≤ Vcc < 4.5V
Min. Max.
0
400
—
50
1.2 —
0.6 —
1.2 —
0.6 —
0.6 —
0.6 —
0.6 —
100 —
0
—
0.6 —
1.2 —
50
—
50
—
—
—
900
300
300
5
4.5V ≤ Vcc ≤ 5.5V(1)
Min.
0
—
0.6
0.4
0.5
0.25
0.25
0.25
0.25
100
0
0.6
1.2
50
Max.
1000
50
—
—
—
—
—
—
—
—
—
—
—
—
Unit
KHz
ns
µs
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
ns
50
—
—
—
400
300
100
5
ns
ns
ns
ms
Notes:
1. This parameter is characterized but not 100% tested.
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCED INFORMATION Rev. 00B
06/27/06
IS24C128A
IS24C256A
ISSI
®
AC ELECTRICAL CHARACTERISTICS
Automotive (TA = -40oC to +125oC)
2.5V ≤ Vcc < 4.5V
Symbol
Parameter
fSCL
SCL Clock Frequency
T
Noise Suppression Time(1)
tLow
Clock Low Period
tHigh
Clock High Period
tBUF
Bus Free Time Before New Transmission(1)
tSU:STA
tSU:STO
4.5V ≤ Vcc ≤ 5.5V(1)
Min.
Max.
Min.
Max.
Unit
0
400
0
1000
KHz
—
50
—
50
ns
1.2
—
0.6
—
µs
0.6
—
0.4
—
µs
1.2
—
0.5
—
µs
Start Condition Setup Time
0.6
—
0.25
—
µs
Stop Condition Setup Time
0.6
—
0.25
—
µs
tHD:STA
Start Condition Hold Time
0.6
—
0.25
—
µs
tHD:STO
Stop Condition Hold Time
0.6
—
0.25
—
µs
tSU:DAT
Data In Setup Time
100
—
100
—
ns
tHD:DAT
Data In Hold Time
0
—
0
—
ns
tSU:WP
WP pin Setup Time
0.6
—
0.6
—
µs
tHD:WP
WP pin Hold Time
1.2
—
1.2
—
µs
tDH
Data Out Hold Time (SCL Low to SDA Data Out Change)
50
—
50
—
ns
tAA
Clock to Output (SCL Low to SDA Data Out Valid)
50
900
50
550
ns
tR
SCL and SDA Rise Time(1)
—
300
—
300
ns
tF
SCL and SDA Fall Time(1)
—
300
—
100
ns
tWR
Write Cycle Time
—
10
—
5
ms
Note:
1. This parameter is characterized but not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCED INFORMATION Rev. 00B
06/27/06
11
IS24C128A
IS24C256A
ISSI
®
AC WAVEFORMS
Figure 11. Bus Timing
tR
tF
tHIGH
tLOW
tSU:STO
SCL
tSU:STA
tBUF
tHD:DAT
tHD:STA
tSU:DAT
SDAIN
tAA
tDH
SDAOUT
tSU:WP
tHD:WP
WP
Figure 12. Write Cycle Timing
SCL
SDA
8th BIT
ACK
tWR
WORD n
STOP
Condition
12
START
Condition
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCED INFORMATION Rev. 00B
06/27/06
IS24C128A
IS24C256A
ISSI
®
ORDERING INFORMATION: IS24C128A
Industrial Range: -40°C to +85°C, Lead-free
Voltage
Range
1.8V
to 5.5V
Part Number
Package
IS24C128A-2PLI
IS24C128A-2GLI
IS24C128A-2WLI
300-mil Plastic DIP (8-pin)
Small Outline (JEDEC STD) (8-pin)
Small Outline (EIAJ STD) (8-pin)
Industrial Range: -40°C to +85°C
Voltage
Range
1.8V
to 5.5V
Part Number
Package
IS24C128A-2PI
IS24C128A-2GI
IS24C128A-2WI
300-mil Plastic DIP (8-pin)
Small Outline (JEDEC STD) (8-pin)
Small Outline (EIAJ STD) (8-pin)
ORDERING INFORMATION: IS24C256A
Industrial Range: -40°C to +85°C, Lead-free
Voltage
Range
1.8V
to 5.5V
Part Number
Package
IS24C256A-2PLI
IS24C256A-2GLI
IS24C256A-2WLI
300-mil Plastic DIP (8-pin)
Small Outline (JEDEC STD) (8-pin)
Small Outline (EIAJ STD) (8-pin)
Industrial Range: -40°C to +85°C
Voltage
Range
1.8V
to 5.5V
Part Number
Package
IS24C256A-2PI
IS24C256A-2GI
IS24C256A-2WI
300-mil Plastic DIP (8-pin)
Small Outline (JEDEC STD) (8-pin)
Small Outline (EIAJ STD) (8-pin)
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCED INFORMATION Rev. 00B
06/27/06
13
IS24C128A
IS24C256A
ISSI
®
ORDERING INFORMATION: IS24C128A
Automotive Range: -40°C to +125°C, Lead-free
Voltage
Range
2.5V
to 5.5V
Part Number
Package
IS24C128A-3PLA3
IS24C128A-3GLA3
IS24C128A-3WLA3
300-mil Plastic DIP (8-pin)
Small Outline (JEDEC STD) (8-pin)
Small Outline (EIAJ STD) (8-pin)
ORDERING INFORMATION: IS24C256A
Automotive Range: -40°C to +125°C, Lead-free
Voltage
Range
2.5V
to 5.5V
14
Part Number
Package
IS24C256A-3PLA3
IS24C256A-3GLA3
IS24C256A-3WLA3
300-mil Plastic DIP (8-pin)
Small Outline (JEDEC STD) (8-pin)
Small Outline (EIAJ STD) (8-pin)
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCED INFORMATION Rev. 00B
06/27/06
ISSI
PACKAGING INFORMATION
®
300-mil Plastic DIP
Package Code: N,P
N
E1
1
D
S
S
SEATING PLANE
B1
E
A
L
C
A1
FOR
32-PIN ONLY
e
MILLIMETERS
Sym.
Min.
INCHES
Max.
Min.
Max.
4.57
9.53
8.26
0.145
0.015
0.014
0.045
0.032
0.008
0.359
0.300
0.180
E
3.68
0.38
0.36
1.14
0.81
0.20
9.12
7.62
E1
6.20
6.60
0.244
0.260
eA
e
8.13
9.65
0.320
0.380
L
3.18
—
0.125
—
S
0.64
0.762
0.025
0.030
N0.
Leads
A
A1
B
B1
B2
C
D
B2
B
eA
Notes:
1. Controlling dimension: inches, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash protrusions and should
be measured from the bottom of the package.
4. Formed leads shall be planar with respect to one another within 0.004
inches at the seating plane.
8
—
0.56
1.52
1.17
0.33
2.54 BSC
—
0.022
0.060
0.046
0.013
0.375
0.325
0.100 BSC
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
02/14/03
ISSI
PACKAGING INFORMATION
150-mil Plastic SOP
Package Code: G, GR
®
N
E
H
1
D
SEATING PLANE
A
A1
e
L
α
C
B
Symbol
Ref. Std.
No. Leads
A
A1
B
C
D
E
H
e
L
150-mil Plastic SOP (G, GR)
Min
Max
Min
Max
Inches
mm
8
8
—
0.068
—
1.73
0.004
0.009
0.1
0.23
0.013
0.020
0.33
0.51
0.007
0.010
0.18
0.25
0.189
0.197
4.8
5
0.150
0.157
3.81
3.99
0.228
0.245
5.79
6.22
0.050 BSC
1.27 BSC
0.020
0.035
0.51
0.89
Notes:
1. Controlling dimension: inches, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash protrusions and should be
measured from the bottom of the package.
4. Formed leads shall be planar with respect to one another within 0.004 inches at the
seating plane.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
10/03/01
2
ISSI
PACKAGING INFORMATION
200-mil Plastic SOP
Package Code: W
®
N
E
H
1
D
SEATING PLANE
A
A1
e
L
α
C
B
Notes:
1. Controlling dimension: mm, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash protrusions
and should be measured from the bottom of the package.
200-mil Plastic SOP (W)
Symbol
Ref. Std.
No. Leads
A
A1
B
C
D
E
H
e
L
Min
Max
Inches
8
—
0.085
0.004
0.009
0.014
0.018
0.006
0.014
0.203
0.211
0.204
0.213
0.303
0.325
0.050 BSC
0.020
0.033
Min
Max
mm
8
—
2.16
0.10
0.23
0.35
0.45
0.15
0.35
5.15
5.35
5.18
5.40
7.70
8.26
1.27 BSC
0.51
0.85
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
10/20/05
2