CY28446 Clock Generator for Intel® Calistoga Chipset Features • 33-MHz PCI clocks • Buffered 14.318-MHz reference clock • Compliant to Intel® CK410M • Low-voltage frequency select input • Selectable CPU frequencies • I2C support with readback capabilities • Low power differential CPU clock pairs • 100-MHz low power differential SRC clocks • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • 96-MHz low power differential DOT clock • 3.3V power supply • 48-MHz USB clock • 64-pin QFN package • SRC clocks stoppable through OE# Table 1. Output Configuration table CPU SRC PCI REF DOT96 48M x2 / x3 x9/10 x5 x1 x1 x1 PCI3 PCI2 PCI1 PCI0 PCIF0/ITP_EN VDD_PCI VSS_PCI VTTPWRGD#/PD FS_C/TEST_SEL USB_48/FS_A VSS_PCI VDD_48 DOTT_96 DOTC_96 FS_B/TEST_MODE OE1# Pin Configuration 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VSS_48 SRCT0 SRCC0 OE0# SRCT1 SRCC1 OEA# SRCT2 SRCC2 VDD_SRC VSS_SRC OE3# SRCT3 SRCC3 OE6# PCI_STOP# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 CY28446 VDD_PCI REF VSS_REF XIN XOUT VDD_REF SDATA SCLK CPU_STOP# CPUT0 CPUC0 VSS_CPU VDD_CPU CPUT1 CPUC1 VSS_SRC Cypress Semiconductor Corporation Document #: 001-00168 Rev *D • 198 Champion Court • CPUT2_ITP/SRCT7 CPUC2_ITP/SRCC7 VSS_SRC VDD_SRC SRCC10 SRCT10 SRCT9 SRCC9 OEB# SRCC8 SRCT8 SRCT6 SRCC6 SRCC5 SRCT5 VDD_SRC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 San Jose, CA 95134-1709 • 408-943-2600 Revised April 03, 2006 CY28446 Table 2. Frequency Table FS_C FS_B FS_A CPU SRC/SATA PCIF/PCI REF LCD DOT96 USB MID 0 1 100 100 33 14.318 100 96 48 0 0 1 133 100 33 14.318 100 96 48 0 1 1 166 100 33 14.318 100 96 48 0 1 0 200 100 33 14.318 100 96 48 0 0 0 MID 0 0 MID 1 0 MID 1 1 Reserved 100 33 14.318 100 96 1 0 x Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 1 1 0 REF/2 REF/8 REF/24 REF REF/8 REF REF 1 1 1 REF/2 REF/8 REF/24 REF REF/8 REF REF Document #: 001-00168 Rev *D 48 Page 2 of 21 CY28446 Pin Description Pin No. 1 Name VSS_48 2, 3, 5, 6, 8, SRC(0:3, 5:6, 8:10) 9, 13, 14, 18, [T/C] 19, 20, 21, 22, 23, 25, 26, 27, 28 4, 7, 12, 15, 24, 64 Type Description GND Ground for outputs. O, DIF 100-MHz Differential serial reference clocks OE[0, 1, 3, 6, A, B]# I, PU 3.3V LVTTL input for enabling assigned SRC clock (active LOW) 10, 17, 29, VDD_SRC PWR 3.3V power supply for outputs. 11, 30, 33 VSS_SRC GND Ground for outputs. 16 PCI_STP# I, PU 3.3V LVTTL input for PCI_STP# Stops SRC and PCI clocks not set to free running in the SMBUS registers. 31, 32 CPU2_ITPT/SRCT7, O, DIF Selectable differential CPU clock/100-MHz Differential serial reference clock. CPU2_ITPC/ SRCC7 Selectable via Pin 53 PCIF0/ITP_EN 34, 35, 38, 39 CPUT/C[0:1] 36 VDD_CPU O, DIF Differential CPU clock outputs. PWR 3.3V power supply for outputs. 37 VSS_CPU GND Ground for outputs. 40 CPU_STP# I, PU 3.3V LVTTL input for CPU_STP# active LOW. 41 SCLK I 42 SDATA I/O, OD 43 VDD_REF PWR 3.3V power supply for outputs. 44 XOUT O, SE 14.318-MHz crystal output. 45 XIN I SMBus-compatible SCLOCK. SMBus-compatible SDATA. 14.318-MHz crystal input. 46 VSS_REF GND Ground for outputs. 47 REF O,SE Fixed 14.318-MHz clock output. 48, 54 VDD_PCI PWR 3.3V power supply for outputs. 49, 50, 51, 52 PCI[0:3] O, SE 33-MHz clock output 53 PCIF0/ITP_EN I/O, PD 33-MHz clock output (not stoppable by PCI_STOP#) / 3.3V LVTTL input for selecting pins 31/32 (CPU2_ITP[T/C]/SRC7[T/C]) (sampled on the VTT_PWRGD# assertion). 0 (default): SRC7[T/C] 1: CPU2_ITP[T/C] 55, 59 VSS_PCI GND Ground for outputs. 56 VTT_PWRGD#/PD I, PD 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B, FS_C, and all I/O configuration pins,. After VTT_PWRGD# (active LOW) assertion, this pin becomes a real-time input for asserting power-down (active HIGH). 57 FS_C/TEST_SEL I, PD 3.3V-tolerant input for CPU frequency selection/Selects test mode if pulled to VIMFS_C when VTT_PWRGD# is asserted LOW. Refer to DC Electrical Specifications table for VILFS_C,VIMFS_C,VIHFS_C specifications. 58 USB_48/FS_A 60 VDD_48 61,62 DOT_96[T/C] 63 FS_B/TEST_MODE Document #: 001-00168 Rev *D I/O, PU Fixed 48-MHz clock output / 3.3V-tolerant input for CPU frequency selection. Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. PWR 3.3V power supply for outputs. O, DIF Fixed 96-MHz clock output. I, PU 3.3V-tolerant input for CPU frequency selection Selects Ref/N or Tri-state when in test mode 0 = Tri-state, 1 = Ref/N Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. Page 3 of 21 CY28446 Frequency Select Pins (FS_A, FS_B, and FS_C) Host clock frequency selection is achieved by applying the appropriate logic levels to FS_A, FS_B, FS_C inputs prior to VTT_PWRGD# assertion (as seen by the clock synthesizer). Upon VTT_PWRGD# being sampled LOW by the clock chip (indicating processor VTT voltage is stable), the clock chip samples the FS_A, FS_B, and FS_C input values. For all logic levels of FS_A, FS_B, and FS_C, VTT_PWRGD# employs a one-shot functionality in that once a valid LOW on VTT_PWRGD# has been sampled, all further VTT_PWRGD#, FS_A, FS_B, and FSC transitions will be ignored, except in test mode. Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 3. The block write and block read protocol is outlined in Table 4 while Table 5 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Table 3. Command Code Definition Bit 7 (6:0) Description 0 = Block read or block write operation, 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' Table 4. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 Description Start Slave address – 7 bits 9 Write 10 18:11 19 27:20 28 36:29 37 45:38 Block Read Protocol Bit 1 8:2 Description Start Slave address – 7 bits 9 Write Acknowledge from slave 10 Acknowledge from slave Command Code – 8 bits 18:11 Command Code – 8 bits Acknowledge from slave 19 Acknowledge from slave Byte Count – 8 bits (Skip this step if I2C_EN bit set) 20 Repeat start Acknowledge from slave 27:21 Slave address – 7 bits Data byte 1 – 8 bits 28 Read = 1 Acknowledge from slave 29 Acknowledge from slave Data byte 2 – 8 bits 46 Acknowledge from slave .... Data Byte /Slave Acknowledges .... Data Byte N – 8 bits .... Acknowledge from slave .... Stop Document #: 001-00168 Rev *D 37:30 38 46:39 47 55:48 Byte Count from slave – 8 bits Acknowledge Data byte 1 from slave – 8 bits Acknowledge Data byte 2 from slave – 8 bits 56 Acknowledge .... Data bytes from slave / Acknowledge .... Data Byte N from slave – 8 bits .... NOT Acknowledge .... Stop Page 4 of 21 CY28446 Table 5. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 Description Start Slave address – 7 bits Byte Read Protocol Bit 1 8:2 Slave address – 7 bits 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 Command Code – 8 bits 18:11 Command Code – 8 bits Acknowledge from slave 19 Acknowledge from slave Data byte – 8 bits 20 Repeated start 19 27:20 28 Acknowledge from slave 29 Stop Document #: 001-00168 Rev *D 9 Description Start 27:21 Write Slave address – 7 bits 28 Read 29 Acknowledge from slave 37:30 Data from slave – 8 bits 38 NOT Acknowledge 39 Stop Page 5 of 21 CY28446 Control Registers Byte 0: Control Register 0 Bit 7 @Pup 1 6 1 5 1 4 3 1 1 2 1 1 1 0 1 Name Description CPU2_ITP[T/C]/SRC7[T/C] CPU2_ITP[T/C]/SRC[T/C]7 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]6 SRC[T/C]6 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]5 SRC[T/C]5 Output Enable 0 = Disable (Tri-state), 1 = Enable Reserved Reserved SRC[T/C]3 SRC[T/C]3 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]2 SRC[T/C]2 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]1 SRC[T/C]1 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]0 SRC[T/C]0 Output Enable 0 = Disable (Tri-state), 1 = Enable Byte 1: Control Register 1 Bit @Pup Name Description 7 1 PCIF0 6 1 DOT_96[T/C] 5 1 USB_48 USB_48 Output Enable 0 = Disable, 1 = Enable 4 1 REF REF Output Enable 0 = Disable, 1 = Enable PCIF0 Output Enable 0 = Disable, 1 = Enable DOT_96 MHz Output Enable 0 = Disable (Tri-state), 1 = Enable 3 1 Reserved Reserved 2 1 CPU[T/C]1 CPU[T/C]1 Output Enable 0 = Disable (Tri-state), 1 = Enable 1 1 CPU[T/C]0 CPU[T/C]0 Output Enable 0 = Disable (Tri-state), 1 = Enable 0 0 CPU PLL Spread Enable PLL1 (CPU PLL) Spread Spectrum Enable 0 = Spread off 1 = Spread on (–0.5% spread spectrum on CPU/SRC/PCI clocks) Byte 2: Control Register 2 Bit @Pup Name 7 1 Reserved Reserved set to 1 6 1 Reserved Reserved set to 1 5 1 PCI3 PCI3 Output Enable 0 = Disable, 1 = Enable 4 1 PCI2 PCI2 Output Enable 0 = Disable, 1 = Enable 3 1 PCI1 PCI1Output Enable 0 = Disable, 1 = Enable 2 1 PCI0 PCI0 Output Enable 0 = Disable, 1 = Enable 1 1 Reserved Reserved set to 1 0 1 Reserved Reserved set to 1 Document #: 001-00168 Rev *D Description Page 6 of 21 CY28446 Byte 3: Control Register 3 Bit @Pup Name Description 7 0 SRC7 6 0 Reserved 5 0 SRC5 4 0 Reserved Reserved set to 0 3 0 Reserved Reserved set to 0 2 0 SRC2 1 0 Reserved Reserved set to 0 0 0 Reserved Reserved set to 0 Allow control of SRC[T/C]7 with assertion of OEB# 0 = Free running, 1 = Stopped with OEB# Reserved set to 0 Allow control of SRC[T/C]5 with assertion of OEB# 0 = Free running, 1 = Stopped with OEB# Allow control of SRC[T/C]2 with assertion of OEB# 0 = Free running, 1 = Stopped with OEB# Byte 4: Control Register 4 Bit @Pup Name 7 1 Reserved Description 6 0 DOT96[T/C] 5 0 Reserved Reserved set to 0 4 1 Reserved Reserved set to 1 3 0 PCIF0 2 1 CPU[T/C]2 Allow control of CPU[T/C]2 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# 1 1 CPU[T/C]1 Allow control of CPU[T/C]1 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# 0 1 CPU[T/C]0 Allow control of CPU[T/C]0 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# Reserved set to 1 DOT PWRDWN Drive Mode 0 = Driven in PWRDWN, 1 = Tri-state Allow control of PCIF0 with assertion of SW and HW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Byte 5: Control Register 5 Bit @Pup Name 7 0 Reserved Reserved set to 0 6 0 CPU[T/C]2 CPU[T/C]2 Stop Drive Mode 0 = Driven when CPU_STP# asserted, 1 = Tri-state when CPU_STP# asserted 5 0 CPU[T/C]1 CPU[T/C]1 Stop Drive Mode 0 = Driven when CPU_STP# asserted, 1 = Tri-state when CPU_STP# asserted 4 0 CPU[T/C]0 CPU[T/C]0 Stop Drive Mode 0 = Driven when CPU_STP# asserted, 1 = Tri-state when CPU_STP# asserted 3 0 SRC[T/C] SRC[T/C] PWRDWN Drive Mode 0 = Driven when PD asserted, 1 = Tri-state when PD asserted 2 0 CPU[T/C]2 CPU[T/C]2 PWRDWN Drive Mode 0 = Driven when PD asserted, 1 = Tri-state when PD asserted 1 0 CPU[T/C]1 CPU[T/C]1 PWRDWN Drive Mode 0 = Driven when PD asserted, 1 = Tri-state when PD asserted 0 0 CPU[T/C]0 CPU[T/C]0 PWRDWN Drive Mode 0 = Driven when PD asserted, 1 = Tri-state when PD asserted Document #: 001-00168 Rev *D Description Page 7 of 21 CY28446 Byte 6: Control Register 6 Bit @Pup Name Description 7 0 6 0 Test Mode Test Mode Control 1 = Ref/N or Tristate, 0 = Normal Operation 5 1 Reserved Reserved set to 1 4 0 REF 3 1 2 HW FS_C FSC Reflects the value of the FS_C pin sampled on power-up 0 = FSC was low during VTT_PWRGD# assertion 1 HW FS_B FSB Reflects the value of the FS_B pin sampled on power-up 0 = FSB was low during VTT_PWRGD# assertion 0 HW FS_A FSA Reflects the value of the FS_A pin sampled on power-up 0 = FSA was low during VTT_PWRGD# assertion REF/N or Tri-state Select REF/N or Tri-state Select 1 = REF/N, 0 = Tri-state REF Output Drive Strength 0 = Low, 1 = High SW PCI_STP Function PCI and PCIF clock outputs except those set 0 = SW PCI_STP assert, 1 = SW PCI_STP deassert When this bit is set to 0, all STOPPABLE PCI and PCIF outputs will be to free running stopped in a synchronous manner with no short pulses. When this bit is set to 1, all STOPPED PCI and PCIF outputs will resume in a synchronous manner with no short pulses. Byte 7: Vendor ID Bit @Pup Name 7 0 Revision Code Bit 3 Revision Code Bit 3 Description 6 0 Revision Code Bit 2 Revision Code Bit 2 5 1 Revision Code Bit 1 Revision Code Bit 1 4 1 Revision Code Bit 0 3 1 Vendor ID Bit 3 Vendor ID Bit 3 2 0 Vendor ID Bit 2 Vendor ID Bit 2 1 0 Vendor ID Bit 1 Vendor ID Bit 1 0 0 Vendor ID Bit 0 Vendor ID Bit 0 Revision Code Bit 0 Byte 8: Control Register 7 Bit @Pup 7 0 Reserved 6 1 SRC[T/C]10 SRC[T/C]10 Output Enable 0 = Disable (Tri-state), 1 = Enable 5 1 SRC[T/C]9 SRC[T/C]9 Output Enable 0 = Disable (Tri-state), 1 = Enable 4 1 SRC[T/C]8 SRC[T/C]8 Output Enable 0 = Disable (Tri-state), 1 = Enable 3 0 Reserved Reserved set to 0 2 0 SRC10 Allow control of SRC[T/C]10 with assertion of OEA# 0 = Free running, 1 = Stopped with OEA# 1 0 SRC9 Allow control of SRC[T/C]9 with assertion of OEB# 0 = Free running, 1 = Stopped with OEB# 0 0 SRC8 Allow control of SRC[T/C]8 with assertion of OEA# 0 = Free running, 1 = Stopped with OEA# Document #: 001-00168 Rev *D Name Description Reserved set to 0 Page 8 of 21 CY28446 Byte 9: Control Register 8 Bit @Pup Name 7 0 PCI3 33-MHz Output drive strength 0 = Low, 1 = High Description 6 0 PCI2 33-MHz Output drive strength 0 = Low, 1 = High 5 0 PCI1 33-MHz Output drive strength 0 = Low, 1 = High 4 0 PCI0 33-MHz Output drive strength 0 = Low, 1 = High 3 0 PCIF0 33-MHz Output drive strength 0 = Low, 1 = High 2 1 Reserved Reserved set to 1 1 1 Reserved Reserved set to 1 0 1 Reserved Reserved set to 1 . Crystal Recommendations Frequency (Fund) Cut Loading Load Cap Drive (max.) Shunt Cap (max.) Motional (max.) Tolerance (max.) Stability (max.) Aging (max.) 14.31818 MHz AT Parallel 0.1 mW 5 pF 0.016 pF 35 ppm 30 ppm 5 ppm 20 pF The CY28446 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28446 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides. Crystal Loading Clock Chip Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance the crystal will see must be considered to calculate the appropriate capacitive loading (CL). Figure 1 shows a typical crystal configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. It’s a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. This is not true. Ci2 Ci1 Pin 3 to 6p Cs1 X2 X1 Cs2 Trace 2.8 pF XTAL Ce1 Ce2 Trim 33 pF Figure 2. Crystal Loading Example Figure 1. Crystal Capacitive Clarification Calculating Load Capacitors In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to Document #: 001-00168 Rev *D As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This mean the total capacitance on each side of the crystal must be twice the specified load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitance loading on both sides. Page 9 of 21 CY28446 Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side) Ce = 2 * CL – (Cs + Ci) Total Capacitance (as seen by the crystal) CLe = 1 1 ( Ce1 + Cs1 + Ci1 + 1 Ce2 + Cs2 + Ci2 ) CL ................................................... Crystal load capacitance CLe .........................................Actual loading seen by crystal using standard value trim capacitors Ce .....................................................External trim capacitors Cs.............................................. Stray capacitance (terraced) Ci ........................................................... Internal capacitance (lead frame, bond wires etc.) OE# Deassertion (OE# -> HIGH) The impact of deasserting the OE# pins is that all SRC outputs that are set in the control registers to stoppable via deassertion of OE# are to be stopped after their next transition. The final state of all stopped SRC clocks is Low/Low. PD (Power-down) Clarification The VTT_PWRGD# /PD pin is a dual-function pin. During initial power-up, the pin functions as VTT_PWRGD#. Once VTT_PWRGD# has been sampled LOW by the clock chip, the pin assumes PD functionality. The PD pin is an asynchronous active HIGH input used to shut off all clocks cleanly prior to shutting off power to the device. This signal is synchronized internal to the device prior to powering down the clock synthesizer. PD is also an asynchronous input for powering up the system. When PD is asserted HIGH, all clocks need to be driven to a low value and held prior to turning off the VCOs and the crystal oscillator. PD (Power-down) Assertion OE# Description The OE# signals are active LOW inputs used for clean enabling and disabling selected SRC outputs. The outputs controlled by OE[A,B]# are determined by the settings in register byte 3 and byte 8. OE[0,1,3,6]# controls SRC[0,1,3,6], respectively. The OE# signal is a debounced signal in that its state must remain unchanged during two consecutive rising edges of SRCC to be recognized as a valid assertion or deassertion. (The assertion and deassertion of this signal is absolutely asynchronous.) OE# Assertion (OE# -> LOW) All differential outputs that were stopped are to resume normal operation in a glitch-free manner. The maximum latency from the assertion to active outputs is between 2 and 6 SRC clock periods (2 clocks are shown) with all SRC outputs resuming simultaneously. All stopped SRC outputs must be driven HIGH within 10 ns of OE# deassertion to a voltage greater than 200 mV. When PD is sampled HIGH by two consecutive rising edges of CPUC, all single-ended outputs will be held LOW on their next HIGH-to-LOW transition and differential clocks must held HIGH or tri-stated (depending on the state of the control register drive mode bit) on the next diff clock# HIGH-to-LOW transition within 4 clock periods. When the SMBus PD drive mode bit corresponding to the differential (CPU, SRC, and DOT) clock output of interest is programmed to ‘0’, the clock output are held with “Diff clock” pin driven HIGH and “Diff clock#” driven LOW. If the control register PD drive mode bit corresponding to the output of interest is programmed to “1”, then both the “Diff clock” and the “Diff clock#” are LOW. Note Figure 4 shows CPUT = 133 MHz and PD drive mode = ‘1’ for all differential outputs. This diagram and description is applicable to valid CPU frequencies 100, 133, 166, and 200 MHz. In the event that PD mode is desired as the initial power-on state, PD must be asserted HIGH in less than 10 µs after asserting Vtt_PwrGd#. It should be noted that 96_100_SSC will follow the DOT waveform is selected for 96 MHz and the SRC waveform when in 100-MHz mode. OE# SRCT(free running) SRCC(free running) SRCT(stoppable) SRCT(stoppable) Figure 3. OE# Deassertion/Assertion Waveform Document #: 001-00168 Rev *D Page 10 of 21 CY28446 PD CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C PCI, 33 MHz REF Figure 4. Power-down Assertion Timing Waveform PD Deassertion The power-up latency is less than 1.8 ms. This is the time from the deassertion of the PD pin or the ramping of the power supply until the time that stable clocks are output from the clock chip. All differential outputs stopped in a three-state condition resulting from power-down will be driven HIGH in less than 300 µs of PD deassertion to a voltage greater than 200 mV. After the clock chip’s internal PLL is powered up and locked, all outputs will be enabled within a few clock cycles of each other. Figure 5 is an example showing the relationship of clocks coming up. It should be noted that 96_100_SSC will follow the DOT waveform is selected for 96 MHz and the SRC waveform when in 100-MHz mode. Tstable <1.8 ms PD CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C PCI, 33MHz REF Tdrive_PWRDN# <300 µσ, >200 mV Figure 5. Power-down Deassertion Timing Waveform Document #: 001-00168 Rev *D Page 11 of 21 CY28446 CPU_STP# Assertion The CPU_STP# signal is an active LOW input used for synchronous stopping and starting the CPU output clocks while the rest of the clock generator continues to function. When the CPU_STP# pin is asserted, all CPU outputs that are set with the SMBus configuration to be stoppable via assertion of CPU_STP# will be stopped within two to six CPU clock periods after being sampled by two rising edges of the internal CPUC clock. The final state of all stopped CPU clocks is High/Low when driven, Low/Low when tri-stated CPU_STP# Deassertion The deassertion of the CPU_STP# signal will cause all CPU outputs that were stopped to resume normal operation in a synchronous manner, synchronous manner meaning that no short or stretched clock pulses will be produce when the clock resumes. The maximum latency from the deassertion to active outputs is no more than two CPU clock cycles. CPU_STP# CPUT CPUC CPUT Internal CPUC Internal Tdrive_CPU_STP#,10 ns > 200 mV Figure 6. CPU_STP# Deassertion Waveform 1.8 ms CPU_STOP# PD CPUT(Free Running CPUC(Free Running CPUT(Stoppable) CPUC(Stoppable) DOT96T DOT96C Figure 7. CPU_STP#= Driven, CPU_PD = Driven, DOT_PD = Driven CPU_STP# CPUT CPUC Figure 8. CPU_STP# Assertion Waveform Document #: 001-00168 Rev *D Page 12 of 21 CY28446 1.8mS CPU_STOP# PD CPUT(Free Running) CPUC(Free Running) CPUT(Stoppable) CPUC(Stoppable) DOT96T DOT96C Figure 9. CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state PCI_STP# Assertion PCI_STP# Deassertion The PCI_STP# signal is an active LOW input used for synchronous stopping and starting the PCI outputs while the rest of the clock generator continues to function. The set-up time for capturing PCI_STP# going LOW is 10 ns (tSU). (See Figure 10.) The PCIF clocks will not be affected by this pin if their corresponding control bit in the SMBus register is set to allow them to be free running. The deassertion of the PCI_STP# signal will cause all PCI and stoppable PCIF clocks to resume running in a synchronous manner within two PCI clock periods after PCI_STP# transitions to a high level. Tsu PCI_STP# PCI_F PCI SRC 100MHz Figure 10. PCI_STP# Assertion Waveform Tsu Tdrive_SRC PCI_STP# PCI_F PCI SRC 100MHz Figure 11. PCI_STP# Deassertion Waveform Document #: 001-00168 Rev *D Page 13 of 21 CY28446 FS_A, FS_B,FS_C VTT_PW RGD# PW RGD_VRM 0.2-0.3mS Delay VDD Clock Gen State 0 Clock State W ait for VTT_PW RGD# State 1 State 2 Off Clock Outputs State 3 On On Off Clock VCO Device is not affected, VTT_PW RGD# is ignored Sample Sels Figure 12. VTT_PWRGD# Timing Diagram S2 S1 Delay >0.25mS VTT_PWRGD# = Low Sample Inputs straps VDD_A = 2.0V Wait for <1.8ms S0 Power Off S3 VDD_A = off Normal Operation Enable Outputs VTT_PWRGD# = toggle Figure 13. Clock Generator Power-up/Run State Diagram Document #: 001-00168 Rev *D Page 14 of 21 CY28446 Absolute Maximum Conditions Parameter Description Condition Min. Max. Unit VDD Core Supply Voltage –0.5 4.6 V VDD_A Analog Supply Voltage –0.5 4.6 V VIN Input Voltage Relative to VSS –0.5 TS Temperature, Storage Non-functional –65 TA Temperature, Operating Ambient Functional 0 85 °C TJ Temperature, Junction Functional – 150 °C ØJC Dissipation, Junction to Case Mil-STD-883E Method 1012.1 – 20 °C/W ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) – 60 °C/W ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 – V UL-94 Flammability Rating At 1/8 in. MSL Moisture Sensitivity Level VDD + 0.5 VDC 150 2000 °C V–0 1 Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. DC Electrical Specifications Parameter Description Condition Min. Max. Unit 3.135 3.465 V SDATA, SCLK – 1.0 V SDATA, SCLK 2.2 – V All VDDs 3.3V Operating Voltage 3.3 ± 5% VILI2C Input Low Voltage VIHI2C Input High Voltage VIL_FS FS_[A,B] Input Low Voltage VSS – 0.3 0.35 V VIH_FS FS_[A,B] Input High Voltage 0.7 VDD + 0.5 V VILFS_C FS_C Input Low Voltage VSS – 0.3 0.35 V VIMFS_C FS_C Input Middle Voltage Typical 0.7 1.7 V Typical VIHFS_C FS_C Input High Voltage VIL 3.3V Input Low Voltage 2.0 VDD + 0.5 V VSS – 0.3 0.8 V VIH 3.3V Input High Voltage IIL Input Low Leakage Current Except internal pull-up resistors, 0 < VIN < VDD 2.0 VDD + 0.3 V –5 5 µA IIH Input High Leakage Current Except internal pull-down resistors, 0 < VIN < VDD – 5 µA VOL 3.3V Output Low Voltage IOL = 1 mA – 0.4 V VOH 3.3V Output High Voltage IOH = –1 mA IOZ High-impedance Output Current 2.4 – V –10 10 µA CIN Input Pin Capacitance 3 5 pF COUT Output Pin Capacitance 3 6 pF LIN Pin Inductance VXIH Xin High Voltage VXIL Xin Low Voltage IDD3.3V Dynamic Supply Current At max. load and freq. per Figure 15 IPD3.3V Power-down Supply Current PD asserted, Outputs Driven IPD3.3V Power-down Supply Current PD asserted, Outputs Tri-state Document #: 001-00168 Rev *D – 7 nH 0.7VDD VDD V 0 0.3VDD V – 250 mA – 70 mA – 5 mA Page 15 of 21 CY28446 AC Electrical Specifications Parameter Description Condition Min. Max. Unit 47.5 52.5 % 69.841 71.0 ns ns Crystal TDC XIN Duty Cycle The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification TPERIOD XIN Period When XIN is driven from an external clock source TR / TF XIN Rise and Fall Times Measured between 0.3VDD and 0.7VDD – 10.0 TCCJ XIN Cycle to Cycle Jitter As an average over 1-µs duration – 500 ps LACC Long-term Accuracy Measured at crossing point VOX – 300 ppm TDC CPUT and CPUC Duty Cycle Measured at crossing point VOX 45 55 % CPU at 0.8V TPERIOD 100-MHz CPUT and CPUC Period Measured at crossing point VOX 9.997001 10.00300 ns TPERIOD 133-MHz CPUT and CPUC Period Measured at crossing point VOX 7.497751 7.502251 ns TPERIOD 166-MHz CPUT and CPUC Period Measured at crossing point VOX 5.998201 6.001801 ns TPERIOD 200-MHz CPUT and CPUC Period Measured at crossing point VOX 4.998500 5.001500 ns TPERIODSS 100-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 9.997001 10.05327 ns TPERIODSS 133-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 7.497751 7.539950 ns TPERIODSS 166-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 5.998201 6.031960 ns TPERIODSS 200-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 4.998500 5.026634 ns TPERIODAbs 100-MHz CPUT and CPUC Absolute period Measured at crossing point VOX 9.912001 10.08800 ns TPERIODAbs 133-MHz CPUT and CPUC Absolute period Measured at crossing point VOX 7.412751 7.587251 ns TPERIODAbs 166-MHz CPUT and CPUC Absolute period Measured at crossing point VOX 5.913201 6.086801 ns TPERIODAbs 200-MHz CPUT and CPUC Absolute period Measured at crossing point VOX 4.913500 5.086500 ns TPERIODSSAbs 100-MHz CPUT and CPUC Absolute period, SSC Measured at crossing point VOX 9.912001 10.13827 ns TPERIODSSAbs 133-MHz CPUT and CPUC Absolute period, SSC Measured at crossing point VOX 7.412751 7.624950 ns TPERIODSSAbs 166-MHz CPUT and CPUC Absolute period, SSC Measured at crossing point VOX 5.913201 6.116960 ns TPERIODSSAbs 200-MHz CPUT and CPUC Absolute period, SSC Measured at crossing point VOX 4.913500 5.111634 ns TCCJ CPUT/C Cycle to Cycle Jitter Measured at crossing point VOX – 85[1] ps TCCJ2 CPU2_ITP Cycle to Cycle Jitter Measured at crossing point VOX – 125 ps LACC Long-term Accuracy Measured at crossing point VOX – 300 ppm TSKEW2 CPU2_ITP to CPU0 Clock Skew Measured at crossing point VOX – 150 ps 700 ps 20 % TR / TF CPUT and CPUC Rise and Fall Time Measured from VOL = 0.175 to VOH = 0.525V TRFM Rise/Fall Matching Determined as a fraction of 2*(TR – TF)/(TR + TF) 175 [1] – ∆TR Rise Time Variation – 125 ps ∆TF Fall Time Variation – 125 ps VHIGH Voltage High 660 850 mV Math averages Figure 15 Note: 1. Measured at typical condition. VDD = 3.3V, Temp=25°C. Document #: 001-00168 Rev *D Page 16 of 21 CY28446 AC Electrical Specifications (continued) Parameter VLOW Description Voltage Low Condition Min. Max. Unit Math averages Figure 15 –150 – mV [1] VOX Crossing Point Voltage at 0.7V Swing 550 mV VOVS Maximum Overshoot Voltage – VHIGH + 0.3 V VUDS Minimum Undershoot Voltage –0.3 – V VRB Ring Back Voltage See Figure 15. Measure SE – 0.2 V TDC SRCT and SRCC Duty Cycle Measured at crossing point VOX 45 55 % TPERIOD 100-MHz SRCT and SRCC Period Measured at crossing point VOX 9.997001 10.00300 ns TPERIODSS 100-MHz SRCT and SRCC Period, SSC Measured at crossing point VOX 9.997001 10.05327 ns TPERIODAbs 100-MHz SRCT and SRCC Absolute Period Measured at crossing point VOX 9.872001 10.12800 ns TPERIODSSAbs 100-MHz SRCT and SRCC Absolute Period, SSC Measured at crossing point VOX 9.872001 10.17827 ns TSKEW Any SRCT/C to SRCT/C Clock Skew Measured at crossing point VOX – 100 ps TCCJ SRCT/C Cycle to Cycle Jitter Measured at crossing point VOX – 125 ps LACC SRCT/C Long Term Accuracy Measured at crossing point VOX – 300 ppm TR / TF SRCT and SRCC Rise and Fall Time Measured from VOL = 0.175 to VOH = 0.525V 175[1] 700[1] ps TRFM Rise/Fall Matching Determined as a fraction of 2*(TR – TF)/(TR + TF) – 20 % 250 SRC at 0.8V ∆TR Rise TimeVariation – 125 ps ∆TF Fall Time Variation – 125 ps VHIGH Voltage High Math averages Figure 15 660 850 mV VLOW Voltage Low Math averages Figure 15 –150 – mV VOX Crossing Point Voltage at 0.7V Swing 250 550 mV VOVS Maximum Overshoot Voltage – VHIGH + 0.3 V VUDS Minimum Undershoot Voltage –0.3 – V VRB Ring Back Voltage See Figure 15. Measure SE – 0.2 V TDC DOT96T and DOT96C Duty Cycle Measured at crossing point VOX 45 55 % TPERIOD DOT96T and DOT96C Period Measured at crossing point VOX 10.41354 10.41979 ns TPERIODAbs DOT96T and DOT96C Absolute Period Measured at crossing point VOX 10.16354 10.66979 ns TCCJ DOT96T/C Cycle to Cycle Jitter – 250 ps LACC DOT96T/C Long Term Accuracy Measured at crossing point VOX TR / TF DOT96T and DOT96C Rise and Fall Time Measured from VOL = 0.175 to VOH = 0.525V TRFM Rise/Fall Matching Determined as a fraction of 2*(TR – TF)/(TR + TF) ∆TR Rise Time Variation ∆TF Fall Time Variation VHIGH Voltage High Math averages Figure 15 VLOW Voltage Low Math averages Figure 15 –150 – mV VOX Crossing Point Voltage at 0.7V Swing 250 550 mV DOT96 at 0.7V Document #: 001-00168 Rev *D Measured at crossing point VOX – 300 ppm 175 [1] 700 ps – 20 % – 125 ps – 125 ps 660 850 mV Page 17 of 21 CY28446 AC Electrical Specifications (continued) Min. Max. Unit VOVS Parameter Maximum Overshoot Voltage Description Condition – VHIGH + 0.3 V VUDS Minimum Undershoot Voltage –0.3 – V VRB Ring Back Voltage – 0.2 V See Figure 15. Measure SE PCI/PCIF at 3.3V TDC PCI Duty Cycle Measurement at 1.5V 45 55 % TPERIOD Spread Disabled PCIF/PCI Period Measurement at 1.5V 29.99100 30.00900 ns TPERIODSS Spread Enabled PCIF/PCI Period, SSC Measurement at 1.5V 29.9910 30.15980 ns TPERIODAbs Spread Disabled PCIF/PCI Period Measurement at 1.5V 29.49100 30.50900 ns TPERIODSSAbs Spread Enabled PCIF/PCI Period, SSC Measurement at 1.5V 29.49100 30.65980 ns Measurement at 2.4V 12.0 – ns PCIF and PCI low time Measurement at 0.4V 12.0 – ns PCIF/PCI rising and falling Edge Rate Measured between 0.8V and 2.0V 1.0 4.0 V/ns TSKEW Any PCI clock to Any PCI clock Skew Measurement at 1.5V – 500 ps TCCJ PCIF and PCI Cycle to Cycle Jitter Measurement at 1.5V – 500 ps LACC PCIF/PCI Long Term Accuracy Measured at crossing point VOX – 300 ppm TDC Duty Cycle Measurement at 1.5V 45 55 % TPERIOD Period Measurement at 1.5V 20.83125 20.83542 ns TPERIODAbs Absolute Period Measurement at 1.5V 20.48125 21.18542 ns THIGH 48_M High time Measurement at 2.4V 8.09 11.3 ns TLOW 48_M Low time Measurement at 0.4V 7.694 11.3 ns TR / TF Rising and Falling Edge Rate Measured between 0.8V and 2.0V 1.0 4.0 V/ns TCCJ Cycle to Cycle Jitter Measurement at 1.5V – 350 ps LACC 48M Long Term Accuracy Measured at crossing point VOX – 300 ppm TDC REF Duty Cycle Measurement at 1.5V 45 55 % TPERIOD REF Period Measurement at 1.5V 69.8203 69.8622 ns TPERIODAbs REF Absolute Period Measurement at 1.5V 68.82033 70.86224 ns TR / TF REF Rising and Falling Edge Rate Measured between 0.8V and 2.0V 1.0 4.0 V/ns TSKEW REF Clock to REF Clock Measurement at 1.5V – 500 ps TCCJ REF Cycle to Cycle Jitter Measurement at 1.5V – 1000 ps LACC Long Term Accuracy Measurement at 1.5V – 300 ppm – 1.8 ms THIGH PCIF and PCI high time TLOW TR / TF 48_M at 3.3V REF at 3.3V ENABLE/DISABLE and SET-UP TSTABLE Clock Stabilization from Power-up TSS Stopclock Set-up Time TSH Stopclock Hold Time Document #: 001-00168 Rev *D 10.0 – ns 0 – ns Page 18 of 21 CY28446 Test and Measurement Set-up For PCI Single-ended Signals and Reference The following diagram shows the test load configuration of single-ended PCI, USB output signals. 33Ω 5 pF Figure 14. Single-ended PCI, USB Load Configuration The following diagram shows the test load configuration for the differential CPU and SRC outputs. CPUT SR CT D O T96T L1 33Ω L2 TPC B M easurem ent point 2 pF 100 ohm D ifferential C PU C SRC C DTO 96C L1 33Ω M easurem ent point L2 TPCB 2 pF Figure 15. 0.7V Differential Load Configuration 3 .3 V s ig n a ls T DC - - 3 .3 V 2 .0 V 1 .5 V 0 .8 V 0V TR TF Figure 16. Single-ended Output Signals (for AC Parameters Measurement) Ordering Information Part Number Package Type Product Flow Lead-free CY28446LFXC 64-pin QFN Commercial, 0° to 70°C CY28446LFXCT 64-pin QFN—Tape and Reel Commercial, 0° to 70°C Document #: 001-00168 Rev *D Page 19 of 21 CY28446 Package Diagram 64-Lead QFN 9 x 9 mm (Punch Version) LF64A DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-220 WEIGHT: 0.2 GRAMS 0.08[0.003] 8.90[0.350] 9.10[0.358] A C 1.00[0.039] MAX. 0.05[0.002] MAX. 0.18[0.007] 0.28[0.011] 0.80[0.031] MAX. 8.70[0.342] 8.80[0.346] PIN1 ID 0.20[0.008] R. 0.20[0.008] REF. N N 1 1 0.80 DIA. 2 0.45[0.018] 2 3 8.90[0.350] 9.10[0.358] 8.70[0.342] 8.80[0.346] E-PAD (PAD SIZE VARY BY DEVICE TYPE) 0.30[0.012] 0.50[0.020] 0.24[0.009] 0.60[0.024] 0°-12° (4X) 0.50[0.020] TOP VIEW 7.45[0.293] 7.55[0.297] C SEATING PLANE SIDE VIEW BOTTOM VIEW 51-85215-** Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. Intel is a registered trademark of Intel Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-00168 Rev *D Page 20 of 21 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY28446 Document History Page Document Title: CY28446 Clock Generator for Intel® Calistoga Chipset Document Number: 001-00168 REV. ECN NO. Issue Date Orig. of Change ** 366781 See ECN RGL New data sheet *A 385257 See ECN RGL Modify Control register byte 4 and 6 Delete 96_100MHz LCD clock AC timing spec from AC Electrical specifications table Modify figure 15 for lower differential buffer Change pin 33 from IREF to VSS_SRC Update IDD, IPD number in DC Electrical Specifications table Updated single-ended PCI, USB loading config. diagram Description of Change *B 391184 See ECN RGL Minor Change: corrected the letter suffix for QFN package *C 402318 See ECN XLZ Modify Control register byte 6, 7, 9 Update DC and AC Electrical Specifications table *D 436731 See ECN RGL Updated Control register bytes 0,1 and 7 Updated AC Electrical Specifications table Removed preliminary status Document #: 001-00168 Rev *D Page 21 of 21