AD AD9245BCPZRL7-802 14-bit, 20 msps/40 msps/65 msps/80 msps, 3 v a/d converter Datasheet

14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,
3 V A/D Converter
AD9245
FEATURES
APPLICATIONS
Medical imaging equipment
IF sampling in communications receivers
WCDMA, CDMA-One, CDMA-2000, and TDS-CDMA
Battery-powered instruments
Hand-held scopemeters
Spectrum analyzers
Power-sensitive military applications
GENERAL DESCRIPTION
The AD9245 is a monolithic, single 3 V supply, 14-bit,
20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital
converter (ADC) featuring a high performance sample-andhold amplifier (SHA) and voltage reference. The AD9245 uses a
multistage differential pipelined architecture with output error
correction logic to provide 14-bit accuracy and guarantee no
missing codes over the full operating temperature range.
The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and common modes, including
single-ended applications. It is suitable for multiplexed systems
that switch full-scale voltage levels in successive channels and
for sampling single-channel inputs at frequencies well beyond
the Nyquist rate. Combined with power and cost savings over
previously available analog-to-digital converters, the AD9245 is
suitable for applications in communications, imaging, and
medical ultrasound.
FUNCTIONAL BLOCK DIAGRAM
AVDD
DRVDD
AD9245
VIN+
8-STAGE
1 1/2-BIT PIPELINE
MDAC1
SHA
VIN–
A/D
16
4
3
A/D
REFT
REFB
CORRECTION LOGIC
OTR
14
OUTPUT BUFFERS
D13 (MSB)
VREF
D0 (LSB)
SENSE
0.5V
REF
SELECT
CLOCK
DUTY CYCLE
STABILIZER
MODE
SELECT
03583-001
Single 3 V supply operation (2.7 V to 3.6 V)
SNR = 72.7 dBc to Nyquist
SFDR = 83.0 dBc to Nyquist
Low power
366 mW at 80 MSPS
300 mW at 65 MSPS
165 mW at 40 MSPS
90 mW at 20 MSPS
Differential input with 500 MHz bandwidth
On-chip reference and sample-and-hold
DNL = ±0.5 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty-cycle stabilizer
AGND
CLK
PDWN
MODE DGND
Figure 1.
A single-ended clock input is used to control all internal conversion cycles. A duty cycle stabilizer (DCS) compensates for
wide variations in the clock duty cycle while maintaining
excellent overall ADC performance. The digital output data is
presented in straight binary or twos complement formats. An
out-of-range (OTR) signal indicates an overflow condition that
can be used with the most significant bit to determine low or
high overflow. Fabricated on an advanced CMOS process, the
AD9245 is available in a 32-lead LFCSP and is specified over
the industrial temperature range (–40°C to +85°C).
PRODUCT HIGHLIGHTS
1. The AD9245 operates from a single 3 V power supply and
features a separate digital output driver supply to
accommodate 2.5 V and 3.3 V logic families.
2. The patented SHA input maintains excellent performance for
input frequencies up to 100 MHz and can be configured for
single-ended or differential operation.
3. The AD9245 is pin-compatible with the AD9215, AD9235,
and AD9236. This allows a simplified migration from 10 bits
to 14 bits and 20 MSPS to 80 MSPS.
4. The clock DCS maintains overall ADC performance over a
wide range of clock pulse widths.
5. The OTR output bit indicates when the signal is beyond the
selected input range.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2006 Analog Devices, Inc. All rights reserved.
AD9245
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ........................................... 13
Applications....................................................................................... 1
Theory of Operation ...................................................................... 18
General Description ......................................................................... 1
Analog Input and Reference Overview ................................... 18
Functional Block Diagram .............................................................. 1
Clock Input Considerations...................................................... 19
Product Highlights ........................................................................... 1
Jitter Considerations .................................................................. 20
Revision History ............................................................................... 2
Power Dissipation and Standby Mode .................................... 20
Specifications..................................................................................... 3
Digital Outputs ........................................................................... 20
DC Specifications ......................................................................... 3
Timing ......................................................................................... 21
AC Specifications.......................................................................... 5
Voltage Reference ....................................................................... 21
Digital Specifications ................................................................... 7
Internal Reference Connection ................................................ 21
Switching Specifications .............................................................. 8
External Reference Operation .................................................. 22
Absolute Maximum Ratings............................................................ 9
Operational Mode Selection ..................................................... 22
Thermal Resistance ...................................................................... 9
Evaluation Board ........................................................................ 22
ESD Caution.................................................................................. 9
Outline Dimensions ....................................................................... 29
Terminology .................................................................................... 10
Ordering Guide .......................................................................... 29
Pin Configuration and Function Descriptions........................... 11
Equivalent Circuits ......................................................................... 12
REVISION HISTORY
1/06—Rev. C to Rev. D
Changes to Differential Input Configurations Section and
Figure 40 .......................................................................................... 19
Changes to Internal Reference Connection Section .................. 21
Changes to Figure 49...................................................................... 23
Changes to Figure 50...................................................................... 24
Changes to Table 12........................................................................ 28
Updated Outline Dimensions ....................................................... 29
Changes to Ordering Guide .......................................................... 29
Added Figure 32 to Figure 37; Renumbered Sequentially ........ 17
Changes to Figure 39...................................................................... 18
Changes to Clock Input Consideration Section......................... 19
Changes to Figure 44...................................................................... 20
Changes to Table 10 ....................................................................... 21
Changes to Figure 51...................................................................... 25
Changes to Table 12 ....................................................................... 28
Changes to Ordering Guide .......................................................... 29
Updated Outline Dimensions....................................................... 29
8/05—Rev. B to Rev. C
Updated Format..................................................................Universal
Changes to Features, Applications, General Description, and
Product Highlights ........................................................................... 1
Added Table 1; Renumbered Sequentially .................................... 3
Changes to Table 2............................................................................ 4
Added Table 3; Renumbered Sequentially .................................... 5
Changes to Table 4............................................................................ 6
Changes to Table 5............................................................................ 7
Changes to Table 6............................................................................ 8
Deleted Explanation of Test Levels Table ...................................... 8
Added Figure 26 to Figure 31; Renumbered Sequentially ........ 16
10/03—Rev. A to Rev. B
Changes to Figure 33...................................................................... 17
5/03—Rev. 0 to Rev. A
Changes to Figure 30...................................................................... 15
Changes to Figure 37...................................................................... 19
Changes to Figure 38...................................................................... 20
Changes to Figure 39...................................................................... 21
Changes to Table 10 ....................................................................... 24
Changes to the Ordering Guide ................................................... 25
Rev. D | Page 2 of 32
AD9245
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes Guaranteed
Offset Error
Gain Error 1
Differential Nonlinearity (DNL) 2
Integral Nonlinearity (INL)2
TEMPERATURE DRIFT1
Offset Error
Gain Error
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
Output Voltage Error (0.5 V Mode)
Load Regulation @ 0.5 mA
INPUT REFERRED NOISE
VREF = 0.5 V
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF = 0.5 V
Input Span, VREF = 1.0 V
Input Capacitance 3
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltages
AVDD
DRVDD
Supply Current
IAVDD2
IDRVDD2
PSRR
POWER CONSUMPTION
DC Input 4
Sine Wave Input2
Standby Power 5
Min
14
AD9245BCP-20
Typ
Max
14
Min
14
AD9245BCP-40
Typ
Max
14
±0.30
±0.30
±0.50
±1.20
±1.60
±3.25
±1.00
±3.10
±5
0.8
±2.5
0.1
2.7
2.25
AD9245BCP-65
Typ
Max
14
±0.50
±0.50
±0.50
±1.40
±2
±12
Min
14
±1.75
±3.25
±1.00
±3.40
±0.50
±0.50
±0.50
±1.60
±2
±12
±35
±5
0.8
±2.5
0.1
±1.75
±6.90
±1.00
±5.55
±3
±12
±35
±5
0.8
±2.5
0.1
Unit
Bits
Bits
% FSR
% FSR
LSB
LSB
ppm/°C
ppm/°C
±35
mV
mV
mV
mV
2.28
1.08
2.28
1.08
2.28
1.08
LSB rms
LSB rms
1
2
7
7
1
2
7
7
1
2
7
7
V p-p
V p-p
pF
kΩ
3.0
3.0
3.6
3.6
2.7
2.25
3.0
3.0
3.6
3.6
2.7
2.25
3.0
3.0
3.6
3.6
V
V
30
2
±0.01
55
5
±0.01
100
7
±0.01
mA
mA
% FSR
90
95
1.0
165
180
1.0
300
320
1.0
mW
mW
mW
120
1
220
Gain errors and gain temperature coefficients are based on the ADC only (with a fixed 1.0 V external reference).
Measured at maximum clock rate, low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
3
Input capacitance refers to the effective capacitance between one differential input pin and AGND.
4
Measured with dc input at maximum clock rate.
5
Standby power is measured with a dc input, the CLK pin inactive (that is, set to AVDD or AGND).
2
Rev. D | Page 3 of 32
375
AD9245
AVDD = 3 V, DRVDD = 2.5 V, sample rate = 80 MSPS, 2 V p-p differential input, 1.0 V external reference, unless otherwise noted.
Table 2.
AD9245BCP-80
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error 1
Gain Error
Gain Error1
Differential Nonlinearity (DNL) 2
Integral Nonlinearity (INL)2
TEMPERATURE DRIFT
Offset Error1
Gain Error
Gain Error1
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
Output Voltage Error (0.5 V Mode)
Load Regulation @ 0.5 mA
INPUT REFERRED NOISE
VREF = 0.5 V
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF = 0.5 V
Input Span, VREF = 1.0 V
Input Capacitance 3
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
IAVDD2
IDRVDD2
PSRR
POWER CONSUMPTION
Low Frequency Input 4
Standby Power 5
Min
14
Typ
Guaranteed
±0.30
±0.28
±0.70
±0.5
±1.4
Max
Unit
Bits
±1.2
% FSR
% FSR
% FSR
LSB
LSB
±4.16
±1.0
±5.15
±10
±12
±17
±3
±2
±6
±1
2.7
2.25
±34
mV
mV
mV
mV
1.86
1.17
LSB rms
LSB rms
1
2
7
7
V p-p
V p-p
pF
kΩ
3.0
2.5
3.6
3.6
V
V
122
9
±0.01
138
mA
mA
% FSR
366
1.0
1
ppm/°C
ppm/°C
ppm/°C
mW
mW
With a 1.0 V internal reference.
Measured at the maximum clock rate, low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
3
Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 4 for the equivalent analog input structure.
4
Measured at ac specification conditions without output drivers.
5
Standby power is measured with a dc input, CLK pin inactive (that is, set to AVDD or AGND).
2
Rev. D | Page 4 of 32
AD9245
AC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, DCS off,
unless otherwise noted.
Table 3.
Parameter
SIGNAL-TO-NOISE RATIO (SNR)
fINPUT = 2.4 MHz
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 32.5 MHz
fINPUT = 100 MHz
SIGNAL-TO-NOISE RATIO AND DISTORTION (SINAD)
fINPUT = 2.4 MHz
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 32.5 MHz
fINPUT = 100 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 32.5 MHz
WORST HARMONIC (SECOND OR THIRD)
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 32.5 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fINPUT = 2.4 MHz
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 32.5 MHz
fINPUT = 100 MHz
AD9245BCP-20
Min
Typ
Max
AD9245BCP-40
Min
Typ
Max
AD9245BCP-65
Min
Typ
Max
73.5
73.3
73.5
73.1
70.6
70.5
70.3
69.4
71.3
72.7
70.2
73.4
73.2
73.4
73.0
70.0
72.6
67.9
dBc
dBc
dBc
dBc
dBc
11.7
Bits
Bits
Bits
–83
dBc
dBc
dBc
73.2
68.4
69.5
dBc
dBc
dBc
dBc
dBc
73.4
70.8
69.1
11.9
11.8
–89
–80
–89
80.0
92.0
89.0
–80
92.0
80.0
92.0
89.0
74.0
84.0
Rev. D | Page 5 of 32
85.0
Unit
83.0
80.5
–74
dBc
dBc
dBc
dBc
dBc
AD9245
AVDD = 3 V, DRVDD = 2.5 V, sample rate = 80 MSPS, 2 V p-p differential input, 1.0 V external reference, AIN = –0.5 dBFS, DCS off,
unless otherwise noted.
Table 4.
Parameter
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.4 MHz
fIN = 40 MHz
fIN = 70 MHz
fIN = 100 MHz
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 2.4 MHz
fIN = 40 MHz
fIN = 70 MHz
fIN = 100 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.4 MHz
fIN = 40 MHz
fIN = 70 MHz
fIN = 100 MHz
WORST HARMONIC (SECOND OR THIRD)
fIN = 2.4 MHz
fIN = 40 MHz
fIN = 70 MHz
fIN = 100 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 2.4 MHz
fIN = 40 MHz
fIN = 70 MHz
fIN = 100 MHz
Min
71.1
70.5
70.7
69.9
11.5
11.3
AD9245BCP-80
Typ
Max
73.3
72.7
71.7
70.2
dB
dB
dB
dB
73.2
72.5
71.2
69.6
dB
dB
dB
dB
11.9
11.8
11.5
11.3
Bits
Bits
Bits
Bits
−92.8
–87.6
−81.6
–79.0
76.5
75.7
Rev. D | Page 6 of 32
Unit
92.8
87.6
81.6
79.0
–76.5
–75.7
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
AD9245
DIGITAL SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, 1.0 V internal reference, unless otherwise noted.
Table 5.
Parameter
LOGIC INPUTS (CLK, PDWN)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
DIGITAL OUTPUT BITS (D0 to D13, OTR) 2
DRVDD = 3.3 V
High Level Output Voltage (IOH = 50 μA)
High Level Output Voltage (IOH = 0.5 mA)
Low Level Output Voltage (IOH = 1.6 mA)
Low Level Output Voltage (IOH = 50 μA)
DRVDD = 2.5 V
High Level Output Voltage (IOH = 50 μA)
High Level Output Voltage (IOH = 0.5 mA)
Low Level Output Voltage (IOH = 1.6 mA)
Low Level Output Voltage (IOH = 50 μA)
1
2
AD9245BCP-20/AD9245BCP-40/AD9245BCP-65/AD9245BCP-80 1
Min
Typ
Max
2.0
0.8
+10
+10
–10
–10
2
3.29
3.25
Rev. D | Page 7 of 32
V
V
μA
μA
pF
0.2
0.05
V
V
V
V
0.2
0.05
V
V
V
V
2.49
2.45
AD9245BCP-80 performance measured with 1.0 V external reference.
Output voltage levels measured with 5 pF load on each output.
Unit
AD9245
SWITCHING SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, unless otherwise noted.
Table 6.
Parameter
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Minimum Conversion Rate
CLK Period
CLK Pulse Width High 1
CLK Pulse Width Low1
DATA OUTPUT PARAMETERS
Output Delay 2 (tPD)
Pipeline Delay (Latency)
Aperture Delay (tA)
Aperture Uncertainty Jitter (tJ)
Wake-Up Time 3
OUT-OF-RANGE RECOVERY TIME
AD9245BCP-20
Min
Typ Max
AD9245BCP-40
Min
Typ Max
AD9245BCP-65
Min
Typ Max
AD9245BCP-80
Min
Typ Max
Unit
20
40
65
80
MSPS
MSPS
ns
ns
ns
1
50.0
15.0
15.0
1
25.0
8.8
8.8
3.5
7
1.0
0.5
3.0
1
1
1
15.4
6.2
6.2
3.5
7
1.0
0.5
3.0
1
12.5
4.6
4.6
3.5
7
1.0
0.5
3.0
2
4.2
7
1.0
0.3
7.0
2
1
ns
Cycles
ns
ps rms
ms
Cycles
For the AD9245BCP-65 and AD9245BCP-80 models only, with duty cycle stabilizer enabled. DCS function not applicable for AD9245BCP-20 and AD9245BCP-40
models.
2
Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output.
3
Wake-up time is dependent on value of decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB.
N
N+1
N+2
N–1
N+3
tA
ANALOG
INPUT
N+8
N+7
N+4
N+5
N+6
DATA
OUT
N–9
N–8
N–7
N–6
N–5
N–4
N–3
N–2
tPD = 6.0ns MAX
2.0ns MIN
Figure 2. Timing Diagram
Rev. D | Page 8 of 32
N–1
N
03583-002
CLK
AD9245
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter
With Respect to
ELECTRICAL
AVDD
AGND
DRVDD
DGND
AGND
DGND
AVDD
DRVDD
D0 to D13
DGND
CLK, MODE AGND
VIN+, VIN–
AGND
VREF
AGND
SENSE
AGND
REFT, REFB
AGND
PDWN
AGND
ENVIRONMENTAL
Storage Temperature Range
Operating Temperature Range
Lead Temperature
(Soldering 10 sec)
Junction Temperature
THERMAL RESISTANCE
Min
Max
Unit
–0.3
–0.3
–0.3
–3.9
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
+3.9
+3.9
+0.3
+3.9
DRVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
V
V
V
V
V
V
V
V
V
V
V
–65
–40
+125
+85
300
°C
°C
°C
150
°C
θJA is specified for the worst-case conditions on a 4-layer board
in still air, in accordance with EIA/JESD51-1.
Table 8. Thermal Resistance
Package Type
32-Lead LFCSP
θJA
32.5
θJC
32.71
Unit
°C/W
Airflow increases heat dissipation, effectively reducing θJA.
In addition, more metal directly in contact with the package
leads from metal traces, through holes, ground, and power
planes reduces the θJA. It is recommended that the exposed
paddle be soldered to the ground plane for the LFCSP package.
There is an increased reliability of the solder joints, and
maximum thermal capability of the package is achieved with
the exposed paddle soldered to the customer board.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. D | Page 9 of 32
AD9245
TERMINOLOGY
Analog Bandwidth (Full Power Bandwidth)
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Signal-to-Noise and Distortion (SINAD)1
The ratio of the rms input signal amplitude to the rms value of
the sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc.
Aperture Delay (tA)
The delay between the 50% point of the rising edge of the clock
and the instant at which the analog input is sampled.
Effective Number of Bits (ENOB)
The effective number of bits for a sine wave input at a given
input frequency can be calculated directly from its measured
SINAD using the following formula:
Aperture Uncertainty (Jitter, tJ)
The sample-to-sample variation in aperture delay.
ENOB =
Integral Nonlinearity (INL)
The deviation of each individual code from a line drawn from
negative full scale through positive full scale. The point used as
negative full scale occurs ½ LSB before the first code transition.
Positive full scale is defined as a level 1½ LSB beyond the last
code transition. The deviation is measured from the middle of
each particular code to the true straight line.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 14-bit resolution indicates that all 16,384
codes must be present over all operating ranges.
Offset Error
The major carry transition should occur for an analog value
½ LSB below VIN+ = VIN–. Offset error is defined as the
deviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value ½ LSB
above negative full scale. The last transition should occur at an
analog value 1½ LSB below the positive full scale. Gain error is
the deviation of the actual difference between first and last code
transitions and the ideal difference between first and last code
transitions.
Temperature Drift
The temperature drift for offset error and gain error specifies
the maximum change from the initial (25°C) value to the value
at TMIN or TMAX.
Power Supply Rejection Ratio
The change in full scale from the value with the supply at the
minimum limit to the value with the supply at its maximum limit.
Total Harmonic Distortion (THD) 1
The ratio of the rms input signal amplitude to the rms value of
the sum of the first six harmonic components.
(SINAD − 1.76 )
6.02
Signal-to-Noise Ratio (SNR)1
The ratio of the rms input signal amplitude to the rms value of
the sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc.
Spurious-Free Dynamic Range (SFDR)1
The difference in dB between the rms input signal amplitude
and the peak spurious signal. The peak spurious component
may or may not be a harmonic.
Two-Tone SFDR1
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.
Clock Pulse Width and Duty Cycle
Pulse width high is the minimum amount of time that the clock
pulse should be left in the Logic 1 state to achieve rated
performance. Pulse width low is the minimum time the clock
pulse should be left in the Logic 0 state. At a given clock rate,
these specifications define an acceptable clock duty cycle.
Minimum Conversion Rate
The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The clock rate at which parametric testing is performed.
Output Propagation Delay (tPD)
The delay between the clock rising edge and the time when all
bits are within valid logic levels.
Out-of-Range Recovery Time
The time it takes for the ADC to reacquire the analog input
after a transition from 10% above positive full scale to 10%
above negative full scale, or from 10% below negative full scale
to 10% below positive full scale.
1
AC specifications may be reported in dBc (degrades as signal levels are
lowered) or in dBFS (always related back to converter full scale).
Rev. D | Page 10 of 32
AD9245
25 REFB
26 REFT
DNC 1
24 VREF
CLK 2
23 SENSE
DNC 3
22 MODE
AD9245
PDWN 4
21 OTR
CSP
(LSB) D0 5
20 D13 (MSB)
TOP VIEW
(Not to Scale)
D1 6
19 D12
DRVDD 16
DGND 15
D9 14
D8 13
D7 12
D6 11
17 D10
D4 9
18 D11
D3 8
D5 10
D2 7
03583-022
27 AVDD
28 AGND
29 VIN+
30 VIN–
31 AGND
32 AVDD
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. LFCSP Pin Configuration
Table 9. Pin Function Descriptions
Pin No.
1, 3
2
4
5 to 14, 17 to 20
15
16
21
22
23
24
25
26
27, 32
28, 31
29
30
Mnemonic
DNC
CLK
PDWN
D0 (LSB) to D13 (MSB)
DGND
DRVDD
OTR
MODE
SENSE
VREF
REFB
REFT
AVDD
AGND
VIN+
VIN–
Description
Do Not Connect
Clock Input Pin
Power-Down Function Select
Data Output Bits
Digital Output Ground
Digital Output Driver Supply
Out-of-Range Indicator
Data Format Select and DCS Mode Selection (See Table 11)
Reference Mode Selection (See Table 10)
Voltage Reference Input/Output
Differential Reference (–)
Differential Reference (+)
Analog Power Supply
Analog Ground
Analog Input Pin (+)
Analog Input Pin (–)
Rev. D | Page 11 of 32
AD9245
EQUIVALENT CIRCUITS
DRVDD
AVDD
D13-D0,
OTR
03583-005
03583-003
VIN+, VIN–
Figure 4. Equivalent Analog Input Circuit
Figure 6. Equivalent Digital Output Circuit
AVDD
AVDD
CLK,
PDWN
03583-006
20kΩ
03583-004
MODE
Figure 5. Equivalent MODE Input Circuit
Figure 7. Equivalent Digital Input Circuit
Rev. D | Page 12 of 32
AD9245
TYPICAL PERFORMANCE CHARACTERISTICS
DUT = AD9245-80, AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate, DCS disabled, TA = 25°C, 2 V p-p differential input,
AIN = −0.5 dBFS, VREF = 1.0 V external, unless otherwise noted.
0
100
AIN = –0.5dBFS
SNR = 73.2dBc
ENOB = 11.8 BITS
SFDR = 92.8dBc
–10
–20
90
SFDR (dBc)
SNR/SFDR (dBc AND dBFS)
–40
–50
–60
–70
–80
–90
–100
SNR (dBFS)
80
70
SFDR = 90dBc
REFERENCE LINE
60
SNR (dBc)
–110
–120
0
5
10
15
20
25
FREQUENCY (MHz)
30
35
–20
–20
–15
–10
INPUT AMPLITUDE (dBFS)
100
AIN = –0.5dBFS
SNR = 72.7dBc
ENOB = 11.8 BITS
SFDR = 87.6dBc
–10
–25
–5
0
Figure 11. Single Tone SNR/SFDR vs. Input Amplitude (AIN) @ 2.5 MHz
Figure 8. Single Tone 8K FFT @ 2.5 MHz
0
40
–30
40
03583-033
03583-032
50
SFDR (dBFS)
90
SFDR (dBc)
SNR/SFDR (dBc AND dBFS)
–30
–40
–50
–60
–70
–80
–90
–100
SNR (dBFS)
80
70
SFDR = 90dBc
REFERENCE LINE
60
SNR (dBc)
03583-023
50
–110
–120
0
5
10
15
20
25
FREQUENCY (MHz)
30
35
Figure 9. Single Tone 8K FFT @ 39 MHz
0
40
–30
40
–20
–25
–20
–15
–10
INPUT AMPLITUDE (dBFS)
–5
0
Figure 12. Single Tone SNR/SFDR vs. Input Amplitude (AIN) @ 39 MHz
100
AIN = –0.5dBFS
SNR = 71.7dBc
ENOB = 11.5 BITS
SFDR = 81.6dBc
–10
03583-034
AMPLITUDE (dBFS)
–30
AMPLITUDE (dBFS)
SFDR (dBFS)
SFDR (DIFF)
90
SFDR (SE)
SNR/SFDR (dBc)
–40
–50
–60
–70
–80
SNR (DIFF)
80
70
SNR (SE)
–90
–100
–110
–120
0
5
10
15
20
25
FREQUENCY (MHz)
30
35
40
03583-025
60
03583-024
AMPLITUDE (dBFS)
–30
50
0
20
40
60
SAMPLE RATE (MSPS)
80
Figure 13. SNR/SFDR vs. Sample Rate @ 40 MHz
Figure 10. Single Tone 8K FFT @ 70 MHz
Rev. D | Page 13 of 32
100
AD9245
100
0
AIN = –6.5dBFS
SNR = 73.4dBFS
SFDR = 86.0dBFS
–10
–20
SFDR (dBFS)
90
SFDR (dBc)
SNR/SFDR (dBc AND dBFS)
–40
–50
–60
–70
–80
–90
80
70
SNR (dBFS)
SNR (dBc)
03583-029
–110
–120
0
5
10
15
20
25
FREQUENCY (MHz)
30
35
40
–30
40
03583-031
50
–100
–27
–24
–21
–18
–15
–12
INPUT AMPLITUDE (dBFS)
–9
–6
Figure 17. Two-Tone SNR/SFDR vs. Input Amplitude @ 30 MHz and 31 MHz
Figure 14. Two-Tone 8K FFT @ 30 MHz and 31 MHz
100
0
SFDR (dBFS)
AIN = –6.5dBFS
SNR = 72.7dBFS
SFDR = 78.8dBFS
–10
–20
90
SFDR (dBc)
SNR/SFDR (dBc AND dBFS)
–30
AMPLITUDE (dBFS)
SFDR = 90dBc
REFERENCE LINE
60
–40
–50
–60
–70
–80
–90
80
70
SNR (dBFS)
SFDR = 90dBc
REFERENCE LINE
60
SNR (dBc)
50
03583-030
–100
–110
–120
0
5
10
15
20
25
FREQUENCY (MHz)
30
35
40
–30
40
Figure 15. Two-Tone 8K FFT @ 69 MHz and 70 MHz
03583-027
AMPLITUDE (dBFS)
–30
–27
–24
–21
–18
–15
INPUT AMPLITUDE (dBFS)
–12
–9
–6
Figure 18. Two-Tone SNR/SFDR vs. Input Amplitude @ 69 MHz and 70 MHz
1.5
1.0
0.8
1.0
0.6
0.4
DNL (LSB)
0
–0.5
0.2
0
–0.2
–0.4
–1.5
0
2048
4096
6144
8192
CODE
03583-028
–0.6
–1.0
03583-026
INL (LSB)
0.5
–0.8
–1.0
10240 12288 14336 16384
Figure 16. Typical INL
0
2048
4096
6144
8192 10240 12288 14336 16384
CODE
Figure 19. Typical DNL
Rev. D | Page 14 of 32
AD9245
75
100
74
–40°C
73
95
+25°C
90
71
SFDR (dBc)
+85°C
70
69
85
–40°C
80
68
+25°C
+85°C
67
03583-036
75
66
65
0
25
50
75
INPUT FREQUENCY (MHz)
70
125
100
03583-038
SNR (dBc)
72
0
Figure 20. SNR vs. Input Frequency
25
50
75
INPUT FREQUENCY (MHz)
100
125
Figure 23. SFDR vs. Input Frequency
0
90
SFDR (DCS ON)
–10
88
–20
86
–30
AMPLITUDE (dBFS)
SNR/SFDR (dBc)
84
SFDR (DCS OFF)
82
80
78
76
–40
–50
–60
–70
–80
–90
03583-037
70
30
SNR (DCS ON)
35
40
45
50
55
DUTY CYCLE (%)
60
65
–110
–120
0
70
–10
–20
–20
–30
–30
AMPLITUDE (dBFS)
–10
–40
–50
–60
–70
–80
28.8
38.4
–40
–50
–60
–70
–80
–90
–90
–100
–100
03583-059
AMPLITUDE (dBFS)
0
–110
–120
19.2
19.2
Figure 24. Two 32K FFT CDMA-2000 Carriers @
FIN = 46.08 MHz; Sample Rate = 61.44 MSPS
0
9.6
9.6
FREQUENCY (MHz)
Figure 21. SNR/SFDR vs. Clock Duty Cycle
0
03583-060
–100
SNR (DCS OFF)
72
28.8
03583-061
74
–110
–120
38.4
0
9.6
19.2
28.8
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 22. 32K FFT WCDMA Carrier @ FIN = 96 MHz; Sample Rate = 76.8 MSPS
Rev. D | Page 15 of 32
Figure 25. Two 32K FFT WCDMA Carriers @
FIN = 76.8 MHz; Sample Rate = 61.44 MSPS
38.4
AD9245
0
0
AIN = –0.5dBFS
SNR = 72.7dBc
ENOB = 11.7 BITS
SFDR = 81.3dBc
AIN = –0.5dBFS
SNR = 73.4dBc
ENOB = 11.9 BITS
SFDR = 88.3dBc
–20
AMPLITUDE (dBFS)
–40
–60
–80
–100
–40
–60
–80
03583-062
–100
–120
0
5
10
15
20
FREQUENCY (MHz)
25
30
03583-065
AMPLITUDE (dBFS)
–20
–120
0
2
4
6
8
10
12
14
FREQUENCY (MHz)
16
18
20
Figure 29. AD9245-40 Single Tone 16K FFT @ 19.7 MHz
Figure 26. AD9245-65 Single Tone 16K FFT @ 35 MHz
2.0
1.0
1.5
0.8
0.6
1.0
0.4
DNL (LSB)
INL (LSB)
0.5
0
–0.5
0.2
0
–0.2
–0.4
–1.0
03583-063
–2.0
0
2048
4096
6144
03583-066
–0.6
–1.5
–0.8
–1.0
8192 10240 12288 14336 16384
CODE
0
2048
Figure 27. AD9245-65 Typical INL
4096
6144
8192 10240 12288 14336 16384
CODE
Figure 30. AD9245-65 Typical DNL
2.0
1.0
1.5
0.8
0.6
1.0
0.4
DNL (LSB)
0
–0.5
0.2
0
–0.2
–0.4
–1.0
–2.0
0
2048
4096
6144
8192 10240 12288 14336 16384
CODE
03583-067
–0.6
–1.5
03583-064
INL (LSB)
0.5
–0.8
–1.0
Figure 28. AD9245-40 Typical INL
0
2048
4096
6144
8192 10240 12288 14336 16384
CODE
Figure 31. AD9245-40 Typical DNL
Rev. D | Page 16 of 32
AD9245
2.0
1.0
1.5
0.8
0.6
1.0
0.4
DNL (LSB)
INL (LSB)
0.5
0
–0.5
0.2
0
–0.2
–0.4
–1.0
–1.5
03583-071
–0.6
–0.8
–1.0
–2.0
0
2048
4096
6144
8192 10240 12288 14336 16384
CODE
0
2048
Figure 32. AD9245-20 Typical INL
6144
8192 10240 12288 14336 16384
CODE
Figure 35. AD9245-20 Typical DNL
0
0
AIN = –0.5dBFS
SNR = 73.4dBc
ENOB = 11.9 BITS
SFDR = 95.0dBc
AIN = –0.5dBFS
SNR = 73.3dBc
ENOB = 11.9 BITS
SFDR = 92.6dBc
–20
AMPLITUDE (dBFS)
–20
–40
–60
–80
–100
–40
–60
–80
–120
0
1
2
3
4
5
6
FREQUENCY (MHz)
7
8
9
03583-072
03583-069
–100
–120
10
0
Figure 33. AD9245-20 Single Tone 16K FFT @ 5 MHz
1
2
3
4
5
6
FREQUENCY (MHz)
7
9
10
547498
03583-073
AMPLITUDE (dBFS)
4096
8
Figure 36. AD9245-20 Single Tone 16K FFT @ 9.7 MHz
75
10004707
–0.5dBFS
70
7996189
7281624
HITS
65
60
3167101
1755666
55
–20dBFS
50
1
10
INPUT FREQUENCY (MHz)
03583-070
SINAD (dBc)
–6dBFS
100
253625
N–3
N–2
N–1
N
CODE
N+1
N+2
Figure 37. AD9245-20 Grounded-Input Histogram
Figure 34. AD9245-20 SINAD vs. Input Frequency
Rev. D | Page 17 of 32
N+3
AD9245
THEORY OF OPERATION
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
The input stage contains a differential SHA that can be
ac-coupled or dc-coupled in differential or single-ended modes.
The output staging block aligns the data, carries out the error
correction, and passes the data to the output buffers. The output
buffers are powered from a separate supply, allowing adjustment of
the output voltage swing. During power-down, the output
buffers go into a high impedance state.
Referring to Figure 39, the clock signal alternately switches the
SHA between sample mode and hold mode. When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source. In addition, a small shunt capacitor
can be placed across the inputs to provide dynamic charging
currents. This passive network creates a low-pass filter at the
ADC’s input; therefore, the precise values are dependent upon
the application. In IF undersampling applications, any shunt
capacitors should be reduced or removed. In combination with
the driving source impedance, they would limit the input
bandwidth.
H
T
CPAR
T
5pF
VIN–
CPAR
Figure 39. Switched-Capacitor SHA Input
The analog input to the AD9245 is a differential switchedcapacitor SHA that has been designed for optimum performance
while processing a differential input signal. The SHA input can
support a wide common-mode range (VCM) and maintain
excellent performance, as shown in Figure 38. An input
common-mode voltage of midsupply minimizes signaldependent errors and provides optimum performance.
100
95
For best dynamic performance, the source impedances driving
VIN+ and VIN– should be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC.
An internal differential reference buffer creates positive and
negative reference voltages, REFT and REFB, that define the
span of the ADC core. The output common mode of the
reference buffer is set to midsupply, and the REFT and REFB
voltages and span are defined as:
REFT = ½ (AVDD + VREF)
SFDR (2.5MHz)
REFB = ½ (AVDD − VREF)
85
SFDR (39MHz)
Span = 2 × (REFT − REFB) = 2 × VREF
80
75
SNR (2.5MHz)
70
SNR (39MHz)
The previous equations show that the REFT and REFB voltages
are symmetrical about the midsupply voltage, and, by definition,
the input span is twice the value of the VREF voltage.
65
60
03583-039
SNR/SFDR (dBc)
T
H
ANALOG INPUT AND REFERENCE OVERVIEW
90
T
5pF
VIN+
03583-012
The AD9245 architecture consists of a front-end sample-andhold amplifier (SHA) followed by a pipelined switched capacitor
ADC. The pipelined ADC is divided into three sections
consisting of a 4-bit first stage followed by eight 1.5-bit stages,
and a final 3-bit flash. Each stage provides sufficient overlap to
correct for flash errors in the preceding stages. The quantized
outputs from each stage are combined into a final 14-bit result
in the digital correction logic. The pipelined architecture
permits the first stage to operate on a new input sample, while
the remaining stages operate on preceding samples. Sampling
occurs on the rising edge of the clock.
55
50
0.5
1.0
1.5
2.0
COMMON-MODE LEVEL (V)
2.5
Figure 38. AD9245-80 SNR/SFDR vs. Common-Mode Level
3.0
The internal voltage reference can be pin strapped to fixed
values of 0.5 V or 1.0 V, or adjusted within the same range as
discussed in the Internal Reference Connection section.
Maximum SNR performance is achieved with the AD9245 set
to the largest input span of 2 V p-p. The relative SNR degradation
is 3 dB when changing from 2 V p-p mode to 1 V p-p mode.
Rev. D | Page 18 of 32
AD9245
The SHA can be driven from a source that keeps the signal
peaks within the allowable range for the selected reference
voltage. The minimum and maximum common-mode input
levels are defined as
VIN+
2V p-p
49.9Ω
20pF
VREF
=
2
VCM MAX =
33Ω
( AVDD + VREF )
AD9245
VIN–
AGND
1kΩ
2
0.1μF
The minimum common-mode input level allows the AD9245 to
accommodate ground referenced inputs.
03583-014
VCM MIN
AVDD
33Ω
1kΩ
Figure 41. Differential Transformer-Coupled Configuration
Differential Input Configurations
As previously detailed, optimum performance is achieved while
driving the AD9245 in a differential input configuration. For
baseband applications, the AD8351 differential driver provides
excellent performance and a flexible interface to the ADC. The
output common-mode voltage of the AD8351 is easily set to
AVDD/2, and the driver can be configured in a Sallen-Key filter
topology to provide band limiting of the input signal.
The signal characteristics must be considered when selecting
a transformer. Most RF transformers saturate at frequencies
below a few MHz, and excessive signal power can also cause
core saturation, which leads to distortion.
Single-Ended Input Configuration
A single-ended input can provide adequate performance in
cost-sensitive applications. In this configuration, there is a
degradation in SFDR and distortion performance due to the
large input common-mode swing (see Figure 13). However, if
the source impedances on each input are matched, there should
be little effect on SNR performance. Figure 42 details a typical
single-ended input configuration.
1kΩ
2V p-p
33Ω
0.33μF 1kΩ
49.9Ω
20pF
1kΩ
1kΩ
0.1μF
1.2kΩ
0.1μF
2V p-p
50Ω
25Ω
+
33Ω
20pF
AD8351
10μF
AVDD
AD9245
1kΩ
VIN–
AGND
VIN–
1kΩ
AGND
Figure 42. Single-Ended Input Configuration
03583-013
0.1μF
33Ω
AD9245
VIN+
0.1μF 33Ω
25Ω
0.1μF
AVDD
VIN+
03583-015
Although optimum performance is achieved with a differential
input, a single-ended source can be applied to VIN+ or VIN–.
In this configuration, one input accepts the signal, while the
opposite input is set to midscale by connecting it to an
appropriate reference. For example, a 2 V p-p signal can be
applied to VIN+ while a 1 V reference is applied to VIN–. The
AD9245 then accepts an input signal varying between 2 V and
0 V. In the single-ended configuration, distortion performance
can degrade significantly as compared to the differential case.
However, the effect is less noticeable at lower input frequencies.
Figure 40. Differential Input Configuration Using the AD8351
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers is not adequate to achieve the
true performance of the AD9245. This is especially true in IF
undersampling applications where frequencies in the 70 MHz to
100 MHz range are being sampled. For these applications,
differential transformer coupling is the recommended input
configuration. The value of the shunt capacitor is dependent on
the input frequency and source impedance and should be
reduced or removed. An example is shown in Figure 41.
CLOCK INPUT CONSIDERATIONS
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals, and as a result can be sensitive
to clock duty cycle. Commonly a 5% tolerance is required on the
clock duty cycle to maintain dynamic performance characteristics.
The AD9245-80 and AD9245-65 contain a clock duty cycle
stabilizer (DCS) that retimes the nonsampling edge, providing an
internal clock signal with a nominal 50% duty cycle. This allows a
wide range of clock input duty cycles without affecting the
performance of the AD9245. As shown in Figure 21, noise and
distortion performance is nearly flat for a 30% to 70% duty cycle
with the DCS on.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately 100 clock cycles to
allow the DLL to acquire and lock to the new rate.
Rev. D | Page 19 of 32
AD9245
which is determined by the sample rate and the characteristics
of the analog input signal.
JITTER CONSIDERATIONS
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given input
frequency (fINPUT) due only to aperture jitter (tJ) can be
calculated with the following equation:
450
400
AD9245-80
SNR = −20log10[2π fINPUT × tj]
The clock input should be treated as an analog signal in cases
where aperture jitter can affect the dynamic range of the
AD9245. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other
methods), it should be retimed by the original clock at the last step.
75
0.2ps
70
AD9245-65
250
200
AD9245-40
150
AD9245-20
100
50
0
10
20
30
40
50
SAMPLE RATE (MSPS)
60
70
80
Figure 44. AD9245 Power vs. Sample Rate @ 2.5 MHz
Reducing the capacitive load presented to the output drivers can
minimize digital power consumption. The data in Figure 44 was
taken with the same operating conditions as those reported in
the Typical Performance Characteristics section, and with a
5 pF load on each output driver.
MEASURED SNR
65
By asserting the PDWN pin high, the AD9245 is placed in
standby mode. In this state, the ADC typically dissipates
1 mW if the CLK and analog inputs are static. During standby,
the output drivers are placed in a high impedance state.
Reasserting the PDWN pin low returns the AD9245 to its
normal operational mode.
0.5ps
SNR (dBc)
300
03583-074
In the equation, the rms aperture jitter represents the rootmean square of all jitter sources, which include the clock input,
analog input signal, and ADC aperture jitter specification. IF
undersampling applications are particularly sensitive to jitter
(see Figure 43).
TOTAL POWER (mW)
350
60
1.0ps
1.5ps
55
2.0ps
2.5ps
50
3.0ps
03583-041
45
40
1
10
100
INPUT FREQUENCY (MHz)
1000
Figure 43. SNR vs. Input Frequency and Jitter
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 44, the power dissipated by the AD9245 is
proportional to its sample rate. The digital power dissipation is
determined primarily by the strength of the digital drivers and
the load on each output bit. The maximum DRVDD current
(IDRVDD) can be calculated as
I DRVDD = VDRVDD × C LOAD × f CLK × N
where N is the number of output bits, 14 in the case of the
AD9245. This maximum current occurs when every output bit
switches on every clock cycle, that is, a full-scale square wave at
the Nyquist frequency, fCLK/2. In practice, the DRVDD current
is established by the average number of output bits switching,
Low power dissipation in standby mode is achieved by shutting
down the reference, reference buffer, and biasing networks. The
decoupling capacitors on REFT and REFB are discharged when
entering standby mode and then must be recharged when
returning to normal operation. As a result, the wake-up time is
related to the time spent in standby mode, and shorter standby
cycles result in proportionally shorter wake-up times. With the
recommended 0.1 μF and 10 μF decoupling capacitors on REFT
and REFB, it takes approximately 1 second to fully discharge the
reference buffer decoupling capacitors and 7 ms to restore full
operation.
DIGITAL OUTPUTS
The AD9245 output drivers can be configured to interface with
2.5 V or 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies, which can affect converter performance.
Applications requiring the ADC to drive large capacitive loads or
large fanouts can require external buffers or latches.
Rev. D | Page 20 of 32
AD9245
As detailed in Table 11, the data format can be selected for either
offset binary or twos complement.
TIMING
The AD9245 provides latched data outputs with a pipeline delay
of seven clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of the clock signal. Refer to
Figure 2 for a detailed timing diagram.
In all reference configurations, REFT and REFB drive the A/D
conversion core and establish its input span. The input range of
the ADC always equals twice the voltage at the reference pin for
either an internal or an external reference.
VIN+
VIN–
The length of the output data lines and the loads placed on
them should be minimized to reduce transients within the
AD9245. These transients can degrade the converter’s dynamic
performance.
The lowest typical conversion rate of the AD9245 is 1 MSPS. At
clock rates below 1 MSPS, dynamic performance can degrade.
REFT
0.1μF
ADC
CORE
0.1μF
+
10μF
REFB
0.1μF
VREF
10μF
+
0.1μF
SELECT
LOGIC
SENSE
VOLTAGE REFERENCE
If the ADC is being driven differentially through a transformer,
the reference voltage can be used to bias the center tap
(common-mode voltage).
0.5V
03583-017
A stable and accurate 0.5 V voltage reference is built into the
AD9245. The input range can be adjusted by varying the
reference voltage applied to the AD9245 using either the
internal reference or an externally applied reference voltage.
The input span of the ADC tracks reference voltage changes
linearly. The various reference modes are summarized in Table 10
and described in the following sections.
AD9245
Figure 45. Internal Reference Configuration
If the internal reference of the AD9245 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 46 depicts
how the internal reference voltage is affected by loading. A
2 mA load is the maximum recommended load.
INTERNAL REFERENCE CONNECTION
0.05
0
–0.05
R2 ⎞
VREF = 0.5 × ⎛⎜1 +
⎟
⎝ R1 ⎠
0.5V ERROR (%)
–0.10
1.0V ERROR (%)
–0.15
–0.20
03583-019
ERROR (%)
A comparator within the AD9245 detects the potential at the
SENSE pin and configures the reference into one of four
possible states, which are summarized in Table 10. If SENSE is
grounded, the reference amplifier switch is connected to the
internal resistor divider (see Figure 45), setting VREF to 1 V.
Connecting the SENSE pin to VREF switches the reference
amplifier output to the SENSE pin, completing the loop and
providing a 0.5 V reference output. If a resistor divider is
connected as shown in Figure 47, the switch is again set to the
SENSE pin. This puts the reference amplifier in a noninverting
mode with the VREF output defined as
–0.25
0
0.5
1.0
1.5
LOAD (mA)
2.0
2.5
Figure 46. VREF Accuracy vs. Load
Table 10. Reference Configuration Summary
Selected Mode
External Reference
Internal Fixed Reference
Programmable Reference
SENSE Voltage
AVDD
VREF
0.2 V to VREF
Resulting VREF (V)
N/A
0.5
Internal Fixed Reference
AGND to 0.2 V
1.0
R2 ⎞ (See Figure 47)
0.5 × ⎛⎜ 1 +
⎟
R1 ⎠
⎝
Resulting Differential Span (V p-p)
2 × External Reference
1.0
2 × VREF
2.0
Rev. D | Page 21 of 32
3.0
AD9245
OPERATIONAL MODE SELECTION
VIN+
VIN–
REFT
0.1μF
ADC
CORE
0.1μF
+
10μF
REFB
0.1μF
VREF
+
10μF
0.1μF
Table 11. Mode Selection
SELECT
LOGIC
R2
MODE Voltage
AVDD
2/3 AVDD
1/3 AVDD
AGND (Default)
SENSE
R1
03583-018
0.5V
AD9245
EXTERNAL REFERENCE OPERATION
The use of an external reference can be necessary to enhance
the gain accuracy of the ADC or improve thermal drift characteristics. When multiple ADCs track one another, a single
reference (internal or external) can be necessary to reduce
gain matching errors to an acceptable level. Figure 48 shows
the typical drift characteristics of the internal reference in both
1.0 V and 0.5 V modes.
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7 kΩ load. The internal buffer still generates the positive and
negative full-scale references, REFT and REFB, for the ADC
core. The input span is always twice the value of the reference
voltage; therefore, the external reference must be limited to a
maximum of 1.0 V.
1.0
0.9
0.8
0.7
It is critical that signal sources with very low phase noise
(<1 ps rms jitter) be used to realize the ultimate performance of
the converter. Proper filtering of the input signal, to remove
harmonics and lower the integrated noise at the input, is also
necessary to achieve the specified noise performance.
The AD9245 can be driven single-ended or differentially
through a transformer. Separate power pins are provided to
isolate the DUT from the support circuitry. Each input
configuration can be selected by proper connection of
various jumpers (refer to the schematics).
An alternative differential analog input path using an
AD8351 op amp is included in the layout but is not populated
in production. Designers interested in evaluating the op amp
with the ADC should remove C15, R12, and R3 and populate
the op amp circuit. The passive network between the AD8351
outputs and the AD9245 allows the user to optimize the
frequency response of the op amp for the application.
0.5
0.4
0.3
VREF = 1.0V
03583-040
0.2
VREF = 0.5V
0
–40 –30 –20 –10
0
10 20 30 40 50
TEMPERATURE (°C)
60
Duty Cycle Stabilizer
Disabled
Enabled
Enabled
Disabled
The AD9245 evaluation board provides the support circuitry
required to operate the ADC in its various modes and
configurations. Complete schematics and layout plots follow
and demonstrate the proper routing and grounding techniques
that should be applied at the system level.
0.6
0.1
Data Format
Twos Complement
Twos Complement
Offset Binary
Offset Binary
EVALUATION BOARD
Figure 47. Programmable Reference Configuration
VREF ERROR (%)
As discussed earlier, the AD9245 can output data in either
offset binary or twos complement format. There is also a
provision for enabling or disabling the clock DCS. The
MODE pin is a multilevel input that controls the data format
and DCS state. The input threshold values and corresponding
mode selections are outlined in Table 11.
70
80
Figure 48. Typical VREF Drift
Rev. D | Page 22 of 32
Figure 49. LFCSP Evaluation Board Schematic—Analog Inputs and DUT
L1
10nH
C6
0.1μF
GND
R11
36Ω
R18
25Ω
AMPINB
0.1μF
C11
R2
DNP
C18
0.10μF
GND
GND
C21
10pF
R15
33Ω
AVDD
R13
1kΩ
C23
10pF
P4
P3
R25
1kΩ
GND
AVDD
3
2
4
P1
AVDD
GND
VIN+
VIN–
R6
1kΩ
R7
1kΩ
R5
1kΩ
GND
GND
20pF C19
OR L1
FOR FILTER
GND
R4
33Ω
R36
1kΩ
R26
1kΩ
C22
10μF
GND GND
C13
0.10μF
AVDD
GND
D
P11
R SINGLE ENDED
R3
0Ω
GND
C5
0.1μF
C26
10pF
R12
0Ω
R3, R16, C18
ONLY ONE SHOULD BE
ON BOARD AT A TIME
XOUTB
GND
C16
0.1μF
R10
36Ω
E 45
XOUT
AMPIN
P10
C
C29
10μF
C7
0.1μF
GND
C9
0.10μF
E
P7 A B
GND
P9 P8
R12, R42, C17
ONLY ONE SHOULD BE
ON BOARD AT A TIME
6
2 CT
4
PRI SEC
XFRIN1 1
5
NC
3
GND
PRI SEC
R42
0Ω
T1
ADT1–1WT
OPTIONAL XFR
T2
FT C1–1–13
5
1
XOUT
X FRIN
2
CT
3
4
GND
XOUTB
C15
AMP 0.1μF
03583-050
GND
J1
GND
0.1μF
C12
FOR SINGLE ENDED INPUT
PLACE R18, R19, R42, C6, AND C18.
REMOVE R3, R12, C15, C17, AND C27
GND
R9
10kΩ
R1
10kΩ
AVDD
P6
MODE
2
P5
24
1
23
22
GND
31 AGND
32 AVDD
28 AGND
29 VIN+
30 VIN–
25 REFB
26 REFT
27 AVDD
AVDD
P14
CLK
1 DNC
2 CLK
GND
C8
0.1μF
U4
AD9245
P13
R8
1kΩ
15
14
16
GND
D5 10
D4 9
13
D7 12
D6 11
DVDD
DGND
D9
D8
D12 19
D11 18
D10 17
1
AVDD
4
GND
3
2.5V DRVDD
2
GND
VDL
2.5V
(LSB)
6
5
RP1 220Ω
13
12
11
10
9
4
6
7
8
15
14
5
16
2
3
10
9
7
8
1
12
11
5
6
13
15
14
4
16
MODE PIN SOLDERABLE JUMPER:
5 TO 1: TWOS COMPLEMENT/DCS OFF
5 TO 2: TWOS COMPLEMENT/DCS ON
5 TO 3: OFFSET BINARY/DCS ON
5 TO 4: OFFSET BINARY/DCS OFF
D0X
D2X
D1X
D4X
D3X
D6X
D5X
D8X
D7X
D9X
D10X
D12X
D11X
DRX
D13X
H4
MTHOLE6
H3
MTHOLE6
H2
MTHOLE6
H1
MTHOLE6
2
3
RP2 220Ω
GND
1
P2
SENSE PIN SOLDERABLE JUMPER:
E TO A: EXTERNAL VOLTAGE DIVIDER
E TO B: INTERNAL 1V REFERENCE (DEFAULT)
E TO C: EXTERNAL REFERENCE
E TO D: INTERNAL 0.5V REFERENCE
DRVDD
GND
(MSB)
OVERRANGE BIT
3.0V
AVDD
21
D13 20
VREF
SENSE
MODE
OTR
3 DNC
4 PDWN
Rev. D | Page 23 of 32
5 D0
6 D1
7 D2
8 D3
VAMP
5.0V
EXTREF
1V MAX E1
AD9245
Figure 50. LFCSP Evaluation Board Schematic—Digital Path
Rev. D | Page 24 of 32
D11X
GND
D12X
DRX
D13X
2DB
2CLK
1
U1
GND
R19
50Ω
AMP
2OE
CC
GND
GND
DRVDD
GND
GND
DRVDD
GND
GND
C35
0.10μF
R33 RPG2 5
25Ω
INLO 4
INHI 3
PWDN 1
RGP1 2
TO USE AMPLIFIER
PLACE ALL COMPONENTS
SHOWN HERE (RIGHT)
EXCEPT R40 OR R41.
REMOVE R12, R3, R18, R42,
C6, C15, AND C18.
OUT
1Q4 7
6
1Q3
5
GND
4
1Q2
3
1Q1
1OE 2
1
C28
0.1μF
R35
25Ω
24
23
2Q7
22
GND
21
2Q6
20
2Q5
19
VCC
18
2Q4
17
2Q3
16
GND
15
2Q2
14
2Q1
13
1Q8
12
1Q7
11
GND
10
1Q6
9
1Q5
8
V
2QB
R40
10kΩ
GND
GND
R41
10kΩ
VAMP
POWER DOWN
USE R40 OR R41
IN
26
2D7
27
GND
28
2D6
29
2D5
30
V
31 CC
2D4
32
2D3
33
GND
34
2D2
35
2D1
36
1D8
37
1D7
38
GND
39
1D6
40
1D5
41
VCC
42
1D4
43
1D3
44
GND
45
1D2
46
1D1
47 1CLK
48
25
AMP IN
CLKLAT/DAC
GND
D0X
D2X
D1X
DRVDD
D4X
D3X
GND
D7X
D6X
D5X
GND
D8X
D10X
D9X
DRVDD
03583-051
LSB
MSB
CLKAT/DAC
74LVTH162374
R34
1.2kΩ
U3
AD8351
GND
VAMP
DRY
6 COMM
7 OPLO
9 VPOS
8 OPHI
10 VOCM
C44
0.1μF
R38
1kΩ
GND
R14
25Ω
VAMP
R39
1kΩ
C45
0.1μF
C24
10μF
R17
0Ω
R16
0Ω
GND
GND
GND
MSB
GND
C17
0.1μF
C27
0.1μF
GND
DRY
GND
DR
AMPINB
AMPIN
11
11
9
7
3
5
1
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
9
12
7
8
10
3
5
1
4
6
2
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
12
10
8
4
6
2
P12
GND
AD9245
C4
10μF
03583-052
AVDD
GND
C3
10μF
Figure 51. LFCSP Evaluation Board Schematic—Clock Input
Rev. D | Page 25 of 32
J2
GND
C25
10μF
R29
50Ω
C43
0.1μF
ENC
ENCX
GND
R30
1kΩ
R31
1kΩ
VDL
R27
0Ω
R28
0Ω
VDL
VDL
E43
E44
E35
E51
E52
VDL
E31
VDL
E50
CLK
FOR A BUFFERED ENCODE USE R28
FOR A DIRECT ENCODE USE R27
ENC
C33
C14
0.1μF 0.001μF
ANALOG BYPASSING
C32
0.001μF
CLOCK TIMING ADJUSTMENTS
GND
AVDD
GND
ENCODE
DUT BYPASSING
C10
10μF
VDL DRVDD
R20
1kΩ
GND
R24
1kΩ
GND
R21
1kΩ
GND
E53
GND
R32
1kΩ
GND
DRVDD
C41
0.1μF
C30
0.001μF
5
9
10
12
13
3A
3B
4A
4B
2B
1 1A
2 1B
4 2A
C31
0.1μF
U5
4Y
3Y
2Y
1Y
74VCX86
DIGITAL BYPASSING
C2
10μF
PWR
GND
14
8
11
6
7
3
C34
0.1μF
VDL
GND
ENCX
C36
0.1μF
R23
0Ω
C1
C39
0.001μF 0.1μF
CLKLAT/DAC
R37
0Ω
Rx
DNP
VDL
DR
R22
0Ω
GND
C49
0.001μF
LATCH BYPASSING
C47
0.1μF
SCHEMATIC SHOWS TWO GATE DELAY SETUP.
FOR ONE DELAY, REMOVE R22 AND R37 AND
ATTACH Rx (Rx = 0Ω).
C38
0.001μF
C48
0.001μF
GND
VAMP
C20
10μF
C46
10μF
C37
0.1μF
C40
0.001μF
AD9245
03583-053
03583-055
AD9245
Figure 52. LFCSP Evaluation Board Layout, Primary Side
03583-054
03583-056
Figure 54. LFCSP Evaluation Board Layout, Ground Plane
Figure 53. LFCSP Evaluation Board Layout, Secondary Side
Figure 55. LFCSP Evaluation Board Layout, Power Plane
Rev. D | Page 26 of 32
03583-058
03583-057
AD9245
Figure 56. LFCSP Evaluation Board Layout, Primary Silkscreen
Figure 57. LFCSP Evaluation Board Layout, Secondary Silkscreen
Rev. D | Page 27 of 32
AD9245
Table 12. LFCSP Evaluation Board Bill of Materials
Item Qty. Omit 1 Reference Designator
1
18
C1, C5, C7, C8, C9, C11, C12,
C13, C15, C16, C31, C33, C34,
C36, C37, C41, C43, C47
8
C6, C17, C18, C27,
C28, C35, C45, C44
2
8
C2, C3, C4, C10, C20,
C22, C25, C29
2
C24, C46
3
8
C14, C30, C32, C38,
C39, C40, C48, C49
4
1
C19
Device
Chip Capacitors
Package
0603
Value
0.1 μF
Tantalum Capacitors
TAJC
10 μF
Chip Capacitors
0603
0.001 μF
Chip Capacitors
0603
20 pF
5
Chip Capacitors
0603
10 pF
Headers
EHOLE
1
C26
2
C21, C23
E31, E35, E43, E44,
E50, E51, E52, E53
E1, E45
6
9
7
8
2
1
J1, J2
L1
SMA Connectors/50 Ω
Inductor
SMA
0603
9
1
P2
Terminal Block
TB6
10
1
P12
Header Dual 20-Pin RT Angle
HEADER40
11
5
R3, R12, R23, R28, Rx
Chip Resistors
0603
R16, R17, R22, R27, R42, R37
R4, R15
2
6
Supplied
by ADI
Jumper Blocks
10 nH
Coilcraft/
0603CS-10NXGBU
Wieland/25.602.2653.0,
z5-530-0625-0
Digi-Key S2131-20-ND
0Ω
12
2
Chip Resistors
0603
33 Ω
13
14
Chip Resistors
R5, R6, R7, R8, R13, R20, R21,
R24, R25, R26, R30, R31, R32, R36
0603
1 kΩ
14
2
R10, R11
Chip Resistors
0603
36 Ω
15
1
R29
Chip Resistors
0603
50 Ω
16
2
R19
RP1, RP2
Resistor Packs
R_742
220 Ω
17
1
T1
ADT1-1WT
AWT1-1T
18
1
U1
74LVTH162374 CMOS Register TSSOP-48
19
1
U4
AD9245BCP ADC (DUT)
1
Recommended
Vendor/Part No.
LFCSP-32
Digi-Key
CTS/742C163221JTR
Mini-Circuits
Analog Devices, Inc.
X
20
1
U5
74VCX86M
SOIC-14
Fairchild
21
1
PCB
AD92XXBCP/PCB
PCB
Analog Devices, Inc.
X
X
22
1
U3
AD8351 Op Amp
MSOP-8
Analog Devices, Inc.
23
1
T2
M/A-COM Transformer
ETC1-1-13 1-1 TX
M/A-COM/ETC1-1-13
24
5
R1, R2, R9, R38, R39
Chip Resistors
0603
SELECT
25
3
R14, R18, R35
Chip Resistors
0603
25 Ω
0603
10 kΩ
26
2
R40, R41
Chip Resistors
27
1
R34
Chip Resistor
1.2 kΩ
28
1
R33
Chip Resistor
25 Ω
Total 81
35
1
These items are included in the PCB design, but are omitted at assembly.
Rev. D | Page 28 of 32
AD9245
OUTLINE DIMENSIONS
0.60 MAX
5.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
TOP
VIEW
0.50
BSC
4.75
BSC SQ
0.50
0.40
0.30
32
1
3.25
3.10 SQ
2.95
EXPOSED
PAD
(BOTTOM VIEW)
17
16
9
8
0.25 MIN
3.50 REF
0.80 MAX
0.65 TYP
12° MAX
1.00
0.85
0.80
PIN 1
INDICATOR
25
24
0.05 MAX
0.02 NOM
0.30
0.23
0.18
SEATING
PLANE
0.20 REF
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 58. 32-Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9245BCP-80
AD9245BCPRL7–80
AD9245BCPZ-80 2
AD9245BCPZRL7-802
AD9245BCPZ-652
AD9245BCPZRL7-652
AD9245BCPZ-402
AD9245BCPZRL7-402
AD9245BCPZ-202
AD9245BCPZRL7-202
AD9245BCP-80EB
AD9245BCP-65EB
AD9245BCP-40EB
AD9245BCP-20EB
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description 1
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
1
Package Option
CP-32-2
CP-32-2
CP-32-2
CP-32-2
CP-32-2
CP-32-2
CP-32-2
CP-32-2
CP-32-2
CP-32-2
It is recommended that the exposed paddle be soldered to the ground plane for the LFCSP package. There is an increased reliability of the solder joints, and the
maximum thermal capability of the package is achieved with the exposed paddle soldered to the customer board.
2
Z = Pb-free part.
Rev. D | Page 29 of 32
AD9245
NOTES
Rev. D | Page 30 of 32
AD9245
NOTES
Rev. D | Page 31 of 32
AD9245
NOTES
© 2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03583–0–1/06(D)
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