ON MC14052BF Analog multiplexers/demultiplexer Datasheet

MC14051B, MC14052B,
MC14053B
Analog
Multiplexers/Demultiplexers
The MC14051B, MC14052B, and MC14053B analog multiplexers
are digitally−controlled analog switches. The MC14051B effectively
implements an SP8T solid state switch, the MC14052B a DP4T, and
the MC14053B a Triple SPDT. All three devices feature low ON
impedance and very low OFF leakage current. Control of analog
signals up to the complete supply voltage range can be achieved.
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MARKING
DIAGRAMS
Features
•
•
•
•
•
•
•
•
•
•
Triple Diode Protection on Control Inputs
Switch Function is Break Before Make
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Analog Voltage Range (VDD − VEE) = 3.0 to 18 V
Note: VEE must be v VSS
Linearized Transfer Characteristics
Low−noise − 12 nV/√Cycle, f ≥ 1.0 kHz Typical
Pin−for−Pin Replacement for CD4051, CD4052, and CD4053
For 4PDT Switch, See MC14551B
For Lower RON, Use the HC4051, HC4052, or HC4053 High−Speed
CMOS Devices
Pb−Free Packages are Available*
16
PDIP−16
P SUFFIX
CASE 648
1
MC1405xBCP
AWLYYWWG
1
16
1
16
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
VDD
DC Supply Voltage Range
(Referenced to VEE, VSS ≥ VEE)
Vin,
Vout
Input or Output Voltage Range
(DC or Transient) (Referenced to VSS for
Control Inputs and VEE for Switch I/O)
Iin
Input Current (DC or Transient)
per Control Pin
Value
Unit
−0.5 to +18.0
V
−0.5 to VDD + 0.5
V
+10
mA
Switch Through Current
± 25
mA
PD
Power Dissipation per Package (Note 1)
500
mW
TA
Ambient Temperature Range
−55 to +125
°C
Tstg
Storage Temperature Range
−65 to +150
°C
TL
Lead Temperature (8−Second Soldering)
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From
65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained to
the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either
VSS, VEE or VDD). Unused outputs must be left open.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
December, 2006 − Rev. 10
1
14
05xB
ALYWG
G
TSSOP−16
DT SUFFIX
CASE 948F
1
16
ISW
© Semiconductor Components Industries, LLC, 2006
1405xBG
AWLYWW
SOIC−16
D SUFFIX
CASE 751B 1
1
1
SOEIAJ−16
F SUFFIX
CASE 966
MC1405xB
ALYWG
1
x
= 1, 2, or 3
A
= Assembly Location
WL, L
= Wafer Lot
Y
= Year
WW, W = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
Publication Order Number:
MC14051B/D
MC14051B, MC14052B, MC14053B
MC14051B
8−Channel Analog
Multiplexer/Demultiplexer
CONTROLS
SWITCHES
IN/OUT
6
11
10
9
13
14
15
12
1
5
2
4
INHIBIT
A
B
C
X0
X1
X
3
X2
COMMON
X3
OUT/IN
X4
X5
X6
X7
MC14052B
Dual 4−Channel Analog
Multiplexer/Demultiplexer
CONTROLS
SWITCHES
IN/OUT
INHIBIT
A
X
B
X0
X1
X2
X3
Y0
Y
Y1
6
10
9
12
14
15
11
1
5
2
4
MC14053B
Triple 2−Channel Analog
Multiplexer/Demultiplexer
CONTROLS
13
COMMONS
OUT/IN
3
Y2
Y3
SWITCHES
IN/OUT
6
11
10
9
12
13
2
1
5
3
INHIBIT
X
A
B
C
X0
Y
X1
Y0
Y1
Z
Z0
Z1
VDD = PIN 16
VSS = PIN 8
VEE = PIN 7
VDD = PIN 16
VSS = PIN 8
VEE = PIN 7
14
COMMONS
OUT/IN
15
4
VDD = PIN 16
VSS = PIN 8
VEE = PIN 7
Note: Control Inputs referenced to VSS, Analog Inputs and Outputs reference to VEE. VEE must be ≤ VSS.
PIN ASSIGNMENT
MC14051B
MC14052B
MC14053B
X4
1
16
VDD
Y0
1
16
VDD
Y1
1
16
VDD
X6
2
15
X2
Y2
2
15
X2
Y0
2
15
Y
X
3
14
X1
Y
3
14
X1
Z1
3
14
X
X1
X7
4
13
X0
Y3
4
13
X
Z
4
13
X5
5
12
X3
Y1
5
12
X0
Z0
5
12
X0
INH
6
11
A
INH
6
11
X3
INH
6
11
A
VEE
7
10
B
VEE
7
10
A
VEE
7
10
B
VSS
8
9
C
VSS
8
9
B
VSS
8
9
C
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2
MC14051B, MC14052B, MC14053B
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ELECTRICAL CHARACTERISTICS
− 55_C
Characteristic
Symbol
VDD
Test Conditions
25_C
125_C
Min
Max
Min
Typ
(Note 2)
Max
Min
Max
Unit
3.0
18
3.0
−
18
3.0
18
V
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
−
−
−
150
300
600
mA
SUPPLY REQUIREMENTS (Voltages Referenced to VEE)
VDD – 3.0 ≥ VSS ≥ VEE
Power Supply Voltage
Range
VDD
−
Quiescent Current Per
Package
IDD
5.0
10
15
Control Inputs:
Vin = VSS or VDD,
Switch I/O: VEE v VI/O v
VDD, and DVswitch v
500 mV (Note 3)
ID(AV)
5.0
10
15
TA = 25_C only (The
channel component,
(Vin – Vout)/Ron, is
not included.)
Total Supply Current
(Dynamic Plus
Quiescent, Per Package
mA
(0.07 mA/kHz) f + IDD
(0.20 mA/kHz) f + IDD
(0.36 mA/kHz) f + IDD
Typical
CONTROL INPUTS — INHIBIT, A, B, C (Voltages Referenced to VSS)
Low−Level Input Voltage
VIL
5.0
10
15
Ron = per spec,
Ioff = per spec
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
V
High−Level Input Voltage
VIH
5.0
10
15
Ron = per spec,
Ioff = per spec
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
V
Input Leakage Current
Iin
15
Vin = 0 or VDD
−
± 0.1
−
± 0.00001
± 0.1
−
1.0
mA
Input Capacitance
Cin
−
−
−
−
5.0
7.5
−
−
pF
SWITCHES IN/OUT AND COMMONS OUT/IN — X, Y, Z (Voltages Referenced to VEE)
Recommended
Peak−to−Peak Voltage
Into or Out of the Switch
VI/O
−
Channel On or Off
0
VDD
0
−
VDD
0
VDD
VPP
Recommended Static or
Dynamic Voltage Across
the Switch (Note 3)
(Figure 5)
DVswitch
−
Channel On
0
600
0
−
600
0
300
mV
Output Offset Voltage
VOO
−
Vin = 0 V, No Load
−
−
−
10
−
−
−
mV
ON Resistance
Ron
5.0
10
15
DVswitch v 500 mV
(Note 3) Vin = VIL or VIH
(Control), and Vin =
0 to VDD (Switch)
−
−
−
800
400
220
−
−
−
250
120
80
1050
500
280
−
−
−
1200
520
300
W
DRon
5.0
10
15
−
−
−
70
50
45
−
−
−
25
10
10
70
50
45
−
−
−
135
95
65
W
Ioff
15
Vin = VIL or VIH
(Control) Channel to
Channel or Any One
Channel
−
± 100
−
± 0.05
± 100
−
± 1000
nA
Capacitance, Switch I/O
CI/O
−
Inhibit = VDD
−
−
−
10
−
−
−
pF
Capacitance, Common O/I
CO/I
−
Inhibit = VDD
(MC14051B)
(MC14052B)
(MC14053B)
−
−
−
−
−
−
−
−
−
60
32
17
−
−
−
−
−
−
−
−
−
Pins Not Adjacent
Pins Adjacent
−
−
−
−
−
−
0.15
0.47
−
−
−
−
−
−
DON Resistance Between
Any Two Channels in the
Same Package
Off−Channel Leakage
Current (Figure 10)
Capacitance, Feedthrough
(Channel Off)
CI/O
−
−
pF
pF
2. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.
3. For voltage drops across the switch (DVswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn, i.e. the
current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the
Maximum Ratings are exceeded. (See first page of this data sheet.)
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3
MC14051B, MC14052B, MC14053B
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ÎÎÎÎ
ÎÎÎ
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ÎÎÎÎÎ
ÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Note 4) (CL = 50 pF, TA = 25_C) (VEE v VSS unless otherwise indicated)
Characteristic
Propagation Delay Times (Figure 6)
Switch Input to Switch Output (RL = 10 kW)
MC14051
tPLH, tPHL = (0.17 ns/pF) CL + 26.5 ns
tPLH, tPHL = (0.08 ns/pF) CL + 11 ns
tPLH, tPHL = (0.06 ns/pF) CL + 9.0 ns
Symbol
VDD – VEE
Vdc
Typ (Note 5)
All Types
Max
tPLH, tPHL
ns
5.0
10
15
35
15
12
90
40
30
MC14052
tPLH, tPHL = (0.17 ns/pF) CL + 21.5 ns
tPLH, tPHL = (0.08 ns/pF) CL + 8.0 ns
tPLH, tPHL = (0.06 ns/pF) CL + 7.0 ns
5.0
10
15
30
12
10
75
30
25
MC14053
tPLH, tPHL = (0.17 ns/pF) CL + 16.5 ns
tPLH, tPHL = (0.08 ns/pF) CL + 4.0 ns
tPLH, tPHL = (0.06 ns/pF) CL + 3.0 ns
5.0
10
15
25
8.0
6.0
65
20
15
Inhibit to Output (RL = 10 kW, VEE = VSS)
Output “1” or “0” to High Impedance, or
High Impedance to “1” or “0” Level
MC14051B
Unit
ns
ns
tPHZ, tPLZ,
tPZH, tPZL
ns
5.0
10
15
350
170
140
700
340
280
MC14052B
5.0
10
15
300
155
125
600
310
250
ns
MC14053B
5.0
10
15
275
140
110
550
280
220
ns
5.0
10
15
360
160
120
720
320
240
MC14052B
5.0
10
15
325
130
90
650
260
180
ns
MC14053B
5.0
10
15
300
120
80
600
240
160
ns
−
10
0.07
−
%
BW
10
17
−
MHz
Off Channel Feedthrough Attenuation (Figure 7)
RL = 1KW, Vin = 1/2 (VDD − VEE) p−p
fin = 4.5 MHz — MC14051B
fin = 30 MHz — MC14052B
fin = 55 MHz — MC14053B
−
10
– 50
−
dB
Channel Separation (Figure 8)
(RL = 1 kW, Vin = 1/2 (VDD−VEE) p−p,
fin = 3.0 MHz
−
10
– 50
−
dB
Crosstalk, Control Input to Common O/I (Figure 9)
(R1 = 1 kW, RL = 10 kW
Control tTLH = tTHL = 20 ns, Inhibit = VSS)
−
10
75
−
mV
Control Input to Output (RL = 10 kW, VEE = VSS)
MC14051B
Second Harmonic Distortion
(RL = 10KW, f = 1 kHz) Vin = 5 VPP
Bandwidth (Figure 7)
(RL = 1 kW, Vin = 1/2 (VDD−VEE) p−p, CL = 50pF
20 Log (Vout/Vin) = − 3 dB)
tPLH, tPHL
ns
4. The formulas given are for the typical characteristics only at 25_C.
5. Data labelled “Typ” is not lo be used for design purposes but In intended as an indication of the IC’s potential performance.
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4
MC14051B, MC14052B, MC14053B
VDD
VDD
VDD
IN/OUT
OUT/IN
VEE
VDD
LEVEL
CONVERTED
CONTROL
IN/OUT
OUT/IN
CONTROL
VEE
Figure 1. Switch Circuit Schematic
16
TRUTH TABLE
Control Inputs
Select
INH6
A11
B10
C9
ON Switches
Inhibit
C*
B
A
MC14051B
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
X0
X1
X2
X3
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
X4
X5
X6
X7
1
x
x x
None
*Not applicable for MC14052
x = Don’t Care
MC14052B
Y0
Y1
Y2
Y3
X0
X1
X2
X3
MC14053B
Z0
Z0
Z0
Z0
Y0
Y0
Y1
Y1
X0
X1
X0
X1
Z1
Z1
Z1
Z1
Y0
Y0
Y1
Y1
X0
X1
X0
X1
None
VDD
BINARY TO 1−OF−8
DECODER WITH
INHIBIT
LEVEL
CONVERTER
8
X013
X114
VSS
7
VEE
X215
X312
3X
X41
X55
X62
X74
None
Figure 2. MC14051B Functional Diagram
16
16
INH6
BINARY TO 1−OF−4
DECODER WITH
INHIBIT
LEVEL
CONVERTER
A10
B9
X012
X114
VDD
8
VSS
7
INH6
A11
B10
C9
VEE
X215
X311
Y01
Y15
Y22
Y34
BINARY TO 1−OF−2
DECODER WITH
INHIBIT
LEVEL
CONVERTER
8
13X
VDD
VSS
7
VEE
X012
X113
Y02
Y11
Z05
3Y
Z13
Figure 3. MC14052B Functional Diagram
Figure 4. MC14053B Functional Diagram
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5
14X
15Y
4Z
MC14051B, MC14052B, MC14053B
TEST CIRCUITS
ON SWITCH
CONTROL
SECTION
OF IC
A
B
C
PULSE
GENERATOR
LOAD
V
Vout
INH
CL
RL
SOURCE
VDD
Figure 5. DV Across Switch
VEE
VEE VDD
Figure 6. Propagation Delay Times,
Control and Inhibit to Output
A, B, and C inputs used to turn ON
or OFF the switch under test.
A
B
C
VSS
Vout
INH
CL = 50 pF
RL
RL
A
B
C
ON
INH
OFF
Vout
Vin
RL
VDD − VEE
VDD − VEE
2
2
Figure 7. Bandwidth and Off−Channel
Feedthrough Attenuation
CL = 50 pF
Vin
Figure 8. Channel Separation
(Adjacent Channels Used For Setup)
OFF CHANNEL UNDER TEST
VDD
A
B
C
CONTROL
SECTION
OF IC
Vout
RL
INH
VEE
OTHER
CHANNEL(S)
VEE
VDD
CL = 50 pF
R1
COMMON
VEE
VDD
Figure 9. Crosstalk, Control Input to
Common O/I
Figure 10. Off Channel Leakage
NOTE: See also Figures 7 and 8 in the MC14016B data sheet.
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6
MC14051B, MC14052B, MC14053B
VDD
KEITHLEY 160
DIGITAL
MULTIMETER
10 k
1 kW
RANGE
VDD
X−Y
PLOTTER
VEE = VSS
Figure 11. Channel Resistance (RON) Test Circuit
350
300
300
R ON , ON" RESISTANCE (OHMS)
R ON , ON" RESISTANCE (OHMS)
TYPICAL RESISTANCE CHARACTERISTICS
350
250
200
150
TA = 125°C
100
25°C
−55 °C
50
0
−10
−8.0 −6.0 −4.0 −2.0
0
0.2
4.0
6.0
8.0
250
200
150
100
25°C
−55 °C
50
0
−10
10
TA = 125°C
−8.0 −6.0 −4.0 −2.0
Vin, INPUT VOLTAGE (VOLTS)
600
300
500
400
TA = 125°C
200
25°C
100
0
−10
−55 °C
−8.0 −6.0 −4.0 −2.0
0
0.2
4.0
0.2
4.0
6.0
8.0
10
Figure 13. VDD = 5.0 V, VEE = − 5.0 V
350
RON , ON" RESISTANCE (OHMS)
RON , ON" RESISTANCE (OHMS)
Figure 12. VDD = 7.5 V, VEE = − 7.5 V
700
300
0
Vin, INPUT VOLTAGE (VOLTS)
6.0
8.0
250
VDD = 2.5 V
200
150
5.0 V
100
7.5 V
50
0
−10
10
TA = 25°C
−8.0 −6.0 −4.0 −2.0
0
0.2
4.0
6.0
8.0
Vin, INPUT VOLTAGE (VOLTS)
Vin, INPUT VOLTAGE (VOLTS)
Figure 14. VDD = 2.5 V, VEE = − 2.5 V
Figure 15. Comparison at 25°C, VDD = − VEE
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7
10
MC14051B, MC14052B, MC14053B
APPLICATIONS INFORMATION
peak. If voltage transients above VDD and/or below VEE are
anticipated on the analog channels, external diodes (Dx) are
recommended as shown in Figure B. These diodes should be
small signal types able to absorb the maximum anticipated
current surges during clipping.
The absolute maximum potential difference between
V DD and VEE is 18.0 V. Most parameters are specified up to
15 V which is the recommended maximum difference
between V DD and V EE.
Balanced supplies are not required. However, V SS must
be greater than or equal to V EE. For example, V DD = + 10
V, VSS = + 5 V, and V EE – 3 V is acceptable. See the Table
below.
Figure A illustrates use of the on−chip level converter
detailed in Figures 2, 3, and 4. The 0−to−5 V Digital Control
signal is used to directly control a 9 V p−p analog signal.
The digital control logic levels are determined by V DD
and VSS. The VDD voltage is the logic high voltage; the VSS
voltage is logic low. For the example, V DD = + 5 V = logic
high at the control inputs; V SS = GND = 0 V = logic low.
The maximum analog signal level is determined by VDD
and V EE. The V DD voltage determines the maximum
recommended peak above V SS. The V EE voltage
determines the maximum swing below V SS. For the
example, V DD − V SS = 5 V maximum swing above V SS ;
V SS − VEE = 5 V maximum swing below VSS. The example
shows a ± 4.5 V signal which allows a 1/2 volt margin at each
+5 V
−5 V
VSS
VDD
VEE
+ 4.5 V
9 Vp−p
+5 V
EXTERNAL
CMOS
DIGITAL
CIRCUITRY
ANALOG SIGNAL
SWITCH
I/O
COMMON
O/I
MC14051B
MC14052B
MC14053B
0−TO−5 V DIGITAL
CONTROL SIGNALS
9 Vp−p
ANALOG SIGNAL
GND
−4.5 V
INHIBIT,
A, B, C
Figure A. Application Example
VDD
VDD
DX
DX
ANALOG
I/O
COMMON
O/I
DX
DX
VEE
VEE
Figure B. External Germanium or Schottky Clipping Diodes
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
POSSIBLE SUPPLY CONNECTIONS
VDD
In Volts
VSS
In Volts
VEE
In Volts
Control Inputs
Logic High/Logic Low
In Volts
Maximum Analog Signal Range
In Volts
+8
0
–8
+ 8/0
+ 8 to – 8 = 16 Vp–p
+5
0
– 12
+ 5/0
+ 5 to – 12 = 17 Vp–p
+5
0
0
+ 5/0
+ 5 to 0 = 5 Vp–p
+5
0
–5
+ 5/0
+ 5 to – 5 = 10 Vp–p
+ 10
+5
–5
+ 10/ + 5
+ 10 to – 5 = 15 Vp–p
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8
MC14051B, MC14052B, MC14053B
ORDERING INFORMATION
Package
Shipping †
MC14051BCP
PDIP−16
500 Units / Rail
MC14051BCPG
PDIP−16
(Pb−Free)
500 Units / Rail
MC14051BD
SOIC−16
48 Units / Rail
MC14051BDG
SOIC−16
(Pb−Free)
48 Units / Rail
MC14051BDR2
SOIC−16
2500 / Tape & Reel
MC14051BDR2G
SOIC−16
(Pb−Free)
2500 / Tape & Reel
MC14051BDTR2
TSSOP−16*
2500 / Tape & Reel
MC14051BDTR2G
TSSOP−16*
2500 / Tape & Reel
MC14051BF
SOEIAJ−16
50 Units / Rail
MC14051BFG
SOEIAJ−16
(Pb−Free)
50 Units / Rail
MC14051BFEL
SOEIAJ−16
2000 / Tape & Reel
MC14051BFELG
SOEIAJ−16
(Pb−Free)
2000 / Tape & Reel
MC14052BCP
PDIP−16
500 Units / Rail
MC14052BCPG
PDIP−16
(Pb−Free)
500 Units / Rail
MC14052BD
SOIC−16
48 Units / Rail
MC14052BDG
SOIC−16
(Pb−Free)
48 Units / Rail
MC14052BDR2
SOIC−16
2500 / Tape & Reel
MC14052BDR2G
SOIC−16
(Pb−Free)
2500 / Tape & Reel
MC14052BDTR2
TSSOP−16*
2500 / Tape & Reel
MC14052BDTR2G
TSSOP−16*
2500 / Tape & Reel
MC14052BF
SOEIAJ−16
50 Units / Rail
MC14052BFG
SOEIAJ−16
(Pb−Free)
50 Units / Rail
MC14052BFEL
SOEIAJ−16
2000 / Tape & Reel
MC14052BFELG
SOEIAJ−16
(Pb−Free)
2000 / Tape & Reel
MC14053BCP
PDIP−16
500 Units / Rail
MC14053BCPG
PDIP−16
(Pb−Free)
500 Units / Rail
MC14053BD
SOIC−16
48 Units / Rail
MC14053BDG
SOIC−16
(Pb−Free)
48 Units / Rail
MC14053BDR2
SOIC−16
2500 / Tape & Reel
MC14053BDR2G
SOIC−16
(Pb−Free)
2500 / Tape & Reel
MC14053BDTR2
TSSOP−16*
2500 / Tape & Reel
MC14053BDTR2G
TSSOP−16*
2500 / Tape & Reel
MC14053BF
SOEIAJ−16
50 Units / Rail
MC14053BFG
SOEIAJ−16
(Pb−Free)
50 Units / Rail
MC14053BFEL
SOEIAJ−16
2000 / Tape & Reel
Device
MC14053BFELG
SOEIAJ−16
2000 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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9
MC14051B, MC14052B, MC14053B
PACKAGE DIMENSIONS
PDIP−16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648−08
ISSUE T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
16
9
1
8
B
F
C
L
DIM
A
B
C
D
F
G
H
J
K
L
M
S
S
−T−
SEATING
PLANE
K
H
G
D
M
J
16 PL
0.25 (0.010)
T A
M
M
INCHES
MIN
MAX
0.740 0.770
0.250 0.270
0.145 0.175
0.015 0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
0_
10 _
0.020 0.040
MILLIMETERS
MIN
MAX
18.80 19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
SOIC−16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
−A−
16
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
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10
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
MC14051B, MC14052B, MC14053B
PACKAGE DIMENSIONS
TSSOP−16
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F−01
ISSUE B
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
K
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
ÇÇÇ
K1
2X
L/2
16
9
J1
B
−U−
L
SECTION N−N
J
PIN 1
IDENT.
8
1
N
0.15 (0.006) T U
S
0.25 (0.010)
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
N
F
DETAIL E
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
H
D
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
DETAIL E
G
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
http://onsemi.com
11
INCHES
MIN
MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.007
0.011
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
MC14051B, MC14052B, MC14053B
PACKAGE DIMENSIONS
SOEIAJ−16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966−01
ISSUE A
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
9
Q1
M_
E HE
1
8
L
DETAIL P
Z
D
e
VIEW P
A
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
−−−
2.05
0.05
0.20
0.35
0.50
0.10
0.20
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
−−−
0.78
INCHES
MIN
MAX
−−− 0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
−−− 0.031
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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MC14051B/D
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