FEDL7344C/E/J-05
Issue Date: Jan 20, 2015
ML7344C/E/J
Sub-GHz(160MHz to 510MHz) band short range wireless transceiver IC
■Overview
ML7344C/E/J is a narrow band sub-GHz IC that integrates RF part, IF part, MODEM part and HOST interface
part in single-chip. It supports various frequency band from 160MHz to 510MHz. ML7344C can output 100mW
(20dBm) transimittion power and it suits for the smart-meter in Chinese market. ML7344E is suitable for Fmode
(434MHz) or N mode (169MHz) of Wireless M-Bus system. ML7344J is suitable for security radio system type III
or IV of the RCR STD-30 and specified low-power radio station in 426 MHz operation of the ARIB STD-T67.
ML7406 and ML7344 have the same package, pins assignment and
major registers.
(32pin WQFN)
ML7406 series
ML7344 series
RF: 750MHz to 960MHz
Rate: 1.2kbps to 500kbps (FSK/GFSK)
Channel Spacing: 100 kHz to 1.6MHz
Wireless M-Bus
IEEE802.15.4g (FEC not supported)
ARIB STD-T108
RF: 160MHz to 510MHz
Rate: 1.2kbps to 15kbps (FSK/GFSK)
Channel Spacing: 25 kHz
Wireless M-Bus
ARIB STD-T67
ML7406 series
Data rate [kbps]
1000
IEEE802.15.4g
(780 to 960MHz)
100
Wireless
M-Bus
(868MHz)
ML7344 series
10
1
Wireless
M-Bus
(169MHz)
0
250
ARIB
STD T67
(426/429
MHz)
500
750
1000
Frequency [MHz]
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■Features
• Frequency Range: 160 – 510MHz
• ML7344C is able to use as communication unit of Q_GDW374.3 (China)
ML7344E is able to use as F mode or N mode of the wirelss M-bus system.
ML7344J is able to use as type III or IV security radio of RCR STD-30 and ARIB STD-T67 in 426 MHz
operation. (Japan)
• High accurate modulation implemented by direct modulation scheme using fractional-N PLL.
• Multiple modulation scheme : GFSK/GMSK, FSK/MSK
• Configurable data ratres from 1.2kbps to 15 kbps
• Supports NRZ code, Manchester code and 3 out of 6 code.
• Programmable modulation frequency deviation
• Polarity conversion for TX and RX data bits
• On chip 26MHz oscillation circuit implemented (ML7344xC x=C, E or J)
Supports 26MHz TCXO input. (ML7344xT, x=C, E or J)
Note: The ordering product name is different from supporting clock source.
• On chip low speed RC oscillation circuit.
• Oscillation frequecy tuning function implemented. (ML7344xC x=C, E or J)
• Frequency tuning function (frequency fine tuning by oscillation circuit and fractional-N PLL)
• Built in Power Amp (PA) and power control function
Programmable from 100mW, 20mW and 10mW (ML7344C)
Programable from 20mW,10mW and 1mW (ML7344E/J)
• Fine output power tuning function implemented. (Tune ±0.2dB)
• TX ramp control function implemented
• High speed carrier checking function
• Support external PA
• Receive Signal Strength Indicator (RSSI) reporting function and threshold comparison function
• Built-in AFC function
• Synchronous serial peripheral interface (SPI)
• Auto wake-up and auto sleep function are implemented
• 2 genral purpose timers are implemented
• Test Pattern generation (PN9, CW, 0/1, all-1, all-0 pattern)
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• Packet mode function
• Support 2 wireless M-bus packet format. (Format A and B)
• Support general packet format (Format C)
• Max packet length 255 bytes (Format A and B)and 2047 bytes (Format C)
• 64 byte TX and RX buffer are implemented
• Preamble pattern detection function (Preamble length can be prgrammable between 1 to 4 Byte)
• Programmable TX preamble length (Max 16383 Byte)
• ID code or SFD detection function (Max 4 Byte x 2codes, available for TX and RX)
• Progrmable CRC generate function for CRC32, CRC16 and CRC8
• Whitenning function
• Address filtering function
Checking C-Fieled, M-Field and A field of wireless M-bus packet (EN13575-4:2011)
• Supply voltage
1.8V to 3.6V Outpur power is set at 1mW
2.1V to 3.6V Output power is set at 10mW
2.6V to 3.6V Output power is set at 20mW
3.3V to 3.6V Output power is set at 100mW
• Operating temperature -40 to +85 ˚C
• Current consumption (operation at 400MHz band)
Deep Sleep Mode:
0.1 uA (Typ)
Sleep Mode1
0.4 uA (Typ) (Maintain Register values)
Sleep Mode2
0.53 uA (Typ) (Maintain Register values and FIFO data)
Idle Mode
0.6 mA (Typ)
TX 100mW
90 mA (Typ.)
20mW
28 mA (Typ.) (ML7344E/J)
45 mA (Typ.) (ML7344C)
10mW
22 mA (Typ.)
1mW
8.8 mA (Typ.)
RX
6.2 mA (Typ.)
• Package
32 pin WQFN 5.0mm x 5.0mm x 0.8mm
Pb free, RoHS compliant
■Ordering Guide
ML7344 x y GDZ05BL
x=C: 470MHz to 510MHz
E: 160MHz to 180MHz
J: 426MHz to 434MHz
y =C: Crystal Input
T: TCXO Input
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■Description Convention
1) Numbers description
‘0xnn’ indicates hexadecimal and ‘0bnn’ indicates binary
Example: 0x11=17 (decimal), 0b11=3 (decimal)
2) Register description
[<register name>: B<Bank No.> <register address>] register
Example: [RF_STATUS: B0 0x0B] register
Register name: RF_STATUS
Bank No.: 0
Register address: 0x0B
3) Bit name description
<bit name> ([<register name>: B<Bank No.> <register address> (<bit location>)])
Example: SET_TRX[3:0]([RF_STATUS: B0 0x0B(3-0)])
Bit name: SET_TRX
Register name: RF_STATUS
Bank No.: 0
Register address: 0x0B
Bit location: bit3 to bit0
4) In this documet
“TX” stands for transmittion.
“RX” stands for reception.
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■Block Diagram
A_MON
RESETN
ML7344C/E/J
RF
LNA_P
BB
LNA
MIX
BPF
RSSI
ED_VAL
Limiter
DEMOD
PHY
S
P
I
100mW/20mW
or
20mW/1mW
VCO
Digital
MOD
FMAP
Reg.(PA)
General
TIMER1/2
OSC
I
R
C
SCEN
XOUT TCXO
LP
VB_EXT
IND1
IND2
REG_OUT
REG_CORE
GPIO0
GPIO1-3
WakeUp
TIMER
Reg.
XIN
SDI
LO PLL
PA
REG_PA
SDO
FIFO
RF_Manager
PA_OUT
SCLK
EXT_CLK
REGPDIN
VBG
Fig.1 Block diagram
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■PIN Configuration
LNA_P
A_MON
VDD_PA
REG_PA
PA_OUT
GPIO3
GPIO2
GPIO1
Package: 32pin WQFN
24
23
22
21
20
19
18
17
VDD_RF
25
16
GPIO0
LP
26
15
SDI
VDD_CP
27
14
SCEN
IND1
28
13
SCLK
GND_VCO
29
12
SDO
IND2
30
11
REGPDIN
VB_EXT
31
10
EXT_CLK
VDD_VCO
32
9
VDDIO
4
5
6
7
8
XIN
XIN (N.C)
XOUT(TCXO, SPXO)
N.C
RESETN
VBG
3
REG_CORE
2
REG_OUT
1
VDD_REG
裏面PKG GND
裏面PKG GND
(T.B.D.)
GND PAD
Fig.2 Pin Assignment
NOTE: Pattern shown in the centre of the chip is located at bottom side of the chip (GND PAD)
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■PIN Definitions
Symbols
I
O
Is
IO
IA
OA
OAH
IOA
ORF
VDDIO
VDDRF
GND
: Digital input
: Digital output
: Shmidt Trigger input
: Digital input/output
: Analog input
: Analog output 1
: Analog output 2
: Analog input/output
: RF output
: I/O power supply
: RF power supply
: Ground
●RF and Analog pins
Pin
Pin name
Reset
state
I/O
Active
Level
20
PA_OUT
−
ORF
−
RF antenna output
23
A_MON
−
OA
−
Temperature information output (*1)
24
LNA_P
−
IA
−
RF antenna input
26
LP
−
IOA
−
Pin for loop filter
28
IND1
−
IOA
−
Pin for VCO tankl inductor
30
IND2
−
IOA
−
Pin for VCO tank inductor
31
VB_EXT
−
IOA
−
Pin for smothing capacitor for internal bias
function
*1 This pin can be configured by [MON_CTRL:B0 0x4D] register, no signal assigned as default setting.
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●SPI Interface pins
Pin
Pin name
Reset
state
I/O
Active
Level
12
SDO
O/L
O
H or L SPI data output or DCLK (*1)
13
SCLK
I
IS
P or N SPI clock input
14
SCEN
I
IS
15
SDI
I
IS
L
function
SPI chip enable
L: enable
H: disable
H or L SPI data input or DIO (*1)
*1 Please refer to “DIO function”
●Regulator pins
Pin
Pin name
Reset
state
I/O
Active
Level
2
VBG (*1)
−
OAH
−
Pin for decouppling capacitor
3
REG_OUT
(*1)
−
OAH
−
Requlator1 ouput (typ. 1.5V)
4
REG_CORE
−
OA
−
Requlator2 ouput (typ. 1.5V)
11
REGPDIN
I
I
H
Power down control pin for regulator
Fix to ‘L’ for nomal use. “H” is for deep sleep mode.
21
REG_PA (*1)
−
OAH
−
Regulator output for PA block
function
*1 These pin will output 0V in the sleep state.
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●Miscellaneous pins
Pin
Pin name
5
XIN
N.C.(*2)
6
Reset
state
I/O
I
IA
−
−
XOUT
TCXO(*2)
O
OA
IA
I
8
RESETN
I
IS
10
EXT_CLK
I
IO
16
GPIO0
O/H
17
GPIO1
O/L
18
ANT_SW/
GPIO2
O/L
19
TRX_SW/
GPIO3
O/L
Active
Level
function
P or N 26MHz crystal pin1
−
(Note) In case of TCXO, it must be open.
P or N 26MHz crystal pin 2 or TCXO input
Reset
L: Hardware reset enable (Forcing reset state)
H: Normal operation
Digital I/O (*3)
P or N Reset state: External RTC (32kHz) input. [ML7344E/J]
External PA control signal output. [ML7344C]
L
IO
or
OD(*1)
IO
or
OD(*1)
IO
or
OD(*1)
IO
or
OD(*1)
H or L
Digital GPIO (*4)
Reset state: interrupt indication signal output
H or L
Digital GPIO (*5)
Reset state: clock output
H or L
Digital GPIO (*6)
Reset state: Antenna diversity selection control signal
H or L
Digital GPIO (*7)
Reset state: TX –RX selection signal control
(Note)
*1 OD is open drain output.
*2 The following pin names are different depend on products.
Pin No.
5
ML7344C
XIN
ML7344T
N.C.
6
XOUT
TCXO
(Note)
*1 In case of using TCXO, set TCXO_EN=0b1. Please make sure only one of the register TCXO_EN,
XTAL_EN is set to 0b1.
*2 For ML7344Jy, the initial value of the register TCXO_EN is 0b1. In case of using ML7344JC, the register
XTAL_EN([CLK_SET2: B0 0x03(4)])=0b1 must be programmed first.
*3 For ML7344Cy, the initial value of the register XTAL_EN is 0b1. In case of using ML7344CT, the
register TCXO_EN([CLK_SET2: B0 0x03(6)])=0b1 must be programmed first.
*4 Please refer to [EXTCLK_CTR: B0 0x52] register.
*5 Please refer to [GPIO0_CTRL: B0 0x4E] register
*6 Please refer to [GPIO1_CTRL: B0 0x4F] register
*7 Please refer to [GPIO2_CTRL: B0 0x50] register
*8 Please refer to [GPIO3_CTRL: B0 0x51] register
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●Power supply/GND pins
Pin
Pin name
Reset
state
I/O
Active
Level
1
VDD_REG
−
VDDIO
−
9
VDDIO
−
VDDIO
−
22
VDD_PA
−
VDDIO
−
25
VDD_RF
−
VDDRF
−
Power supply for RF blocks
(REG-OUT is connected, typ.1.5V)
27
VDD_CP
−
VDDRF
−
Power supply for charge pump
(REG-OUT is connected, typ.1.5V)
32
VDD_VCO
−
VDDRF
−
Power supply for VCO
(REG_OUT is connected, typ.1.5V)
29
GND_VCO
−
GND
−
GND for VCO
function
Power supply pin for Regulator
(input voltage: 1.8V to 3.3V)
Power supply for digital I/O
(input voltage: 1.8 to 3.6V)
Power supply for PA block
(input voltage: 18 to 3.6V, depending on TX mode)
●Unused pins treatment
Unused pins treatments are as follows:
Unused pins treatment
Pin name
Pins number
Recommended treatment
N.C.
5
Open
N.C.
7
GND or Open
EXT_CLK
10
GND
A_MON
23
GND
GPIO0
16
Open
GPIO1
17
Open
GPIO2
18
Open
GPIO3
19
Open
(Note)
*1 If input pins are high-impedence state and leave open, excess current could be drawn. Care must be taken
that unused input pins and unused I/O pins should not be left open.
*2 After reset, GPIO1 pin is CLK_OUT function. If this function is not used, the clock must to be disabled by
setting 0b000 to GPIO1_IO_CFG[2:0] ([GPIO1_CTRL: B0 0x4F (2-0)]). If this pin is left open while
outputing clock signal, it may affect RX sensitivity.
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■Electrical Characteristics
●Absolute Maximum Ratings
Ta=-40˚C to +85˚C and GND=0V is the typical conditoin if not defined specific condition.
item
symbol
condition
Rating
unit
I/O Power supply
VDDIO
-0.3 to +4.6
V
RF Power supply
VDDRF
-0.3 to +2.0
V
RF input power
PRFI
Antenna input in RX
0
dBm
RF output Voltage
VRFO
PA_OUT(#20)
-0.3 to +4.6
V
VRFO
PA_OUT(#20)
Duty Cycle of
transmission at
+20dBm output <1 %
-0.3 to +7.7
V
RF output Voltage[ML7344C]
Voltage on Analog Pins 1
VA
-0.3 to +2.0
V
Voltage on Analog Pins 2
VAH
-1.0 to +4.6
V
Voltage on Digital Pins
VD
-0.3 to +4.6
V
Digital Input Current
IDI
-10 to +10
mA
Digital Output Current
IDO
-8 to +8
mA
Power Dissipation
Pd
Ta= +25˚C
1.2
W
Tstg
−
-55 to +150
˚C
Storage Temperature
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●Recommended Operating Conditions
Item
Power Supply (I/O)
Power Supply (PA)
Symbol
VDDIO
VDDPA
Conditions
Min
Typ.
Max
Unit
VDD_IO, VDD_REG pins
1.8
3.3
3.6
V
VDD_PA pin
TX power = 1mW
1.8
3.3
3.6
V
VDD_PA pin
TX power = 10mW
2.1
3.3
3.6
V
VDD_PA pin
TX power = 20mW
2.6
3.3
3.6
V
VDD_PA pin
TX power = 100mW
3.3
-
3.6
V
-40
+25
+85
ºC
Ambient Temperature
Ta
-
Digital input rising time
TIR
Digital input pins (*1)
-
-
20
ns
Digital input falling time
TIF
Digital Input pins (*1)
-
-
20
ns
Digital output loads
CDL
All Digital Output pins
-
-
20
pF
26
-
MHz
+10
ppm
Master clock frequency
FMCK1
(*2)
-
Master clock accuracy
ACMCK
(*3)
-10
TCXO Input voltage
VTCXO
DC cut
(ML7344xT)
0.8
-
1.5
Vpp
SPI clock frequency
FSCLK
SCLK pin
0.032
2
16
MHz
SPI clock duty ratio
DSCLK
SCLK pin
45
50
55
%
FRF
ML7344C
ML7344E
ML7344J
470
160
315
-
510
180
450
MHz
RF channel frequency
(*1) Those pins with symbol I, Is at pin definition section
(*2) XIN and XOUT pin (ML7344xC), TCXO pin (ML7344xT)
(*3) This difinition is the specification of RF communication availability, not the system requirement.
Use the appropriate frequency accuracy under each specificaton requirement as below.
Specification
Required accuracy
RCR STD-30 type III (Japan)
±10 ppm
RCR STD-30 type IV (Japan)
±4 ppm
Wireless M-bus N mode
±1.5kHz (±8.5 ppm, 4.8kbps)
±2.0kHz (±11.803 ppm, 2.4kbps)
Wireless M-bus F mode
±16 ppm
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●Power Consumption
Item
Symbol
Power Consumption
(*1)
Conditions
Min
Typ. (*2)
Max(*3)
Unit
IDD_DSLP
Deep Sleep mode
-
0.1
11
(0.8)
µA
IDD_SLP1
Sleep mode 1 (*4)
-
0.4
23
(1.6)
µA
IDD_SLP2
Sleep mode 2 (*4)
-
0.53
25.8
(1.9)
µA
IDD_SLP3
Sleep mode 3 (*4)
-
0.7
26
(2.1)
µA
IDD_SLP4
Sleep mode 4 (*4)
-
2.14
28
(4.1)
µA
IDD_IDLE
Idle mode(*5)
-
0.6
-
mA
IDD_RX
RF RX mode (*6)(*7)
LOW_RATE_EN([CLK_SET2:
-
5.9
-
mA
IDD_TX1
RF TX mode (1mW) (*6)
For ML7344E/J
-
8.8
-
mA
IDD_TX10
RF TX mode (10mW) (*6)
-
22.0
-
mA
-
28.0
-
mA
IDD_TX20
RF TX mode
(20mW)
-
45.0
-
mA
For ML7344E/J
(*6)
For ML7344C
(*7)
IDD_TX100
RF TX mode (100mW) (*7)
For ML7344C
-
90
-
mA
IDD_XTAL
X’tal Oscillator Circuit (*8)
-
0.3
-
mA
(*1) Power consumption is sum of current consumption of all power supply pins
(*2) “Typ” value is centre value under condition of VDDIO=3.3V, 25˚C.
(*3) () is a reference maximum value under condition of 25˚C
(*4) The definition od each sleep mode is shown in following table.
Mode.
Register
FIFO
RC Osc.
(32kHz)
Low clock
timer
Sleep mode 1
Not retain
Not retain
OFF
-
Sleep mode 2
Retain
Retain
OFF
-
Sleep mode 3
Retain
Retain
External Input
ON
Sleep mode 4
Retain
Retain
ON
ON
(*5) Under condition of using TCXO.
(*6) Under condition of data receiving speed at 9.6 kbps and 426 MHz operation.
(*7) Under condition of data receiving speed at 9.6 kbps and 490 MHz operation.
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(*8) When using ML7344xC, power consumptions of each mode exluded Deep Sleep and Sleep are added
IDD_XTAL.
●DC characteristics
Item
Symbol
Conditions
Min
VDDIO
*0.75
Typ. (*2)
Max
Unit
-
VDDIO
V
1.35
-
1.5
V
VIH1
Digital input/inout pins
VIH2
XIN pin
VIL1
Digital input/inout pins
0
-
VDDIO
*0.18
V
VIL2
XIN pin
0
-
0.15
V
Schmit Trigger
Threshold High level
VT+
Digital pins with shmitt trigger
gate
-
1.2
VDDIO
*0.75
V
Schmit Trigger
Threshold Low level
VT-
Digital pins with shmitt trigger
gate
VDDIO
*0.18
0.8
-
V
IIH1
Digital input pins
-1
-
1
μA
IIL1
Digital input pins
-1
-
1
μA
IIL2
XIN pin
-0.3
-
0.3
μA
Voltage Input High
Voltage Input Low
Input leakage current
IOZH
EXT_CLK, GPIO0-3 pins
-1
-
1
μA
IOZL
EXT_CLK, GPIO0-3 pins
-1
-
1
μA
Voltage ouput level H
VOH
IOH=-4mA
VDDIO
*0.8
-
VDDIO
V
Voltage ouput evel L
VOL
IOL=4mA
Tri-state output
leakage current
0
-
0.3
V
MAIN_REG
REG_CORE and
REG_OUTpin
When in mode other than
1.4
1.5
1.6
V
SUB_REG
REG_CORE pin
When in sleep mode
0.95
1.5
1.65
V
Input pins
-
6
-
pF
COUT
Output pins
-
9
-
pF
CRFIO
RF inout pins
-
9
-
pF
Analog input pins
-
9
-
pF
Regulator output
voltage
CIN
Pin capacitance
CAI
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●RF characteristics
Data Rate
Modulation scheme
Channel spacing
Definisiton Point
:
:
:
:
1.2 kbps to 15 kbps
2-GFSK/ 2-FSK
25kHz
ANT connector of ML7344 RF board.
[RF frequency]
Item
Condition
ML7344C
LNA_P,PA_OUT pins
ML7344E
ML7344J
Min
Typ.
Max
Unit
470
-
510
MHz
160
-
180
MHz
315
-
450
MHz
NOTE:1) Support 160 MHz to 510 MHz by changing L and C components between IND1 and IND2 pins
2) Integer multiples of the master clock frequency and its around frequency can not be used. Please refer
section of “Programing Channel Frequency ”
[TX characteristics]
170MHz and 426MHz Band (160MHz to 180MHz, 315MHz to 450MHz) [ML7344E/J]
Item
Min
Typ.
Max
Unit
20mW(13dBm) mode
10
13
13.8
dBm
10mW(10dBm) mode
7
10
10.8
dBm
1mW(0dBm) mode
-3
0
0.8
dBm
0.025
-
400
kHz
Band including 99% power
8.5
-
11.8
kHz
Adjacent Channel Power
9600bps (PN9), Fdev=3 kHz
Offset:25 kHz ±8 kHz band
-
-
-40
dB
-
-
-26
dBm
Spurious emission level
+10dBm output
9600 bps (PN9). Fdev = 3 kHz
Total power from 62.5 kHz to
162.5kHz offset
Harmonics
+10dBm output with LC trap
filter
9600 bps (PN9). Fdev = 3 kHz
-
-
-26
dBm
TX Power
Frequency deviation setting
range [Fdev]
Occupied bandwidth
9600 bps (PN9), Fdev=3 kHz
Condition
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470MHz BAND(470MHz to 510MHz) [ML7344C]
Item
TX Power
Frequency Deviation (Fdev)
Range
Occupied bandwidth
9600 bps (PN9), Fdev=3 kHz
Spurious emission level
Condition
100mW(20dBm) mode
20mW(13dBm) mode
Band including 99% power
Harmonics
+20dBm output with LC trap filter
Min
Typ.
Max
Unit
18.5
20
23
dBm
10
13
16
dBm
0.025
-
400
kHz
8.5
-
11.8
kHz
-
-
-36
dBm
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[RX characteristics]
426MHz Band (315MHz to 450MHz) [ML7344J]
Item
Minimum RX sensitivity
BER<0.1%
Condition
Min
Typ.
Max
Unit
4.8 kbps, Fdev=3kHz
-
-115
-108
dBm
9.6 kbps, Fdev=3kHz
-
-114
-107
dBm
-
-118
-111
dBm
-
-117
-110
dBm
-
3
-
dB
±25 kHz
30
33
-
dB
±50 kHz
-
36
-
dB
1 MHz offset
-
69
-
dB
2 MHz offset
-
72
-
dB
6 MHz offset
-
75
-
dB
10 MHz offset
-
80
-
dB
30
40
-
dB
-
-115
-
dBm
-
-120
-
dBm
-
40
-
dB
-
35
-
dB
-
-
-54
dBm
4.8 kbps, Fdev=3kHz
High Gain Mode
9.6 kbps, Fdev=3kHz
High Gain Mode
±12.5 kHz
Adjacent channel rejection
Blocking (426MHz operation)
-400kHz offset (image
frequency), Ta=25 ºC
After I/Q adjustment
Minimum power detection level
Power detection range
Spurious Emission level
RFmin in Figure of
RSSI
characteristics*1
Dynamic Range in
Figure of RSSI
characteristics*1
High Gain
Mode
High Gain
Mode
Compliant with FCC, ARIB,
ETSI standard
*1. RSSI characteristics as shown follow.
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ED
EDmax
Measured Point
Calculated Point
EDmin
-100
No Input
-60
-80
RF input level
RFmax
RFmin
Dynamic Range
470MHz BAND(470MHz to 510MHz) [ML7344C] High Gain Mode
Item
Min
Typ.
Max
Unit
-
-116
-
dBm
-
-115
-
dBm
-
-118
-
dBm
-
-117
-
dBm
±200kHz
-
55
-
dB
1 MHz offset
-
65
-
dB
2 MHz offset
-
66
-
dB
6 MHz offset
-
71
-
dB
10 MHz offset
-
73
-
dB
-400kHz offset (image
frequency),
Ta=25 ºC After I/Q adjustment
-
40
-
dB
Minimum power detection level
RFmin in Figure of RSSI
characteristics*1
-
-120
-
dBm
Power detection range
Dynamic Range in Figure of
RSSI characteristics*1
-
35
-
dB
Spurious Emission level
Compliant with FCC, ARIB,
ETSI standard
-
-
-54
dBm
Minimum RX sensitivity
Adjacent channel rejection
Blocking
Condition
4.8 kbps, Fdev=3kHz
(BER<0.1%)
9.6 kbps, Fdev=3kHz
(BER<0.1%)
4.8 kbps, Fdev=3kHz
(BER<1%)
9.6 kbps, Fdev=3kHz
(BER<1%)
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170MHz Band [ML7344E]
Item
Condition
Minimum RX sensitivity
BER<0.1%
Min
Typ.
Max
Unit
4.8 kbps, Fdev=3kHz
-
-115
-
dBm
9.6 kbps, Fdev=3kHz
-
-114
-
dBm
-
-118
-
dBm
-
-117
-
dBm
±12.5 kHz
-
3
-
dB
±25 kHz
-
33
-
dB
±50 kHz
-
36
-
dB
1 MHz offset
-
69
-
dB
2 MHz offset
-
72
-
dB
6 MHz offset
-
75
-
dB
10 MHz offset
-
80
-
dB
-400kHz offset (image
frequency), Ta=25 ºC
After I/Q adjustment
-
40
-
dB
-
-115
-
dBm
-
-120
-
dBm
-
40
-
dB
-
35
-
dB
-
-
-54
dBm
Min
Typ.
Max
Unit
-
44
-
kHz
4.8 kbps, Fdev=3kHz
High Gain Mode
9.6 kbps, Fdev=3kHz
High Gain Mode
Adjacent channel rejection
Blocking (426MHz operation)
Minimum power detection level
RFmin in Figure of
RSSI
characteristics*1
High Gain
Mode
Dynamic Range in
Figure of RSSI
characteristics*1
Power detection range
High Gain
Mode
Compliant with FCC, ARIB, ETSI
standard
Spurious Emission level
●RC oscillator circuit characteristics
Item
Oscillation Frequency
Symbol
FRCOSC
Condition
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●SPI interface characteristics
Item
Symbol
SCLK clock frequency
Condition
Min
Typ.
Max
Unit
FSCLK
0.032
2
16
MHz
SCEN input setup time
TSCENSU
30
−
−
ns
SCEN input hold time
TSCENH
30
−
−
ns
SCLK high pulse width
TSCLKH
28
−
−
ns
SCLK low pulse width
TSCLKL
SDI input setup time
TSDISU
SDI input hold time
Load capacitance
CL=20pF
28
−
−
ns
5
−
−
ns
TSDIH
15
−
−
ns
SCEN negate time
TSCENNI
200
−
−
ns
SDO output delay time
TSDODLY
−
−
22
ns
NOTE: All timing parameter is defined at voltage level of VDDIO * 20% and VDDIO * 80%.
SCEN
TSCENH
FSCLK
TSCENSU
TSCLKL
SCLK
TSCLKH
TSDISU
SDI
TSDIH
MSB IN
BITS6-1
LSB IN
TSDODLY
SDO
MSB OUT
BITS6-1
LSB
TSCENNI
SCEN
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●DIO interface characteristics
Item
Symbol
Condition
Min
Typ.
Max
Unit
DIO Input setup time
TDISU
1
-
-
µs
DIO Input hold time
TDIH
0
-
-
ns
DIO Output hold time
TDOH
20
-
-
ns
(*3)
-
(*3)
kHz
DCLK frequency
accuracy in TX (*1)
FDCLK_TX
DCLK frequency
accuracy in RX (*2)
FDCLK_RX
-30
-
+30
%
DDCLK_TX
45
-
55
%
DDCLK_RX
30
-
70
%
DCLK output duty ratio
(TX)
DCLK output duty ratio
(RX)
Load capacitance
CL=20pF
(*1) DCLK clock frequency in TX mode will be varied depending on the variance of master clock frequency.
(*2) DCLK clock frequency in RX mode will be varied by reproduced clock and its jitter.
(*3) These values are equal to the accuracy of the master clock frequency
NOTE: All timing parameter is defined at voltage level of VDDIO * 20% and VDDIO * 80%.
FDCLK_TX/ FDCLK_RX
DCLK
TDISU
DIO(input)
TDIH
VALID
VALID
VALID
TDOH
DIO(output)
VALID
VALID
VALID
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●Clock output characteristics
ML7344x has configurable clock output function. It is controlled by [MON_CNTRL: B0 0x4D] register and
[GPIOn_CTRL: B0 0x4E-0x51)] registers (n=0 to 3),. Default settign is the 3.33MHz clock is output from
GPIO1.
Item
Clock output frequency
Clock output duty ratio
Symbol
Condition
Min
Typ.
Max
Unit
0.0064
3.33
26
MHz
8.66 MHz
33
-
67
%
Other than
8.66 MHz
48
50
52
%
FCLKOUT
DCLKOUT
Load
capacitance
CL=20pF
FCLKOUT
GPIOn
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●Reset characteristics
Symbo
Item
Condition
All power supply pins
(After power on)
RESETN delay time
(Power on)
TRDL1
RESETN pulse period
When starting from
VDDIO=0V
TRPW1
RESETN pulse period 2
When starting from
VDDIO≠0V
TRPW2
VDDIO > 1.8V should be
required.
RESETN input delay time
(When ML7344 start up
from VDDIO≠0V)
TRDL2
VDDIO > 1.8V
RESETN rising time
TRRST
VDDIO
Less than 1.8V
TRPW1
TRDL1
Min
Typ.
Max
Unit
0.5
-
-
ms
200
-
-
ns
1.5
-
-
ms
1
-
-
µs
-
-
1
ms
VDD level
1.8V
GND level
TRDL2
TRPW2
RESET
TRRST
NOTE: When ML7344 start up from VDDIO≠0V, RESETN pulse should be asserted after VDDIO becomes over
1.8V.
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●Deep Sleep mode characteristics
Item
Symbol
REGPDIN assert delay
time
TRPFD
REGPDIN assert time
TRPASS
RESETN release delay
time
TREFD
Condition
VDDIO = “H”
Min
Typ.
Max
Unit
0
-
-
µs
1.2
-
-
ms
0.5
-
-
ms
VDD level
VDDIO
GND level
TRPFD
TREFD
RESETN
TRPASS
REGPDIN
●Power-on characteristics
Item
Power on time
Symbol
TPWON
Condition
Power on state
(All power supply pins)
Min
Typ.
Max
Unit
-
-
5
ms
TPWON
VDD
80%
20%
VDD level
GND level
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■Function description
●HOST Interface
●Serial Peripheral Interface (SPI)
ML7344 has a SPI, which supports slave mode. Host MCU can read/write to the ML7344 registers and
on-chip FIFO using MCU clock. Single access and burst access are also supported.
[Single Access Mode Timing Chart]
In write operation, data will be stored into internal register at rising edge of clock which is capturing D0 data.
During write operation, if setting SCEN line to “H”, the data will not be stored into register. For more details of
SCEN negate timing, please refer to the “SPI interface characteristics”. Afetr the internal clock is stabilized,
data will be written into the register in syncrohonization with the internal clock.
[Write]
SCLK
SCEN
SDI
A
6
Address field
A
D
0 “1” 7
D
0
Write data field
W
(Register write timing)
Before clock stable
D7-0
After clock stable
D7-0
Up to 0.45 µs
[Read]
SCLK
SCEN
SDI
A
6
A
“0”
0
Address field
SDO
R
D
0
D
7
Data read field
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[Burst Access Mode Timing Chart]
By maintaining SCEN line as “L”, burst access mode will be active. By setting SCEN line to “H”, exiting
from the burst access mode. During burst access mode, address will be automatically incremented.
When SCEN line becomes “H” before Clock for D0 is input, data transaction will be aborted.
NOTE:
If destination is [WR_TX_FIFO:B0 0x7C] or [RD_FIFO:B0 0x7F], address will not be increment. And
continuous FIFO access is possible.
[Write]
SCLK
SCEN
SDI
A
6
Address field
A
D
0 “1” 7
D
0
Write data field
W
Write data field
(Register write timing)
Before clock stable
D7-0
After clock stable
D7-0
D7-0
D7-0
Up to 0.45µs
Up to 0.45µs
[Read]
SCLK
SCEN
SDI
A
6
Address field
SDO
A
“0”
0
R
D
7
D
0
Read data field
Read data field
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●LSI state transition control
●LSI State transition instruction
State can be controlled from MCU by setting registers below.
State transition command
Instruction
TX_ON
SET_TRX([RF_STATUS:B0 0x0B(3-0)])=0b1001
RX_ON
SET_TRX([RF_STATUS:B0 0x0B(3-0)])=0b0110
TRX_OFF
SET_TRX([RF_STATUS:B0 0x0B(3-0)])=0b1000
Force_TRX_OFF
SET_TRX([RF_STATUS:B0 0x0B(3-0)])=0b0011
SLEEP_EN
SLEEP_EN([SLEEP/WU_SET:B0 0x2D(0)])=0b1
VCO_CAL_EN
VCO_CAL_START([VCO_CAL_START:B0 0x6F(0)])=0b1
State can be changed without command from MCU. If one of the following condition is met, state is changed
automatically according to the following table. In order to enable these functions, the following registers must
be programmed.
Function
Control bit name
Automatic TX_ON after FIFO write completion (AUTO_TX)
AUTO_TX_EN([RF_STATUS_CTRL:B0 0x0A(4)])
Automatic TX_ON during FIFO write (FAST_TX)
FAST_TX_EN([RF_STATUS_CTRL:B0 0x0A(5)])
RF state setting after packet transmission completion
TXDONE_MODE[1:0]([RF_STATUS_CTRL:B0 0x0A(1-0)])
RF state setting after packet reception completion
RXDONE_MODE[1:0]([RF_STATUS_CTRL:B0 0x0A(3-2)])
Automatic RX_ON/TX_ON by Wake-up timer
WAKEUP_MODE([SLEEP/WU_SET:B0 0x2D(6)])
WAKEUP_EN([SLEEP/WU_SET:B0 0x2D(4)])
Automatic VCO calibration after exit from SLEEP
AUTO_VCOCAL_EN([VCO_CAL_START:B0 0x6F(4)])
Automatic SLEEP by timer
WU_DURATION_EN([SLEEP/WU_SET:B0 0x2D(5)])
Automatic SLEEP by high speed carrier checking mode
FAST_DET_MODE_EN([CCA_CTRL:B0 0x39(3)])
Force_TRX_OFF after PLL unlock detection during TX
PLL_LD_EN([PLL_LOCK_DETECT:B1 0x0B(7)])
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●State Diagram
Each state transition control is described in the following state diagram.
TRX_OFF
Force_TRX_OFF
SLEEP
TRX_OFF
Force_TRX_OFF
SLEEP
RECEIVE
TRASMIT
Force_TRX_OFF
SLEEP
TX start
RX completion
(TRX_OFF)
RX start
(SyncWord detection)
TX completion
(TRX_OFF)
TRX_OFF
Force_TRX_OFF
SLEEP
RX_ON
TX_ON
TRX_OFF
Force_TRX_OFF
SLEEP
RX_ON
Force_TRX_OFF
SLEEP
TRX_OFF
Force_TRX_OFF
SLEEP
TX_ON
TRX_OFF
Force_TRX_OFF
SLEEP
TX_ON
RX_ON
RX_ON
TX_ON
TX_ON
RX_ON
Start VCO_CAL
PLLWAIT
VCO_CAL
completion
Start VCO_CAL
VCOCAL
TRX_OFF
Force_TRX_OFF
VCO_CAL completion
SLEEP
TX_ON
RX_ON
VCO_CAL
SLEEP
TRX_OFF
IDLE
Exit from SLEEP
SLEEP
DEEP
SLEEP
DEEP
SLEEP
SLEEP
Exit from
SLEEP
[STATE]
DEEP SLEEP
SLEEP
TRX_OFF/IDLE
PLL_WAIT
TX_ON
TRANSMIT
RX_ON
RECEIVE
VCO_CAL
Exit from
DEEP SLEEP
Exit from
DEEP SLEEP
State transition instruction
: DEEP SLEEP
: SLEEP
: IDLE (TX-RX stand-by)
: PLL stand-by
: TX ready (TX data waiting)
: TX on-going
: RX stand-by (RX data waiting)
: RX on-going
: VCO calibration
Pins control
Normal sequence
(state transition)
Command from
Higher layer state
ML7344 Self controlled state transition
Fig.3 LSI state diagram
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●SLEEP setting
Deep SLEEP mode: Powers for all blocks except for IO pins are turned off.
SLEEP mode: Main regulator and 26MHz oscillation circuits are turned off. But sub-regulator is turned-on.
The following registers can be programmed to control SLEEP state
Function
Control bit name
Power control
PDN_EN([SLEEP?WU_SET:B0 0x2D(1)])
Wake-up setting
WAKEUP_EN([SLEEP/WU_SET:B0 0x2D(4)])
Wake-up timer clock source setting
WUT_CLK_SOURCE([SLEEP/WU_SET:B0 0x2D(2)])
Internal RC oscillator control
RC32K_EN([CLK_SET2:B0 0x03(3)])
main
regulator
Sub
regulator
26MHz
oscillator
RC
oscilator
Low clock
timer
FIFO
Setting method and internal state for DEEP_SLEEP and various SLEEP modes are as follows:
RESETN pin=”L”
REGPDIN pin=”H”
OFF
OFF
OFF
OFF
OFF
OFF
SLEEP1
[SLEEP/WU_SET: B0 0x2D(4-0)] = 0b0_1011 (*2)
[CLK_SET2: B0 0x03(3)] = 0b0 (default)
OFF
ON
OFF
OFF
OFF
OFF
SLEEP2
[SLEEP/WU_SET: B0 0x2D(4-0)] = 0b0_1001 (*2)
[CLK_SET2: B0 0x03(3)] = 0b0 (default)
OFF
ON
OFF
OFF
(*1)
OFF
ON
SLEEP3
[SLEEP/WU_SET: B0 0x2D(4-0)] = 0b1_1001 (*2)
[CLK_SET2: B0 0x03(3)] = 0b0 (default)
OFF
ON
OFF
OFF
ON
ON
SLEEP4
[SLEEP/WU_SET: B0 0x2D(4-0)] = 0b1_1101 (*2)
[CLK_SET2: B0 0x03(3)] = 0b1
OFF
ON
OFF
ON
ON
ON
SLEEP mode
DEEP_SLEEP
Setting method
(*1) Low speed clock is supplied from EXT_CLK pin.
(*2) Please set proper value to [SLEEP/WU_SET: B0 0x2D(3)].
NOTE: Contents of registers are not kept during DEEP_SLEEP. Contents of registers are kept during SLEEP1, SLEEP2,
SLEEP3 and SLEEP4.
However, in SLEEP1 mode, contents of TX FIFO and RX FIFO are not kept, because power to FIFO is turned off.
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●Notes to set RF state
ML7344 is able to change the internal RF state transition autonomously (without commands from MCU) as
well as RF state change commands from MCU. (please refer to ”LSI state transition instruction”). If both
timing of operation (autonomous state and state change from MCU command) overlapped, unintentional RF
state may occur. Timing of autonomous state RF change is described in the following table.
Care must be taken not to overlap the conditions.
Function
RF state change
(before → after)
Automatic TX
FAST_TX
mode
TRX_OFF/RX_ON
→TX_ON
RF state setting
after
TX completion
TX_ON→TRX_OFF
RF state setting
after
RX completion
RX_ON→TRX_OFF
Wake-up timer
SLEEP→TX_ON
TX_ON→RX_ON
TX_ON→SLEEP
RX_ON→TX_ON
RX_ON→SLEEP
SLEEP→RX_ON
SLEEP→VCO_CAL
→TX_ON
SLEEP→VCO_CAL
→RX_ON
Continuous
operation timer
TX_ON→SLEEP
RX_ON→SLEEP
High speed
carrier checking
PLL unlock
detection
RX_ON→SLEEP
TX_ON→TRX_OFF
RF state transition timing (not from
Host MCU command)
Recommended process
After TX data transfer completion interrupt
occurs, {value [TX_RATE_H/L: B1 0x02/03)] ×
2 / 26}[μs] period
When FIFO write access exceed trigger level
+1, {value [RX_RATE1_H/L:B1 0x04/05] × 5 /
26}[μs] period.
After TX completion interrupt (INT[16] group3),
{value [TX_RATE_H/L:B1 0x02/03] × 2 / 26}
[μs] period
After RX completion interrupt (INT[8] group2),
{value [RX_RATE1_H/L:B1 0x04/05] × 2 /
26}[μs] period
Write access to [RF_STATUS:B0
0x0B] is possible after RF state
transition completion interrupt
(INT[3] group1), or move to the
state defined by GET_TRX
([RF_STATUS:B0 0x0B(7-4)]).
After wake-up timer completion interrupt
(INT[6] group1), 1 clock cycle period defined by
WUT_CLK_SET[3:0] ([WUT_CLK_SET: B0
0x2E(3-0)]).
After wake-up timer completion interrupt
(INT[6] group1), before VCO calibration
completion interrupt (INT[1] group1).
Write access to [RF_STATUS:B0
0x0B] and BANK2 is possible
after VCO calibration completion
interrupt (INT[1] group1).
After continuous operation timer completion, 1
clock cycle period defined by WUT_CLK_SET
[3:0] ([WUT_CLK_SET: B0 0x2E(3-0)]).
Write access to [RF_STATUS:B0
0x0B] is possible after RF state
transition completion interrupt
(INT[3] group1), or move to the
state defined by GET_TRX
([RF_STATUS:B0 0x0B(7-4)]).
After CCA completion interrupt (INT[18]
group3), duration 6.3[μs].
After PLL unlock detection interrupt (INT[2]
group1) occurs, duration 147[μs].
Write access to [RF_STATUS:B0
0x0B] is possible 147μs after PLL
unlock interrupt (INT[2] group1)
detected.
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●Packet Handling Function
●Packet format
ML7344 supports Wireless M-BUS frame FormatA/B, and Format C which is non Wireless M-BUS universal
format. The following packet handling are supported in FIFO mode or DIO mode
1) Preamble and SyncWord automatic insertion (TX)
2) Preamble and SyncWord automatic detection (RX)
3) Preamble and SyncWord automatic deletion (RX)
4) CRC data insertion (TX)
5) CRC check and error notification (RX)
-----------
DIO/FIFO mode
DIO/FIFOmode
DIO/FIFO mode
FIFO mode
DIO/FIFO mode
The following table shows the control bit relating with Packet format function.
Function
Packet format setting
RX extended link layer mode disable
Data area bit order setting
Length area bit order setting
Extended link layer mode setting
Length field setting
Control bit name
PKT_FORMAT[1:0] ([PKT_CTRL1: B0 0x04(1-0)])
RX_EXTPKT_OFF ([PKT_CTRL1: B0 0x04(3)])
DAT_LF_EN ([PKT_CTRL1: B0 0x04(4)])
LEN_LF_EN ([PKT_CTRL1: B0 0x04(5)])
EXT_PKT_MODE[1:0] ([PKT_CTRL1: B0 0x04(7-6)])
LENGTH_MODE ([PKT_CTRL2: B0 0x05(0)])
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(1) Format A (Wireless M-BUS)
By setting PKT_FORMAT[1:0] ([PKT_CTRL1: B0 0x04(1-0)])=0b00, Wireless M-BUS Format A is selected.
Format A consists of 1st Block, 2nd Block and Optional Block(s). Each block has 2 bytes of CRC. “L-field” (1st
byte of 1st Block) indicates packet length, which includes subsequenct user data bytes from “C-field”. However,
CRC bytes and postanble are excluded. Depending on “L-field” value, 2nd Block and Optional Block(s) are added.
The following [] indicates register address [bank #, address].
Manchester/3-out-of-6 applicable [B0 0x07(3-2, 1-0)]
CRC applicable
CRC applicable
CRC applicable
LSB
MSB
Sync
Preamble
Word
1st Block
Length
A CRC CI
L
C
M
field field field field field field
> n*2(*1) 10/18/
1
6
2
1
1
2
bits
32bits byte byte bytes bytes bytes byte
[B0 0x07] [B0 0x08]
[B0 0x42] [B1 0x25-2E]
[B0 0x43]
(*2)
2nd Block
Optional Block
Data
field
CRC
field
Data
field
CRC
field
Max.15
bytes
2
bytes
Max.16
bytes
2
bytes
(*2)
(*2)
Postamble
0/2-8
bits
[B0 0x44]
(*3)
[B0 0x05]
[B0 0x7A/7B, 7D/7E]
(*4)
TX: automatic insertion
RX: automatic detection, deletion
*1: Each mode has different minimum value of n.
*2: Indicates TX FIFO data storage area size.
*3: Indicates RX FIFO data storage area size.
*4: When RXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(7-6)])=0b10, indicates DCLK/DIO output area.
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Extended Link Layer Format
If “CI-field” (1st byte of 2nd Block)=0x8C or 0x8D, Extended Link Layer is applied. The packet format is as
follows:
(1) CI-field = 0x8C
For TX, if 2 bytes extention format is used, set EXT_PKT_MODE[1:0] ([PKT_CTRL1: B0 0x04(7-6)])=0b01.
For RX, if RX_EXTPKT_OFF([PKT_CTRL1: B0 0x04(3)])=0b0, ML7344 recognizes “CI-field” and RX
operation is processed.
Manchester/3-out-of-6 applicable [B0 0x07(3-2,1-0)]
CRC applicable
CRC applicable
LSB
MSB
Sync
Preamble
Word
Extended
Length
Block
1st Block
(*1)
2nd Block
L C to CRC CI CC ACC CI
field
field
field field field field
> n*2(*1) 10/18/
1
bits
32bits byte
Data
field
CRC
field
1 Max.12
2
1
1
1
byte byte byte byte bytes bytes
11
bytes
(*2)
[B0 0x07] [B0 0x08]
[B0 0x42] [B1 0x25-2E]
[B0 0x43]
Optional Block
Data
field
CRC
field
Max.16
bytes
2
bytes
(*2)
Postamble
0/2-8
bits
[B0 0x44]
(*3)
[B0 0x05]
[B0 0x7A/7B, 7D/7E]
(*4)
TX: automatic insertion
RX: automatic detection, deletion
*1: 1st Block is identical to normal Format A.
*2: Indicates TX FIFO data storage area size.
*3: Indicates RX FIFO data storage area size.
*4: When RXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(7-6)])=0b10, indicates DCLK/DIO output area.
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(2) CI-field = 0x8D
For TX, if 8 bytes extention format is used, set EXT_PKT_MODE[1:0] ([PKT_CTRL1: B0 0x04(7-6)])=0b10.
For RX, if RX_EXTPKT_OFF([PKT_CTRL1: B0 0x04(3)])=0b0, ML7344 recognizes “CI-field” and RX
operation is processed.
Manchester/3-out-of-6 applicable [B0 0x07(3-2,1-0)]
CRC applicable
CRC applicable
CRC applicable
LSB
MSB
Sync
Preamble
Word
Extended
Length
Block
1st Block
(*1)
2nd Block
L C - CRC CI CC ACC SN CRC CI Data
field field field field field field field field field
> n*2(*1) 10/18/
1
bits
32bits byte
Optional
Block
CRC Data
field field
CRC
field
1
1 Max.15 2 Max.16 2
1
1
4
2
byte byte byte bytes bytes byte bytes bytes bytes bytes
11
bytes
(*2)
[B0 0x07] [B0 0x08]
[B0 0x42] [B1 0x25-2E]
[B0 0x43]
(*2)
(*2)
Postamble
0/2-8
bits
[B0 0x44]
(*3)
[B0 0x05]
[B0 0x7A/7B, 7D/7E]
(*4)
TX: automatic insertion
RX: automatic detection, deletion
*1: 1st Block is identical to normal Format A.
*2: Indicates TX FIFO data storage area size.
*3: Indicates RX FIFO data storage area size.
*4: When RXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(7-6)])=0b10, indicates DCLK/DIO output area.
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(2) Format B (Wireless M-BUS)
By setting PKT_FORMAT[1:0] ([PKT_CTRL1: B0 0x04(1-0)])=0b00, Wireless M-BUS Format B is selected.
Format B consists of 1st Block, 2nd Block and Optional Block(s). Each block has 2 bytes of CRC. “L-field” (1st
byte of 1st Block) indicates packet length, which includes subsequenct user data bytes from “C-field”. However,
unlike Format A, CRC bytes are included. (postanble are excluded.) Depending on “L-field” value, 2nd Block and
Optional Block(s) are added.
The following [] indicates register address [bank #, address].
Manchester/3-out-of-6 applicable [B0 0x07(3-2,1-0)]
CRC applicable
CRC applicable
LSB
MSB
Sync
Preamble
Word
1st Block
Length
2nd Block
Optional Block
L
C
M
field field field
A
field
CI
field
Data
field
CRC
field
Data
field
CRC
field
> n*2(*1) 10/18/
1
1
2
bits
32bits byte byte bytes
6
bytes
1
byte
Max.115
bytes
2
bytes
Max.126
bytes
2
bytes
(*2)
[B0 0x07] [B0 0x08]
[B0 0x42] [B1 0x25-2E]
[B0 0x43]
(*2)
Postamble
0/2-8
bits
[B0 0x44]
(*3)
[B0 0x05]
[B0 0x7A/7B, 7D/7E]
(*4)
TX: automatic insertion
RX: automatic detection, deletion
*1: Each mode has different minimum value of n.
*2: Indicates TX FIFO data storage area size.
*3: Indicates RX FIFO data storage area size.
*4: When RXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(7-6)])=0b10, indicates DCLK/DIO output area.
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Extended Link Layer Format
If “CI-field” (1st byte of 2nd Block)=0x8C or 0x8D, Extended Link Layer is applied. The packet format is as
follows:
(1) CI-field = 0x8C
For TX, if 2 bytes extention format is used, set EXT_PKT_MODE[1:0] ([PKT_CTRL1: B0 0x04(7-6)])=0b01.
For RX, if RX_EXTPKT_OFF([PKT_CTRL1: B0 0x04(3)])=0b0, ML7344 recognizes “CI-field” and RX
operation is processed.
Manchester/3-out-of-6 applicable [B0 0x07(3-2,1-0)]
CRC applicable
CRC applicable
LSB
MSB
Sync
Preamble
Word
Extended
Length
Block
1st Block
(*1)
L
field
> n*2(*1) 10/18/
1
bits
32bits byte
C, M, A
field
CI CC ACC CI
field field field field
2nd Block
Data
field
CRC
field
1 Max.112 2
1
1
1
byte byte byte byte bytes bytes
9
bytes
(*2)
[B0 0x07] [B0 0x08]
[B0 0x42] [B1 0x25-2E]
[B0 0x43]
Optional Block
Data
field
CRC
field
Max.126
bytes
2
bytes
(*2)
Postamble
0/2-8
bits
[B0 0x44]
(*3)
[B0 0x05]
[B0 0x7A/7B, 7D/7E]
(*4)
TX: automatic insertion
RX: automatic detection, deletion
*1: 1st Block is identical to normal Format B.
*2: Indicates TX FIFO data storage area size.
*3: Indicates RX FIFO data storage area size.
*4: When RXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(7-6)])=0b10, indicates DCLK/DIO output area.
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(2) CI-field = 0x8D
For TX, if 8 bytes extention format is used, set EXT_PKT_MODE[1:0] ([PKT_CTRL1: B0 0x04(7-6)])=0b10.
For RX, if RX_EXTPKT_OFF([PKT_CTRL1: B0 0x04(3)])=0b0, ML7344 recognizes “CI-field” and RX
operation is processed.
Manchester/3-out-of-6 applicable [B0 0x07(3-2,1-0)]
CRC applicable
CRC applicable
CRC applicable
LSB
MSB
Sync
Preamble
Word
Extended
Length
Block
1st Block
(*1)
2nd Block
L C,M,A CI CC ACC SN CRC CI
field field field field field field field field
> n*2(*1) 10/18/
1
9
bits
32bits byte bytes
Data
field
Optional
Block
CRC Data
field field
CRC
field
1
1 Max.106 2 Max.126 2
1
1
4
2
byte byte byte bytes bytes byte bytes bytes bytes bytes
[B0 0x07] [B0 0x08]
[B0 0x42] [B1 0x25-2E]
[B0 0x43]
(*2)
(*2)
(*2)
Postamble
0/2-8
bits
[B0 0x44]
(*3)
[B0 0x05]
[B0 0x7A/7B, 7D/7E]
(*4)
TX: automatic insertion
RX: automatic detection, deletion
*1: 1st Block is identical to normal Format B.
*2: Indicates TX FIFO data storage area size.
*3: Indicates RX FIFO data storage area size.
*4: When RXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(7-6)])=0b10, indicates DCLK/DIO output area.
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(3) Format C (non Wireless M-BUS, general purpose format)
By setting PKT_FORMAT([PKT_CTRL1: B0 0x04(1-0)])=0b10, Format C, which is non Wireless M-BUS
format, is selected. Format C consists of 1st Block only, which has 2 bytes of CRC. “L-field” indicates packet
length, which includes subsequent user data bytes, including CRC bytes. The length of “L-field” is defined by
LENGTH_MODE ([PKT_CTRL2:B0 0x5(0]). Data Whitening function is supported.
The following [] indicates register address [bank #, address].
Manchester/3-out-of-6 applicable [B0 0x07(3-2,1-0)]
Whitening applicable [B0 0x08(0)]
CRC applicable
LSB
MSB
Preamble
> n*2(*1)
bits
[B0 0x07]
[B0 0x42]
[B0 0x43]
Sync
Word
Max.
32bits
Length
1st Block
Postamble
L
field
Data
field
CRC
field
1/2
byte
Max.2047
bytes
0/1/2/4
bytes
0/2-8
bits
[B0 0x05]
[B0 0x44]
[B0 0x08]
[B0 0x05]
[B1 0x25-2E] [B0 0x7A/7B]
[B0 0x7D/7E]
(*2)
(*3)
(*4)
TX: automatic insertion
RX: automatic detection, deletion
*1: Preamble length (n) is programable by [TXPR_LEN_H/L: B0 0x42/43] registers.
*2: Indicates TX FIFO data storage area size.
*3: Indicates RX FIFO data storage area size.
*4: When RXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(7-6)])=0b10, indicates DCLK/DIO output area.
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●CRC function
ML7344 has CRC32,CRC16 and CRC8 function. CRC is calculated and appended to TX data. CRC is
checked for RX data. The following modes are used for automatic CRC function.
●FIFO mode:
●DIO mode:
RXDIO_CTRL ([DIO_SET: B0 0x0C(7-6)]) = 0b00
RXDIO_CTRL ([DIO_SET: B0 0x0C(7-6)]) = 0b11
Function
TX CRC setting
RX CRC setting
CRC length setting
CRC complement value OFF setting
CRC polynomial setting
CRC error status
Control bit name / Register
TX_CRC_EN([PKT_CTRL2: B0 0x05(2)])
RX_CRC_EN([PKT_CTRL2: B0 0x05(3)])
CRC_LEN([PKT_CTRL2: B0 0x05(5-4)])
CRC_COMP_OFF([PKT_CTRL2: B0 0x05(6)])
[CRC_POLY3/2/1/0: B1 0x16/17/18/19] registers
[CRC_ERR_H/M/L: B0 0x13/14/15] registers
Any CRC polynomials for CRC32/CRC16/CRC8 can be specified. Reset value is as follows:
CRC16 polynomial = x16 + x13 + x12 + x11 + x10 + x8 + x6 + x5 + x2 + 1 (reset value)
NOTE: CRC result data can be inverted by CRC complement value OFF setting,
CRC data will be generated by the following circuits. By programming [CRC_POLY3/2/1/0] registers, any
CRC polynomials can be supported. Generated CRC will be transfer from the most left bit (S15). If data length
is shorter than CRC length (3 bytes of CRC32 only), data “0”s will be added for CRC calculation. CRC check
result is stored in [CRC_ERR_H/M/L] registers.
Unlike Format C, Format A/B can include multiple CRC fields in one packet. For multiple CRCs check results,
CRC value closest to L-field will be stored in CRC_ERR[0] ([CRC_ERR_L:B0 0x15(0)]). Subsequent bit will
be stored in CRC_ERR from MSB order.
CRC_POLY
[14]
CRC_POLY
[13]
CRC_POLY
[1]
CRC_POLY
[0]
Input
Data
S14
S15
NOTE:
S2
S1
S0
exclusive OR
Fig.4 CRC16 polynomial circuits
General CRC polynomial can be programmed by below [CRC_POLY3/2/1/0] register setting.
CRC length can be set by CRC_LEN.
CRC polynomial
CRC8
CRC16
CRC32
8
2
x +x +x+1
16
12
5
x +x +x +1
16
15
2
x +x +x +1
16
13
12
11
10
8
6
5
2
x +x +x +x +x +x +x +x +x +1
32
26
23
22
16
12
11
10
8
7
x +x +x +x +x +x +x +x +x +x
5
4
2
+x +x +x +x+1
(B1 0x16)
0x00
0x00
0x00
0x00
0x02
[CRC_POLY3/2/1/0]
(B1 0x17) (B1 0x18)
0x00
0x00
0x00
0x08
0x00
0x40
0x00
0x1E
0x60
0x8E
(B1 0x19)
0x03
0x10
0x02
0xB2
0xDB
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●Data whitening function (non Wireless M-BUS standard)
ML7344 supports Data whitening function. In packet format A/B, subsequent data followed by C-field can be
processed data whitening. In packet format C, data Whitening is applied from data field. Data generated by the
following 9 bit pseudo random sequence (PN9) will be “XOR” with TX data (encoded data if Manchester or
3-out-of 6 coding is selected) before transmission. Intialization value of the PN9 generation shift register can be
defined by [WHT_INIT_H/L: B1 0x64/65] registers. PN9 polynomial can be programmed with [WHT_CFG:
B1 0x66] register.
Function
Data whitening setting enable
Data whitening initialization value
Whitening polynomial
Control bit name
WHT_SET ([DATA_SET2: B0 0x08(0)])
WHT_INIT[8:0] ([WHT_INIT_H/L: B1 0x64(0)/65(7-0)])
WHT_CFG[7:0] ([WHT_CFG: B1 0x66(7-0)])
In order to make feedback from S1 register, setting 0b1 to WHT_CFG0 ([WHT_CFG: B1 0x66(0)]). Similaly
in order to make feedback from S2 register, setting 0b1 to WHT_CFG1 ([WHT_CFG: B1 0x66(1)]). Other bits
of [WHT_CFG: B1 0x66] register has same function. Two or more bits can be also set to 0b1. Therefore any
type of PN9 polinominal can be programmed.
Whitening
data
S8
NOTE:
S7
S6
S5
S4
S3
S2
S1
S0
exclusive OR
Fig.5 Whitening data generation circuits
(generator polynomial: x9 + x5 + 1)
General PN9 polynomial can be defined by WHT_CFG[7:0].
PN9 polynomial
9
4
x +x +1
9
5
x +x +1
WHT_CFG[7:0]
[WHT_CFG: B1 0x66]
0x08
0x10
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●SyncWord detection function
ML7344 supports automatic SyncWord recognition function. By having two sets of SyncWord pattern storage
area, it is possible to detect two different packet format (Format A/B) which are defined by Wireless M-Bus.
(For details, please refer to Wireless M-BUS standard) Receiving packet format is indicated by
SW_DET_RSLT([STM_STATE:B0 0x77(5)]). In Format C, it is possible to search for two SyncWords but
detected result is not indicated.
1) TX
SyncWord pattern defined by SYNCWORD_SEL ([DATA_SET2: B0 0x08(4)]) will be selected. SyncWord
length for TX is defined by SYNC_WORD_LEN[5:0] ([SYNC_WORD_LEN: B1 0x25(5-0)]). From high bit
of each SyncWord pattern will be transmitted.
SYNCWORD_SEL
0
1
TX SyncWord pattern
SYNC_WORD1[31:0]
([SYNCWORD1_SET3/2/1/0: B1 0x27/28/29/2A])
SYNC_WORD2[31:0]
([SYNCWORD2_SET3/2/1/0: B1 0x2B/2C/2D/2E])
[Example] SyncWord patten and SyncWord length
If the follwing registers are programmed, from higher bit of SYNC_WORD1[17:0] will be transmitted
sequencially.
[SYNC_WORD_LEN: B1 0x25]=0x12
SYNCWORD_SEL ([DATA_SET2: B0 0x08(4)]) = 0b0
If the following registers are programmed, from higher bit of SYNC_WORD2[23:0] will be transmitted
sequencially.
[SYNC_WORD_LEN: B1 0x25]=0x18
SYNCWORD_SEL ([DATA_SET2: B0 0x08(4)]) = 0b1
2) RX
By setting SYNCWORD_SEL and 2SW_DET_EN ([DATA_SET2: B0 0x08(4,3)]), One SyncWord pattern
waiting or two SyncWord patterns waiting can be selected as follows: Packet format automatic detection is
valid if 2SW_DET_EN=0b1 and Format A or Fromat B is selected by PKT_FORMAT[1:0] ([PKT_CTRL1:B0
0x04(1-0)]).
2SW_
DET_EN
SYNCWORD
_SEL
SyncWord pattern
During Sync
Detection
0
0
SYNC_WORD1[31:0]
0
1
SYNC_WORD2[31:0]
1
−
SYNC_WORD1[31:0]
SYNC_WORD2[31:0]
SyncWord
Detection
operation
Waiting for
1 pattern
Waiting for
1 pattern
Waiting for
2 patterns
Automatic
packet
format
detection
no
no
yes
Data process after SyncWord
Process according to each
Format setting
Process according to each
Format setting
[Format A or Format B setting]
If matched with SYNC_WORD1,
then process as Format A.
If matched with SYNC_WORD2,
then process as Format B.
[Format C setting]
Process as Format C
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Length of SyncWord pattern can be defined by SYNC_WORD_LEN[5:0] ([SYNC_WORD_LEN: B1
0x25(5-0)]). In this case, SyncWord pattern defined by the length from low bit of SYNC_WORD1[31:0] or
SYNC_WORD2[31:0] will be the pattern for checking.
[Example] SyncWord length
If the following registers are set, 18 bit of SYNC_WORD1[17:0] or SYNC_WORD2[17:0] will be reference
pattern for the SyncWord detection. Higher bits (bit31-18) are not checked.
[SYNC_WORD_LEN: B1 0x25]=0x12
[SYNC_WORD_EN: B1 0x26]=0x0F
32bit SyncWord pattern can be controlled by enabling/disabling by each 8bit, when receiving SyncWord. The
following table describes enable/disable control and SyncWord pattern.
[SYNC_WORD_EN]
(B1 0x26)
[31:24]
SYNC_WORD*
[23:16] [15:8]
[7:0]
SyncWord detection operation
No SyncWord detection
0000
0001
D.C.(*1)
ON
0010
D.C.
ON
D.C.
0011
D.C.
ON
ON
0100
D.C.
ON
D.C.
0101
D.C.
ON
D.C.
ON
0110
D.C.
ON
ON
D.C.
0111
D.C.
ON
ON
ON
1000
ON
1001
ON
1010
ON
D.C.
ON
D.C.
1011
ON
D.C.
ON
ON
1100
ON
ON
1101
ON
ON
D.C.
ON
1110
ON
ON
ON
D.C.
1111
ON
ON
ON
ON
D.C.
D.C.
ON
D.C.
Only [7:0] are valid.
Upon [7:0] detection, SyncWord detection.
Only [15:8] are valid.
Upon [7:0] detection, SyncWord detection.
[15:0] are valid.
Upon [7:0] detection, SyncWord detection.
Only [23:16] are valid.
Upon [7:0] detection, SyncWord detection.
[23:16] and [7:0] are valid.
Upon [7:0] detection, SyncWord detection.
[23:8] are valid.
Upon [7:0] detection, SyncWord detection.
[23:0] are valid.
Upon [7:0] detection, SyncWord detection.
Only [31:24] are valid.
Upon [7:0] detection, SyncWord detection.
[31:24] and [7:0] are valid.
Upon [7:0] detection, SyncWord detection.
[31:24] and [15:8] are valid.
Upon [7:0] detection, SyncWord detection.
[31:24] and [15:0] are valid.
Upon [7:0] detection, SyncWord detection.
[31:16] are valid.
Upon [7:0] detection, SyncWord detection.
[31:16] and [7:0] are valid.
Upon [7:0] detection, SyncWord detection.
[31:8] are valid.
Upon [7:0] detection, SyncWord detection.
Whole [31:0] are valid.
Upon [7:0] detection, SyncWord detection.
(*1) D.C. stands for Don’t Care.
(*2) Preamble pattern can be added to the SyncWord detection conditions by RXPR_LEN[5:0]
([SYNC_CONDITION1 :B0 0x45(5-0)]).
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●Field check function
ML7344 has the function of comparing the 9 bytes following L-field (Format A/B: start from C-field, Format
C: start from Data-field) in a receiving packet. Based on comparison with the expected data, possible to
generate interrupts (Field check function). Field check can be possible with the following register setting. When
using this function, RXDIO_CTRL [1:0] ([DIO_SET:B0 0x0C(7-6)]) = 0b00 (FIFO mode) or 0b11 (data
output mode 2) setting is required.
Function
RX data process setting when Field check unmatched
Field check interrupt setting
C-field detection enable setting
M-field detection enable setting
A-field detection enable setting
C-field code setting
M-field code setting
A-field code setting
Register
[C_CHECK_CTRL: B0 0x1B(7)]
[C_CHECK_CTRL: B0 0x1B(6)]
[C_CHECK_CTRL: B0 0x1B(4-0)]
[M_CHECK_CTRL: B0 0x1C(3-0)]
[A_CHECK_CTRL: B0 0x1D(5-0)]
[C_FIELD_CODE1: B0 0x1E]
[C_FIELD_CODE2: B0 0x1F]
[C_FIELD_CODE3: B0 0x20]
[C_FIELD_CODE4: B0 0x21]
[C_FIELD_CODE5: B0 0x22]
[M_FIELD_CODE1: B0 0x23]
[M_FIELD_CODE2: B0 0x24]
[M_FIELD_CODE3: B0 0x25]
[M_FIELD_CODE4: B0 0x26]
[A_FIELD_CODE1: B0 0x27]
[A_FIELD_CODE2: B0 0x28]
[A_FIELD_CODE3: B0 0x29]
[A_FIELD_CODE4: B0 0x2A]
[A_FIELD_CODE5: B0 0x2B]
[A_FIELD_CODE6: B0 0x2C]
The following describes the relation between each comparison code and incoming RX data.
[Format A/B(Wireless M-Bus)]
Field check can be controlled by setting disabled/enabled for each comparison code (1 byte). If all specified
Field data (C-field/M-field/A-field) are matched, Field checking matching will be notified. However, if C-field
data and C_FIELD_CODE5 are matched, even if other Field data (M-field/A-field) are not matched, Field check
result will be notified as ”match”.
MSB
LSB
Preamble
Sync
Word
Over n*2
bit
10/18/
32bits
1st Block
L
field
C
field
M
field
A
field
CRC
field
1
byte
1
byte
2
bytes
6
bytes
0/2
bytes
A1
A2
A3
C1
M3
C2 M1
M4
C3 M2
C4
C1: [C_FIELD_CODE1: B0 0x1E] C5
C2: [C_FIELD_CODE2: B0 0x1F] M1. [M_FIELD_CODE1: B0 0x23]
C3: [C_FIELD_CODE3: B0 0x20] M2. [M_FIELD_CODE2: B0 0x24]
C4: [C_FIELD_CODE4: B0 0x21] M3. [M_FIELD_CODE3: B0 0x25]
C5: [C_FIELD_CODE5: B0 0x22] M4. [M_FIELD_CODE4: B0 0x26]
A4
A5
A6
A1. [A_FIELD_CODE1: B0 0x27]
A2. [A_FIELD_CODE2: B0 0x28]
A3. [A_FIELD_CODE3: B0 0x29]
A4. [A_FIELD_CODE4: B0 0x2A]
A5. [A_FIELD_CODE5: B0 0x2B]
A6. [A_FIELD_CODE6: B0 0x2C]
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Check Field
C-field
st
M-field 1 byte
nd
M-field 2 byte
A-field
Comparison Code
C_FIELD_CODE1 or C_FIELD_CODE2 or
C_FIELD_CODE3 or C_FIELD_CODE4 or
C_FIELD_CODE5
M_FIELD_CODE1 or M_FIELD_CODE2
M_FIELD_CODE3 or M_FIELD_CODE4
A_FIELD_CODE1/2/3/4/5/6
Conditions for match
If one of the 5 comparison code is matched
If one of the 2 comparison code is matched.
If one of the 2 reference pattern is matched.
If comparison codes are matched.
[Format C]
Field check can be controlled by setting disabled/enabled for each comarison code (1 byte). If all specified
Field data (specified table below) are matched, Field checking matching will be notified. However, if 1st byte of
Data field and C_FIELD_CODE5 are matched, even if other Field data(from 2nd byte to 9th byte) are not
matched, Field check result will be notified as ”match”.
MSB
LSB
Preamble
Over n*2
bit
Sync
Word
10/18/
32bits
1st Block
1
byte
C1: [C_FIELD_CODE1: B0 0x1E]
C2: [C_FIELD_CODE2: B0 0x1F]
C3: [C_FIELD_CODE3: B0 0x20]
C4: [C_FIELD_CODE4: B0 0x21]
C5: [C_FIELD_CODE5: B0 0x22]
Check Field
st
Data-field 1 byte
nd
Data-field 2 byte
rd
Data-field 3 byte
th
Data-field 4 byte
th
Data-field 5 byte
th
Data-field 6 byte
th
Data-field 7 byte
th
Data-field 8 byte
th
Data-field 9 byte
Data
field
L
field
1
byte
C1
C2
C3
C4
C5
1
byte
1
byte
M1
M2
M3
M4
···
1
byte
1
byte
1
byte
1
byte
1
byte
1
byte
A1
A2
A3
A4
A5
A6
M1. [M_FIELD_CODE1: B0 0x23]
M2. [M_FIELD_CODE2: B0 0x24]
M3. [M_FIELD_CODE3: B0 0x25]
M4. [M_FIELD_CODE4: B0 0x26]
Comparison Code
C_FIELD_CODE1 or C_FIELD_CODE2 or
C_FIELD_CODE3 or C_FIELD_CODE4 or
C_FIELD_CODE5
M_FIELD_CODE1 or M_FIELD_CODE2
M_FIELD_CODE3 or M_FIELD_CODE4
A_FIELD_CODE1
A_FIELD_CODE2
A_FIELD_CODE3
A_FIELD_CODE4
A_FIELD_CODE5
A_FIELD_CODE6
···
A1. [A_FIELD_CODE1: B0 0x27]
A2. [A_FIELD_CODE2: B0 0x28]
A3. [A_FIELD_CODE3: B0 0x29]
A4. [A_FIELD_CODE4: B0 0x2A]
A5. [A_FIELD_CODE5: B0 0x2B]
A6. [A_FIELD_CODE6: B0 0x2C]
Conditions for match
If one of the 5 comparison code is matched
If one of the 2 comparison code is matched.
If one of the 2 comparison code is matched.
If comparison code is matched.
If comparison code is matched.
If comparison code is matched.
If comparison code is matched.
If comparison code is matched.
If comparison code is matched.
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●Packet processing as a result of Field checking
By setting CA_RXD_CLR ([C_CHECK_CTRL: B0 0x1B(7)])=0b1, if the result of Field check is unmatch,
data packet will be aborted and wait for next packet data.
●Storing number of unmatched packets
Unmatched packets can be counted up to max. 2047 packets and result are stored in [ADDR_CHK_CTR_H:
B1 0x62] and[ADDR_CHK_CTR_L: B1 0x63]. This count value can be cleared by STATE_CLR4
([STATE_CLR: B0 0x16(4)]).
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●FIFO control function
ML7344 has on-chip TX_FIFO(64Byte) and RX_FIFO(64Byte). As TX/RX_FIFO do not support multiple
packets, packet should be processed one by one. If RX_FIFO keeps RX packet and next RX packet is received,
RX_FIFO will be overwritten. It applies to TX_FIFO as well. However TX FIFO access error interrupt
(INT[20] group3) will be generated. When receiving, RX data is stored in FIFO (byte by byte) and the host
MCU will read RX data through SPI. When transmitting, host MCU write TX data to TX_FIFO through SPI
and transmitting through RF.
Writing or reading to FIFO is through SPI with burst access. TX data is written to [WR_TX_FIFO: B0 0x7C]
register. RX data is read from [RD_FIFO: B0 0x7F] register. Continuous access increments internal FIFO
counter automatically. If FIFO access is suspended during write or read operation, address will be kept until the
packet will be process again. Therefore, when resuming FIFO access, next data will be resumed from the
suspended address.
FIFO control register are as follows:
Function
TX FIFO Full level setting
TX FIFO Empty level setting
RX FIFO Full level setting
RX FIFO Empty level setting
FIFO readout setting
RX FIFO data usage status indication
TX packet Length setting
RX packet Length setting
TX FIFO
FIFO read
Register
[TXFIFO_THRH: B0 0x17]
[TXFIFO_THRL: B0 0x18]
[RXFIFO_THRH: B0 0x19]
[RXFIFO_THRL: B0 0x1A]
[FIFO_SET: B0 0x78]
[RX_FIFO_LAST: B0 0x79]
[TX_PKT_LEN_H/L: B0 0x7A/7B]
[RX_PKT_LEN_H/L: B0 0x7D/7E]
[WR_TX_FIFO: B0 0x7C]
[RD_FIFO: B0 0x7F]
[TX]
i) TX data L-field value is set to [TX_PKT_LEN_H: B0 0x7A], [TX_PKT_LEN_L: B0 0x7B] register. If
Length is 1 byte, [TX_PKT_LEN_L] register will be transmitted.
Length can be set to LENGTH_MODE([PKT_CTRL2: B0 0x05(0)]).
ii) TX data is written to [WR_TX_FIFO:B0 0x7C] register.
NOTE:
1. If TX_FIFO write sequence is aborted during transmission, STATE_CLR0 [STATE_CLR:B0 0x16(0)]
(TX FIFO pointer clear) must be issued. Otherwise data pointer is kept in the LSI and the next packet is
not processed properly.
For example, TX FIFO access error interrupt (INT[20] group3) is generated. This interrupt can be
generated when the next packet data is writren to the TX_FIFO before transmitting previous packet data or
FIFO overrun (FIFO is written when no TX_FIFO space) or underrun (attempt to transmit when TX_FIFO
is empty)
2. Depending on the packet format, TX data Length value is different.
Format A: Length includs data area excluding L-field and CRC data.
Format B: Length includes data area excluding L-field.
Format C: Length includes data area excluding L-field.
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[RX]
i) L-field (Length) is read from [RX_PKT_LEN_H: B0 0x7D], [RX_PKT_LEN_L: B0 0x7E] registers.
ii) Reading RX data from FIFO. When reading from RX_FIFO, set FIFO_R_SEL([FIFO_SET: B0
0x78(0)])= 0b0. If FIFO_R_SEL=0b1 , TX_FIFO will be selected. Data usage value of RX_FIFO is
indicated by [RX_FIFO_LAST: B0 0x79] register.
NOTE:
1. If reading FIFO data is terminated before reading all data, STATE_CLR1 [STATE_CLR: B0 0x16(1)]
(RX FIFO pointer clear) must be issued. Otherwise If RX_FIFO is not cleared, the pointer controlling
FIFO data keeps the same status. Next RX data will not be processed in the FIFO properly.
For example, when RX_FIFO access error interrupt (INT[12] group2) is generated. This interrupt occurs
when RX_FIFO overrun (data received when no space in RX_FIFO) or underrun (reading empty
RX_FIFO).
2. If 1 packet data is kept in the RX_FIFO, next RX data will be overwritten.
IF TX/RX pack is larger than FIFO size, FIFO access can be controlled by FIFO-Full trigger or FIFO-Empty
trigger.
(1) TX_FIFO usage notification function
This function is to notice TX_FIFO usage to the MCU using interrupt (SINTN). If TX_FIFO usage
(un-transmitted data in TX_FIFO) exceed the Full level threshold set by [TXFIFO_THRH: B0 0x17] register,
interrupt will generate as FIFO-full interrupt (INT[5] group1). If TX_FIFO usage is smaller than Empty level
threshold set by [TXFIFO_THRL: B0 0x18] register, FIFO-Empty interrupt will generate as FIFO-Empty
interrout (INT[4] grou1). Interrupt signal (SINTN) can be output from GPIO* or EXT_CLK pin.
For output setting, please refer to [GPIO1_CTRL: B0 0x4E], [GPIO1_CTRL: B0 0x4F], [GPIO2_CTRL: B0
0x50], [GPIO3_CTRL: B0 0x51], [EXTCLK_CTRL: B0 0x52] registers for output setting.
[FIFO usage]
SINTN signal
Clear interrupt
Generate interrupt
when written Data
exceed Full level
Full level
(Example 0x2E)
Generate interrupt
when TX data
usage is smaller
than Empty level
TX data amount
TX data amount
Full level
0x2E
Empty level
(Example 0x0F)
0x0F
TX_FIFO usage
0x3F
Empty level
Time
0x00
TX start timing by
FAST_TX trigger
TX_FIFO usage
transition
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[Reference Sequence]:
1.
Set Full level threshold and Empy level threshold..Each threshold should set as TXFIFO_THRH[5:0]
([TXFIFO_THRH:B0 0x17(5-0)]) > TXFIFO_THRL[5:0] ([TXFIFO_THRL:B0 0x18(5-0)]). And
enabling Full level threshold by TXFIFO_THRH_EN([TXFIFO_THRH:B0 0x17(7)=0b1.
2.
Enabling FAST_TX mode by FAST_TX_EN([RF_STATUS_CTRL:B0 0x0A(5)])=0b1 and start
writing TX data to the TX_FIFO[WR_TX_FIFO:B0 0x7C] until FIFO-Full interrupt (INT[5] group1)
occurs.
3.
After FIFO-Full interrupt is generated, Clear the interupt. Then disabling Full level threshold
(TXFIFO_THRH_EN= 0b0) and enabling Empty level threshold (TXFIFO_THRL_EN
([TXFIFO_THRL:B0 0x18(7)])=0b1).
4.
After FIFO-Empty interrupt (INT[4] group1) is generated, Clear the interupt. Then disabling Empty
level threshold (TXFIFO_THRL_EN=0b0) and enabling Full level threshold (TXFIFO_THRH_
EN=0b1). Then resume writing TX data to the TX_FIFO until next FIFO-Full interrupt occurs.
5.
Repeat 3.-4. until completion of TX.
NOTE:
When skip disabling threshold level at sequece 3. or 4., depending on TX data read (PHY block) and
TX_FIFO write timing through SPI, in the middle of TX_FIFO writing, unwiilling FIFO-Full interrupt or
FIFO-Empty interrupt may occurs.
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(2) RX_FIFO usage notification function
This function is to notify remaining RX_FIFO by using interrupt (SINTN) to the MCU. If RX_FIFO usage
(un-read data in RX_FIFO) exceed Full level threshold defined by [RXFIFO_THRH: B0 0x19] register,
interrupt will generate as FIFO-Full interrupt (INT[5] group1). After MCU read RX data from RX_FIFO,
un-read amount become smaller than Empty level threshold defined by [RXFIFO_THRL: B0 0x1A] register,
interrupt will generated as FIFO-Empty (INT[4] group1). Interrupt signal (SINTN) can be output from GPIO*
or EXT_CLK.
For output setting, please refer to [GPIO1_CTRL: B0 0x4E], [GPIO1_CTRL: B0 0x4F], [GPIO2_CTRL: B0
0x50], [GPIO3_CTRL: B0 0x51], [EXTCLK_CTRL: B0 0x52] registers.
[FIFO usage]
SINTN signal
Clear interrupt
Generate interrupt
when RX Data
exceed Full level
Full level
(Example 0x2E)
Generate interrupt
when un-read data
amount is less than
Empty level after
read RX data from
RX FIFO.
RX data amount
RX data amount
0x2E
Empty level
(Example 0x0F)
0x0F
Full level
RX FIFO usage
0x3F
Empty level
Time
0x00
RX_FIFO usage
transition
[Reference Sequence]:
1. Set Full level threshold and Empy level threshold..Each threshold should set as RXFIFO_THRH[5:0]
([RXFIFO_THRH:B0 0x19(5-0)]) > RXFIFO_THRL[5:0] ([RXFIFO_THRL:B0 0x1A(5-0)]). And
enabling Full level threshold by RXFIFO_THRH_EN([RXFIFO_THRH:B0 0x19(7)=0b1.
2. After issuing RX_ON, wait FIFO-Full interrupt (INT[5] group1) generation.
3. After FIFO-Full interrupt is generated, Clear the interupt. Then disabling Full level threshold
(RXFIFO_THRH_EN= 0b0) and enabling Empty level threshold (RXFIFO_THRL_EN
([RXFIFO_THRL:B0 0x1A(7)])=0b1). And start reading RX data from RX_FIFO [RD_FIFO:B0
0x7F].
4. After FIFO-Empty interrupt (INT[4] group1) is generated, Clear the interupt. Then disabling Empty
level threshold (TXFIFO_THRL_EN=0b0) and enabling Full level threshold (TXFIFO_THRH_
EN=0b1). Then resume writing TX data to the TX_FIFO until next FIFO-Full interrupt occurs.
5. Repeat 3.-4. until completion of RX data read out.
NOTE:
When skip disabling threshold level at sequece 3. or 4., depending on RX data write (PHY block) and
RX_FIFO read timing through SPI, in the middle of RX_FIFO reading, unwiilling FIFO-Full interrupt or
FIFO-Empty interrupt may occurs.
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●DIO function
Using GPIO0-3, EXT_CLK or SDI/SDO pins, TX/RX data can be input/output. Pins can be configured by
[GPIO*_CTRL: B0 0x4E/0x4F/0x50/0x51], [EXTCLK_CTRL: B0 0x52] and [SPI/EXT_PA_CTRL: B0 0x53]
registers.
Data format for TX/RX are as follows:
TX --- TX data (NRZ or Manchester/3-out-of-6coding) will be input.
RX --- pre-decoded RX data or decoded RX data will be output. (selectable by [DIO_SET: B0 0x0C] register)
DIO function registers are as follows:
Function
DIO RX data output start setting
DIO RX completion setting
TX DIO mode setting
RX DIO mode setting
Registers
[DIO_SET: B0 0x0C(0)]
[DIO_SET: B0 0x0C(2)]
[DIO_SET: B0 0x0C(5-4)]
[DIO_SET: B0 0x0C(7-6)]
(1)In case of using GPIO*, EXT_CLK pins
If GPIO0-3 or EXT_CLK pins are used as DCLK/DIO, DCLK/DIO should be controlled as follow. (below
DIO/DCLK vertical line part indicate output or input period)
[TX]
i) Continuous input mode (from host)
Set TXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(5-4)]) =0b01.
After TX_ON(SET_TRX[3:0]([RF_STATUS: B0 0x0B(3-0)])=0x9), DCLK is output continuously. At
falling edge of DCLK, TX data is input from DIO pin. TX data must be encoded data.
TX_ON
Preamble
TX data
SyncWord
Data-field
DIO(GPIO0-3,EXT_CLK)
DCLK(GPIO0-3,EXT_CLK)
TX_ON
command
TRX_OFF
command
NOTE: For details of timing, please refer to the “TX” in the “Timing Chart”.
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ii) Data input mode (from host)
Set TXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(5-4)]) =0b10.
After TX_ON, DCLK is output during data input period after SyncWord. TX data is input at falling edge of
DCLK through DIO input. Encoded TX data must be transferred from the host. Preamble and SyncWordis
generated automatically according to the registers setting.
TX_ON
TX data
Preamble
SyncWord
Data-field
DIO(GPIO0-3,EXT_CLK)
DCLK(GPIO0-3,EXT_CLK)
TRX_OFF
command
TX_ON
command
NOTE:.
Preamble can be set by PB_PAT([DATA_SET1: B0 0x07(7)] and TXPR_LEN[15:0] ([TXPR_LEN_H/L:B0
0x42/43]).
SyncWord can be set by SYNCWORD_SEL([DATA_SET1: B0 0x08(4)), SYNCWORD_LEN[5:0]
([SYNC_WORD_ LEN: B1 0x25(5-0)]), SYNC_WORD_EN* ([SYNC_WORD_EN: B1 0x26(3-0)]),
SYNC_WORD1[31:0] ([SYNCWORD1_ SET3/2/1/0: B1 0x27/28/29/2A]) and SYNC_WORD2[31:0]
([SYNCWORD2_SET3/2/1/0: B1 0x2B/2C/2D/2E]).
[RX]
i) Continuous output mode (to host)
Set RXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(7-6)]) =0b01.
After RX_ON(SET_TRX[3:0] ([RF_STATUS: B0 0x0B(3-0)])=0x6), DCLK is output continuously. RX data
(demodulated data) is output from DIO pin at falling edge of DCLK. RX data is not stored into RX_FIRO.
RX_ON
Preamble
RX data
SyncWord
Data-field
DIO(GPIO0-3,EXT_CLK)
DCLK(GPIO0-3,EXT_CLK)
RX_ON
command
TRX_OFF
command
NOTE: For details of timing, please refer to the “RX” in the “Timing Chart”.
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ii) Data output mode 1 (to host)
Set RXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(7-6)]) =0b10.
After SyncWord detection, RX data is buffered in RX_FIFO. RX data buffering will continue until RX sync
signal (SYNC) becomes ”L”. By setting DIO_START ([DIO_SET: B0 0x0C(0)])=0b1, top data of buffered
data will be output through DIO interface (DIO/DCLK). (RX data is output at falling edge of DCLK).
However, if DIO_START setting is done after 64 byte timing, the top byte will be over written. If all buffered
data is output until SYNC becomes ”L”, RX completion interrupt (INT[8] group 2) will be generated. After
RX completion, ready to receive next packet.
RX_ON
RX data
Preamble
SyncWord
Data-field
RX sync signal
Buffering to RX_FIFO
DIO(GPIO0-3,EXT_CLK)
DCLK(GPIO0-3,EXT_CLK)
RX_ON
command
DIO_START =0b1
TRX_OFF
command
NOTE:
1. RX data buffering in RX_FIFO is accessed byte by byte. DIO_START should be issued after 1 byte
access cycle upon SyncWord detection.
2. This mode does not process L-field. Field checking function is not supported.
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If DIO_START is issued before SyncWord detection, data is not buffered in RX_FIFO and RX data after
SyncWord detection will be output at falling edge of DCLK . In order to complete RX before SYNC
becomes ”L”, DIO RX completion setting (DIO_RX_COMPLETE([DIO_SET: B0 0x0C(2)]=0b1) is
necessary. After DIO_RX_COMPLETE setting, ready to receive the next packet.
RX_ON
RX data
Preamble
SyncWord
Data-field
RX sync signal
Buffering to RX_FIFO
DIO(GPIO0-3,EXT_CLK)
DCLK(GPIO0-3,EXT_CLK)
RX_ON
command
DIO_START=0b1
DIO_RX_COMPLETE
=0b1
TRX_OFF
command
iii) Data output mode 2 (to host)
Set RXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(7-6)])=0b11.
Only Data-field of RX data is buffered in RX_FIFO. RX data indicated by L-field is stored in RX_FIFO. By
DIO_START([DIO_SET: B0 0x0C(0)])=0b1, top data of buffered data will be output through DIO interface
(DIO/DCLK). (RX data is output at falling edge of DCLK).
However, if DIO_START setting is done after 64 byte timing, the top byte will be overwritten. If all data
indicated by L-field is output, RX completion interrupt (INT[8] group2) will be generated. After RX
completion, ready to receive next packet. Length information is stored in [RX_PKT_LEN_H/L: B0
0x7D/7E] registers. This mode support fileld check function.
RXON
RX data
Preamble
SyncWord
L-field
Data-field
DIO(GPIO0-3,EXT_CLK)
DCLK(GPIO0-3,EXT_CLK)
RX_ON
command
DIO_START=0b1
TRX_OFF
command
NOTE:
RX data buffering in RX_FIFO is byte by byte access. DIO_START should be issued after elapsed time from
SyncWord detection to L-field length + over 1byte access time.
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(2)In case of using SDI/SDO pins (sharing with SPI interface)
If SDI and SDO pins are used as DCLK/DIO, DCLK/DIO should be controlled as follow. (below DIO/DCLK
vertical line part indicate output or input period) Both SDO_CFG and SDI_CFG ([SDI/EXT_PA_CTRL:B0
0x53(5,4)]) should be set 0b1
[TX]
i) Continuous input mode (from host)
Set TXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(5-4)]) =0b01.
After TX_ON(SET_TRX[3:0] ([RF_STATUS: B0 0x0B(3-0)])=0x9), during SCEN pin is “H”, DCLK is
output from SDO pin., TX data can be input from DIO pin at falling edge of DCLK. TX data must be encoded
data. After TRX_OFF is issued (SET_TRX[3:0] ([RF_STATUS: B0 0x0B(3-0)])=0x8), DCLK output will
stop. During DCLK output, if SCEN pin becomes “L”, DCLK output will stop. (SPI access has priority)
TXON
TX data
Preamble
SyncWord
Data-field
SCEN
DIO(SDI)
DCLK(SDO)
TX_ON
command
TRX_OFF
command
NOTE:
Not to access SPI until TX completion. During packet transmission, if SPI access is attempted by the host, TX
data error can be expected.
ii) Data input mode (from host)
Set TXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(5-4)])=0b10.
After TX_ON, when SCEN is ”H”, DCLK is output from SDO pin during data input period after SyncWord.
At falling edge of DCLK, TX data should be input to SDI from the host. After TRX_OFF is issued
(SET_TRX[3:0] ([RF_STATUS: B0 0x0B(3-0)])=0x8), DCLK output will stop. During DCLK output period,
if SCEN becomes “L”, DCLK output will stop. (SPI access has a priority)
TXON
TX data
Preamble
SyncWord
Data-field
SCEN
DIO(SDI)
DCLK(SDO)
TX_ON
command
TRX_OFF
command
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NOTE:
Not to access SPI until TX completion. During packet transmission, if SPI access is attempted by the host, TX
data error can be expected.
[RX]
i) Continuous output mode (to host)
Set RXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(7-6)])=0b01.
After RX_ON (SET_TRX[3:0]([RF_STATUS: B0 0x0B(3-0)])=0x6) issued, during SCEN is ”H” period,
DCLK is output from SDO pin, RX data is output from SDI pin at falling edge of DCLK. After TRX_OFF
issuing(SET_TRX[3:0] ([RF_STATUS: B0 0x0B(3-0)])=0x8), DCLK/DIO output will stop. Even if
DCLK/DIO are output, when SCEN becomes “L”, DCLK/DIO will stop. (SPI access has a higher priority)
RXON
RX data
Preamble
SyncWord
Data-field
SCEN
DIO(SDI)
DCLK(SDO)
RX_ON
command
TRX_OFF
command
NOTE:
Not to access SPI until RX completion. During packet transmission, if SPI access is attempted by the host, RX
data error can be expected.
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ii) Data ouput mode 1 or data output mode 2 (to host)
Set RXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(7-6)])=0b10/11
After RX_ON, RX data upon SyncWord (output mode 1) or RX data upon L-fileld (output mode 2) is buffered
in RX_FIFO. During SCEN is ”H”, by DIO_START([DIO_SET: B0 0x0C(0)])=0b1, top data of buffered data
will be output through DIO interface (DIO/DCLK). (RX data is output at falling edge of DCLK). Other output
condition is same as the case of using GPIO:/ECT_CLK pins. After TRX_OFF isuing, DCLK/DIO output will
stop. Even during DCLK/DIO are output period, if SCEN becomes “L”, DCLK/DIO output will stop. (SPI
access has a priority)
(In case of data output mode1)
RXON
RX data
Preamble
SyncWord
Data-field
SCEN
DIO(SDI)
DCLK(SDO)
RX_ON
command
DIO_START
DIO_RX_COMPLETE
=0b1
=0b1
TRX_OFF
command
NOTE:
Not to access SPI until RX completion. During packet transmission, if SPI access is attempted by the host, RX
data error can be expected.
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(3)DCLK output method
In Data output mode 2, decoded data is output. Therefore, The DCLK output section in a output interval
changes with the coding method. DCLK output section is as follows.
In othe modes, undecoded data is input or output. DCLK is output continuously. Then, it is not depend on the
coding method.
i) Data output mode 2
DCLK
Clock output (8 cycle)
1 cycle=1/data rate[bps]
Output interval
NRZ:
: 8 cycle
Manchester
:16 cycle
3 out of 6
:12 cycle
Output interval
ii) TX continuous input mode or RX continuous mode
DCLK
1 cycle=1/data rate[bps]
(*) The nuber of cycle per 1 byte
NRZ
: 8 cycle
Manchester
:16 cycle
3 out of 6
:12 cycle
iii) TX Data input mode / RX Data output mode1
DCLK
TX: The timing during transmitting
the last 2 bit SyncWord
RX: DIO_START issue
1 cycle=1/data rate[bps]
(*) The nuber of cycle per 1 byte
NRZ
: 8 cycle
Manchester
:16 cycle
3 out of 6
:12 cycle
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●Timer Function
●Wake-up timer
ML7344 has automatic wake-up function using wake-up timer. The following operations are possible by using
wake-up timer.
• Upon timer completion, automatically wake-up from SLEEP state. After wake-up operation can be selected
as RX_ON state or TX_ON state by WAKEUP_MODE ([SLEEP/WU_SET: B0 0x2D(6)]).
• By setting WUT_1SHOT_MODE ([SLEEP/WU_SET: B0 0x2D(7)]), continuous wake-up operation
(interval operation) or one shot operation can be selected
• In interval operation, if RX_ON/TX_ON state is caused by wake-up timer, continuous operation timer is in
operation.
• After moving to RX_ON state by wake-up timer, when continuous operation timer completed, move to
SLEEP state automatically. However, if SYncWord is detected before timer completion, RX_ON state will
be maintained. In this case, ML7344 does not go back to SLEEP state automatically. SLEEP setting
(SLEEP_EN ([SLEEP/WU_SET: B0 0x2D(0)])=0b1) is necessary to go back to SLEEP state. However, if
RXDONE_ MODE[1:0] ([RF_STATUS_CTRL:B0 0x0A(3-2)])=0b11, after RX completion, move to
SLEEP state automatically.
For ML7344C, when continuous operation timer completed, the condition for continuing reception is
selected from Sync Word detection or Field check result by RCV_CONT_SEL([C_CHECK_CTRL: B0
0x1B(5)]).
• After moving to TX_ON state by wake-up timer, when continuous operation timer completed, move to
SLEEP state automatically.
• After wake-up by combining with high speed carrier checking mode, CCA is automatically performed, if
IDLE is detected, able to move to SLEEP state immediately. For details, please refer to the “(3) high speede
carrier detection mode”.
• By setting WU_CLK_SOURCE ([SLEEP/WU_SET:B0 0x2D(2)]), clock source for wake-up timer are
selectable from EXT_CLK pin or on-chip RC OSC.
Wake-up interval, wake-up timer interval and continuous operation timer can be calculated in the following
formula.
Wake-up interval [s] = Wake-up timer interval [s] + Continuous operation timer [s]
Wake-uptimer interval [s] = Wake-up timer clock cycle *
Division setting ([WUT_CLK_SET: B0 0x2E(3-0)]) *
(Wake-up timer interval setting ([WUT_INTERVAL_H/L: B0 0x2F/0x30]) + 1)
Continuous operation timer [s] = Wake-up timer clock cycle *
Division setting([WUT_CLK_SET: B0 0x2E(7-4)]) *
(Continuous operation timer setting ([WU_DURATION: B0 0x31]) – 1)
NOTE:
• In case of moving to TX_ON state after wake-up, move to SLEEP state when timer completed even in the
middle of transmission. Continuous oeration timer should be set in such manner that timer completing after
TX completion.
• WUDT_CLK_SET[3:0] ([WUT_CLK_SET: B0 0x2E(7-4)]) and WUT_CLK_SET[3:0] ([WUT_CLK_
SET: B0 0x2E (3-0)]) can be set independently. In case of using continuous operation timer, please set the
same value as WUDT_CLK_SET as WUT_CLK_SET.
• Minimum value for wake-up timer interval setting ([WUT_INTERVAL_H/L: B0 0x2F/0x30]) is 0x02. And
minimum value for continuous operation timer setting ([WU_DURATION: B0 0x31]) is 0x01.
• Be noted that the SyncWord detection is not issued when in DIO mode with RXDIO_CTRL([DIO_SET: B0
0x0C(7-6)])=0b01. Therefore, when continuous operation timer completed, forcibly move to SLEEP state.
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(1) Interval operation
[RX]
After wake-up, RX_ON state. If continuous operation timer completed before SyncWord detection,
automatically move to SLEEP state. If SyncWord detected, continue RX_ON. After RX completion, conitune
operation defined by RXDONE_MODE[1:0] ([RF_STATUS_CTRL:B0 0x0A(3-2)]).
[SLEEPWU_SET: B0 0x2D(6-4)]=0b011
Continuous operation timer range
[WU_DURATION: B0 0x31]
Wake-up timer operation range
[WUT_INTERVAL_H/L: B0 0x2F/0x30]
Wake-up timer
Continuous
operation timer
RXON
TXON
LSI state
SLEEP
Wake-up timer
enable setting
RXON
RXON
SLEEP
SLEEP
After Wake-up timer
completion , move to
RX_ON state.
RXON
Before Continuous
operation timer
completion,
SyncWord detected.
Continuous operation
timer completion
move to SLEEP state.
SLEEP RXON
*1
SLEEP
After RX completion, move to
SLEEP state by SLEEP
command.
*1 If not issuing SLEEP
command, continue operation
defined by RXDONE_MDE[1:0]
[TX]
After wake-up, TX_ON state. After TX completion, continue operation defined by TXDONE_MODE[1:0]
([RF_STATUS_CTRL: B0 0x08(1-0)]) .
If continuous operation timer completed, automatically return to SLEEP state. So continuous operation timer
has to be set so that timer completion occur after TX completion.
[SLEEP/WU_SET: B0 0x2D(6-4)]=0b111
Wake-up timer operation period
[WUT_INTERVAL_H/L: B0 0x2F/0x30)
Continuous operation timer range
[WU_DURATION: B0 0x28]
Wake-up timer
Continuous
operation timer
RXON
TXON
LSI state
SLEEP
Wake-up operation
enables setting
TXON
TX data write
to TX_FIFO
IDLE
SLEEP
TX completion and move to
IDLE state.
In case of
TXDONE_MODE[1:0]=0b00
TXON
IDLE
SLEEP
TXON
Continuous operation timer
completion, move to SLEEP state.
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(2) 1 shot operation
[RX]
After wake-up timer completion, move to RX_ON state. And continue RX_ON state. Move to SLEEP state by
SLEEP command. If wake-up timer interval setting ([WUT_INTERVAL_H/L:B0 0x2F/0x30]) is maintained,
after re-issuing SLEEP command, 1 shot operation will be activated again.
If RX completed during RX_ON, continue operation defined by RXDONE_ MODE[1:0] ([RF_STATUS_
CTRL: B0 0x0A(3-2)]) . Same manner in TX_ON state.
[SLEEPWU_SET: B0 0x2D(7-4)]=0b1011
Wake-up timer operation range
[WUT_INTERVAL_H/L: B0 0x2F/0x30]
Wake-up timer
Continuous
operation timer
RXON
TXON
LSI state
SLEEP
Wake-up operation
enable setting
RXON
Wake-up timer completion
and move to RXON state
SLEEP
After SLEEP command,
move to SLEEP state.
RXON
RX_ON is maintained if SLEEP
command is not issued.
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(3) Combination with high speed carrier detection
[Intetval operation]
After wake-up timer completion, move to RX_ON state. Then perform CCA. If no carrier detected,
automatically move to SLEEP state. If carrier detected, maintaining RX_ON state and perform SuncWord
detection. If continuous operation timer completed before SyncWord detection, automatically move to SLEEP
state. And If SyncWord detected, continue RX_ON state.
[SLEEP/WU_SET: B0 0x2D(7-4)]=0b0011
FAST_DET_MODE_EN([CCA_CTRL: B0 0x39(3)])=0b1
Continuous operation timer range
[WU_DURATION: B0 0x28]
Wake-up timer operation range
[WUT_INTERVAL_H/L: B0 0x2F/0x30]
Wake-up timer
Continuous
operation timer
RXON
TXON
SLEEP
LSI state
SLEEP
SLEEP
RXON
RXON
RXON
Wake up operation
enable setting
Continuous operation
timer completion, and
move to SLEEP state.
No carrier detection, and
move to SLEEP state.
Carrier detected, and
continue RX_ON.
SLEEP RXON
SLEEP
After RX completion, move to
SLEEP state by command.
SyncWord detection before
continuous operation timer
completion
[1 shot operation]
After wake-up timer completion, move to RX_ON state. And perform CCA to check carrier. If no carrier
detected, go back to SLEEP state automatically. After wake-up timer completion, wake-up to check the carrier
again. If carrier is detected, continue RX state. Able to go back to SLEEP by setting SLEEP parameters.
[SLEEPWU_SET: B0 0x2D(7-4)]=0b1011
FAST_DET_MODE_EN([CCA_CTRL: B0 0x39(3)])=0b1
Wake-up timer operation range
[WUT_INTERVAL_H/L: B0 0x2F/0x30]
Continuous
operation timer
RXON
TXON
LSI state
SLEEP
Wake-up operation
enable setting
SLEEP
RXON
SLEEP
SLEEP
SLEEP
RXON
No carrier detected.
go to SLEEP state
Carrier detected,
continue RXON
By SLEEP command
go to SLEEP state.
RXON
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●General purpose timer
ML7344 has general purpose timer. 2 channel of timer are able to function independently. Clock sources,
timer setting can be programmed independently. When timer is completed, General purpose timer 1 interrupt
(INT[22] group3) or General purpose timer 2 interrupt (INT[23] group3)will be generated.
General timer interval can be programmed as the following formula.
General purpose timer interval[s] = general purpose timer clock cycle *
Division setting ([GT_CLK_SET: B0 0x33]) *
General purpose timer interval setting
([GT1_TIMER: B0 0x34] or [GT2_TIMER: B0 0x35])
By setting GT2/1_CLK_SOURCE ([GT_SET: B0 0x32(5,1)]), clock sources for general purpose timer can
be selectable from wake-up timer clock or 2MHz.
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●Frequency Setting Function
●Channel frequency setting
Maximum 256 channels can be selected (CH#0 -CH#255) by the following resisters.
Frequency
CH#0 frequency
TX
RX
Channel space
Channel setting
-
Register
[TXFREQ_I: B1 0x1B], [TXFREQ_FH: B1 0x1C], [TXFREQ_FM: B1 0x1D]
and [TXFREQ_FL: B1 0x1E]
[RXFREQ_I: B1 0x1F], [RXFREQ_FH: B1 0x20], [RXFREQ_FM: B1 0x21]
and [RXFREQ_FL: B1 0x22]
[CH_SPACE_H: B1 0x23] and [CH_SPACE_L: B1 0x24]
[CH_SET: B0 0x09]
(1) Channel frequency setting overview
[Channel frequency setting]
Using above registers, channel frequency is defined as following formula.
Channel frequency = i) CH#0 frequency + ii) channel space * iii) channel setting
[Channel frequency allocation image]
iii) channel setting
(setting Nth channel)
ii) channel space setting
Channel No. Æ
0
1
2
3
···
···
n
···
255
···
Frequency
i) CH#0 frequency setting
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NOTE:
The channel frequency to be selected must meet the following conditions. If the following conditions cannot
be met, please change channel #0 frequency or use other channels. If this formula cannot be met, expected
frequency is not functional or PLL may not be locked.
(FMCK1*n + 1MHz ) / N_div ≤ channel frequency ≤ (FMCK1*(n+1) – 1MHz ) / N_div
FMCK1: Master clock frequency
N_div = 1 (PLL_MODE ([PLL_DIV_SET: B1 0x1A (4)])=0b0)
2 (PLL_MODE ([PLL_DIV_SET: B1 0x1A (4)])=0b1)
n = integer
Unusable Frequency
Usable Frequency
A
Frequency
(FMCK1*n )/N_div
(FMCK1*(n+1))/N_div
[Calculation example above “A” range]
Condition: Master clock 26MHz, N_div=1(PLL_MODE=0b0), n=16
(26*16+1)MHz ≤ channel frequency to be used ≤ (26*(16+1)-1)
→ 417 MHz ≤ channel frequency to be used ≤ 441MHz
NOTE:
“CH#0 frequency (Hz)” and “channle space (Hz)” may have error (Hz). Then the “channel frequency error
(Hz)” is defined as following formula.
Channel frequency error (Hz) =
CH#0 frequency error (Hz) + channel space error (Hz)* channel setting
When changing “channel frequency” by setting “channel setting” without “CH#0 frequency” change, the
“channel frequency error” will become larger than by setting both “CH#0 frequency” and “channel setting”. If
the “channle frequency error” is larger than expection, please consider to change “CH#0 frequency”.
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(2) Channel #0 frequency setting
TX frequency can be set by [TXFREQ_I: B1 0x1B], [TXFREQ_FH: B1 0x1C], [TXFREQ_FM: B1 0x1D]
and [TXFREQ_FL: B1 0x1E]. RX frequency can be set by [RXFREQ_I: B1 0x1F], [RXFREQ_FH: B1 0x20],
[RXFREQ_FM: B1 0x21] and [RXFREQ_FL: B1 0x22]. When enabling PLL 1/2 division mode by setting
PLL_MODE([PLL_DIV_SET:B1 0x1A(4)])=0b1, calcurated with fref =FMCK1/2 in the following formula.
Channel #0 frequency setting can be caluculated using the following formula.
I=
f rf
(Integer part)
f ref
⎧⎪ f rf
⎫⎪
F =⎨
− I ⎬ ⋅ 2 20 (Integer part)
⎪⎩ f ref
⎭⎪
Here
f rf
:Channel #0 frequency
f ref
I
F
:PLL reference frequency (=master clock frequency: FMCK1)
:Integer part of frequency setting
:Fractional part of frequency setting
I (Hex) is set to [TXFREQ_I: B1 0x1B], [RXFREQ_I: B1 0x1F] registers.
F (Hex.) is set to the following registers.
For TX, from MSB, set in order of [TXFREQ_FH: B1 0x1C], [TXFREQ_FM: B1 0x1D], [TXFREQ_FL:
B1 0x1E] registers.
For RX, from MSB, set in order of [RXFREQ_FH: B1 0x20], [RXFREQ_FM: B1 0x21], [RXFREQ_FL:
B1 0x22] registers.
Frequency error (
f err ) is calculated as follows :
F ⎫
⎧
f err = ⎨ I + 20 ⎬ ⋅ f ref − f rf
⎩ 2 ⎭
[Example]
When set TX channel #0 frequency to 426MHz (master clock 26MHz), the calculations are as follows.
426 MHz
(Integer part) =16(0x10)
26 MHz
⎧ 426 MHz
⎫
F =⎨
− I ⎬ ⋅ 2 20 (Integer part)=403298(0x062762)
⎩ 26 MHz
⎭
I=
[TXFREQ_I: B1 0x1B] = 0x10
[TXFREQ _FH: B1 0x1C] = 0x06
[TXFREQ _FM: B1 0x1D] = 0x27
[TXFREQ _FL: B1 0x1E] = 0x62
Frequency error
f err is as follows:
403298 ⎫
⎧
f err = ⎨16 +
⎬ ⋅ 26 MHz − 426 MHz = −11.45 Hz
2 20 ⎭
⎩
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(3) Channel space setting
Channel space can be set by [CH_SPACE_H: B1 0x23], [CH_SPACE_L: B1 0x24] registers. Hexadecimal
values calculated in the following formula should be set to [CH_SPACE_H: B1 0x23], [CH_SPACE_L: B1
0x24] registers. (MSB->LSB order) When enabling PLL 1/2 division mode by setting PLL_MODE
([PLL_DIV_SET:B1 0x1A(4)])=0b1, calcurated with fref =FMCK1/2 in the following formula.
Channel space is from the center frequency of given channel to adjacent channel center frequency.
Channel space setting value can be calculated using the following formula:
⎧⎪ f sp
CH _ SPACE = ⎨
⎪⎩ f ref
⎫⎪ 20
⎬ ⋅ 2 (Integer part)
⎪⎭
Here
CH _ SPACE : Channel space setting
f sp : Channel space [MHz]
f ref : PLL reference frequency (=master clock frequency : FMCK1)
[Example]
When set channle space to 25kHz (master clock 26MHz), the calculation is as follows.
⎧ 0.025MHz ⎫ 20
CH _ SPACE = ⎨
⎬ ⋅ 2 (Integer part) = 1008 (0x03F0)
⎩ 26 MHz ⎭
[CH_SPACE_H: B1 0x23] = 0x03
[CH_SPACE_L: B1 0x24] = 0xF0
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●IF frequency setting
IF frequency is 200kHz. IF frequency corresponds to each oepration frquency must be selected as below.
169MHz
(ML7344E)
PLL division setting
[PLL_DIV_SET:B1 0x1A]
IF frequency setting
[IF_FREQ_H/L:B0 0x54-55]
Operating Frequency
315 to 450MHz
(ML7344J)
470 t0 510MHz
(ML7344C)
0x10
0x00
0x1F81
0x0FC0
IF frequency setting value can be calculated using the following formula:
⎧⎪ ( f / 2) ⎫⎪ 20
IF _ FREQ = ⎨ IF
⎬ ⋅ 2 (Integer part)
⎪⎩ f ref ⎪⎭
Here
IF _ FREQ : IF frequency setting
f IF : IF frequency [MHz]
f ref : PLL reference frequency (=master clock frequency: FMCK1)
[Example] ML7344C/J
IF_FREQ= {(0. 2MHz / 2) / 26MHz} * 220 (Integer part) = 4032 (0x0FC0)
[IF_FREQ_H: B0 0x54] = 0x0F
[IF_FREQ_L: B0 0x55] = 0xC0
[Example] ML7344E
IF_FREQ= {(0. 2MHz / 2) / (26/2)MHz} * 220 (Integer part) = 8065 (0x1F81)
[IF_FREQ_H: B0 0x54] = 0x1F
[IF_FREQ_L: B0 0x55] = 0x81
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●Modulation setting
ML7344 supports GFSK modulation and FSK modulation.
(1) GFSK modulation setting
By setting GFSK_EN([DATA_SET1: B0 0x07(4)])=0b1, GFSK mode can be selected. In GFSK modulation,
frequency deviation can be set by [GFSK_DEV_H: B1 0x30] and [GFSK_DEV_L: B1 0x31] registers and
Gaussian filter can be set by [FSK_DEV0_H/GFIL0: B1 0x32] to [FSK_DEV3_H/GFIL6: B1 0x38] registers.
When enabling PLL 1/2 division mode by setting PLL_MODE ([PLL_DIV_SET:B1 0x1A(4)])=0b1,
calcurated with fref =FMCK1/2 in the following formula.
i) GFSK frequency deviation setting
F_DEV value can be calculated as the following formula:
⎧⎪ f ⎫⎪
F _ DEV = ⎨ dev ⎬ ⋅ 2 20 (Integer part)
⎪⎩ f ref ⎪⎭
Here
F _ DEV : Frequency deviation setting
f dev : Frequency deviation [MHz]
f ref : PLL reference frequency (= master clock frequency: FMCK1)
[Example]
When set frequency deviation to 50kH (master clock 26MHz), the calculation is as follows.
F_DEV = {0.05MHz ÷ 26MHz} ×220 (Integer value) = 2016 (0x07E0)
[GFSK_DEV_H: B1 0x30] = 0x07
[GFSK_DEV_L: B1 0x31] = 0xE0
ii) Gaussian filter setting
BT value of Gaussian filter and setting value to related registers are shown in the below table.
Register
[FSK_DEV0_H/GFIL0: B1 0x32]
[FSK_DEV0_L/GFIL1: B1 0x33]
[FSK_DEV1_H/GFIL2: B1 0x34]
[FSK_DEV1_L/GFIL3: B1 0x35]
[FSK_DEV2_H/GFIL4: B1 0x36]
[FSK_DEV2_L/GFIL5: B1 0x37]
[FSK_DEV3_H/GFIL6: B1 0x38]
BT value
0.5
0x49
0xA7
0x0F
0x14
0x19
0x1D
0x1E
1.0
0x00
0x10
0x04
0x0D
0x1E
0x32
0x3C
NOTE:
GFSK filter coefficient setting register and FSK frequency deviation setting register are common. In GFSK
mode, filter coefficient applies to this register. In FSK mode, frequency deviation applies to this register.
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(2) FSK modulation setting
By setting GFSK_EN([DATA_SET1: B0 0x07(4)])=0b0, FSK mode can be selected. Fine frequency
deviation can be set by [FSK_DEV0_H/GFIL0: B1 0x32] to [FSK_DEV4_L: B1 0x3B] registers. By adjusting
[FSK_TIM_ADJ4-0: B1 0x3C-40] registers, FSK timing can be fine tuned.
+ΔF
IV
V
III
iv iii ii
i
i ii iii iv
II
I
v iv iii ii i
i ii iii iv
v
I
II
III
-ΔF
IV
V
0 output
1 output
TX_FSK_POL ([DATA_SET1:B0 0x07(6)]) = 0b0 setting
Frequency deviation setting
symbol
Register name
address
I
FSK_FDEV0_H/GFIL0
FSK_FDEV0_L/GFIL1
II
FSK_FDEV1_H/GFIL2
FSK_FDEV1_L/GFIL3
III
FSK_FDEV2_H/GFIL4
FSK_FDEV2_L/GFIL5
IV
FSK_FDEV3_H/GFIL6
FSK_FDEV3_L
V
FSK_FDEV4_H
FSK_FDEV4_L
B1
0x32/33
B1
0x34/35
B1
0x36/37
B1
0x38/39
B1
0x3A/3B
function
Frequency
deviation
Resolution:
Approx.25
Hz
symbol
Timing setting
Register
address
name
i
FSK_TIM_ADJ4
B1 0x3C
ii
FSK_TIM_ADJ3
B1 0x3D
iii
FSK_TIM_ADJ2
B1 0x3E
iv
FSK_TIM_ADJ1
B1 0x3F
v
FSK_TIM_ADJ0
B1 0x40
function
Modulation
timing
4.3MHz/13
MHz
counter
value
(*1)
(*1) Modulation timing resolution can be changed by FSK_CLK_SET ([FSK_CTRL: B1 0x2F(0)]).
NOTE:
GFSK filter coefficient setting register and FSK frequency deviation setting register are common. In GFSK
mode, filter coefficient applies to this register. In FSK mode, frequency deviation applies to this register.
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●RX Related Function
●AFC function
ML7344 supports AFC function. Master clock Frequency accuracy (max. ±10ppm) between transmitter and
receiver can be compensated by this function. Using this function, stable RX sensitivity and interference
blocking performance can be achieved. This function can be enabled by setting AFC_EN([AFC/GC_CTRL:
B1 0x15(7)])=0b1. AFC range is defined by AFC_LIM_OFF ([DEMOD_SET0:B1 0x56(2)]. When setting
0b0 (limit ON), AFC range is ±9ppm. When setting 0b1 (limit OFF), ±10ppm AFC range is avilable.
●Energy detection value (ED value) acquisition function
ML7344 supports calculating Energy detection value (ED value) based on Received signal strength indicator
(RSSI). ED value acquisition can be enabled by setting ED_CALC_EN ([ED_CTRL: B0 0x41(7)])=0b1 and as
soon as transition to RX_ON state, automatically start acquiring ED value. During RX_ON state, ED value
constantly updated.
ED value is not RSSI value at given timing, but average values. Number of average times can be specified by
ED_AVG[2:0] ([ED_CTRL: B0 0x41(2-0)]). After acquiring specified average ED value, ED_DONE
([ED_CTRL: B0 0x41(4)]) becomes ”0b1” and ED_VALUE[7:0] ([ED_RSLT: B0 0x3A]) is updated.
ED_DONE bit will be cleared if one of the following conditions are met.
1. Gain is switched..
2. Once stopping ED value acquisition and then resume it
Timing from ED value starting point to ED value acquisition is calculated as below formula.
ED value average time = AD conversion time (18.5μs/14.7μs) * (Number of average times + 8(Deley)).
NOTE: AD conversion time can be slected by ADC_CLK_SEL([ADC_CLK_SET: B1 0x08(4)]).
Reset value is 1.73MHz and AD conversion time is 18.5μs.
Digital filter delay is “AD conversion time * 8”.
The timing example is as follows:
Set ADC_CLK_SEL ([ADC_CLK_SET: B1 0x08(4)]) =0b1. (1.73 MHz)
Set ED_AVG[2:0] ([ED_CTRL: B0 0x41(2-0)])=0b011. (8 times averaging)
ED value calculation
execution flag
(internal signal)
RSSI value
(internal signal)
AD conversion (18.5μs)
RSSI
1
RSSI
2
RSSI
3
RSSI
4
RSSI
5
RSSI
6
RSSI
7
RSSI
8
RSSI
9
RSSI
10
RSSI
8
ED
1-8
ED
2-9
ED
3-10
Compensation and averaging
ED_VALUE[7:0]
[ED_RSLT: B0 0x3A]
INVALID
ED value averaging period (18.5μs*(8+8)=296μs)
Constantly update
by moving average
ED_DONE
([ED_CTRL:B0 0x41(4)])
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●CCA (Clear Channel Assessment) function
ML7344 supports CCA function. CCA function is to make a judment wheher the specified frequency channel
is in-use or available. Normal mode, continuous mode and IDLE detection mode are supported as following
table.
[CCA mode setting]
Normal mode
Continuous mode
IDLE detection mode
Bit4 (CCA_EN)
0b1
0b1
0b1
[CCA_CTRL: B0 0x39]
Bit5 (CCA_CPU_EN) Bit6 (CCA_IDLE_EN)
0b0
0b0
0b1
0b0
0b0
0b1
(1) Normal mode
Normal mode determines IDLE or BUSY. CCA (Normal mode) will be executed when RX_ON is issued
whille CCA_EN(CCA_CTRL: B0 0x39(4)])=0b1, CCA_CPU_EN (CCA_CTRL: B0 0x39(5)])=0b0 and
CCA_IDLE_EN(CCA_CTRL: B0 0x39(6)])=0b0 are set.
CCA judgement is determined by average ED value in [ED_RSLT: B0 0x3A] register and CCA threshold
value defined by [CCA_LVL: B0 0x37] register. IF average ED value exceeds the CCA threshold value, it is
considered as “BUSY”. And CCA_RSLT[1:0]([CCA_CTRL: B0 0x39(1-0)]) =0b01 is set
If average ED value is smaller than CCA threshold value and maintains IDLE detection period which is
defined by IDLE_WAIT[9:0] of the [IDLE_WAIT_L: B0 0x3B], [IDLE_WAIT_H: B0 0x3C] registers, it is
considered as “IDLE”. And CCA_RSLT[1:0] =0b00 is set. For details operation of CCA_IDLE_WAIT[9:0],
please refer to ”IDLE detection for long time period”
If “BUSY” or “IDLE” state is detected, CCA completion interrupt (INT[18] group3) is generated, CCA_EN
bit is cleared to 0b0 automatically.
Upon clearing CCA completion interrupt, CCA_RSLT[1:0] are reset to 0b00. Therefore CCA_RSLT[1:0]
should be read before clearing CCA completion interrupt.
If an ED value exceeds the value defined by [CCA_IGNORE_LVL: B0 0x36] register, and a given ED value
is included in the averaging target of ED value calculation, IDLE judgement is not performed. In this case if
average ED value exceed CCA threshold value, it is considered as “BUSY” and CCA operation is terminated.
If average ED value is smaller than CCA threshold value, IDLE judgement is not determined. And
CCA_RSLT[1:0] indicates 0b11. CCA operation continues until “BUSY” is determined or the gievn ED value
is out of averaging target and “IDLE” is determined. For details operation of ED value execeeding
[CCA_IGNORE_LVL: B0 0x36] register, please refer to ”IDLE determination exclusion under strong signal
input”.
Time from CCA command issue to CCA completion is in the formula below.
[IDLE detection]
CCA execution time = (ED value average times + Dgital filter delay + IDLE_WAIT setting) *
AD conversion time
[BUSY detection]
CCA execution time = (ED value average times + Digtal filter delay)* AD conversion time
NOTE:
1. Above formula does not consider IDLE judgement exclusion based on [CCA_IGNORE_LVL: B0 0x36]
register. For details, please refer to ”IDLE detection exclusion under strong signal input”.
2. AD conversion time can be slected by ADC_CLK_SEL([ADC_CLK_SET: B1 0x08(4)]).
ADC_CLK_SEL=0b0:14.7μs , 0b1:18.5μs (default)
3. Digital filter delay is “AD conversion time * 8”.
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The following is timing chart for normal mode.
Set ADC_CLK_SEL ([ADC_CLK_SET: B1 0x08(4)]) =0b1. (1.73 MHz)
Set ED_AVG[2:0] ([ED_CTRL: B0 0x41(2-0)])=0b011. (8 times average)
Set IDLE_WAIT[9:0] ([IDLE_WAIT_L/H:B0 0x3C/3B(1-0)])=0b00 0000 0000 (IDLE detection 0µs)
[IDLE detection case]
CCA_EN
[CCA_CTRL: B0 0x39(4)]
AD conversion
(18.5μs)
*1
ED value
ED value average period (16μs*8=128μs)
ED0
(internal signal)
ED1
ED2
ED3
ED4
ED5
ED6
ED7
averaging
ED_VALUE[7:0]
ED
(0-7)
[ED_RSLT: B0 0x3A]
< CCA_LVL
B0 0x37
CCA_RSLT[1:0]
0b00 (IDLE)
0b10 (CCA on-going)
[CCA_CTRL: B0 0x39(1-0)]
INT[18] (CCA completion)
[INT_SOURCE_GRP3: B0 0x0F(2)]
IDLE_WAIT[9:0]
should be set, for
IDLE detection
for longer period.
CCA execution period (Min.296μs)
[BUSY detection case]
CCA_EN
[CCA_CTRL: B0 0x39(4)]
AD conversion
(18.5μs)
ED value
(internal signal)
*1
ED value average period (16μs*8=128μs)
ED0
ED1
ED2
ED3
ED4
ED5
ED6
ED7
averaging
ED_VALUE[7:0]
ED
(0-7)
[ED_RSLT: B0 0x3A]
> CCA_LVL
B0 0x37
CCA_RSLT[1:0]
[CCA_CTRL: B0 0x39(1-0)]
0b10 (CCA on-going)
0b01 (BUSY)
INT[18] (CCA completion)
[INT_SOURCE_GRP3: B0 0x0F(2)]
CCA execution period (Min.296μs)
IDLE_WAIT[9:0]
should be set, for
IDLE detection
for longer period.
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NOTE:
*1 Digital filter delay is “AD conversion time * 8”. AD conversion time can be slected by ADC_CLK_SEL
([ADC_CLK_SET: B1 0x08(4)]). Reset value is 1.73MHz and AD conversion time is 18.5μs.
(2) Continuous mode
Continuous mode continues CCA untill terminated by the host MCU. CCA continuous mode will be executed
when RX_ON is issued while CCA_EN(CCA_CTRL: B0 0x39(4)])=0b1, CCA_CPU_EN(CCA_CTRL: B0
0x39(5)])=0b1 and CCA_IDLE_EN(CCA_CTRL: B0 0x39(6)])=0b0 are set.
Like normal mode, CCA judgement is determined by average ED value in [ED_RSLT: B0 0x3A] register and
CCA threshold defined by [CCA_LVL: B0 0x37] register. IF average ED value exceeds the CCA threshold
value, it is considered as “BUSY”. And CCA_RSLT[1:0]([CCA_CTRL: B0 0x39(1-0)]) = 0b01 is set.
If average ED value is smaller than CCA threshold value and maintains IDLE detection period which is
defined by IDLE_WAIT[9:0] of the [IDLE_WAIT_L: B0 0x3B], [IDLE_WAIT_H: B0 0x3C] registers, it is
considered as “IDLE”. And CCA_RSLT[1:0] =0b00 is set. For details operation of CCA_IDLE_WAIT[9:0],
please refer to ”IDLE detection for long time period”.
If an ED value exceeds the value defined by [CCA_IGNORE_LVL: B0 0x36] register, a given ED value is
included in the averaging target of ED value calculation, IDLE judgement is not performed. In this case if
average ED value exceeds CCA threshold level, it is considered as “BUSY” and CCA_RSLT[1:0] indicates
0b01. If average ED value is smaller than CCA threshold level, IDLE judgement is not determined. And
CCA_RSLT[1:0] indicates 0b11. For details operation of ED value execeeding [CCA_IGNORE_LVL: B0
0x36] register, please refer to ”IDLE determination exclusion under strong signal input”.
Continuous mode does not stop when “BUSY” or “IDLE” is detected. CCA operation continues until 0b1 is
set to CCA_STOP([CCA_CTRL: B0 0x39(7)]). Result is updated every time ED value is acquired. CCA
completion interrup (INT[18] group3) will not be generated.
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The following is timing chart for continuous mode.
Set ADC_CLK_SEL ([ADC_CLK_SET: B1 0x08(4)]) =0b1. (1.73 MHz)
Set ED_AVG[2:0] ([ED_CTRL: B0 0x41(2-0)])=0b011. (8 times average)
Set IDLE_WAIT[9:0] ([IDLE_WAIT_L/H:B0 0x3C/3B(1-0)])=0b00 0000 0000 (IDLE detection 0µs)
[BUSY to IDLE transition, terminated with CCA_STOP]
After CCA_STOP is issued,
CCA_CPU_EN, CCA_EN and,
CCA_STOP are automatically
cleared.
CCA_CPU_EN/CCA_EN
[CCA_CTRL: B0 0x39(5-4)]
CCA_STOP
[CCA_CTRL]B0 0x39
AD conversion
(18.5μs)
ED value
(Internal signal)
*1
ED value average period
(148μs)
ED0
●●●
ED7
ED8
●●●
ED28
ED
(1-8)
●●●
●●●
ED50
averaging
ED_VALUE[7:0]
[ED_RSLT: B0 0x3A]
INVALID
ED
(0-7)
ED
(21-28)
> CCA_LVL
B0 0x37
CCA_RSLT[1:0]
[CCA_CTRL: B0 0x39(1-0)]
0b10 (CCA on-going)
0b01 (BUSY)
INT[18] (CCA Completion)
[INT_SOURCE_GRP3: B0 0x0F(2)]
Interrupt not generated
●●●
ED
(43-50)
<CCA_LVL
B0 0x37
0b00 (IDLE)
IDLE_WAIT[9:0]
should be set, for
IDLE detection for
longer period.
ED_DONE
[ED_CTRL: B0 0x41(4)]
When 8 times ED value acquisition,
ED_DONE=0b1 (8 time averaging setting)
NOTE:
*1 Digital filter delay is “AD conversion time * 8”. AD conversion time can be slected by ADC_CLK_SEL
([ADC_CLK_SET: B1 0x08(4)]). Reset value is 1.73MHz and AD conversion time is 18.5μs.
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(3) IDLE detection mode
IDLE detection mode continues CCA untill IDLE detection. Idle detectin CCA will be executed when
RX_ON is issued while CCA_EN(CCA_CTRL: B0 0x39(4)])=0b1, CCA_CPU_EN(CCA_CTRL: B0
0x39(5)])=0b0 and CCA_IDLE_EN(CCA_CTRL: B0 0x39(6)])=0b1 are set.
Like normal mode, CCA judgement is determined by average ED value in [ED_RSLT: B0 0x3A] register and
CCA threshold defined by [CCA_LVL: B0 0x37] register. IF average ED value exceeds the CCA threshold
value, it is considered as “BUSY”. And CCA_RSLT[1:0]([CCA_CTRL: B0 0x39(1-0)]) =0b01 is set.
If average ED value is smaller than CCA threshold value and maintains IDLE detection period which is
defined by IDLE_WAIT[9:0] of the [IDLE_WAIT_L: B0 0x3B], [IDLE_WAIT_H: B0 0x3C] registers. it is
considered as “IDLE”. And CCA_RSLT[1:0] =0b00 is set. For details operation of CCA_IDLE_WAIT[9:0],
please refer to ”IDLE detection for longer period”.
In IDLE detection mode, only when IDLE is detected, CCA completion interrupt (INT[18] group3) is
generated. After IDLE detection, CCA_EN and CCA_IDLE_EN are reset to 0b0.
Upon clearing CCA completion interrupt, CCA_RSLT[1:0] are reset to 0b00. Therefore CCA_RSLT[1:0]
should be read before clearing CCA completion interrupt.
If an ED value exceeds the value defined by [CCA_IGNORE_LVL: B0 0x36] register, as long as a given ED
value is included in the averaging target of ED value calculation, IDLE judgement is not performed. In this
case, if average ED value is smaller than CCA threshold level, IDLE determination is not performed and
CCA_RSLT[1:0] indicates 0b11. CCA operation continues until given ED value is out of averaging target and
“IDLE” is determined. For details of ED value exceeding [CCA_IGNORE_LVL: B0 0x36] register, please
refer to ”IDLE determination exclusion under strong signal input”.
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The following is timing chart for IDLE detection mode.
Set ADC_CLK_SEL ([ADC_CLK_SET: B1 0x08(4)]) =0b1. (1.73 MHz)
Set ED_AVG[2:0] ([ED_CTRL: B0 0x41(2-0)])=0b011. (8 times average)
Set IDLE_WAIT[9:0] ([IDLE_WAIT_L/H:B0 0x3C/3B(1-0)])=0b00 0000 0000 (IDLE detection 0µs)
[Upon BUSY detection, continue CCA and IDLE detection case]
After IDLE detection, CCA will be completed,
then CCA_EN, CCA_IDLE_EN are reset to
0b0 automatically.
CCA_IDLE_EN/CCA_EN
[CCA_CTRL: B0 0x39(6/4)]
AD conversion
(18.5μs)
ED value
(Internal signal)
*1
ED value average period
(148μs)
ED0
●●●
ED7
ED8
IDLE detection period
●●●
ED27
ED
(1-8)
●●●
ED28 ED29
averaging
ED_VALUE[7:0]
[ED_RSLT: B0 0x3A]
INVALID
ED
(0-7)
ED
ED
ED
(20-27) (21-28) (22-29)
> CCA_LVL
B0 0x37
CCA_RSLT[1:0]
[CCA_CTRL: B0 0x39(1-0)]
0b10 (CCA on-going)
0b01 (BUSY)
<CCA_LVL
B0 0x37
0b00 (IDLE)
INT[18] (CCA Completion)
[INT_SOURCE_GRP3: B0 0x0F(2)]
Interrupt not generated
CCA execution period (Min. 296μs + IDLE detection period)
IDLE_WAIT[9:0]
should be set, for
IDLE detection for
longer period.
NOTE:
*1 Digital filter delay is “AD conversion time * 8”. AD conversion time can be slected by ADC_CLK_SEL
([ADC_CLK_SET: B1 0x08(4)]). Reset value is 1.73MHz and AD conversion time is 18.5μs.
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(4) IDLE determination exclusion under strong signal input
If acquired ED value exceeds [CCA_IGNORE_LVL: B0 0x36] register, IDLE dertermination is not
performed as lon as a given ED value is included in the averaging target range. If average ED value including
this strong ED value indicated in [ED_RSLT: B0 0x39] rehgiser exceeds the CCA threshold value defined by
[CCA_LVL: B0 0x37] register, it is considered as ”BUSY”. And CCA_RSLT[1:0]([CCA_CTRL: B0
0x39(1-0)])=0b01 is set.
If average ED value is smaller than CCA threshold value, IDLE determination is not performed and
CCA_RSLT[1:0] indicates 0b11 ”CCA evaluation on-going (ED value excluding CCA judgement
acquisition)”. CCA will continue until “IDLE” or “BUSY” determination (in case of IDLE detection mode,
“IDLE” is determined. In case of continuous mode, CCA_STOP([CCA_CTRL: B0 0x39(7)]) is issued.)
NOTE:
CCA completion interrupt (INT[18] group3) is generated only when “IDLE” or “BUSY” is determined.
Therefore, if data whose ED value exceeds CCA_IGNORE_LVL are input intermittently, neither “IDLE” or
“BUSY” can be determined and CCA may continues.
[ED value acquisition under extrem strong signal]
ED value >CCA_IGNORE_LVL
[CCA_IGNORE_LVL: B0 0x36]
ED value (analog)
ED value
Shift register [Time 1]
(ED value 8 times
average)
[Time2]
[Time 3]
Averaging target includes
ED value exceeding
CCA_IGNORE_LVL.
In this case “IDLE” is not
determined.
Time
However, if averaging value
exceeds CCA threshold,
“BUSY” is determined.
●
●
●
[Time 8]
[Time 9]
ED value, which includes CCA_IGNORE_LVL,
is out of averaging target. In this case, “IDLE”
can be determined.
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The following is timing chart for IDLE detemination exclusion under strong signal.
Set ADC_CLK_SEL ([ADC_CLK_SET: B1 0x08(4)]) =0b1. (1.73 MHz)
Set ED_AVG[2:0] ([ED_CTRL: B0 0x41(2-0)])=0b011. (8 times average)
Set IDLE_WAIT[9:0] ([IDLE_WAIT_L/H:B0 0x3C/3B(1-0)])=0b00 0000 0111 (IDLE detection 129.5µs)
[During IDLE_WAIT counting, detected extremly strong signal. After the given signal is out of averaging
target, IDLE detection case]
ED VALUE>CCA_IGNORE_LVL
ED value <CCA_IGNORE_LVL
ED value
(internal signal)
●●●
ED7
ED8
●●●
ED value<CCA_IGNORE_LVL
ED13 ED14 ED15
●●●
ED21 ED22
●●●
ED29
Average ED value<CCA_LEVEL
(If average ED value >CCA_LVL, then BUSY detection)
ED_VALUE[7:0]
[ED_RSLT: B0 0x3A]
INVALID
ED
(0-7)
ED
(1-8)
●●●
ED
ED
ED
(6-13) (7-14) (8-15)
ED value>CCA_IGNORE_LVL
detection and reset
CCA_PROG[9:0]
[CCA_PROG_L/H:B0 0x3E/3D]
0x001
●●●
0x006
Due to extreme strong signal detection,
CCA_RSLT is not indicating IDLE.
CCA_RSLT[1:0]
[CCA_CTRL: B0 0x39(1-0)]
INT[18] (CCA completion)
0b10
(on-going)
●●●
ED
ED
(14-21) (15-22)
●●●
ED
(22-29)
Resume counting due to the extreme
strong signal is out of averaging target.
●●●
0x000
0x007
CCA _RSLT maintains until
IDLE/BUSY detected.
0b11
(on-going)
0b00
(IDLE)
CCA_RSLT[1:0]=0b11 do not generate interrupt
[INT_SOURCE_GRP3: B0 0x0F(2)]
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(5) IDLE detection for longer period
When CCA IDLE detection is performed for longer time period, IDLE_WAIT[9:0]([IDLE_WAIT_L/H:B0
0x3C/3B(1-0)] can be used. By setting IDLE_WAIT [9:0], averaging period longer than the period (for
example, AD conversion16μs, 8 times average setting 128μs) can be possible.
This function can be used for IDLE determination – by counting times when average ED value becomes
smaller than CCA threshold defined by [CCA_LVL: B0 0x37] register. When counting exceed IDLE_WAIT
[9:0], IDLE is determined. If average ED value exceeds CCA threshold level, imemediately “Busy” is
determined without wait for IDLE_WAIT [9:0] period.
The following timing chart is IDLE detection setting IDLE_WAIT[9:0].
Set ADC_CLK_SEL ([ADC_CLK_SET: B1 0x08(4)]) =0b1. (1.73 MHz)
Set ED_AVG[2:0] ([ED_CTRL: B0 0x41(2-0)])=0b011. (8 times average)
Set IDLE_WAIT[9:0] ([IDLE_WAIT_L/H:B0 0x3C/3B(1-0)])=0b00 0000 0011 (IDLE detection 55.5µs)
[ED value 8 timesv average IDLE detection case]
CCA_EN
[CCA_CTRL: B0 0x39(4)]
AD conversion
(18.5μs)
ED value
(internal signal)
IDLE detection period
(55.5μs)
ED value average period
(148μs)
*1
ED0
ED1
ED2
●●●
ED7
ED8
ED9
ED10 ED11
ED
(0-7)
ED
(1-8)
ED
ED
(2-9) (3-10)
averaging
ED_VALUE[7:0]
[ED_RSLT: B0 0x3A]
INVALID
< CCA_LVL
B0 0x37
IDLE_WAIT[9:0]
[IDLE_WAIT_L\H: B0 0x3C/3B]
CCA_RSLT[1:0]
[CCA_CTRL: B0 0x39(1-0)]
INT[18] (CCA completion)
0x000
0x001 0x002 0x003
0b10 (CCA on-going)
0b00 (IDLE)
IDLE_WAIT start
[INT_SOURCE_GRP3: B0 0x0F(2)]
CCA execution period (Min.296μs+55.5μs=351.5μs)
(average ED value < CCA_LVL)
continue for AD conversion period
3 times ( 55.5μs), then IDLE is
determined.
NOTE:
*1 Digital filter delay is “AD conversion time * 8”. AD conversion time can be slected by ADC_CLK_SEL
([ADC_CLK_SET: B1 0x08(4)]). Reset value is 1.73MHz and AD conversion time is 18.5μs.
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[ED value 1time IDLE detection case]
Set ADC_CLK_SEL ([ADC_CLK_SET: B1 0x08(4)]) =0b1. (1.73 MHz)
Set ED_AVG[2:0] ([ED_CTRL: B0 0x41(2-0)])=0b000. (1 time average)
Set IDLE_WAIT[9:0] ([IDLE_WAIT_L/H:B0 0x3C/3B(1-0)])=0b00 0000 1110 (IDLE detection 259µs)
CCA_EN
[CCA_CTRL: B0 0x39(4)]
AD conversion
(18.5μs)
ED value
(internal signal)
ED value average
period (18.5μs)
*1
IDLE detection period (259μs)
ED0
ED1
ED2
ED3
●●●
ED13
ED14
●●●
ED
(12)
ED
(13)
Do not average
ED_VALUE[7:0]
[ED_RSLT: B0 0x3A]
INVALID
ED
(0)
ED
(1)
ED
(2)
ED
(14)
< CCA_LVL
B0 0x37
IDLE_WAIT[9:0]
[IDLE_WAIT_L\H: B0 0x3C/3B]
CCA_RSLT[1:0]
[CCA_CTRL: B0 0x39(1-0)]
0x000
0x001 0x002
●●●
0x00C 0x00D 0x00E
0b10 (CCA on-going)
0b00 (IDLE)
INT[18] (CCA completion)
[INT_SOURCE_GRP3: B0 0x0F(2)]
CCA execution period (Min.148μs+18.5μs+259μs =425.5μs)
(average ED value < CCA_LVL)
continue for AD conversion period
14 times (259μs), then IDLE is
determined.
NOTE:
*1 Digital filter delay is “AD conversion time * 8”. AD conversion time can be slected by ADC_CLK_SEL
([ADC_CLK_SET: B1 0x08(4)]). Reset value is 1.73MHz and AD conversion time is 18.5μs.
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(6) CCA threshold setting
CCA threshold value defined by [CCA_LVL: B0 0x37] register, should be considered desired input leve (ED
value), components variation, temperature fluctuation, loss at antenna and matching circuits. Input level and
ED value are described in the follow table.
RSSI value = 1.35 * (input level[dBm] – variations[dBm] – other losses[dBm]) + offset
ED value (CCA threshold) = (RSSI value + RSSI_ADJ) * RSSI_MAG_ADJ
Item
Value
High Sensitivity Mode
High Linearity Mode
offset
164.5
156
Variation (individual, temp.)[dBm]
10
7
Other loss[dBm]
Antenna, matching circuits loss
RSSI_ADJ
The setting of [RSSI_VAL:B1 0x14]
RSSI_MAG_ADJ
The setting of [RSSI_ADJ: B0 0x66]
Example) When input level threshold is set to -85dBm
conditions: High Linearity Mode, other loss = 1dB, RSSI_ADJ=0, RSSI_MAG_ADJ=4.5
RSSI value = 1.35 * (-85 - 7 – 1) + 156
= 30.45
CCA threshold = (30.45 + 0) * 4.5
= 137.025
~ 0x89
In order to validate whether CCA threshold is optimised or not, CCA should be executed and confirmimg
level changing from IDLE to BUSY, every time input level is changed,
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●Other Functions
●Data rate setting function
(1) Data rate change setting
ML73444 supports various TX/RX data rate setting defined by the following registers.
TX: [TX_RATE_H: B1 0x02] and [TX_RATE_L: B1 0x03] registers
RX: [RX_RATE1_H: B1 0x04], [RX_RATE1_L: B1 0x05] and [RX_RATE2: B1 0x06] registers
TX/RX data rate can be defined in the following formula.
[TX]
TX data rate [bps] = round (26MHz / 13/ TX_RATE[11:0])
Recommended values for each data rate are in the table below. Registers value below are automatically set to
[TX_RATE_H],[ TX_RATE_L] registers by setting TX_DRATE[3:0] ([DRATE_SET: B0 0x06(3-0)]).
TX data rate [kbps]
1.2
2.4
4.8
9.6
10.0
11.52
15
[TX_RATE_H][ TX_RATE_L]
register setting value
1667d
833d
417d
208d
200d
174d
133d
Data rate deviation
[%] *1
-0.02
0.04
-0.08
0.16
0.00
-0.22
0.25
*1 Data rate deviation is assumption that frequency deviation of master clock(26MHz crystal oscillator or
TCXO) is 0ppm.
[RX]
RX data rate [bps] = round (26MHz / {RX_RATE1[11:0] ×[RX_RATE2[6:0]})
Recommended values for each data rate are in the table below. Registers value below are automatically set to
[RX_RATE1_H][ RX_RATE1_L] [RX_RATE2] registers by setting RX_DRATE[3:0]( [DRATE_SET:B0
0x06(7-4)] ).
RX dta rate [kbps]
1.2
2.4
4.8
9.6
10
11.52
15
[RX_RATE1_H][RX_RATE1_L]
register setting value
169d
85d
42d
21d
[RX_RATE2]
register setting
0d
0d
0d
0d
NOTE:
When LOW_RATE_EN([CLK_SET2:B0 0x03(0)])=0b1, [RX_RATE1_H/L] and [RX_RATE2] registers
are not set automatically by setting RX_DRATE[3:0]. Please calcurate appropriate values by replacing the
8.66MHz to 26MHz in the above formula and set them to each register.
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(2) Other register setting associate with data rate change
Data rate can be cahnged by RX_DRATE[3:0] ([DRATE_SET(7-4)]) and TX_DRATE[3:0]
([DRATE_SET(3-0)]), below registers may have to be changed.
NOTE:
Depending on data rate, the following chage may not be necessary. For details, please refer to each register
description.
Parameters
Data rate
Channel space
Frequency deviation(GFSK)
Frequencydeviation (FSK)
Frequency deviation time(FSK)
IF adjustment
Demodulator adjustment1
Demodulator adjustment2
Demodulator adjustment3
Demodulator adjustment4
Demodulator adjustment5
Demodulator adjustment6
Demodulator adjustment7
Demodulator adjustment8
Demodulator adjustment9
Registers
Name
DRATE_SET
CH_SPACE_H
CH_SPACE_L
GFSK_DEV_H
GFSK_DEV_L
FSK_DEV0_H/GFIL0
FSK_DEV0_L/GFIL1
FSK_DEV1_H/GFIL2
FSK_DEV1_L/GFIL3
FSK_DEV2_H/GFIL4
FSK_DEV2_L/GFIL5
FSK_DEV3_H/GFIL6
FSK_DEV3_L
FSK_DEV4_H
FSK_DEV4_L
FSK_TIM_ADJ4
FSK_TIM_ADJ3
FSK_TIM_ADJ2
FSK_TIM_ADJ1
FSK_TIM_ADJ0
IFF_ADJ_H
IFF_ADJ_L
DEMOD_SET1
DEMOD_SET2
DEMOD_SET3
DEMOD_SET4
DEMOD_SET5
DEMOD_SET6
DEMOD_SET7
DEMOD_SET8
DEMOD_SET9
Address
B0 0x06
B1 0x23
B1 0x24
B1 0x30
B1 0x31
B1 0x32
B1 0x33
B1 0x34
B1 0x35
B1 0x36
B1 0x37
B1 0x38
B1 0x39
B1 0x3A
B1 0x3B
B1 0x3C
B1 0x3D
B1 0x3E
B1 0x3F
B1 0x40
B0 0x5E
B0 0x5F
B1 0x57
B1 0x58
B1 0x59
B1 0x5A
B1 0x5B
B1 0x5C
B1 0x5D
B1 0x5E
B1 0x5F
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●Interrupt generation function
ML7344 support interrupt generation function. When interrupt occurs, interrupt notification signal (SINTN)
become “L” to notify interrupt to the host MCU. Interrupt elements are divided into the 3 groups,
[INT_SOURCE_GRP1: B0 0x0D], [INT_SOURCE_GRP2: B0 0x0E] and [INT_SOURCE_GRP3: B0 0x0F].
Each interrupt element can be maskalable using [INT_EN_GRP1: B0 0x10], [INT_EN_GRP2: B0 0x11] and
[INT_EN_GRP3: B0 0x12] registers. Interrupt notification signal (SINTN) can be output from GPIO* or
EXT_CLK. For output setting, please refer to [GPIO1_CTRL: B0 0x4E], [GPIO1_CTRL: B0 0x4F],
[GPIO2_CTRL: B0 0x50], [GPIO3_CTRL: B0 0x51] and [EXTCLK_CTRL: B0 0x52] registers.
NOTE: In one of unmask interrupt event occurs, SINTN maintains Low.
(1) Interrupt events table
Each interrupt event is described below table.
Register
Interrupt name
INT[0]
INT[1]
INT[2]
INT_SOURCE_GRP1
INT_SOURCE_GRP2
INT_SOURCE_GRP3
INT[3]
INT[4]
INT[5]
INT[6]
INT[7]
INT[8]
INT[9]
INT[10]
INT[11]
INT[12]
INT[13]
INT[14]
INT[15]
INT[16]
INT[17]
INT[18]
INT[19]
INT[20]
INT[21]
INT[22]
INT[23]
Description
Clock stabilization completion interrupt
VCO calibration completion interrupt/
PLL unlock interrupt or
VCO CAL request interrupt
RF state transition completion interrupt
FIFO-Empty interrupt
FIFO-Full interrupt
Wake-up timer completion interrupt
Clock calibration completion interrupt
RX completion interrupt
CRC error interrupt
Reserved
RX Length error interrupt
RX FIFO access error interrupt
SyncWord detection interrupt
Field checking interrupt
Sync error interrupt
TX completion interrupt
TX Data request accept completion interrupt
CCA completion interrupt
TX Length error interrupt
TX FIFO access error interrupt
Reserved
General purpose timer 1 interrupt
General purpose timer 2 interrupt
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(2) Interrupt generation timing
In each interrupt generation, timing from reference point to interrupt generation (notification) are described in
the following table. Timeout procedure for interrupt notification waiting are also described below.
NOTE:
(1)The values are described in units of “bit cycle” in the below table is the value at 100kbps. If using other data
rate, please esitimate with appropriate “bit cycle”.
(2)Below table uses the following format for TX/RX data.
10 byte
2 byte
1 byte
24 byte
2 byte
Preamble
SyncWord
Length
User data
CRC
(3)Even if each interrupt notification is masked, in case of interrupt occurence, interrupt elements are stored
internally. Therefore, as soon as interrupt notification is unmasked, interrupt will generate.
Interrupt notice
INT[0]
INT[1]
INT[2]
INT[3]
INT[4]
Reference point
Timing from reference point to interrupt generation
or interrupt generation timing
RESETN release
(upon power-up)
50μs
SLEEP release
(recovered from SLEEP)
50μs
VCO calibration
completion
VCO calibration start
230μs
PLL unlock
detection
-
(TX) during TX after PA enable.
(RX) during RX after RX enable.
VCO CAL request
-
(TX) rising edge of PA_ON signal.
(RX) rising edge of RX enable signal.
TX_ON command
(IDLE) 1406μs
(RX) 1188μs
RX_ON command
(IDLE) μs
(TX) 244μs
TRX_OFF command
(TX) 147μs
(RX) 4μs
Force_TRX_OFF
Command
(TX) 147μs
(RX) 4μs
(TX)
TX_ON command
(*1)
NRZ coding, Empty trigger level is set to 0x02
RF wake-up(1406μs)+ 35 byte (preamble to 22nd Data byte) *
8bit *10(bit cycle) =4206μs
CLK stabilization
completion
RF state
transition
completion
FIFO-Empty
detection
(RX) -
By FIFO read, remaining FIFO data is under trigger level
(TX) -
By FIFO write, FIFO usage exceed trigger level
(RX)
SyncWord detection
NRZ coding, Full trigger level is set to 0x05
6byte (Length to 5th Data byte) * 8bit * 10μs(bit cycle) = 480μs
INT[5]
FIFO-FULL
detection
INT[6]
Wake-up timer
completion
SLEEP setting
Wake-up timer is completed.
For details, please refer to “wake-up timer”
INT[7]
Clock calibration
completion
Calibration start
Calibration timer is completed.
For details, please refer to “low speed clock shift detection
function”.
(*1) Before issuing TX_ON, writing full-length TX data to the TX_FIFO.
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Interrupt notice
Timing From reference point to interrupt generation
or interrupt generation timing
Reference point
INT[8]
RX completion
SyncWord detection
NRZ coding, Full trigger level is set to 0x05
27byte (Length to CRC) * 8bit * 10μs(bit cycle) = 2160μs
INT[9]
CRC error
detection
SyncWord detection
(Format A/B) each RX CRC block calculation completion
(Format C) RX completion
INT[10]
Reserved
INT[11]
RX Length error
detection
INT[12]
RX FIFO access
error detection
-
(1)overflow occurs because FIFO read is too slow.
(2)underflow occurs because too many FIFO data is read
INT[13]
SyncWord
detection
-
SyncWord detection
INT[14]
Field check
completion
-
Match or mismatch detected in Field check
INT[15]
Sync error
detection
-
During RX after SyncWord detection, out-of-sync detected.
(When RXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(7-6)]) =0b00 or
0b11.)
INT[16]
TX completion
INT[17]
TX Data request
accept completion
SyncWord detection
TX_ON command
(*1)
-
80μs (L-field 1byte)
160μs (L-field 2byte)
RF wake-up+[TX data+3](bit) after
=1406μs+(39byte ×10 +3 )bit * 10μs (bit cycle)=4556μs
After full length data are written to the TX FIFO.
(1)Normal mode
(ED value calculation averaging time + IDLE_WAIT setting
[IDLE_WAIT_H/L:B0 0x3B,3C] ) * AD conversion time
(2) IDLE detection mode
○IDLE judgment case
(ED value calculation averaging time + IDLE_WAIT setting
[IDLE_WAIT_H/L:B0 0x3B,3C] ) * AD conversion time
○BUSY judgment case
(ED value calculation averaging time) * AD conversion time
AD conversion time can be changed by ADC_CLK_SEL
([ADC_CLK_SET:B1 0x08(4)] ).
ADC conversion time = 14.8μs at 2.17MHz
18.5μs at 1.73MHz
For details, please refer to the “CCA (Clear Channel
Assessment) function”.
INT[18]
CCA completion
CCA execution start
INT[19]
TX Length error
detection
-
After set length value to [TX_PKT_LEN_H/L: B0 0x7A/7B]
register
INT[20]
TX FIFO access
error detection
-
(1) When the next packet data is written to the TX_FIFO before
transmitting previous packet data.
(2) FIFO overflow when writing
(3) FIFO underflow (no data) when transmitting
INT[21]
Reserved
-
(*1) Before issuing TX_ON, writing full-length TX data to the TX_FIFO.
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Interrupt notice
INT[22]
INT[23]
General purpose
timer 1 completion
General purpose
timer 2 completion
Reference point
Timing From reference point to interrupt generation
or interrupt generation timing
Timer start
General purpose timer 1 completion
General purpose timer clock cycle * Division setting
[GT_CLK_SET: B0 0x33] * general purpose timer interval
setting [GT1_TIMER:B0 0x34]
For details, please refer to the “General purpose timer”.
Timer start
General purpose timer 2 completion
General purpose timer clock cycle * Division setting
[GT_CLK_SET: B0 0x33] * general purpose timer interval
setting [GT2_TIMER:B0 0x35]
For details, please refer to the “General purpose timer”.
(3) Clearing interrupt condition
The following table shows the condition of clearing each intereupt. As a procedure to clear the interrup, it is
recommended that the interrupt to be cleared after masking the interrupt.
INT[0]
INT[1]
INT[2]
INT[3]
INT[4]
Interrupt notification
CLK stabilization completion
VCO calibration completion
PLL unlock or VCO CAL request
RF state transition completion
FIFO-Empty
INT[5]
FIFO-Full
INT[6]
INT[7]
INT[8]
INT[9]
INT[10]
INT[11]
INT[12]
INT[13]
INT[14]
INT[15]
INT[16/]
INT[17]
INT[18]
Wake-up timer completion
Clock calibration completion
RX completion
CRC error
Reserved
RX Length error
RX FIFO access error
SyncWord detection
Field checking
Sync error
TX completion
TX Data request accept completion
CCA completion
INT[19]
INT[20]
INT[21]
INT[22]
INT[23]
TX Length error
TX FIFO access error
Reserved
General purpose timer 1
General purpose timer 2
Conditions for clearing interrupts
After interrupt generated
After interrupt generated
After interrupt generated
After interrupt generated
After interrupt generated
(must clear before next FIFO-Empty trigger timing)
After interrupt generated
(must clear before next FIFO-Full trigger timing)
After interrupt generated
After interrupt generated
After interrupt generated
After interrupt generated
After interrupt generated
After interrupt generated
After interrupt generated
After interrupt generated
After interrupt generated
After interrupt generated
After interrupt generated
After interrupt generated
Note: Clearing interrupt erase CCA result as well.
After interrupt generated
After interrupt generated
After interrupt generated
After interrupt generated
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●Low speed clock shift detection function
ML7344 has low spleed frequency shift detection function to compensate inaccurate clock generated by RC
oscillator (external clock or internal RC oscillation circuits). By detecting frequency shift of the wake up timer,
host can set wake-up timer parameters which taking frequency shift into consideration. More accurate timer
operation is possible by adjusting wake-up timer interval setting ([WUT_INTERVAL_H/L: B0 0x2F/0x30]) or
continuous operation timer interval ([WU_DURATION: B0 0x31]).
Setting
Frequency shift detection clock frequency setting
Register
[CLK_CAL_SET: B0 0x70]
Clock calibration time
[CLK_CAL_TIME: B0 0x71]
Clock calibration result value
[CLK_CAL_H: B0 0x72], [CLK_CAL_L: B0 0x73]
This function is to measure low speed wake-up timer cycle by using accurate high speed internal clock and
count result will be stored in [CLK_CAL_H/L: B0 0x72/0x73] registers. Above setting and count numbers are
as follows:
High speed clock counter = {Wakeup timer clock cycle[SLEEP/WU_SET:B0 0x2D(2)] *
Clcok calibration time setting ([CLK_CAL_TIME:B0 0x71(5-0)]) /
{master clock cycle (26MHz) / clock division setting value ([CLK_CAL_SET:
B0 0x70(7-4)])}
Clock calibration time is as follows:
Clock calibration time[s] = Wakeup timer clock cycle * Clock calibration time setting
[Example]
Assuming no division in the internal high speed clock, calibration time is set as 10 cycle and set 1,000 to the
Wake-up interval timer value.
condition: Wakeup timer clock frequency = 44kHz
Detection clock division setting CLK_CAL_DIV[3:0][CLK_CAL_SET: B0 0x70(7-4)] = 0b0000
Clock calibration time setting [CLK_CAL_TIME] = 0x0A
Wake-up interval timert setting [WUT_INTERVAL_H/L:B0 0x2F,30] = 0x03E8
Theoretical high speed clock count = (1/44kHz) * 10 / (1/(26/1)MHz)
= 5909(0x1715)
If getting [CLK_CAL_H/L:B0 0x72,73] = 0x162E (5678)
Counter difference = 5678-5909 = -231
Frequency shift = 1/{1/44kHz + (-231) / 10 * 1 / 26MHz} – 44kHz = 1.79 kHz
Then finding wake-up timer clock frequency accuracy is +4.1% higher. And the compensation vale (C) is
calcurared as below:
C = Wake-up timer interval([WUT_INTERVAL_H/L:B0 0x2F,30]) * frequecy shift / 44kHz
= 1000 * 1.79kHz / 44kHz =41
Therefore, setting [WUT_INTERVAL_H/L:B0 0x2F,30] = 1000+41 =0x0411 to achive more accurate
inteval timinig.
NOTE:
If calibration time is too short or if high speed counter is divided into low speed clock, calibration may not be
accurate.
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●Antenna switching function
(1) Antenna switching function
By using [2DIV_CTRL: B0 0x48], [ANT_CTRL: B0 0x4C], [SPI/EXT_PA_CTRL: B0 0x53] registers,
TX-RX signal selection (TRX_SW), antenna switching signal (ANT_SW) can be controlled.
ML7344 can support both SPDT antena swith control. ANT_SW signal and TRX_SW signal output considion
for each antenna switch are explained below.
ANT_SW, TRX_SW output condition of each Idle, TX, RX state are as follow. (default setting) If
INV_TRX_SW([2DIV_CTRL: B0 0x48(2)])=0b1, polarity of TRX_SW is reversed.
TX/RX
condition
Idle
TX
RX
INV_TRX_SW=0b0
(default setting)
ANT_SW
TRX_SW
L
L
L
H
L
L
INV_TRX_SW=0b1
(polarity reverse)
ANT_SW
TRX_SW
L
H
L
L
L
H
Description
Idle state
TX state
RX state
In the above setting, If INV_ANT_SW([2DIV_CTRL: B0 0x48(3)])=0b1, ANT_CTRL1([2DIV_CTRL: B0
0x48(5)])=0b1 are set, polarity of ANT_SW pin is reversed.
TX/RX
state
Idle
TX
RX
INV_ANT_SW=0b0
ANT_CTRL1=any
(default setting)
ANT_SW
TRX_SW
L
L
L
H
L
L
INV_ANT_SW=0b1
ANT_CTRL1=0b1
ANT_SW
H
H
H
TRX_SW
L
H
L
Description
Idle state
TX state
RX state
(2) Antenna switch forced setting
By [ANT_CTRL: B0 0x4C] register, ANT_SW pin output conditions can be set to fix.
TX: By TX_ANT_EN([ANT_CTRL: B0 0x4C(0)])=0b1, TX_ANT([ANT_CTRL: B0 0x4C(1)]) condition
will be output.
RX: By RX_ANT_EN([ANT_CTRL: B0 0x4C(4)])=0b1, RX_ANT([ANT_CTRL: B0 0x4C(5)]) condition
will be output.
However, output is defined by [GPIIO*_CTRL: B0 0x4E - 0x51] register , [GPIIO*_CTRL:B0 0x4E - 0x51]
registers setting has higer priority.
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Antenna switching control signals can be also used as below.
Example 1) using SPDT switches
LSI
SPDT
LNA_P pin
PA_OUT pin
ANT_SW
(GPIOx)
output
pin
(Note) altenate external PA control signal exsits. (GPIOx or EXT_CLK pin)
(Note) external circuits around LNA_P pin, PA_OUTpin and antenna switch(SPDT) are omitted in this
example.
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■LSI adjustment items and adjustment method
●PA adjustment
ML7344E/J have output circuits for 1mW and 20mW (10mW as well) and ML7344C has output circuit for
20mW and 100mW. Output circuits can be selected by PA_MODE[1:0] ([PA_MODE: B0 0x67(5-4)]).
PA_MODE[1:0]
Output circuit
ML7344E/J
ML7344C
0b00
1mW
Not allowed
0b01
10mW
20mW
0b10
20mW
100mW
0b11
Not allowed
Output power can be adjusted by the following 3 registers.
Coarse adjustment 1 PA_REG[3:0] ([PA_MODE: B0 0x67(3-0)]) 16 resolutions
Coarse adjustment 2 PA_ ADJ[3:0] ([PA_ADJ: B0 0x69(3-0)] ) 16 resolutions
Fine adjustment
PA REG_FINE_ADJ[4:0] ([PA_REG_FINE_ADJ: B0 0x68(4-0)]) 32 resolutions
Coarse adjustment 1: PA regulator adjustment
Setting regulator voltage according to the desired output level.
However, please set PA regulator voltage to less than [VDD_PA(pin#22) – 0.3V].
PA_REG[3:0]
[PA_MODE:B0 0x67]
0b0000
0b0001
0b0010
0b0011
0b0100
0b0101
0b0110
0b0111
0b1000
0b1001
0b1010
0b1011
0b1100
0b1101
0b1110
0b1111
PA regulator
Voltage [V]
1.20
1.32
1.44
1.56
1.68
1.80
1.92
2.04
2.16
2.28
2.40
2.52
2.64
2.76
2.88
3.00
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Coarse adjustment 2: PA output gain adjustment
Controlling output power by adjusting PA gain. The typical PA output for PA_ADJ at 10mW is as follows.
10mW
[PA_ADJ:
B0 0x69(3-0)]
PA_REG[3:0]
=0
PA_REG[3:0]
=1
Power [dBm]
PA_REG[3:0] PA_REG[3:0]
=2
=3
0
3.8
5.0
5.9
1
4.8
6.2
7.1
2
5.5
6.9
8.0
8.6
9.1
9.5
3
6.1
7.5
8.7
9.4
10.0
10.4
4
6.5
8.0
9.1
9.8
10.5
11.0
5
6.9
8.5
9.6
10.4
11.0
11.5
PA_REG[3:0]
=4
PA_REG[3:0]
=5
6.3
6.8
7.0
7.6
8.2
8.4
6
7.2
8.8
9.9
10.8
11.4
12.0
7
7.5
9.1
10.2
11.0
11.8
12.3
8
7.6
9.2
10.3
11.2
11.9
12.4
9
7.8
9.4
10.6
11.4
12.1
12.7
10
8.0
9.6
10.8
11.6
12.5
12.9
11
8.2
9.7
10.9
11.8
12.6
13.1
12
8.3
9.8
11.0
11.9
12.7
13.2
13
8.4
9.9
11.2
12.0
12.8
13.4
14
8.4
10.1
11.3
12.1
13.0
13.5
15
8.6
10.1
11.4
12.3
13.0
13.6
Fine adjustment: PA regulator voltage fine adjustment
Fine tuning output power by adjusting PA regulator voltage. Adjustment step is less than 0.2dB. However,
please set PA regulator voltage to less than [VDD_PA(pin#22) – 0.3V].
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PA_REG_FINE_ADJ[4:0]
[PA_REG_FINE_ADJ:B0 0x68]
PA regulator
Voltage [V]
0b0_0000
89.5%
0b0_0001
90.1%
0b0_0010
90.7%
0b0_0011
91.3%
0b0_0100
91.9%
0b0_0101
92.5%
0b0_0110
93.2%
0b0_0111
93.8%
0b0_1000
94.4%
0b0_1001
95.1%
0b0_1010
95.8%
0b0_1011
96.5%
0b0_1100
97.1%
0b0_1101
97.8%
0b0_1110
98.6%
0b0_1111
99.3%
0b1_0000
100.0%
0b1_0001
100.7%
0b1_0010
101.5%
0b1_0011
102.3%
0b1_0100
103.0%
0b1_0101
103.8%
0b1_0110
104.6%
0b1_0111
105.4%
0b1_1000
106.3%
0b1_1001
107.1%
0b1_1010
107.9%
0b1_1011
108.8%
0b1_1100
109.7%
0b1_1101
110.6%
0b1_1110
111.5%
0b1_1111
112.4%
NOTE:
In order to achieve the most optimized result, Matching circuits may vary depending on the output mode.
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●PA output adjustment flow
START
Coarse adjustment 1: PA_MODE setting and PA
regulator adjustment [PA_MODE: B0 0x67]
Coarse adjustment 2: PA output gain adjustment
PA output gain adjustment [PA_ADJ: B0 0x69]
Fine adjustment: PA regulator fine adjustment
[PA_REG_FINE_ADJ: B0 0x68]
END
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●I/Q adjustment
Image rejection ratio can be adjusted by tuning IQ signal balance. The adjustment procedure is as follows:
1. From SG, image frequency signal is input to ANT pin (#24).
Input signal:
no modulation wave
Input frequency:
channel frequency - (2 * IF frequency)
IF frequency = 200kHz:
Input level:
-70dBm
2. Isuuing RX_ON by [RF_STATUS:B0 0x0b] register, by adjusting
z [LO_BIAS_IP: B2 0x2C]、From 0x50 To 0xD0 Step 0x04
z [LO_BIAS_IN: B2 0x2D]、From 0x60 To 0xA0 Step 0x10
z [LO_BIAS_QP: B2 0x2E]、From 0x50 To 0xD0 Step 0x04
z [LO_BIAS_QN: B2 0x2F]、From 0x60 To 0xA0 Step 0x10
, finding setting value so that ED value [ED_RSLT: B0 0x3A] is minimum.
3. It is possible to choice the adjusted value and break the above search flow at halfway.
To obtain minimum 30dB blocking characteristic for image frequency, ML7344 requires more than
40dB attenuation for image frequency (IMRR: IMage Rejection Ratio). The 10dB differ is caused by
co-channel blocking characteristic of ML7344. Because input -70dBm signal during IQ adjustment,
IMRR is more than 40dB if ML7344 indicates less than -110dBm by ED value. It is possible to break
adjustment flow at halfway by using the ED value as “Target value” in the IQ adjustment flow.
●IQ adjustment flow
For IQ adjustment, using Bank2 (closed Bank) registers. Any other register access is inhibited.
START
Power on
1
Initialize setting
* Please refer to
“Initialization table”.
IQ Bias initializing setting
[LO_BIAS_IN: B2 0x2D] = 0x80
[LO_BIAS_QN:B2 0x2F] = 0x80
SG output setting
modulation: no modulation
level : -70dBm
frequency: CH frequency- 2 * IF
frequency
IQ adjustment by following register
[LO_BIAS_IP: B2 0x2C]
[LO_BIAS_QP:B2 0x2E]
RX_ON setting
[RF_STATUS: B0 0x0B]
Read ED value
[ED_RSLT: B0 0x3A]
Change setting value of
[LO_BIAS_IN: B2 0x2C]
[LO_BIAS_QN:B2 0x2E]
1
Read ED value < Target value ?
No
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Yes
END
●VCO adjustment
In order to compensate VCO operation margin, optimized capacitance compensation value should be set in
each TX/RX operation and frequency. This capacitance compensation value can be acquired by VCO
calibration.
By performing VCO calibration when power-up or reset, acquired capacitance compensation values for upper
limit and lower limit of operation frequency range (for both TX/RX), based on this value optimised capacitance
value is applied during TX/RX operation.
●VCO adjustment flow
The following flow is the procedure for acquiring capacitance compensation value when power-up or reset.
START
Initialize
setting
Setting low limit frequency
[VCO_CAL_MIN_I: B1 0x4D]
[VCO_CAL_MIN_FH: B1 0x4E]
[VCO_CAL_MIN_FM: B1 0x4F]
[VCO_CAL_MIN_FL: B1 0x50]
Setting operation frequency range
[VCO_CAL_MAX_N: B1 0x51]
VCO calibration completion INT. clear
INT[1] ([INT_SOURCE_GRP1: B0 0x0D])
Start
calibration
Calibration operation
Completion wait
Set VCO_CAL_START = 0b1
[VCO_CAL_START: B0 0x6F(0)]
VCO calibration completion INT?
No
INT[1] [INT_SOURCE_GRP1: B0 0x0D]
Yes
END
NOTE:1) VCO calibration should be performed only during IDLE state.
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VCO calibration is necessary every 2.6ms to 8.8ms.
After completion, capacitance compensation values are stored in the following registers.
Capacitance compensation value at TX low limit frequency: [TXVCAL_MIN: B1 0x52]
Capacitance compensation value at TX upper limit frequency: [TXVCAL_MAX: B1 0x53]
Capacitance compensation value at RX low limit frequency: [RXVCAL_MIN: B1 0x54]
Capacitance compensation value at RX upper limit frequency: [RXVCAL_MAX: B1 0x55]
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In actual operation, based on the 2 compensation values for each TX/RX, the most optimized capacitance value
for the frequency is calculated and applied. The calculated value is stored in [VCO_CAL: B0 0x6E].
By evaluation stage, if below values are stored in the MCU memory and uses these values upon reset or
power-up, calibration operation can be omitted.
Registers to be saved in the MCU memory.
[VCO_CAL_MIN_I: B1 0x4D]
[VCO_CAL_MIN_FH: B1 0x4E]
[VCO_CAL_MIN_FM: B1 0x4F]
[VCO_CAL_MIN_FL: B1 0x50]
[VCO_CAL_MAX_N: B1 0x51]
[TXVCAL_MIN: B1 0x52]
[TXVCAL_MAX: B1 0x53]
[RXVCAL_MIN: B1 0x54]
[RXVCAL_MAX: B1 0x55]
After issuing VCO calibration, VCO tuning voltage may be out of control range by the temperature difference
between operating timing and VCO calibration timing. If activating RF when VCO tuninng voltage is out of
control range, the margine of VCO operation will be lost and it may cause the PLL unlock. When detecting VCO
tuning voltage is out of control range, VCO calibration should be re-issued or set VCO caluibration value which
has operating margine at that temperature.
The ML7344 has the function of comparing the VCO tunign voltage with upper and lower limit voltages and
determining it is in the control range or not and indiacting the result. After detecting VCO tuning voltage is out
of contol range, it can be notified by INT[2] (group1: VCO CAL request interrupt).
[Relative controlo bit]
The comparison result with maximum threshold: VTUNE_COMP_H ([VCO_VTRSLT:B0 0x40(1)])
The comparison result with minimum threshold: VTUNE_COMP_L ([VCO_VTRSLT:B0 0x40(0)])
VCO CAL request interrupt enable setting: VTUNE_INT_ENB ([VCO_VTRSLT:B0 0x40(2)])
State control after PLL unlock detection: PLL_LD_EN ([PLL_LOCK_DETECT:B1 0x0B(7)]
[VCO voltage condition]
VTUNE_COMP_L
[VCO_VTRSLT:B0 0x40(0)]
0b0
VTUNE_COMP_H
[VCO_VTRSLT:B0 0x40(1)]
0b0
0b0
0b1
0b1
0b0
0b1
0b1
Condition
Ordinary
Out of control range
(beyond upper level)
Out of control range
(below lower level)
Extra ordinary
NOTE:
1. For low limit frequency, please use frequency at least 400kHz lower than operation frequency
2. For upper limit frequency should be selected so that operation frequency is in the frequency range.
3. In case of like a channel change, if the setting frequency is outside of calibration frequency range,
calibration process has to be performed again with proper frequency.
4. INT[2] (group1) will generate by detecting PLL unlock or VCO CAL request (when VTUNE_INT_ENB
([VCO_VTRSLT:B0 0x40(2)])=0b1). The following shows the ML7344 opereation related with LSI
state and PLL_LD_EN([PLL_LOCK_DETECT:B1 0x0B(7)]) setting, after interrupt generation.
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[In case of PLL unlock interrupt]
LSI
state
check timig of
PLL unlock
detection
TX
RX
PA_ON =”H”
RX enable =”H”
PLL lock detection control setting and ML7344 operation after interrupt generation
PLL_LD_EN=0b1
[PLL_LOCK_DETECT:B1 0x0B(7)]
interrupt occurs and TX stops forcibly
interrupt occurs and RX is continued
PLL_LD_EN=0b0
[PLL_LOCK_DETECT:B1 0x0B(7)]
interrupt occurs and TX is continued
interrupt occurs and RX is continued
[In case of VCO CAL request interrupt]
LSI
state
TX
RX
check timig of
PLL unlock
detection
Rising edge of
PA_ON signal
Rising edhe of
RX enable signal
PLL lock detection control setting and ML7344 operation after interrupt generation
PLL_LD_EN=0b1
[PLL_LOCK_DETECT:B1 0x0B(7)]
PLL_LD_EN=0b0
[PLL_LOCK_DETECT:B1 0x0B(7)]
interrupt occurs and TX stops forcibly
interrupt occurs and TX is continued
interrupt occurs and RX is continued
interrupt occurs and RX is continued
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●VCO low limit frequency setting
VCO low limit frequency can be set as described in the “channel frequency setting”. I is set to
[VCO_CAL_MIN_I:B1 0x4D] register, F is set to [VCO_CAL_MIN_FH:B1 0x4E], [VCO_CAL_MIN_FM:B1
0x4F], [VCO_CAL_MIN_FL:B1 0x50] in MSB – LSB order.
example) If operation low limit frequency is 426.6MHz, setting value should be lower than 400kHz. Then in
following example, low limit frequency is set to 426.MHz, master clock frequency is 26MHz.
I = 426MHz/26MHz (Integer part) = 16(0x10)
F =(426MHz/26MHz-16) * 220 (Integer part) = 403298 (0x062762)
Setting values for each register is as follows:
[VCO_CAL_MIN_I]
[VCO_CAL_MIN_FH]
[VCO_CAL_MIN_FM]
[VCO_CAL_MIN_FL]
= 0x10
= 0x06
= 0x27
= 0x62
●VCO upper limit frequency setting
VCO upper limit frequency is calculated as following formula, based on low limit frequency values and
[VCO_CAL_MAX_N:B1 0x51] register.
VCO calibration upper limit frequency =
VCO calibration low limit frequency (B1 0x4D-0x50) + ΔF(B1 0x51)
ΔF is defined in the table below
VCO_CAL_MAX_N[3:0]
0b0000
0b0001
0b0010
0b0011
0b0100
0b0101
0b0110
0b0111
0b1000
0b1001
Other than above
ΔF[MHz]
0
0.8125
1.625
3.25
6.5
13
26
52
82.875
104
prohibited
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●Energy detection value (ED value) adjustment
ED value is calculated by RSSI signal (analog signal) from RF part, By performing the following adjustment, it
is possible to correct the variation in LSIs.
[ED value]
ED value is calculated as following formula,
RSSI value = 1.35 * (input level[dBm] – variations[dBm] – other losses[dBm]) + offset
ED value (CCA threshold) = (RSSI value + RSSI_ADJ) * RSSI_MAG_ADJ
Item
Value
High Sensitivity Mode
High Linearity Mode
offset
164.5
156
Variation (individual, temp.)[dBm]
10
7
Other loss[dBm]
Antenna, matching circuits loss
RSSI_ADJ
The setting of [RSSI_VAL:B1 0x14]
RSSI_MAG_ADJ
The setting of [RSSI_ADJ: B0 0x66]
[ED value asjustment]
At first, inputting the low-level signal to ANT terminal. Adjusting the RSSI_ADJ value so that ED_VALUE
[ED_RSLT:B0 0x3A(7-0)] indicates the target value of the low-level signal.. Next inputting the high-level signal
and adjusting the RSSI_MAG_ADJ value so that ED_VALUE indicates the target value of the high-level signal.
Repeat several times in accordance with the required accuracy.
ED value
RSSI_MAG_ADJ
(B1 0x13)
RSSI_ADJ
(B0 0x66)
low-
high
RF input level
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●Oscillation circuit adjustment
In case of using a crystal oscillator (ML7344xC), crystal oscillator frequency deviation can be tuned by
adjusting load capacitance of XIN pin (pin#5) and XOUT pin (pin #6). Load capacitance can be adjusted by
[OSC_ADJ1: B0 0x62] and [OSC_ADJ2: B0 0x63].
Adjustable capacitance is as follows:
[OSC_ADJ1] Coarse adjustment of load capacitance: 0.7pF/step (setting range: 0x00 to 0x0F)
Oscillating frequency
[OSC_ADJ2] Fine adjustment of load capacitance: 0.02pF/step (setting range: 0x00 to 0x77)
OSC_ADJ
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■Resister setting
●Initialization table
ML7344 needs initilaization. For the value to each register, please refer to the “ML7344 Initilaization Table”
document.
●RX mode setting
ML7344 has two RX modes. One is “High sensitivity mode” that is tuned for minimum RX sensitivity. It
achieves -118dBm under condition of BER<0.1%, 4.8kbps and Fdev=3kHz. The other is “High linearity mode”
that improves linearity about 6dB, so characteristics of blocking and power detection rang are grown instead of
sensitivity degradation about 3dB. For swtiching RX mode, set the register [LNA_GAIN1:B2 0x28] as below.
RX mode
High sensitivity mode
High linearity mode
[LNA_GAIN1:B2 0x28]
0xF7
0x07
●BER measurement setting
The following registers setting are necessary for RX side when measuring BER.
[DIO_SET: B0 0x0C] = 0x40
[MON_CTRL: B0 0x4D] = 0x80
[GPIO0_CTRL: B0 0x4F] to [GPIO3_CTRL: B0 0x52] for setting DCLK/DIO output pins.
[GAIN_HTOM: B1 0x0E] = 0x1E
When termiate BER measurement and reurn from RX state, Force TRX_OFF should be issued by
SET_TRX[3:0] ([RF_STATUS:B0 0x0b(3-0]) =0b0011.
●Wireless M-bus setting
The following parameter tables are example for programing each Wireless M-Bus mode (N/F).
●Mode N
(Channel frequency: 169.4125MHz, Modulation: GFSK, Data Rate: 4800bps)
Parameter
TX frequency
RX frequency
Channel space
PLL frequency division
Register
Name
TXFREQ_I
TXFREQ_FH
TXFREQ_FM
TXFREQ_FL
RXFREQ_I
RXFREQ_FH
RXFREQ_FM
RXFREQ_FL
CH_SPACE_H
CH_SPACE_L
PLL_DIV_SET
Address
B1 0x1B
B1 0x1C
B1 0x1D
B1 0x1E
B1 0x1F
B1 0x20
B1 0x21
B1 0x22
B1 0x23
B1 0x24
B1 0x1A
Setting
Value
0x0D
0x00
0x81
0xF8
0x0D
0x00
0x81
0xF8
0x07
0xE0
0x10
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Data rate
TX\RX data configulation
Frequency deviation (GFSK)
DRATE_SET
DATA_SET1
DATA_SET2
GFSK_DEV_H
GFSK_DEV_L
B0 0x06
B0 0x07
B0 0x08
B1 0x30
B1 0x31
0x22
0x10
0x00
0x00
0x60
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Mode N setting (continued)
Parameter
Frequency deviation (FSK)
Frequency deviation time
Preamble length
SyncWord length
SyncWord pattern 1
SyncWord pattern 2
Postamble setting
Demodulator DC level
Demodulator adjustment 1
Demodulator adjustment 2
Demodulator adjustment 3
Demodulator adjustment 4
Demodulator adjustment 5
Demodulator adjustment 6
Demodulator adjustment 7
Demodulator adjustment 8
Demodulator adjustment 9
Register
Name
FSK_DEV0_H/GFIL0
FSK_DEV0_L/GFIL1
FSK_DEV1_H/GFIL2
FSK_DEV1_L/GFIL3
FSK_DEV2_H/GFIL4
FSK_DEV2_L/GFIL5
FSK_DEV3_H/GFIL6
FSK_DEV3_L
FSK_DEV4_H
FSK_DEV4_L
FSK_TIM_ADJ0
FSK_TIM_ADJ1
FSK_TIM_ADJ2
FSK_TIM_ADJ3
FSK_TIM_ADJ4
TXPR_LEN_H
TXPR_LEN_L
SYNC_WORD_LEN
SYNC_WORD1_SET0
SYNC_WORD1_SET1
SYNC_WORD1_SET2
SYNC_WORD1_SET3
SYNC_WORD2_SET0
SYNC_WORD2_SET1
SYNC_WORD2_SET2
SYNC_WORD2_SET3
POSTAMBLE_SET
IFF_ADJ_H
IFF_ADJ_L
DEMOD_SET1
DEMOD_SET2
DEMOD_SET3
DEMOD_SET4
DEMOD_SET5
DEMOD_SET6
DEMOD_SET7
DEMOD_SET8
DEMOD_SET9
Address
B1 0x32
B1 0x33
B1 0x34
B1 0x35
B1 0x36
B1 0x37
B1 0x38
B1 0x39
B1 0x3A
B1 0x3B
B1 0x3C
B1 0x3D
B1 0x3E
B1 0x3F
B1 0x40
B0 0x42
B0 0x43
B1 0x25
B1 0x27
B1 0x28
B1 0x29
B1 0x2A
B1 0x2B
B1 0x2C
B1 0x2D
B1 0x2E
B0 0x44
B0 0x5E
B0 0x5F
B1 0x57
B1 0x58
B1 0x59
B1 0x5A
B1 0x5B
B1 0x5C
B1 0x5D
B1 0x5E
B1 0x5F
Setting
Value
0x49
0xA7
0x0F
0x14
0x19
0x1D
0x1E
0x00
0x08
0x10
0x00
0x00
0xF6
0x8D
0x00
0x00
0x00
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
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●Mode F
Parameter
TX frequency
RX frequency
Channel space
PLL frequency division
Data rate
TX\RX data configulation
Frequency deviation (GFSK)
Frequency deviation (FSK)
Frequency deviation time
Preamble length
SyncWord length
SyncWord pattern 1
SyncWord pattern 2
Postamble setting
Register
Name
TXFREQ_I
TXFREQ_FH
TXFREQ_FM
TXFREQ_FL
RXFREQ_I
RXFREQ_FH
RXFREQ_FM
RXFREQ_FL
CH_SPACE_H
CH_SPACE_L
PLL_DIV_SET
DRATE_SET
DATA_SET1
DATA_SET2
GFSK_DEV_H
GFSK_DEV_L
FSK_DEV0_H/GFIL0
FSK_DEV0_L/GFIL1
FSK_DEV1_H/GFIL2
FSK_DEV1_L/GFIL3
FSK_DEV2_H/GFIL4
FSK_DEV2_L/GFIL5
FSK_DEV3_H/GFIL6
FSK_DEV3_L
FSK_DEV4_H
FSK_DEV4_L
FSK_TIM_ADJ0
FSK_TIM_ADJ1
FSK_TIM_ADJ2
FSK_TIM_ADJ3
FSK_TIM_ADJ4
TXPR_LEN_H
TXPR_LEN_L
SYNC_WORD_LEN
SYNC_WORD1_SET0
SYNC_WORD1_SET1
SYNC_WORD1_SET2
SYNC_WORD1_SET3
SYNC_WORD2_SET0
SYNC_WORD2_SET1
SYNC_WORD2_SET2
SYNC_WORD2_SET3
POSTAMBLE_SET
Address
B1 0x1B
B1 0x1C
B1 0x1D
B1 0x1E
B1 0x1F
B1 0x20
B1 0x21
B1 0x22
B1 0x23
B1 0x24
B1 0x1A
B0 0x06
B0 0x07
B0 0x08
B1 0x30
B1 0x31
B1 0x32
B1 0x33
B1 0x34
B1 0x35
B1 0x36
B1 0x37
B1 0x38
B1 0x39
B1 0x3A
B1 0x3B
B1 0x3C
B1 0x3D
B1 0x3E
B1 0x3F
B1 0x40
B0 0x42
B0 0x43
B1 0x25
B1 0x27
B1 0x28
B1 0x29
B1 0x2A
B1 0x2B
B1 0x2C
B1 0x2D
B1 0x2E
B0 0x44
Setting
Value
0x10
0x0A
0xF7
0x55
0x10
0x0A
0xF7
0x55
0x00
0x11
0x00
0x00
0x00
0x44
0x00
0x82
0x00
0xB3
0x00
0xD2
0x00
0xD0
0x7F
0x7F
0x7F
0x7F
0x7f
0x00
0x27
0x10
0x00
0x00
0xF6
0x8D
0x00
0x00
0xF6
0x72
0x00
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Mode F setting (continued)
Parameter
Demodulator DC level
Demodulator adjustment 1
Demodulator adjustment 2
Demodulator adjustment 3
Demodulator adjustment 4
Demodulator adjustment 5
Demodulator adjustment 6
Demodulator adjustment 7
Demodulator adjustment 8
Demodulator adjustment 9
Register
Name
IFF_ADJ_H
IFF_ADJ_L
DEMOD_SET1
DEMOD_SET2
DEMOD_SET3
DEMOD_SET4
DEMOD_SET5
DEMOD_SET6
DEMOD_SET7
DEMOD_SET8
DEMOD_SET9
Address
B0 0x5E
B0 0x5F
B1 0x57
B1 0x58
B1 0x59
B1 0x5A
B1 0x5B
B1 0x5C
B1 0x5D
B1 0x5E
B1 0x5F
Setting
Value
0x00
0x00
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
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■Flowcharts
Category
Turn on
Sequence
TX/RX
common
Sequence
TX Sequence
RX Sequence
Condition 1
Data Rate
Change
Process
Name of flow
-
-
(1) Initialization flow
-
-
(1) RF state transition wait
DIO mode
FIFO mode
Under 64 byte
65 byte or more
(FAST_TX)
Under 64 byte
65 byte or mode
Normal mode
Continuous execution
mode
IDLE detection mode
TX (1) DIO mode
TX (2) FIFO mode
TX (3) FIFO mode
TX (4) automatic TX
RX (1) DIO mode
RX (2) FIFO mode
RX (3) FIFO mode
RX (4) ACK transmission
RX (5) Field checking
RX (6) CCA normal mode
RX (6) CCA continuous execution
mode
RX (6) CCA IDLE detection mode
Automatic TX
DIO mode
FIFO mode
ACK transmission
Field check
CCA
SLEEP
Sequence
Error Process
Condition 2
High speed carrier
checking
ED-SCAN
SLEEP
Wake-up timer
Sync error
TX FIFO access error
RX FIFO access error
PLL unlock
-
RX (7) high speed carrier checking
-
RX (8) ED-SCAN
(1) SLEEP
(2) Wake-up timer
(1) Sync error
(2) TX FIFO access error
(3) RX FIFO access error
(4) PLL unlock
-
-
(1) Change Data Rate
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●Turn on Sequence
(1) Initialization flow
In initialization status, interrupt process, registers setting, VCO calibration are necessary.
(1) Interrupt process
Upon reset, all interrupt notification settings ([INT_EN_GRP1-3: B0 0x10-0x12]) are disabled.
After hard reset is released, INT[0] (group 1: Clock stabilization completion interrupt) will be detected.
INT[0] should be enabled by [INT_EN_GRP1:B0 0x10] register.
(2) Registers setting
After hard reset is released, all registers in BANK0 and BANK1 except FIFO access registers
([WR_TX_FIFO: B0 0x7C] and [RD_FIFO: B0 0x7F]), are accessible before INT[0] notification.
(3) VCO calibration
VCO calibration is executed after setting upper and low limit of the operation frequency.
For details, please refer to the “VCO adjustment”.
START
INT_EN setting
[INT_EN_GRP1-3: B0 0x10-0x12]
No
Clock stabilized completion int. ?
INT[0] [INT_SOURCE_GRP1: B0 0x0D]
(1)Interrupt process
Yes
INT[0] clear
[INT_SOURCE_GRP1 B0 0x0D]
Register setting
VCO calibration execution
(2)Register setting
(3)VCO calibration
*For details, please refer to
the ”VCO adjustment”
END
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●TX/RX Common Sequence
(1) RF state transition wait
If below setting for RF state change is selected, please confirm the completion of RF state transtion by INT[3]
(group1: RF state transtion completion interrupt).
○RF state transition by [RF_STATUS: B0 0x0B] register
○RF state transition by [RF_STATUS_CTRL: B0 0x0A] resgister
●FAST_TX mode setting
●automatic TX setting
●RF state setting after TX completion
●RF state setting after RX completion
○RF state modification by wake-up timer setting
i) TRX_OFF flow
RF state change by [RF_STATUS: B0 0x0B]
SET_TRX[3:0]=0b1000
START
TRX_OFF issue
[RF_STATUS: B0 0x0B]
RF state transition completion
Interrupt confirmation
INT[3]([INT_SOURCE_GRP1: B0 0x0D]
END
RF state change by [RF_STATUS_CTRL: B0 0x0A]
TXDONE_MODE[1:0=0b00
RXDONE_MODE[1:0]=0b00
START
No
TX completion interrupt?
INT[16] [INT_SOURCE_GRP3: B0 0x0F]
Yes
START
No
TX completion interrupt?
INT[8] [INT_SOURCE_GRP2: B0 0x0E]
Yes
RF state transition completion
Interrupt confirmation
RF state transition completion
Interrupt confirmation
INT[3] [INT_SOURCE_GRP1: B0 0x0D]
INT[3] [INT_SOURCE_GRP1: B0 0x0D]
END
END
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ii) TX_ON flow
RF state transition change by [RF_STATUS: B0 0x0B]
SET_TRX[3:0]=0b1001
START
TX_ON issue
[RF_STATUS: B0 0x0B]
RF state transition completion
Interrupt confirmation
INT[3] [INT_SOURCE_GRP1: B0 0x0D]
END
RF state transition by [RF_STATUS_CTRL]register(B0 0x0A)
RXDONE_MODE[1:0]=0b10
No
FAST_TX_EN=0b1 and
AUTO_TX_EN=0b1
START
START
RX completion int.?
INT[8] [INT_SOURCE_GRP2: B0 0x0E]
FIFO write
Yes
RF state transition completion
Interrupt confirmation
RF state transition completion
Interrupt confirmation
INT[3] [INT_SOURCE_GRP1: B0 0x0D]
INT[3] [INT_SOURCE_GRP1: B0 0x0D]
END
END
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iii) RX_ON flow
RF state change by [RF_STATUS: B0 0x0B]
RF state change by [RF_STATUS_CTRL: B0 0x0A]
SET_TRX[3:0]=0b0110
TXDONE_MODE[1:0]=0b10
START
RX_ON issue
[RF_STATUS: B0x0B]
RF state transition completion
Interrupt confirmation
INT[3] [INT_SOURCE_GRP1: B0 0x0D]
START
No
TX completion INT ?
INT[16] ([[INT_SOURCE_GRP2: B0
0x0F]]
Yes
RF state transition completion
Interrupt confirmation
INT[3] [INT_SOURCE_GRP1: B0 0x0D]
END
END
iv) Wake-up flow
The following flow doses not apply to the case when waiting for INT[14] (group 1: Field checking
interrupt) after wake-up.
START
SLEEP setting
RF state transition completion
Interrupt confirmation
INT[3] [INT_SOURCE_GRP1: B0 0x0D]
END
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●TX Sequence
(1) DIO mode
DIO(TX) mode can be selected by setting TXDIO_CTRL[1:0]([DIO_SET: B0 0x0C(5-4)])=0b01 or 0b10. In
DIO mode, when TX_ON is issued, data input on the pin related DIO will be transimitted to the air. After TX
completion, TRX_OFF should be issued.
START
*1 DIO/DCLK pins are defined as follows:
DIO pins setting *1
TXDIO_CTRL setting=0b10
[GPIO0_CTRL: B0 0x4E]
[GPIO1_CTRL: B0 0x4F]
[GPIO2_CTRL: B0 0x50]
[GPIO3_CTRL: B0 0x51]
[EXT_CLK_CTRL: B0 0x52]
[SPI/EXT_PA_CTRL: B0 0x53]
[DIO_SET: B0 0x0C(5-4)]
Preamble/SyncWord setting *2
*2: preamble/SyncWord is transmitted based on the
following registers.
Preamble
SyncWord
[DATA_SET1: B0 0x07]
[TXPR_LEN_H/L: B0 0x42-43]
[SYNCWORD1_SET0-3: B1 0x27-2A]
[SYNCWORD2_SET0-3: B1 0x2B-2E]
[SYNC_WORD_LEN: B1 0x25]
[DATA_SET2: B0 0x08]
TX_ON issue
[RF_STATUS: B0 0x0B]
DCLK output wait *3
No
*3: Timing up to DCLK output varies depending on
TX preamble, SFC, data rate.
TX data input *4
(DIO pins)
*4: TX data must be input at falling edge of DCLK.
TX completed?*5
*5: Please refer to RF state transition wait flow.
Yes
TRX_OFF issue
[RF_STATUS: B0 0x0B]
Yes
Next packet to be transmitted?
No
END
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(2) FIFO mode (less than 64 byte)
FIFO mode (packet mode) can be selected by setting TXDIO_CTRL[1:0]([DIO_SET: B0 0x0C(5-4)])=0b00.
In FIFO mode, data is written to the TX_FIFO by [WR_TX_FIFO:B0 0x7C] register. After writing full data of
a packet, issuing TX_ON by [RF_STATUS:B0 0x0B] resister. Following preamble/SyncWord, TX_FIFO data
is transmitted to the air. Upon TX completion interrupt (INT[16] group 3) occurs, interrupt must be cleared. If
the next TX packet is sent, the next TX packet data is written to the TX_FIFO. If RX is expected after TX,
RX_ON should be issued by [RF_STATUS: B0 0x0B] resister. TX can be terminated by issuing TRX_OFF by
[RF_STATUS:B0 0x0B] register.
START
If the TX data length is shorter than the
FAST_TX trigger level, TX will start by
writing all data to FIFO.
TX_FIFO trigger level setting
[TXFIFO_THRH: B0 0x17]=0x00
[TXFIFO_THRL: B0 0x18]=0x00
Write TX data
[WR_TX_FIFO:B0 0x7C]
From CCA flowchart
TX data request accept
Completion (INT[17])?
No
[INT_SOURCE_GRP3: B0 0x0F(1)]
No
Yes
INT[17] clear
To CCA flowchart
i) If random back-off period specified in
the IEEE is used, go to CCA normal
mode.
ii) If IDLE is detected in minimum period,
go to CCA IDLE detection mode.
Yes
[INT SOURCE GRP3: B0 0x0F]
Yes
CCA result=BUSY?
Yes
CCA continue?
No
CCA execution ?
No
TX FIFO clear
※please refer to RF state
transition wait flow.
TX_ON issue
[RF STATUS: B0 0x0B]
[STATE CLR: B0 0x16]
TRX_OFF issue
[RF_STATUS: B0 0x0B]
No
TX completion (INT[16])?
To RF state transition wait
flow
[INT_SOURCE_GRP3: B0 0x0F(0)]
Yes
INT[16] clear
Write TX data
[WR_TX_FIFO:B0 0x7C]
[INT_SOURCE_GRP3: B0 0x0F])
Set RX_ON after TX completion?
[RF_STATUS_CTRL:B0 0x0A]
Yes
No
Set TRX_OFF/SLEEP after TX?
[RF_STATUS_CTRL:B0 0x0A]
Yes
To RF state transition wait
flow
No
Yes
Next packet TX ?
No
RX?
Yes
RX_ON issue
[RF_STATUS: B0 0x0B]
No
TRX_OFF issue
[RF_STATUS: B0 0x0B]
To RF state transition wait flow
To RF state transition wait
and RX flow
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(3) FIFO mode (65 byte or more)
The Host must write TX data to the TX_FIFO while checking INT[5] (group1: FIFO-Full interrupt) and
INT[4] (group1: FIFO-Empty interrupt) in order to avoid FIFO-Overrun or FIFO-Underrun. Other operations
are identical to the FIFO mode (less than 64byte). Enabling FAST_TX mode by FAST_TX_EN
([RF_STATUS_CTRL: B0 0x0A(5)] =0b1, TX will start when data amount written to the FIFO exceeds the
bytes+1 in the [TXFIFO_THRL: B0 0x18].
START
FAST_TX mode setting
[RF_STATUS_CTRL: B0 0x0A]
TX FIFO-Full level setting [TXFIFO_THRH: B0 0x17]
TX FIFO-Empty level setting [TXFIFO_THRL: B0 0x18]
●If data written to FIFO exceed THFIFO_THRL[5:0]
([TXFIFO_THRL:B0 0x18(5-0)] +1, TX will start.
●Please refer to RF state transition wait flow.
Write TX data
[WR_TX_FIFO:B0 0x7C]
FIFO-Empty (INT[4])?
[INT_SOURCE_GRP1: B0 0x0D(4)]
Yes
INT[4] clear
[INT_SOURCE_GRP: B0 0x0D]
No
TX FIFO-Empty level
Disable setting
[TX_FIFO_THRL: B0 0x18]
Write TX data
[WR_TX_FIFO:B0 0x7C]
TX FIFO-Empty level
Enable setting
[TX_FIFO_THRL: B0 0x18]
TX data request accept
completion (INT[17])?
No
[INT_SOURCE_GRP3: B0 0x0F(1)]
.Total data amount should be identical
to the Length. Length data is (Length –
CRC size). If TX data written exceed
the Length, after TX completion
interrupt, TX FIFO must be cleared by
issuing TRX_OFF.
Yes
No
TX completion (INT[16])?
[INT_SOURCE_GRP3: B0 0x0F(0)]
INT[16] and INT[17] clear
Write TX data
[WR_TX_FIFO:B0 0x7C]
[INT_SOURCE_GRP3:
Yes B0 0x0F])
Set RX_ON after TX completion?
[RF_STATUS_CTRL:B0 0x0A]
Yes
No
Set TRX_OFF/SLEEP after TX?
[RF_STATUS_CTRL:B0 0x0A]
Yes
To RF state transition wait
flow
No
Yes
Next packet TX ?
No
RX?
Yes
RX_ON issue
[RF_STATUS: B0 0x0B]
No
TRX_OFF issue
[RF_STATUS: B0 0x0B]
To RF state transition wait flow
To RF state transition wait
and RX flow
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(4) Automatic TX (less than 64 byte)
If AUTO_TX_EN([RF_STATUS_CTRL: B0 0x0A(4)]=0b1, TX starts automatically when FIFO is filled
with data equivalent to the Langth. Afer TX completion, RFstate transition setting is by TXDONE_MODE
([RF_STATUS_CTRL: B0 0x0A(1-0)]).
START
Automatic TX setting
[RF_STATUS_CTRL:B0 0x0A]
●When data equivalent to Length is written to FIFO,
TX starts automatically.
●Please refer to RF state transition wait flow.
Write TX data
[WR_TX_FIFO:B0 0x7C]
TX data request accept
completion (INT[17])?
No
[INT_SOURCE_GRP3: B0 0x0F(1)]
Yes
No
TX completion (INT[16])?
[INT_SOURCE_GRP3: B0 0x0F(0)]
Yes
INT[16] and [INT17] clear
Write TX data
[WR_TX_FIFO:B0 0x7C]
[INT_SOURCE_GRP3: B0 0x0F])
Set RXON after TX completion?
[RF_STATUS_CTRL:B0 0x0A]
Yes
No
Set TRXOFF/SLEEP after TX?
[RF_STATUS_CTRL:B0 0x0A]
Yes
To RF state transition wait
flow
No
Yes
Next packet TX ?
No
RX?
Yes
RX_ON issue
[RF_STATUS: B0 0x0B]
No
TRX_OFF issue
[RF_STATUS: B0 0x0B]
To RF state transition wait flow
To RF state transition wait
and RX flow
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●RX Sequence
(1) DIO mode
DIO mode can be selected by setting RXDIO_CTRL[1:0]([DIO_SET: B0 0x0C(7-6)])=0b10/0b11. Upon
setting DIO mode and issuing RX_ON by [RF_STATUS:B0 0x0B] register, SyncWord detection will be
started.
○DIO output mode 1 operation
When RXDIO_CTRL[1:0]=0b10 setting, after SyncWord pattern detection, RX data will be strored into the
RX_FIFO. RX data stored in the RX_FIFO is output through DIO pins, if setting DIO_START ([DIO_SET: B0
0x0C(0)])=0b1. After RX completion, if more data is to be received, by setting DIO_RX_COMPLETE
([DIO_SET: B0 0x0C(2)]) =0b1 (DIO RX Completion), the next packet will be ready to receive. In case of
TRX_OFF, issuing TRX_OFF by [RF_STATUS:B0 0x0B] register.
START
*1 DIO/DCLK pins are defined as follows:
DIO pins setting *1
RXDIO_CTRL setting=0b10
[DIO_SET: B0 0x0C(7-6)]
Preamble/SyncWord
Error tolerance setting *2
[GPIO0_CTRL: B0 0x4E]
[GPIO1_CTRL: B0 0x4F]
[GPIO2_CTRL: B0 0x50]
[GPIO3_CTRL: B0 0x51]
[EXT_CLK_CTRL: B0 0x52]
[SPI/EXT_PA_CTRL: B0 0x53]
*2: Preamble, SyncWord and Error tolerance are set
by following registers.
Preamble
SyncWord
RX_ON issue *3
[RF_STATUS: B0 0x0B]
[DATA_SET1: B0 0x07]
[SYNC_CONDITION1-3: B0 0x45-47]
[SYNCWORD1_SET0-3: B1 0x27-2A]
[SYNCWORD2_SET0-3: B1 0x2B-2E]
[SYNC_WORD_LEN: B1 0x25]
[DATA_SET2: B0 0x08]
*3: Please refer to RF state transition wait flow
No
SyncWord Detection (INT[13])?
[INT_SOURCE_GRP3: B0 0x0F(5)]
Yes
Wait *4
*4 Wait time should be more than 1 byte data
receiving period
DIO_START =0b1
[DIO_SET:0B 0x0C(0)]
No
DIO_RX_COMPLETION=0b1
[DIO_SET: B0 0x0C(2)]
DCLK output?
(DCLK function pin)
Yes
Read RX data *5
(DIO pins)
No
*5 RX data must be transferred to the HOST
at rising edge of DCLK.
RX completed?
Yes
Yes
Next packet to be RX?
No
TRX_OFF issue
[RF_STATUS: B0 0x0B]
To RF state transition wait flow
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○DIO output mode 2 operation
While RXDIO_CTRL[1:0]=0b11, RX data (after L-field) will be stored into the RX_FIFO. RX data stored in
the RX_FIFO is output through DIO pins, if setting DIO_START ([DIO_SET: B0 0x0C(0)])=0b1. Upon
outputting RX data defined by L-field, RX is completed and generate RF completion interrupt (INT[8] group2).
In case of TRX_OFF, issuing TRX_OFF by [RF_STATUS:B0 0x0B] register.
START
*1 DIO/DCLK pins are defined as follows:
DIO pins setting *1
RXDIO_CTRL setting=0b11
[DIO_SET: B0 0x0C(7-6)]
Preamble/SyncWord
Error tolerance setting *2
RX_ON issue *3
[RF_STATUS: B0 0x0B]
[GPIO0_CTRL: B0 0x4E]
[GPIO1_CTRL: B0 0x4F]
[GPIO2_CTRL: B0 0x50]
[GPIO3_CTRL: B0 0x51]
[EXT_CLK_CTRL: B0 0x52]
[SPI/EXT_PA_CTRL: B0 0x53]
*2: Preamble, SyncWord and Error tolerance are set
by following registers.
Preamble
SyncWord
[DATA_SET1: B0 0x07]
[SYNC_CONDITION1-3: B0 0x45-47]
[SYNCWORD1_SET0-3: B1 0x27-2A]
[SYNCWORD2_SET0-3: B1 0x2B-2E]
[SYNC_WORD_LEN: B1 0x25]
[DATA_SET2: B0 0x08]
*3: Please refer to RF state transition wait flow
No
SyncWord Detection (INT[13])?
[INT_SOURCE_GRP3: B0 0x0F(5)]
Yes
Wait *4
DIO_START =0b1
*4 Wait time should be more than Length field
+ 1 byte data receiving period.
1 byte data is decoded 8 bit data. If using
Manchester code, 1 byte period becomes
160μs (@ 100kbps).
[DIO_SET:0B 0x0C(0)]
No
DCLK output?
(DCLK function pin)
Yes
Read RX data *5
(DIO pins)
No
*5 RX data must be transferred to the HOST
at rising edge of DCLK.
RX completion (INT[8])?
[INT_SOURCE_GRP2: B0 0x0E(0)]
Yes
Yes
Next packet to be RX?
No
TRX_OFF issue
[RF_STATUS: B0 0x0B]
To RF state transition wait flow
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(2) FIFO mode (less than 64 byte)
FIFO mode can be selected by RXDIO_CTRL[1:0]([DIO_SET: B0 0x0C(7-6)])=0b00. After SyncWord
detection, RX data will be stored into the RX_FIFO. Upon Data RX completion interrupt (INT[8] group2)
occurs, the host will read RX data from [RD_FIFO:B0 0x7F] registers. If CRC errors interrupt (INT[9] group2)
is generated, the next packet can be ready to receive without reading all current RX data by setting
STATE_CLR1 [STATE_CLR: B0 0x16(1)](RX FIFO pointer clear). If FIFO-Full trigger and FIFO-Empty
trigger are not used, please set 0b0 to both RXFIFO_THRH_EN([RXFIFO_THRH: B0 0x19(7)]) and
RXFIFO_THRL_EN([RXFIFO_THRH: B0 0x1A(7)]) .
START
RX FIFO trigger level setting
[RXFIFO_THRH: B0 0x19]=0x00
[RXFIFO_THRL: B0 0x1A]=0x00
*1 At lease following 2 interrupts in the group 2
should be un-masked for data receiving.
INT[8]: RX completion interrupt
INT[15]: Sync error interrupt
RX_ON issue *1
[RF_STATUS: B0 0x0B]
No
RX completion (INT[8])?
[INT_SOURCE_GRP2] B0 0x0E(0)]
Yes
Yes
CRC error (INT[9])?
[INT_SOURCE_GRP2] B0 0x0E(1)]
RX FIFO pointer clear
No
[STATE_CLR: B0 0x16(1)]
Read RX data
INT[9] clear
[RD_FIFO:B0 0x7F]
[INT_SOURCE_GRP2: B0 0x0E]
INT[8] clear
[INT_SOURCE_GRP2: B0 0x0E]
Set TX_ON after RX completion? Yes
[RF_STATUS_CTRL:B0 0x0A]
No
Set TRX_OFF/SLEEP after RX completion?
[RF_STATUS_CTRL:B0 0x0A]
Yes
No
Yes
Next packet to be received?
TX?
No
Yes
TRX_OFF issue
[RF_STATUS: B0 0x0B]
TX_ON issue
[RF_STATUS: B0 0x0B]
To RF state transition wait
flow and TX flow
To RF state transition wait flow
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(3) FIFO mode (65 byte or more)
The Host must read RX data from the RX_FIFO while checking INT[5] (group1: FIFO-Full interrupt) and
INT[4] (group1: FIFO-Empty interrupt) in order to avoid FIFO-Overrun or FIFO-Underrun. Other operations
are identical to the FIFO mode (less than 64byte).
START
*1 At lease following 2 interrupts in the group 2
should be un-masked for data receiving.
INT[8]: RX completion interrupt
INT[15]: Sync error interrupt
RX_ON issue *1
[RF_STATUS: B0 0x0B]
FIFO-FULL (INT[5])?
[INT_SOURCE_GRP1: B0 0x0D(5)]
Yes
INT[5] clear
No
[INT_SOURCE_GRP1: B0 0x0D]
RX FIFO-Full level Disable setting
[RX_FIFO_THRH: B0 0x19]
Read RX data from FIFO
[RD FIFO:B0 0x7F]
RX FIFO-Full level Enable setting
[RX_FIFO_THRH: B0 0x19]
No
ACK_TX?
RX completion (INT[8])?
[INT_SOURCE_GRP2: B0 0x0E(0)]
Yes
To ACK_TX flow
Yes
CRC error (INT[9])?
[INT_SOURCE_GRP2: B0 0x0E(1)]
RX FIFO pointer clear
No
[STATE_CLR: B0 0x16(1)]
Read RX data
[RD_FIFO:B0 0x7F]
INT[9] clear
[INT_SOURCE_GRP2: B0 0x0E(1)]
INT[8] clear
[INT_SOURCE_GRP2: B0 0x0E(0)]
Set TX_ON after RX completion?
[RF_STATUS_CTRL:B0 0x0A]
Yes
No
Set TRX_OFF/SLEEP after RX completion? Yes
[RF_STATUS_CTRL:B0 0x0A]
To RF state transition wait
flow
No
Yes
Next packet to be received ?
No
TX?
Yes
TX_ON issue
[RF_STATUS: B0 0x0B]
No
TRX_OFF issue
[RF_STATUS: B0 0x0B]
To RF state transition wait flow
To RF state transition wait
flow and TX flow
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(4) ACK transmission
ACK TX flow is as follows. During RX, ACK frame can be set in the TX FIFO.
START
RX FIFO trigger setting *1
[RXFIFO_THRH: B0 0x19]
[RXFIFO_THRL: B0 0x1A]
RX_ON issue*2
[RF_STATUS: B0 0x0B]
No
* In case of using interrupt,
FIFO-Full interrupt notification should be ON.
*2 Please refer to RF state transition wait
flow.
From RX flow
FIFO-Full interrupt?
INT[5] [INT_SOURCE_GRP1: B0 0x0D]
No
Yes
Read RX data *3
Self addressed?
Yes
[RD_FIFO:B0 0x7F]
Write TX data *4
*3 read address field to
check length and
packet destination.
[WR_TX_FIFO:B0 0x7C]
No
*4 ACK frame is set to TX FIFO.
RX completion (INT[8])? *5
[INT_SOURCE_GRP2: B0 0x0E(0)]
*5 Please refer the following
“NOTE”
Yes
Yes
CRC error (INT[9])?
[INT_SOURCE_GRP2] B0 0x0E(1)]
No
*6 Please refer to RF state
transition wait flow.
No
TX_ON issue *6
INT[8] and [9] clear
[RF_STATUS: B0 0x0B]
[INT_SOURCE_GRP2: B0 0x0E]
Clear TX FIFO pointer
TX completion (INT[16])?
[INT_SOURCE_GRP3] B0 0x0F(0)]
[STATE_CLR: B0 0x16(0)]
Yes
TRX_OFF issue
[RF_STATUS: B0 0x0B]
Yes
Read all RX data
[RD_FIFO:B0 0x7F]
Read RX data?
No
Clear RX FIFO pointer
[STATE_CLR: B0 0x16(1)]
END
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NOTE:
If setting “FAST_TX_EB=0b1” or “AUTO_TX_EN=0b1 or “RXDONE_MODE[1:0]=0b01 (move to TX
state)” at the [RF_STATUS:CTRL:B0 0x0A] register, moving to TX_ON state automatically after RX
completion in above flowchart.
Even if CRC error occurs, moving to TX_ON state. Since CRC errors interrupt (INT[9] group2) and RX
completion interrupt (INT[8] group2) occur almost same timeing, Therefore in case of CRC error interrupt
occurs, Force_TRX_OFF should be issued by [RF_STATUS:B0 0x0B] register withing the transition time from
RX state to TX state(1.188msec), and clear TX FIFO pointer by [STATE_CLR:B0 0x16] register. When it is
hard to issue Force_TRX_OFF during the trasition time due to MCU performance, “FAST_TX”, “AUTO_TX”
and “move to TX state after RX completion” should be disabled. (In “FAST_TX”, trnasmitting conditoin
depends on [TXFIFO_THRL:B0 0x18] register.)
(5) Field check transmission
After enabling Filedcheck functions, issuing RX_ON by [RF_STATUS:B0 0x0B] register. According to the
setting of CA_INT_CTRL([C_CHECK_CTRL:B0 0x1B(6)]), filed checking result (match or no match) can be
notified by the INT[14](group2: Field checking interrupt). Numbers of unmatched packets can be counted and
stored into [ADDR_CHK_CTR_H/L: B1 0x62/0x63]) registers. This counter can be cleared by STATE_CLR4
[STATE_CLR: B0 0x16(4)](Address check counter clear).
*1 C-field/M-field/A-field check can be possible with
the setting below.
START
[C_CHECK_CTRL: B0 0x1B]
[M_CHECK_CTRL: B0 0x1C]
[A_CHECK_CTRL: B0 0x1D]
[C_FIELD_WORD1-5: B0 0x1E-0x22]
[M_FIELD_WORD1-4: B0 0x21-0x26]
[A_FIELD_WORD1-6: B0 0x27-0x2C]
Field check setting *1
RX_ON issue
[RF_STATUS] B0 0x0B]
No
Field checking compete (INT[14])?
[INT_SOURCE_GRP2] B0 0x0E(6)]
Yes
INT[14] clear
[INT SOURCE GRP2: B0
Yes
Read RX data?
No
Yes
RX flow
No
RX completion (INT[8])?
[INT_SOURCE_GRP2] B0 0x0E(0)]
Yes
*2 Clear all remaining interrupt
in the group 2.
INT GRP2 clear *2
[INT_SOURCE_GRP2: B0 0x0E]
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(6) CCA
○Normal mode
After setting CCA_EN([CCA_CTRL: B0 0x39(4)])=0b1, issuing RX_ON by [RF_STATUS:B0 0x0B]
register. Comparing aquired ED average value with CCA threshold value in [CCA_LVL: B0 0x37] register
and noitce the result. After CCA execution, CCA_EN([CCA_CTRL: B0 0x39(4)]) is disabled and RF
maintains RX_ON state.
Even if set CCA_EN=0b1 in the RX_ON state, CCA execution is possible.
START
CCA_EN setting
[CCA_CTRL: B0 0x39(4)]
RX_ON issue *1
[RF_STATUS: B0 0x0B]
No
*1 CCA start
CCA completion (INT[18]) ?
[INT_SOURCE_GRP3: B0 0x0F(2)]
Yes
Read CCA result
[CCA_CTRL: B0 0x39(1-0)]
CCA_EN setting
[CCA_CTRL: B0 0x39(4)]
INT[18] clear
[INT_SOURCE_GRP3: B0 0x0F(2)]
No
Discontinue CCA ?
Yes
TRX_OFF issue
[RF_STATUS: B0 0x0B]
END
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○Continuous mode
Continuous CCA mode is executed by issuing RX_ON by [RF_STATU:B0 0x0B] register after setting
CCA_EN([CCA_CTRL: B0 0x39(4)])=0b1 and CCA_CPU_EN([CCA_CTRL: B0 0x39(5)])=0b1. In this
mode, CCA continues until CCA_STOP([CCA_CTRL: B0 0x39(7)])=0b1 is set. CCA completion interupt
(INT[18]: group3) is not generated. During CCA execution, CCA_RSLT([CCA_CTRL: B0 0x39(1-0)]),
[CCA_PROG_L: B0 0x3E], [CCA_PROG_H: B0 0x3D] are constantly updated. The value will be kept by
setting CCA_STOP([CCA_CTRL: B0 0x39(7)])=0b1.
START
CCA_EN setting
CCA_CPU_EN setting *1
*1 CCA_IDLE_EN should be 0b0
[CCA_CTRL: B0 0x39(5-4)]
RX_ON issue *2
[RF_STATUS: B0 0x0B]
No
*2 CCA start
*3 RF state transition (RX_ON) completion can
be confirmed by [RF_STATUS: B0 0x0B]=
0x66.
RX_ON completion (INT[3]) ? *3
[INT_SOURCE_GRP1: B0 0x0D(3)]
Yes
No
ED_DONE=0b1 ? *4
[ED_CTRL: B0 0x41(4)]
*4 CCA result before RX_ON are invalid.
Please read the value after RX_ON and
ED calculation flag is valid.
Yes
Read CCA result *5
CCA_RSLT[1:0] [CCA_CTRL: B0 0x39(1-0)]
CCA_PROG[9:0]
[CCA_PROG_H/L: B0 0x3D/3E]
No
*5CCA result can be read after
CCA_STOP execution.
Stop CCA ?
Yes
CCA_STOP setting *6
[CCA_CTRL: B0 0x39(7)]
*6 CCA stop
TRX_OFF issue
[RF_STATUS: B0 0x0B]
END
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○IDLE detection mode
CCA is continuously executed untill IDLE is detected. CCA (IDLE detection mode) will be executing by .
issuing RX_ON by [RF_STATU:B0 0x0B] register after setting CCA_EN([CCA_CTRL: B0 0x39(4)])=0b1,
CCA_IDLE_EN ([CCA_CTRL: B0 0x39(6)])=0b1.
START
CCA_IDLE_EN setting *1
CCA_EN setting
[CCA_CTRL: B0 0x39(6-4)]
*1 CCA_CPU_EN should be 0b0
RX_ON issue
[RF_STATUS: B0 0x0B]
No
CCA completion (INT[18])?
[INT_SOURCE_GRP3: B0 0x0F(2)]
Yes: IDLE detection
INT[18] clear
[INT_SOURCE_GRP3: B0 0x0F(2)]
END
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(7) High speed carrier checking mode
This mode is used for deciding whether continuing RX state or stoping RX state during RX state, based on
RSSI level and SyncWord detection time. The value set in the [CCA_LVL:B0 0x37] register is used for RSSI
level decision, continuous operation timer is used for SyncWord detection time decision. After decision,
operation will automaticall switch to – either SLEEP state or RX state.
START
CCA threshold setting
[CCA_LVL:B0 0x37]
Continuous operation timer setting
[WUT_CLK_SET:B0 0x2E]
[WUT_DURATION:B0 0x31]
FAST_DET_MODE_EN setting
CCA_EN setting
[CCA_CTRL:B0 0x39(4-3)]
RX_ON issue *1
*1 CCA start
[RF_STATUS: B0 0x0B]
Carrier detected?
(Automatic)
No: IDLE detection
Yes: BUSY detection
Keep RX state
SyncWord detection?
No *2
*2: Expiring the continuous
operation timer
Yes
SLEEP command
(Automatic)
Receive RX data
SLEEP state
END
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(8) ED scan
ED value will be automatically acquired by issuing RX_ON by [RF_STATU:B0 0x0B] register after setting
ED_CALC_EN ([ED_CTRL: B0 0x41(7)])=0b1. ED value is constanty updated when ED_RSLT_SET
([ED_CTRL:B0 0x41(3)] )=0b0.
START
ED calculations enable setting
ED value constantly updated setting
[ED_CTRL: B0 0x41(7,3)]
ED value will be acquired by enabling ED
calculation after RX_ON issue,
RX_ON issue
[RF_STATUS:B0 0x0B]
No
ED value calculation
completion?
[ED_CTRL:B0 0x41(4)]
Yes
Read ED value
[ED_RSLT:B0 0x3A]
ED value will be constantly updated
constantly
Yes
Channel change ?
No
RF channel change
[CH_SET:B0 0x09]
TRX_OFF issue
[RF_STATUS:B0 0x0B]
General purpose timer start
[GT_SET:B0 0x32]
To RF state transition wait flow
No
General Timer INT ?
[INT_SOURCE_GRP3:B0 0x0F]
INT[22]/INT[23]
Yes
General timer INT clear
These processes are not necessary if 250μs wait
is added after RF channel change setting.
[INT_SOURCE_GRP3:B0 0x0F]
INT[22]/INT[23]
(*1)
(*1) general purpose timer setting example
If 250μs wait is programmed using general purpose timer 1,
The following registers can be used.
[GT_CLK_SET:B0 0x33]
0x01(128 division)
[GT_INTERVAL1:B0 0x34]
0x04(timer setting)
[GT_SET:B0 0x32]
0x03(2MHz clock, timer start)
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●SLEEP Sequence
(1) SLEEP
SLEEP can be executed by setting SLEEP_EN([SLEEP/WU_SET:B0 0x2D(0)])=0b1. SLEEP can be
released by setting SLEEP_EN=0b0. If VCO calibration automatic execution setting AUTO_VCOCAL_EN
([VCO_CAL_START:B0 0x6F (4)])=0b1, VCO calibration is performed after clock stabilization completion
interrupt (INT[0] group1) from SLEEP release.
START
SLEEP state
[SLEEP/WU_SET:B0 0x2D]
No
SLEEP released?
Yes
SLEEP released
[SLEEP/WU_SET: B0 0x2D]
No
Clock stabilization
completion(INT[0])?
[INT_SOURCE_GRP1:B0 0x0D(0)]
Yes
Automatic VCO calibration?
No
[VCO_CAL_START:B0 0x6F(4)]
Yes
No
VCO calibration
Completion (INT[1])?
[INT_SOURCE_GRP1:B0 0x0D(1)]
Yes
END
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(2) Wake-up timer
By setting the following registers, after SLEEP, automatically wake-up to RX_ON state.
If SyncWord is detected before continuous operation timer-up, RX_ON will be continued to receive a packet.
After receiving RX completion interrupt(INT[8]: group2), by reading INT group2, MCU can determine read
RX data or not. In order to re-enter SLEEP state, executing SLEEP command after clearing all interrupts in INT
group2. If generating Sync error interrupt(INT[15]: group2), executing SLEEP command after clearing
RX_FIFO and INT group2.
If SyncWord cannot be detected, automatically go back to SLEEP state after continuous operation timer-up.
[Wake-up timer setting]
WAKEUP_EN([SLEEP_SET:B0 0x2D(4)]) =0b1
RX_DURATION_EN([SLEEP_SET:B0
0x2D(5)])=0b1
WAKEUP_MODE([SLEEP_SET:B0 0x2D(6)])=0b0
[WUT_CLK_SET:B0 0x2E]
[WUT_INTERVAL_H:B0 0x2F]
[WUT_INTERVAL_L:B0 0x30]
[RX_DURATION:B0 0x31]
START *1
SLEEP execution
[Field check function setting]
*1 At lease following 2 interrupts in the group 2
should be un-masked for data receiving.
INT[8]: RX completion interrupt
INT[15]: Sync error interrupt
[SLEEP/WU_SET:B0 0x2D(0)]
[C_CHECK_CTR:B0 0x1B]
[M_CHECK_CTRL:B0 0x1C]
[A_CHECK_CTRL:B0 0x1D]
[C_FIELD_WORD1:B0 0x1E] to
[C_FIELD_WORD5:B0 0x22]
[M_FIELD_WORD1:B0 0x23] to
[M_FIELD_WORD4:B0 0x26]
[A_FIELD_WORD1:B0 0x27] to
[A_FIELD_WORD6:B0 0x2C]
RX completion(INT[8])?
No
[INT_SOURCE_GRP2:B0 0x0E(0)]
Sync error (INT[15])?
No
[INT_SOURCE_GRP2:B0 0x0E(7)]
Yes
Yes
Read INT_SOURCE_GRP2
[INT_SOURCE_GRP2:B0 0x0E]
Field checking (INT[14])?
No
[INT_SOURCE_GRP2:B0 0x0E(6)]
Yes
RX FIFO clear
[SATE_CLR:B0 0x16(1)]
Read all RX data from RX_FIFO
[RD_FIFO:B0 0x7F]
Clear INT_SOURCE_GRP2
[INT_SOURCE_GRP2:B0 0x0E]
SLEEP execution
[SLEEP/WU_SET:B0 0x2D(0)]
No
Wake-up timer OFF)?
Wake-up timer OFF execution
[SLEEP/WU_SET:B0 0x2D(4)]
END
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●Error Process
(1) Sync error
When out-of-sync is detected during data reception after SyncWord detection, Sync error interrupt (INT[15]
group2) will be generated, RX completion interrupt (INT[8]: group2) will not be generated. If Sync error
interrupt occurs, issuing STATE_CLR1 [STATE_CLR: B0 0x16(1)](RX FIFO pointer clear) without read
RX_FIFO data and clear Sync error interrupt.
”data reception” indicates receiving data (L-field, data, CRC). after SyncWord detection.
START
RX_ON issue *1
[RF_STATUS:B0 0x0B]
*1 At lease following 2 interrupts in the group 2
should be un-masked for data receiving.
INT[8]: RX completion interrupt
INT[15]: Sync error interrupt
Out-of-Sync detection
Sync Word error (INT[15])?
No
[INT_SOURCE_GRP2:B0 0x0D(7)]
Yes
Clear RX FIFO
Normal reception
(To RX flow)
[STATE_CLR:B0 0x16(1)]
INT[15] clear
[INT_SOURCE_GRP2:B0 0x0E]
Yes
Next packet received?
No
TRX_OFF issue
[RF_STATUS:B0 0x0B]
RF state transition wait flow
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(2) TX FIFO access error
If one of the following conditions is met, TX FIFO access error interrupt (INT[20]: group3) will be generated.
●After TX Data request accept completion interrupt (INT[17]: group3] was generated, next packet is written
to the TX_FIFO without transmiting the current TX data.
●Data write overflow occurs to the TX_FIFO.
●No TX data in the TX_FIFO during TX data transimission.
When TX FIFO acccess error interrupt occurs, issuing TRX_OFF after TX completion interrupt (INT[16]:
group3) is recognized, or issueing Force_TRX_OFF by [RF_STATUS:B0 0x0A] register without waiting for TX
completion interrupt. After that, issuing TX FIFO pointer clear by [STATE_CLR:B0 0x16] register and clear
remaining interrupts relative with TX in the [INT_SOURCE_GRP3:B0 0x0F] register.
If TX FIFO access error occurs, subquent TX data will be inverted. CRC error should be detected at rexeiver
side even if TRX_OFF is issued when TX completion interrupt detected.
START
FAST_TX setting
[RF_STATUS_CTRL:B0 0x0A]
[TXFIFO_THRH/L:B0 0x17/18]
Write TX data *1
[WR_TX_FIFO:B0 0x7C]
*1 If data written to FIFO exceed THFIFO_THRL[5:0]
[TXFIFO_THRL:B0 0x18(5-0)]+1, TX will start.
(Length is included in the data length written to
FIFO)
TX FIFO access error (INT[20])?
No
[NT_SOURCE_GRP3:B0 0x0F(4)]
Yes
Forced to stop TX ?
Yes
Normal TX
(To TX flowchart)
No
No
TX completion (INT[16]) ?
[INT_SOURCE_GRP3:B0 0x0F(0)]
Yes
Force_TRX_OFF issue
[RF_STATUS:B0 0x0B]
TRX_OFF issue
[RF_STATUS:B0 0x0B]
TX FIFO pointer clear
[STATE_CLR:B0 0x16(0)]
Clear INT GRP3
INT[16]-[20]
[INT SOURCE GRP3:B0 0x0F]
Yes
Next packet TX ?
No
RF state transition wait flow
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(3) RX FIFO access error
If one of the following conditions is met, RX FIFO access error interrupt (INT[12]: group2) will be generated.
●RX data overflow occurs to RX_FIFO
●Read RX_FIFO during no data in the RX_FIFO
When RX FIFO acccess error interrupt occurs, issuing TRX_OFF after RX completion interrupt (INT[8]:
group2) is recognized, or issueing Force_TRX_OFF by [RF_STATUS:B0 0x0B] register without waiting for
RX completion interrupt. After that, issuing RX FIFO pointer clear by [STATE_CLR:B0 0x16] register and
clear remaining interrupts in the [INT_SOURCE_GRP2:B0 0x0E] register.
START
RX_ON issue
[RF_STATUS:B0 0x0B]
RX FIFO access error (INT[12])?
No
[NT_SOURCE_GRP2:B0 0x0E(4)]
Yes
Forced to stop RX ?
Yes
Normal RX
(To RX flowchart)
No
No
RX completion (INT[8]) ?
[INT_SOURCE_GRP2:B0 0x0E(0)]
Yes
Force_TRX_OFF issue
[RF_STATUS:B0 0x0B]
TRX_OFF issue
[RF_STATUS:B0 0x0B]
RX FIFO pointer clear
[STATE_CLR:B0 0x16(1)]
Clear INT GRP2
[INT_SOURCE_GRP2:B0 0x0E]
Yes
Next packet to be received?
No
RF state transition wait flow
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(4) PLL unlock detection
○TX
During TX, if PLL unlock is detected, PLL unlock interrupt (INT[2] group1) will be generated. When PLL
unlock interrupt occurs, Force_TRX_OFF is automaticcally issued and move to IDLE state. SET_TRX[3:0]
([RF_STATUS: B0 0x0B(3-0)]) will be written to 0b0011(Force_TRX_OFF). PLL unlock might be occurred
when VCO calibration value is not correct. Please confirm VCO calibration or perform VCOcalibration again.
After PLL unlock interrupt occurs, max. 147 μs is necessary to move to IDLE state. Please wait for at least
147μs before next TX, RX or VCO calibration is performed.
START
Write TX data
[WR_TX_FIFO:B0 0x7C]
TX_ON issue
[RF_STATUS:B0 0x0B]
PLL unlock (INT[12])?
[INT_SOURCE_GRP1:B0 0x0D(2)]
No
Yes
* Force_TRX_OFF is issued
automatically.
Normal TX
(To TX flowchart)
INT[12] clear
[INT_SOURCE_GRP1:B0 0x0D(2)]
Wait TRX_OFF(IDLE)
(147μsec)
Yes
Next packet TX?
No
END
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○RX
During RX, if PLL unlock is detected, PLL unlock interrupt (INT[2] group1) will be generated. During RX,
even if PLL unlock is detected, RX state is maintained (do not move to IDLE state). Please receive next packet
after clearing PLL unlock interrupt.
When PLL unlock interrupt occurs frequently, PLL unlock cause mitgh be due to the mismatch of the VCO
circuit and using frequency band. Please use after removing the cause by circuit verification.
START
RX_ON issue
[RF_STATUS:B0 0x0B]
PLL unlock (INT[2])?
No
[INT_SOURCE_GRP1:B0 0x0D (2)]
Yes
Normal RX
(To RX flowchart)
INT[2] clear
[INT_SOURCE_GRP1:B0 0x0D(2)]
Yes
Next packet to be received?
No
Force_TRX_OFF issue
[RF_STATUS:B0 0x0B]
END
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●Data Rate Change Sequence
When changing data rate during operation, registers relative data rate should be set in TRX_OFF state and issuing
RST1([RST_SET: B0 0x01(1)])(MODEM reset) after register setting. If not issuing RST1, ML7344 can not
transmit or receive correctlly.
START *1
*1 TX_ON or RX_ON state
TRX_OFF issue
[RF_STATUS:B0 0x0B]
Change Data Rate *2
*2 Relating registers
refer to “Data rate setting function”
RST1 issue
[RST_SET:B0 0x0B]
END
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■Timing Chart
The followings are operation timing for major functions.
NOTE: Bold characters indicate pins related signals. Non bold characters indicate internal signals.
●Start-up
Regulator voltage wake up time
VDD
RESETN
500μs *1
OSC/Reg enable
Clock stabilization time
INT[0]
50μs *2
(CLK stabilized completion)
[INT_SOURCE_GRP1: B0 0x0D]
Regulator stabilization time
625μs *3
REG_WAIT_DONE
SPI access
prohibited
BANK0, 1 & 3
Access possible
All BANK&FIFO
Access possible
RF operation
possible
*1 : For wake-up timing of VDD and RESETN, please refer to the “Reset characteristics”.
*2 : When setting XTAL_EN(CLK_SET2:B0 0x03(4)))=0b1, it is possible to adjust to 10/50/250/500 μs, by
setting OSC_W_SEL[1:0]([ADC_CLK_SET: B1 0x08(6-5)]).
When using TCXO (TCXO_EN([CLK_SET2:B0 0x03(6)])=0b1), clock stabilization time is 5.5μs.
*3 : [VCO_CAL_START:B0 0x6F] and [RF_STATUS:B0 0x0B] resister access is possible, but process is
pending until REG_WAIT_DONE is asserted.
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●TX
FIFO write
TX_ON
command
INT[3] clear
command
SCEN
TX completion
interrupt *1
SET_TRX[3:0]
[RF_STATUS: B0 0x0B]
0x8(TRX_OFF)
0x9(TX_ON)
1406μs
GET_TRX[3:0]
[RF_STATUS: B0 0x0B]
0x8(TRX_OFF)
0x8(TRX_OFF)
147μs
0x8(TRX_OFF)
0x9(TX_ON)
1222μs
144μs
1271μs
143μs
TX_ON
PA_ON
Data TX time *2
Air
INT[17]
(TX Data request accept completion)
[INT_SOURCE_GRP3: B0 0x0F]
INT[3]
(RF state transition completion)
[INT_SOURCE_GRP1: B0 0x0D]
INT[16]
(TX completion)
[INT_SOURCE_GRP3: B0 0x0F]
DCLK output (*3)
0.4 bit time
(at 100kbps, 4μs)
*1 : When TXDONE_MODE[1:0]([RF_STATUS_CTRL: B0 0x0A(1-0)]) = 0b00(default), SET_TRX[3:0]
([RF_STATUS: B0 0x0B(3-0)]) will be set to 0x8(TRX_OFF) automatically, upon detection of TX
completion.
*2 : Data TX time calculation is as follows:
Data TX time [sec] = (number of TX bits+3)×1bit TX duration time[sec]
1bit TX duration time [sec] = 1/data rate [bps]
*3 : When setting TXDIO_CTRL[1:0]([DIO_SET: B0 0x0C(5-4)])=0b01.
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●RX
RX_ON
INT[3]clear
command
DIO data output command
(When DIO function is used)
TRX_OFF
command
SCEN
SET_TRX[3:0]
[RF_STATUS: B0 0x0B]
0x8(TRX_OFF)
0x8(TRX_OFF)
0x6(RX_ON)
4μs
471μs
GET_TRX[3:0]
[RF_STATUS: B0 0x0B]
0x8(TRX_OFF)
0x6(RX_ON)
0x8(TRX_OFF)
RX enable
Demod data
PB
Sync
Word
Length
Data CRC
INT[3](RF state transition completion )
[INT_SOURCE_GRP1: B0 0x0D]
INT[13] (SyncWord detection)
[INT_SOURCE_GRP2: B0 0x0E]
INT[8] (RX completion)
[INT_SOURCE_GRP2: B0 0x0E]
DCLK output (*1)
1 to 2 bit time
(at 100kbps , 10 to 20µs)
*1 : When setting RXDIO_CTRL[1:0]([DIO_SET: B0 0x0C(7-6)])=0b10 or 0b11.
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●Transition from TX to RX
SET_TRX[3:0]
[RF_STATU: B0 0x0B]
0x6(RX_ON)
0x9(TX_ON)
611μs
GET_TRX[3:0]
[RF_STATUS: B0 0x0B]
0x9(TX_ON)
0x6(RX_ON)
INT[3] (RF state transition completion)
[INT_SOURCE_GRP1: B0 0x0D]
PA_ON
143μs
●Transition from RX to TX
SET_TRX[3:0]
[RF_STATUS: B0 0x0B]
0x9(TX_ON)
0x6(RX_ON)
1188μs
GET_TRX[3:0]
[RF_STATUS: B0 0x0B]
0x6(RX_ON)
0x9(TX_ON)
INT[3] (RF state transition completion)
[INT_SOURCE_GRP1: B0 0x0D]
1053μs
PA_ON
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●Transition from IDLE to SLEEP
SLEEP
command
SLEEP_EN
[SLEEPWU_SET: B0 0x2D]
SET_TRX[3:0]
[RF_STATUS: B0 0x0B]
By SLEEP_EN=0b1,
automatic switching
0x8(TRX_OFF)
0x3(Force_TRX_OFF)
GET_TRX[3:0]
0x8(TRX_OFF)
[RF_STATUS: B0 0x0B]
SLEEP transition time *1
OSC/Reg enable
0.3μs
CLK_INIT_DONE
[CLK_SET: B0 0x02]
*1 : Clock input should be required for SLEEP transition. If TCXO is stopped during SLEEP stae, please wait
0.3μs after SLEEP command issued (SLEEP_EN([SLEEP/WU_SET: B0 0x2D(0)])=0b1) and then stop TCXO.
●Transition from TX/RX to SLEEP
SLEEP
command
SLEEP_EN
[SLEEPWU_SET: B0 0x2D]
SET_TRX[3:0]
[RF_STATUS: B0 0x0B]
By SLEEP_EN=0b1,
automatic switching
0x6(RX_ON)
0x9(TX_ON)
0x3(Force_TRX_OFF)
From RX_ON:4μs
From TX_ON:147μs
GET_TRX[3:0]
[RF_STATUS: B0 0x0B]
0x6(RX_ON)
0x9(TX_ON)
INT[3] (RF state transition completion)
0x8(TRX_OFF)
1μs
[INT_SOURCE_GRP1: B0 0x0D]
Time required from INT[3]
to SLEEP *1
OSC/Reg enable
CLK_INIT_DONE
1.3μs
[CLK_SET: B0 0x02]
*1 : If TCXO is used, please stop TCXO(clock) input after 1.3μs from INT[3] notification. by setting SLEEP command
(SLEEP_EN ([SLEEP/WU_SET: B0 0x2D(0)])=0b1).
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●Transition from SLEEP to IDLE
SLEEP_EN
SLEEP_EN=0b0
setting
[SLEEPWU_SET: B0 0x2D]
OSC/Reg enable
INT[0] (CLK stabilized complete)
[INT_SOURCE_GRP1: B0 0x0D]
Clock stabilization time
50μs +α *1
REG_WAIT_DONE
Sleep mode1: Register access possible
Sleep mode2: Register & FIFO access possible
Regulator stabilization time
1125μs *2
Resisters and FIFOs
access possible
RFoperation
possible
*1: When setting XTAL_EN([CLK_SET2: B0 0x03(4)])=0b1, it is possible to adjust to 10/50/250/500μs , by
setting [ADC_CLK_SET: B1 0x08(6-5)]. α is oscillation cuircuits start-up time, and max. is 500μs.
When using TCXO (TCXO_EN([CLK_SET2:B0 0x03(6)])=0b1), clock stabilization time is 5μs.
*2: [VCO_CAL_START:B0 0x6F] and [SET_TRX:B0 0x0B] registers access is possible, but process is pending
until REG_WAIT_DONE is asserted.
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●High speed carrier checking mode
Condition)
Use TCXO
ED averaging: 1 time
RX_ON
command
INT[3] clear
command
SCEN
SET_TRX[3:0]
[RF_STATUS: B0 0x0B] 0x8(TRX_OFF)
4μs
471μs
GET_TRX[3:0]
[RF_STATUS: B0 0x0B]
0x8(TRX_OFF)
0x6(RX_ON)
0x8(TRX_OFF)
0x6(RX_ON)
0x8(TRX_OFF)
166.5μs
CCA on-going flag
INT[3] (RF state transition completion)
[INT_SOURCE_GRP1: B0 0x0D]
1μs
1.3μs (*1)
SLEEP flag
*1: Clock input should be required for SLEEP transition. If TCXO is stopped during SLEEP state, please wait
1.3μs from INT[3] and then stop TCXO.
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■Registers
●Register map
It is consist of 4 banks, BANK0, BANK1, BANK2 and BANK3. Each BANK has address space of 0x00 to 0x7F,
128 byte in total.
The space shown as gray highlighted part is not implemented in LSI or reserved bits. Reserved bits may be
assigned closed function. Please use default values to reserved bits, when write a register which contains reserved
bits. Regarding reserved register, access is inhibited. BANK3 is closed BANK, then access is limited..
Transition between banks can be controlled by bit 3-0 ( BANK[3:0] ) of [BANK_SEL] register.
: Implemented as functionable register
: Impelemted as reserved bits
BANK0
Address
Symbol
(# test register)
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
BANK_SEL
RST_SET
CLK_SET1
CLK_SET2
PKT_CTRL1
PKT_CTRL2
DRATE_SET
DATA_SET1
DATA_SET2
CH_SET
RF_STATUS_CTRL
RF_STATUS
DIO_SET
INT_SOURCE_GRP1
INT_SOURCE_GRP2
INT_SOURCE_GRP3
INT_EN_GRP1
INT_EN_GRP2
INT_EN_GRP3
CRC_ERR_H
CRC_ERR_M
CRC_ERR_L
STATE_CLR
TXFIFO_THRH
0x18
TXFIFO_THRL
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
RXFIFO_THRH
RXFIFO_THRL
C_CHECK_CTRL
M_CHECK_CTRL
A_CHECK_CTRL
C_FIELD_CODE1
C_FIELD_CODE2
Bit
7
6
5
4
3
2
1
0
Description
Register access bank selection
Software reset setting
Clock configuration 1
Clock configuration 2
Packet configuration 1
Packet configuration 2
Data rate setting
TX/RX data configuration 1
TX/RX data configuration 2
RF channel setting
RF auto status transition control
RF state setting and status indication
DIO mode configuration
Interrupt status for INT0 to INT7
Interrupt status for INT8 to INT15 (RX)
Interrupt status for INT16 to INT23 (TX)
Interrupt mask for INT0 to INT7
Interrupt mask for INT8 to INT15
Interrupt mask for INT16 to INT23
CRC error status (high byte)
CRC error status (middle byte)
CRC error status (low byte)
State clear control
TX FIFO-Full level setting
TX FIFO-Empty level setting and TX trigger level
setting in FAST_TX mode
RX FIFO-Full level setting
RX FIFO-Empty level setting
Control field (C-field) detection setting
Manufacture ID field (M-field) detection setting
Address field (A-Field) detection setting
C-field setting code #1
C-field setting code #2
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BANK0 (continued)
Address
Symbol
(# test register)
Bit
7
6
5
4
3
2
1
0
Description
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
C_FIELD_CODE3
C_FIELD_CODE4
C_FIELD_CODE5
M_FIELD_CODE1
M_FIELD_CODE2
M_FIELD_CODE3
M_FIELD_CODE4
A_FIELD_CODE1
A_FIELD_CODE2
A_FIELD_CODE3
A_FIELD_CODE4
A_FIELD_CODE5
A_FIELD_CODE6
SLEEP/WU_SET
WUT_CLK_SET
WUT_INTERVAL_H
WUT_INTERVAL_L
WU_DURATION
GT_SET
GT_CLK_SET
C-field setting code #3
C-field setting code #4
C-field setting code #5
M-field 1st byte setting code #1
M-field 1st byte setting code #2
M-field 2nd byte setting code #1
M-field 2nd byte setting code #2
A-field 1st byte setting
A-field 2nd byte setting
A-field 3rd byte setting
A-field 4th byte setting
A-field 5th byte setting
A-field 6th byte setting
SLEEP execution and Wake-up operation setting
Wake-up timer clock division setting
Wake-up timer interval setting (high byte)
Wake-up timer interval setting (low byte)
Continue operation timer (after Wake-up) setting
General purpose timer configuration
General purpose timer clock division setting
0x34
GT1_TIMER
General purpose timer #1 setting
0x35
GT2_TIMER
0x36
CCA_IGNORE_LVL
0x37
CCA_LVL
0x38
CCA_ABORT
0x39
0x3A
0x3B
0x3C
CCA_CTRL
ED_RSLT
IDLE_WAIT_H
IDLE_WAIT_L
0x3D
CCA_PROG_H
0x3E
CCA_PROG_L
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
Reserved
VCO_VTRSLT
ED_CTRL
TXPR_LEN_H
TXPR_LEN_L
POSTAMBLE_SET
SYNC_CONDITION1
SYNC_CONDITION2
0x47
SYNC_CONDITION3
General purpose timer #2 setting
ED threshold level setting for excluding CCA
judgement
CCA threshold level setting
Timing setting for forced termination of CCA
operation
CCA control setting and result indication
ED value indication
IDLE detection period setting during CCA (high 2bits)
IDLE detection period setting during CCA (low byte)
IDLE judgement elapsed time indication during CCA
(high 2 bits)
DLE judgement elapsed time indication during CCA
(low byte)
Reserved
VCO voltage adjustment result indication
ED detection control setting
TX preamble length setting (high byte)
TX preamble length setting (low byte)
Postamble length and pattern setting
RX preamble setting and ED threshold check setting
ED threshold setting during synchronization
Bit error tolerance setting in RX preamble and
SyncWord detection
Reserved
Monitor function setting
GPIO0 pin (pin #16) configuration setting
GPIO1 pin (pin #17) configuration setting
0x48-4C
0x4D
0x4E
0x4F
Reserved
MON_CTRL
GPIO0_CTRL
GPIO1_CTRL
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BANK0 (continued)
Address
Symbol
(# test register)
0x50
0x51
0x52
GPIO2_CTRL
GPIO3_CTRL
EXTCLK_CTRL
0x53
SPI/EX_PA_CTRL
0x54
0x55
0x56-61
IF_FREQ_H
IF_FREQ_L
Reserved
0x62
OSC_ADJ1
0x63
OSC_ADJ2
0x64-65
0x66
0x67
0x68
0x69
0x6A-6D
0x6E
0x6F
0x70
0x71
Reserved
RSSI_ADJ
PA_MODE
PA_REG_FINE_ADJ
PA_ADJ
Reserved
VCO_CAL
VCO_CAL_START
CLK_CAL_SET
CLK_CAL_TIME
0x72
CLK_CAL_H
0x73
CLK_CAL_L
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
Reserved
SLEEP_INT_CLR
RF_TEST_MODE
STM_STATE
FIFO_SET
RX_FIFO_LAST
TX_PKT_LEN_H
TX_PKT_LEN_L
WR_TX_FIFO
RX_PKT_LEN_H
RX_PKT_LEN_L
RD_FIFO
Bit
7
6
5
4
3
2
1
0
Description
GPIO2 pin (pin #18) configuration setting
GPIO3 pin (pin #19) configuration setting
EXT_CLK pin (pin #10) configuration setting
SPI interface IO configuration/external PA control
setting
IF frequency setting (high byte)
IF frequency setting (low byte)
Reserved
Coarse adjustment of load capacitance for oscillation
circuit
Fine adjustment of load capacitance for oscillation
circuit
Reserved
RSSI value adjustment
PA mode setting / PA regulator coarse adjustment
PA regulator fine adjustment
PA gain adjustment
Reserved
VCO calibration setting or status indication
VCO calibration execution
Low speed clock calibration control
Low speed clock calibration time setting
Low speed clock calibration result indication
(high byte)
Low speed clock calibration result indication
(low byte)
Interruption clear setting during SLEEP state
TX test pattern setting
State machine status / synchronization status indication
FIFO readout setting
RX FIFO data usage status indication
Tx packet length setting (high byte)
Tx packet length setting (low byte)
TX_FIFO
Rx packet length indication (high byte)
Rx packet length indication (low byte)
FIFO read
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BANK1
Address
Symbol
(# test register)
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09-0A
0x0B
0x0C-0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
BANK_SEL
CLK_OUT
TX_RATE_H
TX_RATE_L
RX_RATE1_H
RX_RATE1_L
RX_RATE2
Reserved
ADC_CLK_SET
Reserved
PLL_LOCK_DETECT
Reserved
RSSI_MAG_ADJ
RSSI_VAL
AFC_CTRL
CRC_POLY3
CRC_POLY2
CRC_POLY1
CRC_POLY0
PLL_DIV_SET
TXFREQ_I
TXFREQ_FH
TXFREQ_FM
TXFREQ_FL
RXFREQ_I
RXFREQ_FH
RXFREQ_FM
RXFREQ_FL
CH_SPACE_H
CH_SPACE_L
SYNC_WORD_LEN
SYNC_WORD_EN
SYNC_WORD1_SET0
SYNC_WORD1_SET1
SYNC_WORD1_SET2
SYNC_WORD1_SET3
SYNC_WORD2_SET0
SYNC_WORD2_SET1
SYNC_WORD2_SET2
SYNC_WORD2_SET3
FSK_CTRL
Bit
7
6
5
4
3
2
1
0
Description
Register access bank select
CLK_OUT (GPIOn) output frequency setting
TX data rate conversion setting (high 4 bits)
TX data rate conversion setting (low byte)
RX data rate conversion setting 1 (high 4 bits)
RX data rate conversion setting 1 (low byte)
RX data rate conversion setting 2
Reserved
RSSI ADC clock frequency setting
Reserved
PLL lock detection setting
Reserved
Scale factor setting for ED value conversion
RSSI value indication
AFC control setting
CRC Polynomial setting 3
CRC Polynomial setting 2
CRC Polynomial setting 1
CRC Polynomial setting 0
PLL frequency division setting
TX frequency setting (I counter)
TX frequency setting (F counter high 4 bits)
TX frequency setting (F counter middle byte)
TX frequency setting (F counter low byte)
RX frequency setting (I counter)
RX frequency setting (F counter high 4 bits)
RX frequency setting (F counter middle byte)
RX frequency setting (F counter low byte)
Channel space setting (high byte)
Channel space setting (low byte)
SyncWord length setting
SyncWord enable setting
SyncWord #1 setting (bit24 to 31)
SyncWord #1 setting (bit16 to 23)
SyncWord #1 setting (bit8 to 15)
SyncWord #1 setting (bit0 to 7)
SyncWord #2 setting (bit24 to 31)
SyncWord #2 setting (bit16 to 23)
SyncWord #2 setting (bit8 to 15)
SyncWord #2 setting (bit0 to 7)
GFSK/FSK modulation timing resolution setting
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BANK1 (continued)
Address
Symbol
(# test register)
0x30
0x31
GFSK_DEV_H
GFSK_DEV_L
0x32
FSK_DEV0_H/GFIL0
0x33
FSK_DEV0_L/GFIL1
0x34
FSK_DEV1_H/GFIL2
0x35
FSK_DEV1_L/GFIL3
0x36
FSK_DEV2_H/GFIL4
0x37
FSK_DEV2_L/GFIL5
0x38
FSK_DEV3_H/GFIL6
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
FSK_DEV3_L
FSK_DEV4_H
FSK_DEV4_L
FSK_TIM_ADJ4
FSK_TIM_ADJ3
FSK_TIM_ADJ2
FSK_TIM_ADJ1
0x40
FSK_TIM_ADJ0
0x41-4C
Reserved
0x4D
VCO_CAL_MIN_I
0x4E
VCO_CAL_MIN_FH
0x4F
VCO_CAL_MIN_FM
Bit
7
6
5
4
3
2
1
0
Description
GFSK frequency deviation setting (high 6 bits)
GFSK frequency deviation setting (low byte)
FSJ 1st frequency deviation setting (high 6 bits) /
Gaussian filter coefficient setting 0
FSJ 1st frequency deviation setting (low byte) /
Gaussian filter coefficient setting 1
FSJ 2nd frequency deviation setting (high 6 bits) /
Gaussian filter coefficient setting 2
FSJ 2nd frequency deviation setting (low byte) /
Gaussian filter coefficient setting 3
FSJ 3rd frequency deviation setting (high 6 bits) /
Gaussian filter coefficient setting 4
FSJ 3rd frequency deviation setting (low byte) /
Gaussian filter coefficient setting 5
FSJ 4th frequency deviation setting (high 6 bits) /
Gaussian filter coefficient setting 6
FSJ 4th frequency deviation setting (low byte)
FSJ 5th frequency deviation setting (high 6 bits)
FSJ 5th frequency deviation setting (low byte)
FSK 4th frequency deviation hold timing setting
FSK 3rd frequency deviation hold timing setting
FSK 2nd frequency deviation hold timing setting
FSK 1st frequency deviation hold timing setting
FSK no-deviation frequency (carrier frequency) hold
timing setting
Reserved
VCO calibration low limit frequency setting
(I counter)
VCO calibration low limit frequency setting
(F counter high 4 bits)
VCO calibration low limit frequency setting
(F counter middle byte)
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BANK1 (continued)
Address
Symbol
(# test register)
0x50
VCO_CAL_MIN_FL
0x51
VCO_CAL_MAX_N
0x52
TXVCAL_MIN
0x53
TXVCAL_MAX
0x54
RXVCAL_MIN
0x55
RXVCAL_MAX
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67-7E
0x7F
Bit
7
6
5
4
3
2
1
Description
0
VCO calibration low limit frequency setting
(F counter low byte)
VCO calibration upper limit frequency setting
TX VCO calibration low limit value indication and
setting
TX VCO calibration upper limit value indication and
setting
RX VCO calibration low limit value indication and
setting
RX VCO calibration upper limit value indication and
setting
Demodulator configuration #0
Demodulator configuration #1
Demodulator configuration #2
Demodulator configuration #3
Demodulator configuration #4
Demodulator configuration #5
Demodulator configuration #6
Demodulator configuration #7
Demodulator configuration #8
Demodulator configuration #9
Demodulator configuration #10
DEMOD_SET0
DEMOD_SET1
DEMOD_SET2
DEMOD_SET3
DEMOD_SET4
DEMOD_SET5
DEMOD_SET6
DEMOD_SET7
DEMOD_SET8
DEMOD_SET9
DEMOD_SET10
Reserved
ADDR_CHK_CTR_H
ADDR_CHK_CTR_L
WHT_INIT_H
WHT_INIT_L
WHT_CFG
Reserved
ID_CODE
Address check counter indication (high 3 bits)
Address check counter indication (low byte)
Whitening initialized state setting (high 1 bit)
Whitening initialized state setting (low byte)
Whitening polynomial setting
Reserved
ID code
BANK2
Address
0x00
0x01-2B
0x2C
0x2D
0x2E
0x2F
0x30-7F
Symbol
(# test register)
Bit
7
6
5
4
3
2
1
Description
0
BANK_SEL
Reserved
LO_BIAS_IP
LO_BIAS_IN
LO_BIAS_QP
LO_BIAS_QN
Register access bank select
Closed register
Local bias adjustment (I-Phase Positive)
Local bias adjustment (I-Phase Negative)
Local bias adjustment (Q-Phase Positive)
Local bias adjustment (Q-Phase Negative)
Reserved
Closed register
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■Application circuit example
The below diagram does not show decoupling capacitors for LSI power pins.
10uF decoupling capacitor should be placed to common 3.3V power pins .
MURATA LQW15series inductors are recommended.
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■Package dimensions
Remarks for surface mount type package
Surface mount type package is very sensitive affected by heating from reflow process, humidity during storaging
Therefore, in case of reflow mouting process, please contact sales representative about product name, package
name, number of pin, package code and required reflow process condition (reflow method, temperature, number of
reflow process), storage condition.
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■Footprint Pattern (Recommendation)
When laying out PC boards, it is important to design the foot pattern so as to give consideration to ease of
mounting, bonding, positioning of parts, reliability, wiring, and elimination of slder bridges.
The optimum design for the foot pattern varies with the materials of the substrate, the sort and thichness of used
soldering paste, and the way of soldering. Therefore when laying out the foot pattern on the PC boards, refer to this
figure which mean the mounting area that the package leads are allowable for soldering PC boards.
P-WQFN32-0505-0.50-A63
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■Revision History
Document
No.
Date
FEDL7344C/E/J-01
July 8, 2013
FEDL7344C/E/J-02
July 9, 2013
FEDL7344C/E/J-03
Apr 15, 2014
Page
Previous
Current
Edition
Edition
Description
–
–
Initial release
3
3
Correct mistype(100mW TX power consumption)
13
13
Add RX power consumption of ML7344xC.
21
21
Change figure in DIO interface characteristics.
Initial level of DCLK is modified from L to H.
15
15
Added min. / max. value for TX power
17
17
Added max. value for minimum RX sensitivity.
58
58
Corrected formula of Wake-up timer interval and
continuous operation timer.
81, 96
81, 96
Updated a formula for calculating the ED value.
89, 90
Added typical values for PA adjustments.
98
98
Removed “BPF adjustment”. This is no longer
necessary.
99
98
Added “RX
132
134
Added TX_ON signal in “TX Timing-chart”
148
150
Added note of LEN_LF_EN[PKT_CTRL1: B0
0x04(5)] and PKT_FORMAT[PKT_CTRL1: B0
0x04(1-0)].
176
178
Corrected formula of wake-up timer interval in
function description.
176
178
Corrected formula of continuous operation timer
interval in function description.
193
195
194
196
204
207
Added note of LEN_LF_EN[PKT_CTRL1: B0
0x04(5)] and PKT_FORMAT[PKT_CTRL1: B0
0x04(1-0)].
208
211
Added note of CLK_OUT function
144, 239
143, 238
mode setting.”
Corrected function description of EXT_CLK pin
configuration setting (EXTCLK_IO_CFG
[EXTCLK_CTRL: B0 0x52 (2-0)])
Corrected function description of external setting
EXT_PA_CNT[SPI/EXT_PA_CTRL: B0 0x53(1)]
and EXT_PA_EN[SPI/EXT_PA_CTRL: B0
0x53(0)]
Removed a register [BPF_ADJ: B2 0x10]. BPF
adjustment is no longer necessary.
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Document
No.
Date
FEDL7344C/E/J-04
Oct 2, 2014
FEDL7344C/E/J-05
Jan 20, 2015
Page
Previous
Current
Edition
Edition
Description
-
-
Removed SPXO support
12
12
Removed Master Clock Accuracy(ACMCK2)
14
14
Corrected Regulator voltage output when sleep
mode(SUB_REG)
15
15
Corrected Typ. value of TX Power.
18
18
Corrected typ. value of blocking (470MHz
BAND).
70
70
Corrected compensation range of AFC
198
-
Removed a register [IFF_ADJ_H: B0 0x5E]
198
-
Removed a register [IFF_ADJ_L: B0 0x5F]
216
215
9
9
Added description of EXT_CLK pin
88
88
Changed frequency from 32.768kHz to 44kHz in the
example.
-
89-90
97
97
Modified registers
135
138
Corrected TX-RX transition time in Timing chart
136
139
Corrected RX start-up time in Timing chart
139
142
Corrected RX start-up time and CCA time in Timing
chart
176
179
Added note of RCOSC_MODE[SLEEP/WU_SET:
B0 0x2D(3)]
177
180
Added note of
WUDT_CLK_SET[WUT_CLK_SET: B0
0x2E(7-4)]
-
195
added [2DIV_CTRL: B0 0x48] and [ANT_CTRL:
B0 0x4C]
234
238
added equation for setting value and note of
[DEMOD_SET6: B1 0x5C]
Removed registers bit6-4 of [AFC_CTRL: B1 0x15]
Added antenna switching function.
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NOTES
No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS
Semiconductor Co., Ltd.
The content specified herein is subject to change for improvement without notice.
Examples of application circuits, circuit constants and any other information contained herein illustrate the
standard usage and operations of the Products. The peripheral conditions must be taken into account when
designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document. However, should you
incur any damage arising from any inaccuracy or misprint of such information, LAPIS Semiconductor shall bear
no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and examples of
application circuits for the Products. LAPIS Semiconductor does not grant you, explicitly or implicitly, any license
to use or exercise intellectual property or other rights held by LAPIS Semiconductor and other parties. LAPIS
Semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical
information.
The Products specified in this document are intended to be used with general-use electronic equipment or devices
(such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and
amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While LAPIS Semiconductor always makes efforts to enhance the quality and reliability of its Products, a Product
may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard against the possibility
of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating,
redundancy, fire control and fail-safe designs. LAPIS Semiconductor shall bear no responsibility whatsoever for
your use of any Product outside of the prescribed scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or system which requires an
extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or
create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery,
nuclear-reactor controller, fuel-controller or other safety device). LAPIS Semiconductor shall bear no
responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to
be used for any such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may be controlled under
the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
Copyright 2013-2015 LAPIS Semiconductor Co., Ltd.
2-4-8 Shinyokohama, Kouhoku-ku,
Yokohama 222-8575, Japan
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