Freescale MC68HC908GR8MP M68hc08 microcontroller Datasheet

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MC68HC908GR8
MC68HC908GR4
Technical Data
M68HC08
Microcontrollers
MC68HC908GR8/D
Rev. 4, 6/2002
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MC68HC908GR8
MC68HC908GR4
Technical Data — Rev 4.0
Motorola reserves the right to make changes without further notice to any products
herein. Motorola makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Motorola assume any
liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental
damages. "Typical" parameters which may be provided in Motorola data sheets and/or
specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including "Typicals" must be validated for
each customer application by customer’s technical experts. Motorola does not convey
any license under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Motorola product could create a
situation where personal injury or death may occur. Should Buyer purchase or use
Motorola products for any such unintended or unauthorized application, Buyer shall
indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of personal
injury or death associated with such unintended or unauthorized use, even if such claim
alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Motorola and
are registered trademarks of Motorola, Inc.
DigitalDNA is a trademark of Motorola, Inc.
MC68HC908GR8 — Rev 4.0
© Motorola, Inc., 2002
Technical Data
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MC68HC908GR8 — Rev 4.0
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Technical Data — MC68HC908GR8
List of Paragraphs
List of Paragraphs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
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Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Section 1. General Description . . . . . . . . . . . . . . . . . . . . 25
Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Section 3. Low Power Modes. . . . . . . . . . . . . . . . . . . . . . 49
Section 4. Resets and Interrupts . . . . . . . . . . . . . . . . . . . 61
Section 5. Analog-to-Digital Converter (ADC) . . . . . . . . 79
Section 6. Break Module (BRK) . . . . . . . . . . . . . . . . . . . . 91
Section 7. Clock Generator Module (CGMC) . . . . . . . . . 99
Section 8. Configuration Register (CONFIG) . . . . . . . . 129
Section 9. Computer Operating Properly (COP) . . . . . 133
Section 10. Central Processing Unit (CPU) . . . . . . . . . 139
Section 11. Flash Memory . . . . . . . . . . . . . . . . . . . . . . . 157
Section 12. External Interrupt (IRQ) . . . . . . . . . . . . . . . 167
Section 13. Keyboard Interrupt (KBI) . . . . . . . . . . . . . . 175
Section 14. Low-Voltage Inhibit (LVI) . . . . . . . . . . . . . . 183
Section 15. Monitor ROM (MON) . . . . . . . . . . . . . . . . . . 189
Section 16. Input/Output Ports (I/O) . . . . . . . . . . . . . . . 205
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Section 17. RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Section 18. Serial Communications Interface (SCI) . . . 231
Section 19. System Integration Module (SIM) . . . . . . . 271
Section 20. Serial Peripheral Interface (SPI). . . . . . . . . 297
Section 21. Timebase Module (TBM) . . . . . . . . . . . . . . . 329
Section 22. Timer Interface Module (TIM) . . . . . . . . . . . 335
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Section 23. Electrical Specifications. . . . . . . . . . . . . . . 361
Section 24. Mechanical Specifications . . . . . . . . . . . . . 387
Section 25. Ordering Information . . . . . . . . . . . . . . . . . 391
Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
Technical Data
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Table of Contents
List of Paragraphs
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Table of Contents
List of Tables
List of Figures
Section 1. General Description
1.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.4
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.5
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.6
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Section 2. Memory Map
2.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.3
Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . . 35
2.4
Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.5
Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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Section 3. Low Power Modes
3.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.3
Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . 50
3.4
Break Module (BRK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.5
Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.6
Clock Generator Module (CGM) . . . . . . . . . . . . . . . . . . . . . . . . 52
3.7
Computer Operating Properly Module (COP). . . . . . . . . . . . . . 52
3.8
External Interrupt Module (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . 53
3.9
Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . 53
3.10
Low-Voltage Inhibit Module (LVI) . . . . . . . . . . . . . . . . . . . . . . . 54
3.11
Serial Communications Interface Module (SCI) . . . . . . . . . . . . 54
3.12
Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . . 55
3.13
Timer Interface Module (TIM1 and TIM2) . . . . . . . . . . . . . . . . . 55
3.14
Timebase Module (TBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.15
Exiting Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.16
Exiting Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Section 4. Resets and Interrupts
4.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.3
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
4.4
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Section 5. Analog-to-Digital Converter (ADC)
5.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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5.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.5
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.6
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
5.7
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.8
I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
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Section 6. Break Module (BRK)
6.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.5
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
6.6
Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Section 7. Clock Generator Module (CGMC)
7.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.5
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
7.6
CGMC Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
7.7
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
7.8
Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
7.9
Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . .125
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Section 8. Configuration Register (CONFIG)
8.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
8.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
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Section 9. Computer Operating Properly (COP)
9.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
9.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
9.4
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
9.5
COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
9.6
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
9.7
Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
9.8
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
9.9
COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . .137
Section 10. Central Processing Unit (CPU)
10.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
10.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
10.4
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
10.5
Arithmetic/logic unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
10.6
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
10.7
CPU during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 146
10.8
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
10.9
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
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Section 11. Flash Memory
11.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
11.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
11.4
FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
11.5
FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . 160
11.6
FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . 161
11.7
FLASH Program/Read Operation . . . . . . . . . . . . . . . . . . . . . .162
11.8
FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
11.9
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
11.10 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Section 12. External Interrupt (IRQ)
12.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
12.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
12.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
12.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
12.5
IRQ1 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
12.6
IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .171
12.7
IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . 172
Section 13. Keyboard Interrupt (KBI)
13.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
13.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
13.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
13.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
13.5
Keyboard Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
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13.6
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
13.7
Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .180
13.8
I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
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Section 14. Low-Voltage Inhibit (LVI)
14.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
14.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
14.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
14.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
14.5
LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
14.6
LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
14.7
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
Section 15. Monitor ROM (MON)
15.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
15.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
15.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
15.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
15.5
Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Section 16. Input/Output Ports (I/O)
16.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
16.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
16.3
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
16.4
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
16.5
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
16.6
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
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16.7
Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Section 17. RAM
17.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
17.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
17.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
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Section 18. Serial Communications Interface (SCI)
18.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
18.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
18.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
18.4
Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
18.5
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
18.6
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
18.7
SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . . 251
18.8
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
18.9
I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Section 19. System Integration Module (SIM)
19.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
19.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
19.3
SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . 275
19.4
Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . 276
19.5
SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
19.6
Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
19.7
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290
19.8
SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
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Section 20. Serial Peripheral Interface (SPI)
20.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
20.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
20.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
20.4
Pin Name Conventions and I/O Register Addresses . . . . . . . 298
20.5
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
20.6
Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
20.7
Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . 309
20.8
Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
20.9
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
20.10 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
20.11 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317
20.12 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .318
20.13 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
20.14 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Section 21. Timebase Module (TBM)
21.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
21.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
21.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
21.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
21.5
Timebase Register Description. . . . . . . . . . . . . . . . . . . . . . . . 331
21.6
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
21.7
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
Section 22. Timer Interface Module (TIM)
22.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
Technical Data
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22.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
22.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
22.4
Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
22.5
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
22.6
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
22.7
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347
22.8
TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 348
22.9
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
22.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Section 23. Electrical Specifications
23.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
23.2
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .362
23.3
Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 363
23.4
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
23.5
5.0 V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . 364
23.6
3.0 V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . 366
23.7
5.0 V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
23.8
3.0 V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
23.9
Output High-Voltage Characteristics . . . . . . . . . . . . . . . . . . .370
23.10 Output Low-Voltage Characteristics . . . . . . . . . . . . . . . . . . . . 373
23.11 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
23.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
23.13 5.0 V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
23.14 3.0 V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
23.15 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . 383
MC68HC908GR8 — Rev 4.0
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23.16 Clock Generation Module Characteristics . . . . . . . . . . . . . . . 383
23.17 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
Freescale Semiconductor, Inc...
Section 24. Mechanical Specifications
24.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
24.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
24.3
32-Pin LQFP (Case #873A) . . . . . . . . . . . . . . . . . . . . . . . . . .388
24.4
28-Pin PDIP (Case #710) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
24.5
28-Pin SOIC (Case #751F). . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Section 25. Ordering Information
25.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
25.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
25.3
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
25.4
Development Tools. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Glossary
Revision History
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
Changes from Rev 3.0 published in February 2002 to Rev 4.0
published in June 2002. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
Changes from Rev 2.0 published in January 2002 to Rev 3.0 published in February 2002 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Changes from Rev 1.0 published in April 2001 to Rev 2.0 published in December 2001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Technical Data
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MC68HC908GR8 — Rev 4.0
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List of Tables
Table
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2-1
4-1
4-2
5-1
5-2
7-1
7-2
7-3
10-1
10-2
11-1
14-1
15-1
15-2
15-3
15-4
15-5
15-6
15-7
15-8
15-9
16-1
16-2
16-3
16-4
16-5
16-6
18-1
18-2
Title
Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Interrupt Source Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Mux Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Numeric Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
PRE 1 and PRE0 Programming . . . . . . . . . . . . . . . . . . . . . . . 117
VPR1 and VPR0 Programming . . . . . . . . . . . . . . . . . . . . . . . 117
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Examples of protect start address: . . . . . . . . . . . . . . . . . . . . . 166
LVIOUT Bit Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Monitor Mode Signal Requirements and Options . . . . . . . . . . 193
Mode Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Monitor Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . 197
READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . . . 199
WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . . . 199
IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . . . 200
IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . . 200
READSP (Read Stack Pointer) Command . . . . . . . . . . . . . . .201
RUN (Run User Program) Command . . . . . . . . . . . . . . . . . . . 201
Port Control Register Bits Summary. . . . . . . . . . . . . . . . . . . . 208
Port A Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Port B Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Port C Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Port D Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Port E Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Start Bit Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
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18-3
18-4
18-5
18-6
18-7
18-8
19-1
19-2
19-3
19-4
20-1
20-2
20-3
20-4
21-1
22-1
22-2
22-3
23-1
23-2
23-3
23-4
23-5
23-6
23-7
23-8
23-9
25-1
25-2
25-3
Data Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Stop Bit Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Character Format Selection . . . . . . . . . . . . . . . . . . . . . . . . . .255
SCI Baud Rate Prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
SCI Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
SCI Baud Rate Selection Examples . . . . . . . . . . . . . . . . . . . . 268
Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277
Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
SPI Master Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . 327
Timebase Rate Selection for OSC1 = 32.768 kHz . . . . . . . . . 331
Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
Mode, Edge, and Level Selection . . . . . . . . . . . . . . . . . . . . . .358
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .362
Functional Operation Range. . . . . . . . . . . . . . . . . . . . . . . . . . 363
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
5.0V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 364
3.0 V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . 366
5.0 V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
3.0 V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . 383
CGM Component Specifications. . . . . . . . . . . . . . . . . . . . . . . 383
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
Development Tool Kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Development Tool Components . . . . . . . . . . . . . . . . . . . . . . . 393
Technical Data
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List of Figures
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1-1
1-2
1-3
1-4
2-1
2-2
4-1
4-2
4-3
4-4
4-5
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4-8
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5-1
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5-3
5-4
6-1
6-2
6-3
6-4
6-5
6-6
6-7
7-1
7-2
7-3
Title
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
QFP Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DIP And SOIC Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . 31
Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . . 39
Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Power-On Reset Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . . . . 65
Interrupt Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . . . 68
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Interrupt Status Register 1 (INT1). . . . . . . . . . . . . . . . . . . . . . .76
Interrupt Status Register 2 (INT2). . . . . . . . . . . . . . . . . . . . . . .76
Interrupt Status Register 3 (INT3). . . . . . . . . . . . . . . . . . . . . . .77
ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
ADC Status and Control Register (ADSCR) . . . . . . . . . . . . . . . 85
ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
ADC Clock Register (ADCLK) . . . . . . . . . . . . . . . . . . . . . . . . . 88
Break Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 92
I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Break Status and Control Register (BRKSCR). . . . . . . . . . . . . 95
Break Address Register High (BRKH) . . . . . . . . . . . . . . . . . . . 96
Break Address Register Low (BRKL) . . . . . . . . . . . . . . . . . . . . 96
SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . . . 96
SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . . . 98
CGMC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
CGMC External Connections . . . . . . . . . . . . . . . . . . . . . . . . . 111
CGMC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 114
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7-4
7-5
7-6
7-7
7-8
7-9
7-10
8-1
8-2
9-1
9-2
10-1
10-2
10-3
10-4
10-5
10-6
11-1
11-2
11-3
11-4
12-1
12-2
12-3
13-1
13-2
13-3
13-4
14-1
14-2
14-3
15-1
15-2
15-3
15-4
15-5
15-6
15-7
PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . . . 115
PLL Bandwidth Control Register (PBWC) . . . . . . . . . . . . . . . 118
PLL Multiplier Select Register High (PMSH) . . . . . . . . . . . . . 119
PLL Multiplier Select Register Low (PMSL) . . . . . . . . . . . . . . 120
PLL VCO Range Select Register (PMRS) . . . . . . . . . . . . . . . 121
PLL Reference Divider Select Register (PMDS) . . . . . . . . . . 122
PLL Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . .130
Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . .130
COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
COP Control Register (COPCTL) . . . . . . . . . . . . . . . . . . . . . .136
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Index register (H:X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Stack pointer (SP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Program counter (PC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Condition code register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . 143
FLASH Control Register (FLCR) . . . . . . . . . . . . . . . . . . . . . . 159
FLASH Programming Flowchart . . . . . . . . . . . . . . . . . . . . . . . 164
FLASH Block Protect Register (FLBPR). . . . . . . . . . . . . . . . . 165
FLASH Block Protect Start Address . . . . . . . . . . . . . . . . . . . . 165
IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .169
IRQ I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 169
IRQ Status and Control Register (INTSCR) . . . . . . . . . . . . . . 172
Keyboard Module Block Diagram . . . . . . . . . . . . . . . . . . . . . .177
I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Keyboard Status and Control Register (INTKBSCR) . . . . . . . 181
Keyboard Interrupt Enable Register (INTKBIER) . . . . . . . . . . 182
LVI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
LVI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
LVI Status Register (LVISR) . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Monitor Mode Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Low-Voltage Monitor Mode Entry Flowchart. . . . . . . . . . . . . . 195
Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Break Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Stack Pointer at Monitor Mode Entry . . . . . . . . . . . . . . . . . . .202
Technical Data
20
MC68HC908GR8 — Rev 4.0
List of Figures
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List of Figures
Freescale Semiconductor, Inc...
15-8
16-1
16-2
16-3
16-4
16-5
16-6
16-7
16-8
16-9
16-10
16-11
16-12
16-13
16-14
16-15
16-16
16-17
16-18
16-19
18-1
18-2
18-3
18-4
18-5
18-6
18-7
18-8
18-9
18-10
18-11
18-12
18-13
18-14
18-15
18-16
19-1
19-2
Monitor Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 203
I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . .209
Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . . 210
Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Port A Input Pullup Enable Register (PTAPUE) . . . . . . . . . . . 212
Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . .213
Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . . 214
Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . . .216
Data Direction Register C (DDRC) . . . . . . . . . . . . . . . . . . . . . 217
Port C I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Port C Input Pullup Enable Register (PTCPUE) . . . . . . . . . . . 219
Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . .220
Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . . . . . 222
Port D I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Port D Input Pullup Enable Register (PTDPUE) . . . . . . . . . . . 224
Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . .225
Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . . . 226
Port E I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
SCI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 234
SCI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
SCI Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
SCI Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 242
Receiver Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
Slow Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Fast Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
SCI Control Register 1 (SCC1). . . . . . . . . . . . . . . . . . . . . . . . 253
SCI Control Register 2 (SCC2). . . . . . . . . . . . . . . . . . . . . . . . 256
SCI Control Register 3 (SCC3). . . . . . . . . . . . . . . . . . . . . . . . 258
SCI Status Register 1 (SCS1) . . . . . . . . . . . . . . . . . . . . . . . . 260
Flag Clearing Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
SCI Status Register 2 (SCS2) . . . . . . . . . . . . . . . . . . . . . . . . 264
SCI Data Register (SCDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
SCI Baud Rate Register (SCBR) . . . . . . . . . . . . . . . . . . . . . . 265
SIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
SIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 274
MC68HC908GR8 — Rev 4.0
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19-3
19-4
19-5
19-6
19-7
19-8
19-9
19-10
19-11
19-12
19-13
19-14
19-15
19-16
19-17
19-18
19-19
19-20
19-21
19-22
20-1
20-2
20-3
20-4
20-5
20-6
20-7
20-8
20-9
20-10
20-11
20-12
20-13
20-14
20-15
21-1
21-2
22-1
CGM Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Interrupt Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Interrupt Recovery Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . . 285
Interrupt Status Register 1 (INT1). . . . . . . . . . . . . . . . . . . . . .288
Interrupt Status Register 2 (INT2). . . . . . . . . . . . . . . . . . . . . .288
Interrupt Status Register 3 (INT3). . . . . . . . . . . . . . . . . . . . . .289
Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291
Wait Recovery from Interrupt or Break . . . . . . . . . . . . . . . . . . 291
Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . . 292
Stop Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
Stop Mode Recovery from Interrupt or Break . . . . . . . . . . . . . 293
SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . . 294
SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . . . 295
SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . . 296
SPI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
SPI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Full-Duplex Master-Slave Connections . . . . . . . . . . . . . . . . . 301
Transmission Format (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . 305
CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Transmission Format (CPHA = 1) . . . . . . . . . . . . . . . . . . . . . 306
Transmission Start Delay (Master) . . . . . . . . . . . . . . . . . . . . . 308
.SPRF/SPTE CPU Interrupt Timing . . . . . . . . . . . . . . . . . . . . 309
Missed Read of Overflow Condition . . . . . . . . . . . . . . . . . . . . 311
Clearing SPRF When OVRF Interrupt Is Not Enabled . . . . . . 312
SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . . . . 315
CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . . 322
SPI Status and Control Register (SPSCR) . . . . . . . . . . . . . . .325
SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Timebase Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Timebase Control Register (TBCR) . . . . . . . . . . . . . . . . . . . . 331
TIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Technical Data
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List of Figures
TIM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . 343
TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . . . 349
TIM Counter Registers High (TCNTH) . . . . . . . . . . . . . . . . . . 352
TIM Counter Registers Low (TCNTL) . . . . . . . . . . . . . . . . . . . 352
TIM Counter Modulo Register High (TMODH) . . . . . . . . . . . .353
TIM Counter Modulo Register Low (TMODL) . . . . . . . . . . . . . 353
TIM Counter Register High (TCNTH) . . . . . . . . . . . . . . . . . . . 354
TIM Counter Register Low (TCNTL). . . . . . . . . . . . . . . . . . . . 354
TIM Channel 0 Status and Control Register (TSC0) . . . . . . . 355
TIM Channel 1 Status and Control Register (TSC1) . . . . . . . 355
CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
TIM Channel 0 Register High (TCH0H) . . . . . . . . . . . . . . . . . 360
TIM Channel 0 Register Low (TCH0L) . . . . . . . . . . . . . . . . . . 360
TIM Channel 1 Register High (TCH1H) . . . . . . . . . . . . . . . . . 360
TIM Channel 1 Register Low (TCH1L) . . . . . . . . . . . . . . . . . . 360
Typical High-Side Driver Characteristics –
Port PTA3–PTA0 (VDD = 4.5 Vdc) . . . . . . . . . . . . . . . . . . . . . 370
23-2 Typical High-Side Driver Characteristics –
Port PTA3–PTA0 (VDD = 2.7 Vdc) . . . . . . . . . . . . . . . . . . . . . 370
23-3 Typical High-Side Driver Characteristics –
Port PTC1–PTC0 (VDD = 4.5 Vdc) . . . . . . . . . . . . . . . . . . . . . 371
23-4 Typical High-Side Driver Characteristics –
Port PTC1–PTC0 (VDD = 2.7 Vdc) . . . . . . . . . . . . . . . . . . . . . 371
23-5 Typical High-Side Driver Characteristics – Ports PTB5–PTB0,
PTD6–PTD0, and PTE1–PTE0 (VDD = 5.5 Vdc) . . . . . . . . . . 372
23-6 Typical High-Side Driver Characteristics – Ports PTB5–PTB0,
PTD6–PTD0, and PTE1–PTE0 (VDD = 2.7 Vdc) . . . . . . . . . . 372
23-7 Typical Low-Side Driver Characteristics –
Port PTA3–PTA0 (VDD = 5.5 Vdc) . . . . . . . . . . . . . . . . . . . . . 373
23-8 Typical Low-Side Driver Characteristics –
Port PTA3–PTA0 (VDD = 2.7 Vdc) . . . . . . . . . . . . . . . . . . . . . 373
23-9 Typical Low-Side Driver Characteristics –
Port PTC1–PTC0 (VDD = 4.5 Vdc) . . . . . . . . . . . . . . . . . . . . . 374
23-10 Typical Low-Side Driver Characteristics –
Port PTC1–PTC0 (VDD = 2.7 Vdc) . . . . . . . . . . . . . . . . . . . . . 374
23-11 Typical Low-Side Driver Characteristics – Ports PTB5–PTB0,
PTD6–PTD0, and PTE1–PTE0 (VDD = 5.5 Vdc) . . . . . . . . . . 375
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22-2
22-3
22-4
22-5
22-6
22-7
22-8
22-9
22-10
22-11
22-12
22-13
22-14
22-15
22-16
22-17
23-1
MC68HC908GR8 — Rev 4.0
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23-12 Typical Low-Side Driver Characteristics – Ports PTB5–PTB0,
PTD6–PTD0, and PTE1–PTE0 (VDD = 2.7 Vdc) . . . . . . . . . . 375
23-13 Typical Operating IDD, with All Modules Turned On
(–40 °C to 125 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .376
23-14 Typical Wait Mode IDD, with all Modules Disabled
(–40 °C to 125 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .376
23-15 Typical Stop Mode IDD, with all Modules Disabled
(–40 °C to 125 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377
23-16 SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381
23-17 SPI Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
Technical Data
24
MC68HC908GR8 — Rev 4.0
List of Figures
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Technical Data — MC68HC908GR8
Section 1. General Description
1.1 Contents
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.4
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.5
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.6
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.2 Introduction
The MC68HC908GR8 is a member of the low-cost, high-performance
M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the
family use the enhanced M68HC08 central processor unit (CPU08) and
are available with a variety of modules, memory sizes and types, and
package types.
This document also describes the MC68HC908GR4. The
MC68HC908GR4 is a device identical to the MC68HC908GR8 except
that it has less Flash memory. Only when there are differences from the
MC68HC908GR8 is the MC68HC908GR4 specifically mentioned in the
text.
MC68HC908GR8 — Rev 4.0
MOTOROLA
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General Description
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General Description
1.3 Features
For convenience, features have been organized to reflect:
•
Standard features of the MC68HC908GR8
•
Features of the CPU08
Freescale Semiconductor, Inc...
1.3.1 Standard Features of the MC68HC908GR8
•
High-performance M68HC08 architecture optimized for Ccompilers
•
Fully upward-compatible object code with M6805, M146805, and
M68HC05 Families
•
8-MHz internal bus frequency
•
FLASH program memory security(1)
•
On-chip programming firmware for use with host personal
computer which does not require high voltage for entry
•
In-system programming
•
System protection features:
– Optional computer operating properly (COP) reset
– Low-voltage detection with optional reset and selectable trip
points for 3.0 V and 5.0 V operation
– Illegal opcode detection with reset
– Illegal address detection with reset
•
Low-power design; fully static with stop and wait modes
•
Standard low-power modes of operation:
– Wait mode
– Stop mode
•
Master reset pin and power-on reset (POR)
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
Technical Data
26
MC68HC908GR8 — Rev 4.0
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General Description
Features
•
7680 bytes of on-chip FLASH memory on the MC68HC908GR8
and 4096 bytes of on-chip FLASH memory on the
MC68HC908GR4 with in-circuit programming capabilities of
FLASH program memory
•
384 bytes of on-chip random-access memory (RAM)
•
Serial peripheral interface module (SPI)
•
Serial communications interface module (SCI)
•
One 16-bit, 2-channel timer (TIM1) and one 16-bit, 1-channel
timer (TIM2) interface modules with selectable input capture,
output compare, and PWM capability on each channel
•
6-channel, 8-bit successive approximation analog-to-digital
converter (ADC)
•
BREAK module (BRK) to allow single breakpoint setting during incircuit debugging
•
Internal pullups on IRQ and RST to reduce customer system cost
•
Clock generator module with on-chip 32-kHz crystal compatible
PLL (phase-lock loop)
•
Up to 21 general-purpose input/output (I/O) pins, including:
– 19 shared-function I/O pins
– Up to two dedicated I/O pins, depending on package choice
•
Selectable pullups on inputs only on ports A, C, and D. Selection
is on an individual port bit basis. During output mode, pullups are
disengaged.
•
High current 10-mA sink/10-mA source capability on all port pins
•
Higher current 15-mA sink/source capability on PTC0–PTC1
•
Timebase module with clock prescaler circuitry for eight user
selectable periodic real-time interrupts with optional active clock
source during stop mode for periodic wakeup from stop using an
external 32-kHz crystal
•
Oscillator stop mode enable bit (OSCSTOPENB) in the CONFIG
register to allow user selection of having the oscillator enabled or
disabled during stop mode
MC68HC908GR8 — Rev 4.0
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General Description
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General Description
•
4-bit keyboard wakeup port
•
32-pin quad flat pack (QFP) or 28-pin plastic dual-in-line package
(DIP) or 28-pin small outline integrated circuit (SOIC)
•
Specific features of the MC68HC908GR8 in 28-pin DIP and 28-pin
SOIC are:
– Port B is only 4 bits: PTB0–PTB3; 4-channel ADC module
– No Port C bits
1.3.2 Features of the CPU08
Features of the CPU08 include:
•
Enhanced HC05 programming model
•
Extensive loop control functions
•
16 addressing modes (eight more than the HC05)
•
16-bit index register and stack pointer
•
Memory-to-memory data transfers
•
Fast 8 × 8 multiply instruction
•
Fast 16/8 divide instruction
•
Binary-coded decimal (BCD) instructions
•
Optimization for controller applications
•
Efficient C language support
1.4 MCU Block Diagram
Figure 1-1 shows the structure of the MC68HC908GR8.
Technical Data
28
MC68HC908GR8 — Rev 4.0
General Description
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ARITHMETIC/LOGIC
UNIT (ALU)
MC68HC908GR8 — Rev 4.0
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* IRQ
POWER
† Ports are software configurable with pullup device if input port.
‡ Higher current drive port pins
* Pin contains integrated pullup device
VDD
VSS
VDDA
VSSA
VSSAD / VREFL
8-BIT ANALOG-TO-DIGITAL
CONVERTER MODULE
SINGLE EXTERNAL IRQ
MODULE
VDDAD / VREFH
24 INTR SYSTEM INTEGRATION
MODULE
PHASE-LOCKED LOOP
32-kHz OSCILLATOR
CLOCK GENERATOR MODULE
* RST
CGMXFC
OSC1
OSC2
USER FLASH VECTOR SPACE — 36 BYTES
FLASH PROGRAMMING (BURN-IN) ROM — 544 BYTES
MONITOR ROM — 310 BYTES
USER RAM — 384 BYTES
MC68HC908GR8 USER FLASH — 7680 BYTES
MC68HC908GR4 USER FLASH — 4096BYTES
CONTROL AND STATUS REGISTERS — 64 BYTES
CPU
REGISTERS
M68HC08 CPU
MASK OPTION REGISTER2
MODULE
MASK OPTION REGISTER1
MODULE
MEMORY MAP
MODULE
DATA BUS SWITCH
MODULE
MONITOR MODULE
SERIAL PERIPHERAL
INTERFACE MODULE
COMPUTER OPERATING
PROPERLY MODULE
SERIAL COMMUNICATIONS
INTERFACE MODULE
1-CHANNEL TIMER INTERFACE
MODULE 2
2-CHANNEL TIMER INTERFACE
MODULE 1
4-BIT KEYBOARD
INTERRUPT MODULE
DUAL V. LOW-VOLTAGE INHIBIT
MODULE
SINGLE BRKPT BREAK
MODULE
PROGR. TIMEBASE
MODULE
INTERNAL BUS
PTC1–PTC0 † ‡
MONITOR MODE ENTRY
MODULE
SECURITY
MODULE
POWER-ON RESET
MODULE
PTE1/RxD
PTE0/TxD
PTB5/AD5–PTB0/AD0
PTD6/T2CH0 †
PTD5/T1CH1 †
PTD4/T1CH0 †
PTD3/SPSCK †
PTD2/MOSI †
PTD1/MISO †
PTD0/SS †
PTA3/KBD3–PTA0/KBD0 †
DDRA
DDRB
DDRC
DDRD
DDRE
PORTA
PORTB
PORTC
PORTD
MOTOROLA
PORTE
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General Description
MCU Block Diagram
Figure 1-1. MCU Block Diagram
Technical Data
29
Freescale Semiconductor, Inc.
General Description
OSC2
CGMXFC
VSSA
VDDA
PTC1
PTC0
PTA3/KBD3
30
29
28
27
26
25
1
24
PTA2/KBD2
VDDAD/VREFH
PTD1/MISO
6
19
PTB5/AD5
PTD2/MOSI
7
18
PTB4/AD4
PTD3/SPSCK
8
17
PTB3/AD3
16
20
PTB2/AD2
5
15
PTD0/SS
PTB1/AD1
VSSAD/VREFL
14
21
PTB0/AD0
4
13
IRQ
PTD6/T2CH0
PTA0/KBD0
12
22
PTD5/T1CH1
3
11
PTE1/RxD
PTD4/T1CH0
PTA1/KBD1
10
23
VDD
2
9
PTE0/TxD
VSS
Freescale Semiconductor, Inc...
RST
31
32 OSC1
1.5 Pin Assignments
NOTE: Ports PTB4, PTB5, PTC0, and PTC1 are available only with the QFP.
Figure 1-2. QFP Pin Assignments
Technical Data
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General Description
Pin Functions
CGMXFC
1
28
VSSA
OSC2
2
27
VDDA
OSC1
3
26
PTA3/KBD3
RST
4
25
PTA2/KBD2
PTE0/TxD
5
24
PTA1/KBD1
PTE1/RxD
6
23
PTA0/KBD0
IRQ
7
22
VSSAD/VREFL
PTD0/SS
8
21
VDDAD/VREFH
PTD1/MISO
9
20
PTB3/AD3
PTD2/MOSI
10
19
PTB2/AD2
PTD3/SPSCK
11
18
PTB1/AD1
VSS
12
17
PTB0/AD0
VDD
13
16
PTD6/T2CH0
PTD4/T1CH0
14
15
PTD5/T1CH1
NOTE: Ports PTB4, PTB5, PTC0, and PTC1 are available only with the QFP.
Figure 1-3. DIP And SOIC Pin Assignments
1.6 Pin Functions
Descriptions of the pin functions are provided here.
1.6.1 Power Supply Pins (VDD and VSS)
VDD and VSS are the power supply and ground pins. The MCU operates
from a single power supply.
Fast signal transitions on MCU pins place high, short-duration current
demands on the power supply. To prevent noise problems, take special
care to provide power supply bypassing at the MCU as Figure 1-4
shows. Place the C1 bypass capacitor as close to the MCU as possible.
Use a high-frequency-response ceramic capacitor for C1. C2 is an
optional bulk current bypass capacitor for use in applications that require
the port pins to source high current levels.
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General Description
MCU
VDD
VSS
C1
0.1 µF
+
C2
VDD
NOTE: Component values shown represent typical applications.
Figure 1-4. Power Supply Bypassing
1.6.2 Oscillator Pins (OSC1 and OSC2)
The OSC1 and OSC2 pins are the connections for the on-chip oscillator
circuit. See Clock Generator Module (CGMC).
1.6.3 External Reset Pin (RST)
A logic 0 on the RST pin forces the MCU to a known startup state. RST
is bidirectional, allowing a reset of the entire system. It is driven low when
any internal reset source is asserted. This pin contains an internal pullup
resistor that is always activated, even when the reset pin is pulled low.
See Resets and Interrupts.
1.6.4 External Interrupt Pin (IRQ)
IRQ is an asynchronous external interrupt pin. This pin contains an
internal pullup resistor that is always activated, even when the reset pin
is pulled low. See External Interrupt (IRQ).
1.6.5 CGM Power Supply Pins (VDDA and VSSA)
VDDA and VSSA are the power supply pins for the analog portion of the
clock generator module (CGM). Decoupling of these pins should be as
per the digital supply. See Clock Generator Module (CGMC).
Technical Data
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MC68HC908GR8 — Rev 4.0
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General Description
Pin Functions
1.6.6 External Filter Capacitor Pin (CGMXFC)
CGMXFC is an external filter capacitor connection for the CGM. See
Clock Generator Module (CGMC).
1.6.7 Analog Power Supply/Reference Pins (VDDAD/VREFH and VSSAD/VREFL)
VDDAD and VSSAD are the power supply pins for the analog-to-digital
converter. Decoupling of these pins should be as per the digital supply.
NOTE:
VREFH is the high reference supply for the ADC. The VREFH signal is
internally connected with VDDAD and have the same potential as VDDAD.
VDDAD should be tied to the same potential as VDD via separate traces.
VREFL is the low reference supply for the ADC. The VREFL pin is
internally connected with VSSAD and has the same potential as VSSAD.
VSSAD should be tied to the same potential as VSS via separate traces.
See Analog-to-Digital Converter (ADC).
1.6.8 Port A Input/Output (I/O) Pins (PTA3/KBD3–PTA0/KBD0)
PTA3–PTA0 are special-function, bidirectional I/O port pins. Any or all of
the port A pins can be programmed to serve as keyboard interrupt pins.
See Input/Output Ports (I/O) and External Interrupt (IRQ).
These port pins also have selectable pullups when configured for input
mode. The pullups are disengaged when configured for output mode.
The pullups are selectable on an individual port bit basis.
When the port pins are configured for special-function mode (KBI),
pullups will be automatically engaged. As long as the port pins are in
special-function mode, the pullups will always be on.
1.6.9 Port B I/O Pins (PTB5/AD5–PTB0/AD0)
PTB5–PTB0 are special-function, bidirectional I/O port pins that can also
be used for analog-to-digital converter (ADC) inputs. See Input/Output
Ports (I/O) and Analog-to-Digital Converter (ADC).
There are no pullups associated with this port.
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General Description
1.6.10 Port C I/O Pins (PTC1–PTC0)
PTC1–PTC0 are general-purpose, bidirectional I/O port pins. See
Input/Output Ports (I/O). PTC0 and PTC1 are only available on 32-pin
QFP packages.
These port pins also have selectable pullups when configured for input
mode. The pullups are disengaged when configured for output mode.
The pullups are selectable on an individual port bit basis.
1.6.11 Port D I/O Pins (PTD6/T2CH0–PTD0/SS)
PTD6–PTD0 are special-function, bidirectional I/O port pins.
PTD3–PTD0 can be programmed to be serial peripheral interface (SPI)
pins, while PTD6–PTD4 can be individually programmed to be timer
interface module (TIM1 and TIM2) pins. See Timer Interface Module
(TIM), Serial Peripheral Interface (SPI), and Input/Output Ports (I/O).
These port pins also have selectable pullups when configured for input
mode. The pullups are disengaged when configured for output mode.
The pullups are selectable on an individual port bit basis.
When the port pins are configured for special-function mode (SPI, TIM1,
TIM2), pullups can be selectable on an individual port pin basis.
1.6.12 Port E I/O Pins (PTE1/RxD–PTE0/TxD)
PTE1–PTE0 are special-function, bidirectional I/O port pins. These pins
can also be programmed to be serial communications interface (SCI)
pins. See Serial Communications Interface (SCI) and Input/Output Ports
(I/O).
NOTE:
Any unused inputs and I/O ports should be tied to an appropriate logic
level (either VDD or VSS). Although the I/O ports of the MC68HC908GR8
do not require termination, termination is recommended to reduce the
possibility of electro-static discharge damage.
Technical Data
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MC68HC908GR8 — Rev 4.0
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Technical Data — MC68HC908GR8
Section 2. Memory Map
2.1 Contents
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.3
Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . . 35
2.4
Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.5
Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.2 Introduction
The CPU08 can address 64K bytes of memory space. The memory
map, shown in Figure 2-1, includes:
•
8K bytes of FLASH memory, 7680 bytes of user space on the
MC68HC908GR8 or
4K bytes of FLASH memory, 4096 bytes of user space on the
MC68HC908GR4
•
384 bytes of random-access memory (RAM)
•
36 bytes of user-defined vectors
•
310 bytes of monitor routines in read-only memory (ROM)
•
544 bytes of integrated FLASH burn-in routines in ROM
2.3 Unimplemented Memory Locations
Accessing an unimplemented location can cause an illegal address
reset if illegal address resets are enabled. In the memory map (Figure 21) and in register figures in this document, unimplemented locations are
shaded.
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Memory Map
2.4 Reserved Memory Locations
Accessing a reserved location can have unpredictable effects on MCU
operation. In the Figure 2-1 and in register figures in this document,
reserved locations are marked with the word Reserved or with the letter
R.
2.5 Input/Output (I/O) Section
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Most of the control, status, and data registers are in the zero page area
of $0000–$003F. Additional I/O registers have these addresses:
•
$FE00; SIM break status register, SBSR
•
$FE01; SIM reset status register, SRSR
•
$FE03; SIM break flag control register, SBFCR
•
$FE09; interrupt status register 1, INT1
•
$FE0A; interrupt status register 2, INT2
•
$FE0B; interrupt status register 3, INT3
•
$FE07; reserved FLASH test control register, FLTCR
•
$FE08; FLASH control register, FLCR
•
$FE09; break address register high, BRKH
•
$FE0A; break address register low, BRKL
•
$FE0B; break status and control register, BRKSCR
•
$FE0C; LVI status register, LVISR
•
$FF7E; FLASH block protect register, FLBPR
Data registers are shown in Figure 2-2, and Table 2-1 is a list of vector
locations.
Technical Data
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Memory Map
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Memory Map
Input/Output (I/O) Section
$0000
I/O Registers
64 Bytes
↓
$003F
$0040
RAM
384 Bytes
↓
$01BF
$01C0
Unimplemented
6720 Bytes
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↓
$1BFF
$1C00
↓
Reserved for Integrated FLASH Burn-in Routines
544 Bytes
$1E1F
$1E20
Unimplemented
49,632 Bytes
↓
$DFFF
$E000
MC68HC908GR4
Unimplemented
3584 Bytes
↓
$EDFF
$EE00
MC68HC908GR8
FLASH Memory
7680 Bytes
MC68HC908GR4
FLASH Memory
4096 Bytes
↓
$FDFF
$FE00
SIM Break Status Register (SBSR)
$FE01
SIM Reset Status Register (SRSR)
$FE02
Reserved
$FE03
SIM Break Flag Control Register (SBFCR)
$FE09
Interrupt Status Register 1 (INT1)
$FE0A
Interrupt Status Register 2 (INT2)
$FE0B
Interrupt Status Register 3 (INT3)
$FE07
Reserved for FLASH Test Control Register (FLTCR)
Figure 2-1. Memory Map
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Memory Map
$FE08
FLASH Control Register (FLCR)
$FE09
Break Address Register High (BRKH)
$FE0A
Break Address Register Low (BRKL)
$FE0B
Break Status and Control Register (BRKSCR)
$FE0C
LVI Status Register (LVISR)
$FE0D
↓
Reserved
3 Bytes
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$FE0F
$FE10
↓
$FE1F
Unimplemented
16 Bytes
Reserved for Compatibility with Monitor Code
for A-Family Parts
$FE20
↓
Monitor ROM
310 Bytes
$FF55
$FF56
↓
Unimplemented
40 Bytes
$FF7D
$FF7E
FLASH Block Protect Register (FLBPR)
$FF7F
↓
Unimplemented
93 Bytes
$FFDB
Note: $FFF6–$FFFD
contains
8 security bytes
$FFDC
↓
FLASH Vectors
(36 Bytes inluding $FFFF)
$FFFE
$FFFF
Low byte of reset vector when read
COP Control Register (COPCTL)
Figure 2-1. Memory Map (Continued)
Technical Data
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Memory Map
Input/Output (I/O) Section
Addr.
Bit 7
6
5
4
Read:
Port A Data Register
Write:
(PTA)
Reset:
0
0
0
0
Read:
Port B Data Register
Write:
(PTB)
Reset:
0
Read:
Port C Data Register
Write:
(PTC)
Reset:
0
Read:
Port D Data Register
Write:
(PTD)
Reset:
0
Read:
Data Direction Register A
$0004
Write:
(DDRA)
Reset:
0
0
0
0
0
0
0
Read:
Data Direction Register B
$0005
Write:
(DDRB)
Reset:
0
0
0
Read:
Data Direction Register C
$0006
Write:
(DDRC)
Reset:
Read:
Data Direction Register D
$0007
Write:
(DDRD)
Reset:
0
$0000
$0001
$0002
$0003
$0008
Register Name
Read:
Port E Data Register
Write:
(PTE)
Reset:
3
2
1
Bit 0
PTA3
PTA2
PTA1
PTA0
PTB2
PTB1
PTB0
PTC1
PTC0
PTD2
PTD1
PTD0
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
0
0
0
0
0
0
0
DDRC1
DDRC0
0
0
0
0
0
0
0
0
DDRD6
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
DDRD0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PTE1
PTE0
0
0
Unaffected by reset
0
PTB5
PTB4
PTB3
Unaffected by reset
0
0
0
0
0
Unaffected by reset
PTD6
PTD5
PTD4
PTD3
Unaffected by reset
Unaffected by reset
Read:
$0009
Unimplemented Write:
Reset:
0
0
0
= Unimplemented
0
0
R = Reserved
0
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 8)
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Memory Map
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
Reset:
0
0
0
0
0
0
0
0
Read:
Data Direction Register E
$000C
Write:
(DDRE)
Reset:
0
0
0
0
0
0
DDRE1
DDRE0
0
0
0
0
0
0
0
0
Read:
Port A Input Pullup Enable
$000D
Write:
Register (PTAPUE)
Reset:
0
0
0
0
0
0
0
0
0
0
Read:
Port C Input Pullup Enable
$000E
Write:
Register (PTCPUE)
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
Read:
Port D Input Pullup Enable
$000F
Write:
Register (PTDPUE)
Reset:
0
Read:
Unimplemented Write:
$000A
Reset:
Read:
$000B
$0010
$0011
$0012
$0013
Unimplemented Write:
Read:
SPI Control Register
Write:
(SPCR)
Reset:
Read:
SPI Status and Control
Write:
Register (SPSCR)
Reset:
Read:
SPI Data Register
Write:
(SPDR)
Reset:
0
SPRIE
0
SPRF
PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
0
0
PTCPUE1 PTCPUE0
0
0
PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0
0
DMAS
0
ERRIE
0
0
0
0
0
0
SPMSTR
CPOL
CPHA
SPWOM
SPE
SPTIE
1
0
1
0
0
0
OVRF
MODF
SPTE
MODFEN
SPR1
SPR0
0
0
0
0
1
0
0
0
R7
R6
R5
R4
R3
R2
R1
R0
T7
T6
T5
T4
T3
T2
T1
T0
Read:
LOOPS
SCI Control Register 1
Write:
(SCC1)
Reset:
0
Unaffected by reset
ENSCI
TXINV
M
WAKE
ILTY
PEN
PTY
0
0
0
0
0
0
0
= Unimplemented
R = Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 8)
Technical Data
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Input/Output (I/O) Section
Addr.
Register Name
$0014
Read:
SCI Control Register 2
Write:
(SCC2)
Reset:
$0015
$0016
$0017
$001A
6
5
4
3
2
1
Bit 0
SCTIE
TCIE
SCRIE
ILIE
TE
RE
RWU
SBK
0
0
0
0
0
0
0
0
T8
DMARE
DMATE
ORIE
NEIE
FEIE
PEIE
Read:
SCI Control Register 3
Write:
(SCC3)
Reset:
R8
U
U
0
0
0
0
0
0
Read:
SCI Status Register 1
Write:
(SCS1)
Reset:
SCTE
TC
SCRF
IDLE
OR
NF
FE
PE
1
1
0
0
0
0
0
0
BKF
RPF
Read:
SCI Status Register 2
Write:
(SCS2)
Reset:
Read:
SCI Data Register
Write:
(SCDR)
Reset:
$0018
$0019
Bit 7
Read:
SCI Baud Rate Register
Write:
(SCBR)
Reset:
Read:
Keyboard Status
and Control Register Write:
(INTKBSCR)
Reset:
0
0
0
0
0
0
0
0
R7
R6
R5
R4
R3
R2
R1
R0
T7
T6
T5
T4
T3
T2
T1
T0
Unaffected by reset
SCP1
SCP0
R
SCR2
SCR1
SCR0
0
0
IMASKK
MODEK
0
0
0
0
0
0
0
0
0
0
KEYF
0
ACKK
0
0
0
0
Read:
Keyboard Interrupt Enable
$001B
Write:
Register (INTKBIER)
Reset:
Read:
Time Base Module Control
$001C
Write:
Register (TBCR)
Reset:
$001D
Read:
IRQ Status and Control
Write:
Register (INTSCR)
Reset:
TBIF
0
0
0
0
KBIE3
KBIE2
KBIE1
KBIE0
0
0
0
0
TBIE
TBON
R
0
0
IMASK1
MODE1
0
0
0
TBR2
TBR1
TBR0
0
0
0
0
0
0
0
0
0
0
IRQF1
0
TACK
ACK1
0
0
0
= Unimplemented
0
0
R = Reserved
0
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 8)
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Addr.
$001E
$001F
Register Name
Bit 7
6
5
4
3
2
Read:
Configuration Register 2
(CONFIG2)† Write:
0
0
0
0
0
0
Reset:
0
0
0
0
0
0
0
0
SSREC
STOP
COPD
0
0
0
PS2
PS1
PS0
Read:
COPRS
Configuration Register 1
Write:
(CONFIG1)†
Reset:
0
LVISTOP LVIRSTD LVIPWRD LVI5OR3†
0
0
TOIE
TSTOP
0
0
0
0
1
Bit 0
OSCSCIBDSTOPENB
SRC
Read:
Timer 1 Status and Control
$0020
Write:
Register (T1SC)
Reset:
TOF
0
0
1
0
0
0
0
0
Read:
Timer 1 Counter Register
$0021
Write:
High (T1CNTH)
Reset:
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
Read:
Timer 1 Counter Register
$0022
Write:
Low (T1CNTL)
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
1
1
1
1
1
1
1
1
Bit 7
6
5
4
3
2
1
Bit 0
1
1
1
1
1
1
1
1
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
Read:
Timer 1 Counter Modulo
$0023
Write:
Register High (T1MODH)
Reset:
$0024
Read:
Timer 1 Counter Modulo
Write:
Register Low (T1MODL)
Reset:
Read:
Timer 1 Channel 0 Status
$0025
and Control Register Write:
(T1SC0)
Reset:
$0026
$0027
Read:
Timer 1 Channel 0
Write:
Register High (T1CH0H)
Reset:
Read:
Timer 1 Channel 0
Write:
Register Low (T1CH0L)
Reset:
0
CH0F
0
TRST
Indeterminate after reset
Bit 7
6
5
4
3
Indeterminate after reset
† One-time writeable register after each reset, except LVI5OR3 bit. LVI5OR3 bit is only reset via POR (power-on reset).
= Unimplemented
R = Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 8)
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Addr.
Register Name
Bit 7
Read:
Timer 1 Channel 1 Status
$0028
and Control Register Write:
(T1SC1)
Reset:
CH1F
$0029
$002A
Read:
Timer 1 Channel 1
Write:
Register High (T1CH1H)
Reset:
Read:
Timer 1 Channel 1
Write:
Register Low (T1CH1L)
Reset:
0
6
CH1IE
5
0
4
3
2
1
Bit 0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
PS2
PS1
PS0
Indeterminate after reset
Bit 7
6
5
4
3
Indeterminate after reset
Read:
Timer 2 Status and Control
$002B
Write:
Register (T2SC)
Reset:
TOF
0
0
TOIE
TSTOP
0
0
1
0
0
0
0
0
Read:
Timer 2 Counter Register
$002C
Write:
High (T2CNTH)
Reset:
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
Read:
Timer 2 Counter Register
$002D
Write:
Low (T2CNTL)
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
1
1
1
1
1
1
1
1
Bit 7
6
5
4
3
2
1
Bit 0
1
1
1
1
1
1
1
1
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
Read:
Timer 2 Counter Modulo
$002E
Write:
Register High (T2MODH)
Reset:
$002F
Read:
Timer 2 Counter Modulo
Write:
Register Low (T2MODL)
Reset:
Read:
Timer 2 Channel 0 Status
$0030
and Control Register Write:
(T2SC0)
Reset:
$0031
Read:
Timer 2 Channel 0
Write:
Register High (T2CH0H)
Reset:
0
CH0F
0
TRST
Indeterminate after reset
= Unimplemented
R = Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 8)
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Addr.
$0032
Register Name
Read:
Timer 2 Channel 0
Write:
Register Low (T2CH0L)
Reset:
Unimplemented
$0033
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
Indeterminate after reset
Read:
Write:
Reset:
0
0
0
0
0
Read:
$0034
Unimplemented Write:
Reset:
Indeterminate after reset
Read:
$0035
Unimplemented Write:
Reset:
$0036
$0037
Read:
PLL Control Register
Write:
(PCTL)
Reset:
Read:
PLL Bandwidth Control
Write:
Register (PBWC)
Reset:
Read:
PLL Multiplier Select High
$0038
Write:
Register (PMSH)
Reset:
Read:
PLL Multiplier Select Low
$0039
Write:
Register (PMSL)
Reset:
$003A
$003B
Read:
PLL VCO Select Range
Write:
Register (PMRS)
Reset:
Read:
PLL Reference Divider
Write:
Select Register (PMDS)
Reset:
Indeterminate after reset
PLLIE
0
AUTO
PLLF
0
LOCK
PLLON
BCS
PRE1
PRE0
VPR1
VPR0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
MUL11
MUL10
MUL9
MUL8
ACQ
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MUL7
MUL6
MUL5
MUL4
MUL3
MUL2
MUL1
MUL0
0
1
0
0
0
0
0
0
VRS7
VRS6
VRS5
VRS4
VRS3
VRS2
VRS1
VRS0
0
1
0
0
0
0
0
0
0
0
0
0
RDS3
RDS2
RDS1
RDS0
0
0
0
0
0
0
0
1
= Unimplemented
R = Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 8)
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Addr.
$003C
$003D
$003E
Register Name
Bit 7
Read:
Analog-to-Digital Status
and Control Register Write:
(ADSCR)
Reset:
Read:
Analog-to-Digital Data
Write:
Register (ADR)
Reset:
Read:
Analog-to-Digital Input
Write:
Clock Register (ADCLK)
Reset:
6
5
4
3
2
1
Bit 0
AIEN
ADCO
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
0
0
0
1
1
1
1
1
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
R
R
R
R
R
R
R
R
0
0
0
0
R
R
R
R
0
0
COCO
R
Indeterminate after reset
ADIV2
ADIV1
ADIV0
ADICLK
0
0
0
0
0
0
R
R
R
R
R
R
0
0
0
0
0
0
0
0
POR
PIN
COP
ILOP
ILAD
MODRST
LVI
0
1
0
0
0
0
0
0
0
BCFE
R
R
R
R
R
R
R
Read:
$003F
Unimplemented Write:
Reset:
Read:
SIM Break Status Register
$FE00
Write:
(SBSR)
Reset:
SBSW
NOTE
R
Note: Writing a logic 0 clears SBSW.
Read:
SIM Reset Status Register
$FE01
Write:
(SRSR)
POR:
Read:
$FE02
Unimplemented Write:
Reset:
$FE03
Read:
SIM Break Flag Control
Write:
Register (SBFCR)
Reset:
0
Read:
Interrupt Status Register 1
$FE09
Write:
(INT1)
Reset:
IF6
IF5
IF4
IF3
IF2
IF1
0
0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Read:
Interrupt Status Register 2
$FE0A
Write:
(INT2)
Reset:
IF14
IF13
IF12
IF11
IF10
IF9
IF8
IF7
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
= Unimplemented
R = Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 8)
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Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Interrupt Status Register 3
$FE0B
Write:
(INT3)
Reset:
0
0
0
0
0
0
IF16
IF15
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
HVEN
MASS
ERASE
PGM
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
BRKE
BRKA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BPR7
BPR6
BPR5
BPR4
BPR3
BPR2
BPR1
BPR0
U
U
U
U
U
U
U
U
$FE07
$FE08
$FE09
$FE0A
Read:
FLASH Test Control
Write:
Register (FLTCR)
Reset:
Read:
FLASH Control Register
Write:
(FLCR)
Reset:
Read:
Break Address Register
Write:
High (BRKH)
Reset:
Read:
Break Address Register
Write:
Low (BRKL)
Reset:
Read:
Break Status and Control
$FE0B
Write:
Register (BRKSCR)
Reset:
$FE0C
$FF7E
$FFFF
Read: LVIOUT
LVI Status Register
Write:
(LVISR)
Reset:
0
Read:
FLASH Block Protect
Write:
Register (FLBPR)†
Reset:
Read:
COP Control Register
Write:
(COPCTL)
Reset:
Low byte of reset vector
Writing clears COP counter (any value)
Unaffected by reset
† Non-volatile FLASH register
= Unimplemented
R = Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 8)
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.
Table 2-1. Vector Addresses
Vector Priority
Lowest
Vector
IF16
IF15
IF14
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IF13
IF12
IF11
IF10
IF9
IF8
IF7
IF6
IF5
IF4
IF3
IF2
IF1
—
Highest
—
Address
Vector
$FFDC
Timebase Vector (High)
$FFDD
Timebase Vector (Low)
$FFDE
ADC Conversion Complete Vector (High)
$FFDF
ADC Conversion Complete Vector (Low)
$FFE0
Keyboard Vector (High)
$FFE1
Keyboard Vector (Low)
$FFE2
SCI Transmit Vector (High)
$FFE3
SCI Transmit Vector (Low)
$FFE4
SCI Receive Vector (High)
$FFE5
SCI Receive Vector (Low)
$FFE6
SCI Error Vector (High)
$FFE7
SCI Error Vector (Low)
$FFE8
SPI Transmit Vector (High)
$FFE9
SPI Transmit Vector (Low)
$FFEA
SPI Receive Vector (High)
$FFEB
SPI Receive Vector (Low)
$FFEC
TIM2 Overflow Vector (High)
$FFED
TIM2 Overflow Vector (Low)
$FFEE
Reserved
$FFEF
Reserved
$FFF0
TIM2 Channel 0 Vector (High)
$FFF1
TIM2 Channel 0 Vector (Low)
$FFF2
TIM1 Overflow Vector (High)
$FFF3
TIM1 Overflow Vector (Low)
$FFF4
TIM1 Channel 1 Vector (High)
$FFF5
TIM1 Channel 1 Vector (Low)
$FFF6
TIM1 Channel 0 Vector (High)
$FFF7
TIM1 Channel 0 Vector (Low)
$FFF8
PLL Vector (High)
$FFF9
PLL Vector (Low)
$FFFA
IRQ Vector (High)
$FFFB
IRQ Vector (Low)
$FFFC
SWI Vector (High)
$FFFD
SWI Vector (Low)
$FFFE
Reset Vector (High)
$FFFF
Reset Vector (Low)
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Section 3. Low Power Modes
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3.1 Contents
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.3
Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . 50
3.4
Break Module (BRK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.5
Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.6
Clock Generator Module (CGM) . . . . . . . . . . . . . . . . . . . . . . . . 52
3.7
Computer Operating Properly Module (COP). . . . . . . . . . . . . . 52
3.8
External Interrupt Module (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . 53
3.9
Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . 53
3.10
Low-Voltage Inhibit Module (LVI) . . . . . . . . . . . . . . . . . . . . . . . 54
3.11
Serial Communications Interface Module (SCI) . . . . . . . . . . . . 54
3.12
Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . . 55
3.13
Timer Interface Module (TIM1 and TIM2) . . . . . . . . . . . . . . . . . 55
3.14
Timebase Module (TBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.15
Exiting Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.16
Exiting Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.2 Introduction
The MCU may enter two low-power modes: wait mode and stop mode.
They are common to all HC08 MCUs and are entered through instruction
execution. This section describes how each module acts in the lowpower modes.
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3.2.1 Wait Mode
The WAIT instruction puts the MCU in a low-power standby mode in
which the CPU clock is disabled but the bus clock continues to run.
Power consumption can be further reduced by disabling the LVI module
and/or the timebase module through bits in the CONFIG register. (See
Configuration Register (CONFIG).)
3.2.2 Stop Mode
Stop mode is entered when a STOP instruction is executed. The CPU
clock is disabled and the bus clock is disabled if the OSCSTOPENB bit
in the CONFIG register is at a logic 0. (See Configuration Register
(CONFIG).)
3.3 Analog-to-Digital Converter (ADC)
3.3.1 Wait Mode
The ADC continues normal operation during wait mode. Any enabled
CPU interrupt request from the ADC can bring the MCU out of wait
mode. If the ADC is not required to bring the MCU out of wait mode,
power down the ADC by setting ADCH4–ADCH0 bits in the ADC status
and control register before executing the WAIT instruction.
3.3.2 Stop Mode
The ADC module is inactive after the execution of a STOP instruction.
Any pending conversion is aborted. ADC conversions resume when the
MCU exits stop mode after an external interrupt. Allow one conversion
cycle to stabilize the analog circuitry.
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Break Module (BRK)
3.4 Break Module (BRK)
3.4.1 Wait Mode
If enabled, the break module is active in wait mode. In the break routine,
the user can subtract one from the return address on the stack if the BW
bit in the break status register is set.
3.4.2 Stop Mode
The break module is inactive in stop mode. A break interrupt causes exit
from stop mode and sets the BW bit in the break status register. The
STOP instruction does not affect break module register states.
3.5 Central Processor Unit (CPU)
3.5.1 Wait Mode
The WAIT instruction:
•
Clears the interrupt mask (I bit) in the condition code register,
enabling interrupts. After exit from wait mode by interrupt, the I bit
remains clear. After exit by reset, the I bit is set.
•
Disables the CPU clock
3.5.2 Stop Mode
The STOP instruction:
•
Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from stop mode by external
interrupt, the I bit remains clear. After exit by reset, the I bit is set.
•
Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.
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3.6 Clock Generator Module (CGM)
3.6.1 Wait Mode
The CGM remains active in wait mode. Before entering wait mode,
software can disengage and turn off the PLL by clearing the BCS and
PLLON bits in the PLL control register (PCTL). Less power-sensitive
applications can disengage the PLL without turning it off. Applications
that require the PLL to wake the MCU from wait mode also can deselect
the PLL output without turning off the PLL.
3.6.2 Stop Mode
If the OSCSTOPEN bit in the CONFIG register is cleared (default), then
the STOP instruction disables the CGM (oscillator and phase-locked
loop) and holds low all CGM outputs (CGMXCLK, CGMOUT, and
CGMINT).
If the STOP instruction is executed with the VCO clock, CGMVCLK,
divided by two driving CGMOUT, the PLL automatically clears the BCS
bit in the PLL control register (PCTL), thereby selecting the crystal clock,
CGMXCLK, divided by two as the source of CGMOUT. When the MCU
recovers from STOP, the crystal clock divided by two drives CGMOUT
and BCS remains clear.
If the OSCSTOPEN bit in the CONFIG register is set, then the phase
locked loop is shut off, but the oscillator will continue to operate in stop
mode.
3.7 Computer Operating Properly Module (COP)
3.7.1 Wait Mode
The COP remains active in wait mode. To prevent a COP reset during
wait mode, periodically clear the COP counter in a CPU interrupt routine
or a DMA service routine.
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External Interrupt Module (IRQ)
3.7.2 Stop Mode
Stop mode turns off the CGMXCLK input to the COP and clears the COP
prescaler. Service the COP immediately before entering or after exiting
stop mode to ensure a full COP timeout period after entering or exiting
stop mode.
The STOP bit in the configuration register (CONFIG) enables the STOP
instruction. To prevent inadvertently turning off the COP with a STOP
instruction, disable the STOP instruction by clearing the STOP bit.
3.8 External Interrupt Module (IRQ)
3.8.1 Wait Mode
The IRQ module remains active in wait mode. Clearing the IMASK1 bit
in the IRQ status and control register enables IRQ CPU interrupt
requests to bring the MCU out of wait mode.
3.8.2 Stop Mode
The IRQ module remains active in stop mode. Clearing the IMASK1 bit
in the IRQ status and control register enables IRQ CPU interrupt
requests to bring the MCU out of stop mode.
3.9 Keyboard Interrupt Module (KBI)
3.9.1 Wait Mode
The keyboard module remains active in wait mode. Clearing the
IMASKK bit in the keyboard status and control register enables keyboard
interrupt requests to bring the MCU out of wait mode.
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3.9.2 Stop Mode
The keyboard module remains active in stop mode. Clearing the
IMASKK bit in the keyboard status and control register enables keyboard
interrupt requests to bring the MCU out of stop mode.
3.10 Low-Voltage Inhibit Module (LVI)
3.10.1 Wait Mode
If enabled, the LVI module remains active in wait mode. If enabled to
generate resets, the LVI module can generate a reset and bring the MCU
out of wait mode.
3.10.2 Stop Mode
If enabled, the LVI module remains active in stop mode. If enabled to
generate resets, the LVI module can generate a reset and bring the MCU
out of stop mode.
3.11 Serial Communications Interface Module (SCI)
3.11.1 Wait Mode
The SCI module remains active in wait mode. Any enabled CPU
interrupt request from the SCI module can bring the MCU out of wait
mode.
If SCI module functions are not required during wait mode, reduce power
consumption by disabling the module before executing the WAIT
instruction.
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Serial Peripheral Interface Module (SPI)
3.11.2 Stop Mode
The SCI module is inactive in stop mode. The STOP instruction does not
affect SCI register states. SCI module operation resumes after the MCU
exits stop mode.
Because the internal clock is inactive during stop mode, entering stop
mode during an SCI transmission or reception results in invalid data.
3.12 Serial Peripheral Interface Module (SPI)
3.12.1 Wait Mode
The SPI module remains active in wait mode. Any enabled CPU interrupt
request from the SPI module can bring the MCU out of wait mode.
If SPI module functions are not required during wait mode, reduce power
consumption by disabling the SPI module before executing the WAIT
instruction.
3.12.2 Stop Mode
The SPI module is inactive in stop mode. The STOP instruction does not
affect SPI register states. SPI operation resumes after an external
interrupt. If stop mode is exited by reset, any transfer in progress is
aborted, and the SPI is reset.
3.13 Timer Interface Module (TIM1 and TIM2)
3.13.1 Wait Mode
The TIM remains active in wait mode. Any enabled CPU interrupt
request from the TIM can bring the MCU out of wait mode.
If TIM functions are not required during wait mode, reduce power
consumption by stopping the TIM before executing the WAIT instruction.
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3.13.2 Stop Mode
The TIM is inactive in stop mode. The STOP instruction does not affect
register states or the state of the TIM counter. TIM operation resumes
when the MCU exits stop mode after an external interrupt.
3.14 Timebase Module (TBM)
3.14.1 Wait Mode
The timebase module remains active after execution of the WAIT
instruction. In wait mode, the timebase register is not accessible by the
CPU.
If the timebase functions are not required during wait mode, reduce the
power consumption by stopping the timebase before enabling the WAIT
instruction.
3.14.2 Stop Mode
The timebase module may remain active after execution of the STOP
instruction if the oscillator has been enabled to operate during stop mode
through the OSCSTOPEN bit in the CONFIG register. The timebase
module can be used in this mode to generate a periodic wakeup from
stop mode.
If the oscillator has not been enabled to operate in stop mode, the
timebase module will not be active during stop mode. In stop mode, the
timebase register is not accessible by the CPU.
If the timebase functions are not required during stop mode, reduce the
power consumption by stopping the timebase before enabling the STOP
instruction.
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Exiting Wait Mode
3.15 Exiting Wait Mode
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These events restart the CPU clock and load the program counter with
the reset vector or with an interrupt vector:
•
External reset — A logic 0 on the RST pin resets the MCU and
loads the program counter with the contents of locations $FFFE
and $FFFF.
•
External interrupt — A high-to-low transition on an external
interrupt pin (IRQ pin) loads the program counter with the contents
of locations: $FFFA and $FFFB; IRQ pin.
•
Break interrupt — A break interrupt loads the program counter
with the contents of $FFFC and $FFFD.
•
Computer operating properly module (COP) reset — A timeout of
the COP counter resets the MCU and loads the program counter
with the contents of $FFFE and $FFFF.
•
Low-voltage inhibit module (LVI) reset — A power supply voltage
below the Vtripf voltage resets the MCU and loads the program
counter with the contents of locations $FFFE and $FFFF.
•
Clock generator module (CGM) interrupt — A CPU interrupt
request from the phase-locked loop (PLL) loads the program
counter with the contents of $FFF8 and $FFF9.
•
Keyboard module (KBI) interrupt — A CPU interrupt request from
the KBI module loads the program counter with the contents of
$FFDE and $FFDF.
•
Timer 1 interface module (TIM1) interrupt — A CPU interrupt
request from the TIM1 loads the program counter with the
contents of:
– $FFF2 and $FFF3; TIM1 overflow
– $FFF4 and $FFF5; TIM1 channel 1
– $FFF6 and $FFF7; TIM1 channel 0
•
Timer 2 interface module (TIM2) interrupt — A CPU interrupt
request from the TIM2 loads the program counter with the
contents of:
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– $FFEC and $FFED; TIM2 overflow
– $FFF0 and $FFF1; TIM2 channel 0
•
Serial peripheral interface module (SPI) interrupt — A CPU
interrupt request from the SPI loads the program counter with the
contents of:
– $FFE8 and $FFE9; SPI transmitter
– $FFEA and $FFEB; SPI receiver
•
Serial communications interface module (SCI) interrupt — A CPU
interrupt request from the SCI loads the program counter with the
contents of:
– $FFE2 and $FFE3; SCI transmitter
– $FFE4 and $FFE5; SCI receiver
– $FFE6 and $FFE7; SCI receiver error
•
Analog-to-digital converter module (ADC) interrupt — A CPU
interrupt request from the ADC loads the program counter with the
contents of: $FFDE and $FFDF; ADC conversion complete.
•
Timebase module (TBM) interrupt — A CPU interrupt request from
the TBM loads the program counter with the contents of: $FFDC
and $FFDD; TBM interrupt.
3.16 Exiting Stop Mode
These events restart the system clocks and load the program counter
with the reset vector or with an interrupt vector:
•
External reset — A logic 0 on the RST pin resets the MCU and
loads the program counter with the contents of locations $FFFE
and $FFFF.
•
External interrupt — A high-to-low transition on an external
interrupt pin loads the program counter with the contents of
locations:
– $FFFA and $FFFB; IRQ pin
– $FFDE and $FFDF; keyboard interrupt pins
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•
Low-voltage inhibit (LVI) reset — A power supply voltage below
the LVItripf voltage resets the MCU and loads the program counter
with the contents of locations $FFFE and $FFFF.
•
Break interrupt — A break interrupt loads the program counter
with the contents of locations $FFFC and $FFFD.
•
Timebase module (TBM) interrupt — A TBM interrupt loads the
program counter with the contents of locations $FFDC and $FFDD
when the timebase counter has rolled over. This allows the TBM
to generate a periodic wakeup from stop mode.
Upon exit from stop mode, the system clocks begin running after an
oscillator stabilization delay. A 12-bit stop recovery counter inhibits the
system clocks for 4096 CGMXCLK cycles after the reset or external
interrupt.
The short stop recovery bit, SSREC, in the configuration register
controls the oscillator stabilization delay during stop recovery. Setting
SSREC reduces stop recovery time from 4096 CGMXCLK cycles to 32
CGMXCLK cycles.
NOTE:
Use the full stop recovery time (SSREC = 0) in applications that use an
external crystal.
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Technical Data — MC68HC908GR8
Section 4. Resets and Interrupts
4.1 Contents
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.3
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
4.4
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.2 Introduction
Resets and interrupts are responses to exceptional events during
program execution. A reset re-initializes the MCU to its startup condition.
An interrupt vectors the program counter to a service routine.
4.3 Resets
A reset immediately returns the MCU to a known startup condition and
begins program execution from a user-defined memory location.
4.3.1 Effects
A reset:
•
Immediately stops the operation of the instruction being executed
•
Initializes certain control and status bits
•
Loads the program counter with a user-defined reset vector
address from locations $FFFE and $FFFF
•
Selects CGMXCLK divided by four as the bus clock
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4.3.2 External Reset
A logic 0 applied to the RST pin for a time, tIRL, generates an external
reset. An external reset sets the PIN bit in the SIM reset status register.
4.3.3 Internal Reset
Sources:
•
Power-on reset (POR)
•
Computer operating properly (COP)
•
Low-power reset circuits
•
Illegal opcode
•
Illegal address
All internal reset sources pull the RST pin low for 32 CGMXCLK cycles
to allow resetting of external devices. The MCU is held in reset for an
additional 32 CGMXCLK cycles after releasing the RST pin.
PULLED LOW BY MCU
RST PIN
32 CYCLES
32 CYCLES
CGMXCLK
INTERNAL
RESET
Figure 4-1. Internal Reset Timing
4.3.3.1 Power-On Reset
A power-on reset is an internal reset caused by a positive transition on
the VDD pin. VDD at the POR must go completely to 0 V to reset the MCU.
This distinguishes between a reset and a POR. The POR is not a brownout detector, low-voltage detector, or glitch detector.
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Resets
A power-on reset:
•
Holds the clocks to the CPU and modules inactive for an oscillator
stabilization delay of 4096 CGMXCLK cycles
•
Drives the RST pin low during the oscillator stabilization delay
•
Releases the RST pin 32 CGMXCLK cycles after the oscillator
stabilization delay
•
Releases the CPU to begin the reset vector sequence 64
CGMXCLK cycles after the oscillator stabilization delay
•
Sets the POR bit in the SIM reset status register and clears all
other bits in the register
OSC1
PORRST(1)
4096
CYCLES
32
CYCLES
32
CYCLES
CGMXCLK
CGMOUT
RST PIN
INTERNAL
RESET
1. PORRST is an internally generated power-on reset pulse.
Figure 4-2. Power-On Reset Recovery
4.3.3.2 COP Reset
A COP reset is an internal reset caused by an overflow of the COP
counter. A COP reset sets the COP bit in the system integration module
(SIM) reset status register.
To clear the COP counter and prevent a COP reset, write any value to
the COP control register at location $FFFF.
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4.3.3.3 Low-Voltage Inhibit Reset
A low-voltage inhibit (LVI) reset is an internal reset caused by a drop in
the power supply voltage to the LVI trip voltage, VTRIPF.
An LVI reset:
•
Holds the clocks to the CPU and modules inactive for an oscillator
stabilization delay of 4096 CGMXCLK cycles after the power
supply voltage rises to VTRIPF
•
Drives the RST pin low for as long as VDD is below VTRIPF and
during the oscillator stabilization delay
•
Releases the RST pin 32 CGMXCLK cycles after the oscillator
stabilization delay
•
Releases the CPU to begin the reset vector sequence
64 CGMXCLK cycles after the oscillator stabilization delay
•
Sets the LVI bit in the SIM reset status register
4.3.3.4 Illegal Opcode Reset
An illegal opcode reset is an internal reset caused by an opcode that is
not in the instruction set. An illegal opcode reset sets the ILOP bit in the
SIM reset status register.
If the stop enable bit, STOP, in the mask option register is a logic 0, the
STOP instruction causes an illegal opcode reset.
4.3.3.5 Illegal Address Reset
An illegal address reset is an internal reset caused by opcode fetch from
an unmapped address. An illegal address reset sets the ILAD bit in the
SIM reset status register.
A data fetch from an unmapped address does not generate a reset.
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Resets
4.3.4 SIM Reset Status Register
This read-only register contains flags to show reset sources. All flag bits
are automatically cleared following a read of the register. Reset service
can read the SIM reset status register to clear the register after poweron reset and to determine the source of any subsequent reset.
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The register is initialized on powerup as shown with the POR bit set and
all other bits cleared. During a POR or any other internal reset, the RST
pin is pulled low. After the pin is released, it will be sampled 32 XCLK
cycles later. If the pin is not above a VIH at that time, then the PIN bit in
the SRSR may be set in addition to whatever other bits are set.
NOTE:
Only a read of the SIM reset status register clears all reset flags. After
multiple resets from different sources without reading the register,
multiple flags remain set.
Address:
Read:
$FE01
Bit 7
6
5
4
3
2
1
Bit 0
POR
PIN
COP
ILOP
ILAD
0
LVI
0
1
0
0
0
0
0
0
0
Write:
POR:
= Unimplemented
Figure 4-3. SIM Reset Status Register (SRSR)
POR — Power-On Reset Flag
1 = Power-on reset since last read of SRSR
0 = Read of SRSR since last power-on reset
PIN — External Reset Flag
1 = External reset via RST pin since last read of SRSR
0 = POR or read of SRSR since last external reset
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by timeout of COP counter
0 = POR or read of SRSR
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Resets and Interrupts
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR
ILAD — Illegal Address Reset Bit
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
LVI — Low-Voltage Inhibit Reset Bit
1 = Last reset caused by low-power supply voltage
0 = POR or read of SRSR
4.4 Interrupts
An interrupt temporarily changes the sequence of program execution to
respond to a particular event. An interrupt does not stop the operation of
the instruction being executed, but begins when the current instruction
completes its operation.
4.4.1 Effects
An interrupt:
•
Saves the CPU registers on the stack. At the end of the interrupt,
the RTI instruction recovers the CPU registers from the stack so
that normal processing can resume.
•
Sets the interrupt mask (I bit) to prevent additional interrupts.
Once an interrupt is latched, no other interrupt can take
precedence, regardless of its priority.
•
Loads the program counter with a user-defined vector address
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Interrupts
•
•
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•
5
CONDITION CODE REGISTER
1
4
ACCUMULATOR
2
INDEX REGISTER (LOW BYTE)*
STACKING 3
ORDER
2
PROGRAM COUNTER (HIGH BYTE)
3 UNSTACKING
ORDER
4
1
PROGRAM COUNTER (LOW BYTE)
5
•
•
•
$00FF DEFAULT ADDRESS ON RESET
*High byte of index register is not stacked.
Figure 4-4. Interrupt Stacking Order
After every instruction, the CPU checks all pending interrupts if the I bit
is not set. If more than one interrupt is pending when an instruction is
done, the highest priority interrupt is serviced first. In the example shown
in Figure 4-5, if an interrupt is pending upon exit from the interrupt
service routine, the pending interrupt is serviced before the LDA
instruction is executed.
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CLI
BACKGROUND
ROUTINE
LDA #$FF
INT1
PSHH
INT1 INTERRUPT SERVICE ROUTINE
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PULH
RTI
INT2
PSHH
INT2 INTERRUPT SERVICE ROUTINE
PULH
RTI
Figure 4-5. Interrupt Recognition Example
The LDA opcode is prefetched by both the INT1 and INT2 RTI
instructions. However, in the case of the INT1 RTI prefetch, this is a
redundant operation.
NOTE:
To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, save the
H register and then restore it prior to exiting the routine.
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Interrupts
FROM RESET
BREAK
INTERRUPT
?
NO
YES
YES
BIT SET?
SET?
II BIT
NO
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IRQ
INTERRUPT
?
YES
NO
CGM
INTERRUPT
?
NO
YES
OTHER
INTERRUPTS
?
YES
NO
STACK CPU REGISTERS
SET I BIT
LOAD PC WITH INTERRUPT VECTOR
FETCH NEXT
INSTRUCTION
SWI
YES
INSTRUCTION
?
NO
RTI
YES
INSTRUCTION
?
UNSTACK CPU REGISTERS
NO
EXECUTE INSTRUCTION
Figure 4-6. Interrupt Processing
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4.4.2 Sources
The sources in Table 4-1 can generate CPU interrupt requests.
Table 4-1. Interrupt Sources
Flag
Mask(1)
INT Register
Flag
Priority(2)
Vector
Address
Reset
None
None
None
0
$FFFE–$FFFF
SWI instruction
None
None
None
0
$FFFC–$FFFD
IRQ pin
IRQF
IMASK1
IF1
1
$FFFA–$FFFB
CGM (PLL)
PLLF
PLLIE
IF2
2
$FFF8–$FFF9
TIM1 channel 0
CH0F
CH0IE
IF3
3
$FFF6–$FFF7
TIM1 channel 1
CH1F
CH1IE
IF4
4
$FFF4–$FFF5
TOF
TOIE
IF5
5
$FFF2–$FFF3
CH0F
CH0IE
IF6
6
$FFF0–$FFF1
TOF
TOIE
IF8
8
$FFEC–$FFED
SPI receiver full
SPRF
SPRIE
SPI overflow
OVRF
ERRIE
IF9
9
$FFEA–$FFEB
SPI mode fault
MODF
ERRIE
SPI transmitter empty
SPTE
SPTIE
IF10
10
$FFE8–$FFE9
SCI receiver overrun
OR
ORIE
SCI noise fag
NF
NEIE
SCI framing error
FE
FEIE
IF11
11
$FFE6–$FFE7
SCI parity error
PE
PEIE
SCI receiver full
SCRF
SCRIE
SCI input idle
IDLE
ILIE
IF12
12
$FFE4–$FFE5
SCI transmitter empty
SCTE
SCTIE
TC
TCIE
IF13
13
$FFE2–$FFE3
Keyboard pin
KEYF
IMASKK
IF14
14
$FFDE–$FFDF
ADC conversion complete
COCO
AIEN
IF15
15
$FFDE–$FFDF
TBIF
TBIE
IF16
16
$FFDC–$FFDD
Source
TIM1 overflow
TIM2 channel 0
TIM2 overflow
SCI transmission complete
Timebase
Note:
1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI instruction.
2. 0 = highest priority
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Interrupts
4.4.2.1 SWI Instruction
The software interrupt instruction (SWI) causes a non-maskable
interrupt.
NOTE:
A software interrupt pushes PC onto the stack. An SWI does not push
PC – 1, as a hardware interrupt does.
4.4.2.2 Break Interrupt
The break module causes the CPU to execute an SWI instruction at a
software-programmable break point.
4.4.2.3 IRQ Pin
A logic 0 on the IRQ1 pin latches an external interrupt request.
4.4.2.4 CGM
The CGM can generate a CPU interrupt request every time the phaselocked loop circuit (PLL) enters or leaves the locked state. When the
LOCK bit changes state, the PLL flag (PLLF) is set. The PLL interrupt
enable bit (PLLIE) enables PLLF CPU interrupt requests. LOCK is in the
PLL bandwidth control register. PLLF is in the PLL control register.
4.4.2.5 TIM1
TIM1 CPU interrupt sources:
•
TIM1 overflow flag (TOF) — The TOF bit is set when the TIM1
counter value rolls over to $0000 after matching the value in the
TIM1 counter modulo registers. The TIM1 overflow interrupt
enable bit, TOIE, enables TIM1 overflow CPU interrupt requests.
TOF and TOIE are in the TIM1 status and control register.
•
TIM1 channel flags (CH1F–CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. The channel
x interrupt enable bit, CHxIE, enables channel x TIM1 CPU
interrupt requests. CHxF and CHxIE are in the TIM1 channel x
status and control register.
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4.4.2.6 TIM2
TIM2 CPU interrupt sources:
•
TIM2 overflow flag (TOF) — The TOF bit is set when the TIM2
counter value rolls over to $0000 after matching the value in the
TIM2 counter modulo registers. The TIM2 overflow interrupt
enable bit, TOIE, enables TIM2 overflow CPU interrupt requests.
TOF and TOIE are in the TIM2 status and control register.
•
TIM2 channel flag (CH0F) — The CH0F bit is set when an input
capture or output compare occurs on channel 0. The channel 0
interrupt enable bit, CH0IE, enables channel 0 TIM2 CPU interrupt
requests. CH0F and CH0IE are in the TIM2 channel 0 status and
control register.
4.4.2.7 SPI
SPI CPU interrupt sources:
•
SPI receiver full bit (SPRF) — The SPRF bit is set every time a
byte transfers from the shift register to the receive data register.
The SPI receiver interrupt enable bit, SPRIE, enables SPRF CPU
interrupt requests. SPRF is in the SPI status and control register
and SPRIE is in the SPI control register.
•
SPI transmitter empty (SPTE) — The SPTE bit is set every time a
byte transfers from the transmit data register to the shift register.
The SPI transmit interrupt enable bit, SPTIE, enables SPTE CPU
interrupt requests. SPTE is in the SPI status and control register
and SPTIE is in the SPI control register.
•
Mode fault bit (MODF) — The MODF bit is set in a slave SPI if the
SS pin goes high during a transmission with the mode fault enable
bit (MODFEN) set. In a master SPI, the MODF bit is set if the SS
pin goes low at any time with the MODFEN bit set. The error
interrupt enable bit, ERRIE, enables MODF CPU interrupt
requests. MODF, MODFEN, and ERRIE are in the SPI status and
control register.
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Interrupts
•
Overflow bit (OVRF) — The OVRF bit is set if software does not
read the byte in the receive data register before the next full byte
enters the shift register. The error interrupt enable bit, ERRIE,
enables OVRF CPU interrupt requests. OVRF and ERRIE are in
the SPI status and control register.
4.4.2.8 SCI
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SCI CPU interrupt sources:
•
SCI transmitter empty bit (SCTE) — SCTE is set when the SCI
data register transfers a character to the transmit shift register.
The SCI transmit interrupt enable bit, SCTIE, enables transmitter
CPU interrupt requests. SCTE is in SCI status register 1. SCTIE is
in SCI control register 2.
•
Transmission complete bit (TC) — TC is set when the transmit
shift register and the SCI data register are empty and no break or
idle character has been generated. The transmission complete
interrupt enable bit, TCIE, enables transmitter CPU interrupt
requests. TC is in SCI status register 1. TCIE is in SCI control
register 2.
•
SCI receiver full bit (SCRF) — SCRF is set when the receive shift
register transfers a character to the SCI data register. The SCI
receive interrupt enable bit, SCRIE, enables receiver CPU
interrupts. SCRF is in SCI status register 1. SCRIE is in SCI
control register 2.
•
Idle input bit (IDLE) — IDLE is set when 10 or 11 consecutive logic
1s shift in from the RxD pin. The idle line interrupt enable bit, ILIE,
enables IDLE CPU interrupt requests. IDLE is in SCI status
register 1. ILIE is in SCI control register 2.
•
Receiver overrun bit (OR) — OR is set when the receive shift
register shifts in a new character before the previous character
was read from the SCI data register. The overrun interrupt enable
bit, ORIE, enables OR to generate SCI error CPU interrupt
requests. OR is in SCI status register 1. ORIE is in SCI control
register 3.
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•
Noise flag (NF) — NF is set when the SCI detects noise on
incoming data or break characters, including start, data, and stop
bits. The noise error interrupt enable bit, NEIE, enables NF to
generate SCI error CPU interrupt requests. NF is in SCI status
register 1. NEIE is in SCI control register 3.
•
Framing error bit (FE) — FE is set when a logic 0 occurs where the
receiver expects a stop bit. The framing error interrupt enable bit,
FEIE, enables FE to generate SCI error CPU interrupt requests.
FE is in SCI status register 1. FEIE is in SCI control register 3.
•
Parity error bit (PE) — PE is set when the SCI detects a parity error
in incoming data. The parity error interrupt enable bit, PEIE,
enables PE to generate SCI error CPU interrupt requests. PE is in
SCI status register 1. PEIE is in SCI control register 3.
4.4.2.9 KBD0–KBD4 Pins
A logic 0 on a keyboard interrupt pin latches an external interrupt
request.
4.4.2.10 ADC (Analog-to-Digital Converter)
When the AIEN bit is set, the ADC module is capable of generating a
CPU interrupt after each ADC conversion. The COCO/IDMAS bit is not
used as a conversion complete flag when interrupts are enabled.
4.4.2.11 TBM (Timebase Module)
The timebase module can interrupt the CPU on a regular basis with a
rate defined by TBR2–TBR0. When the timebase counter chain rolls
over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase
interrupt, the counter chain overflow will generate a CPU interrupt
request.
Interrupts must be acknowledged by writing a logic 1 to the TACK bit.
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Interrupts
4.4.3 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt
sources. Table 4-2 summarizes the interrupt sources and the interrupt
status register flags that they set. The interrupt status registers can be
useful for debugging.
Table 4-2. Interrupt Source Flags
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Interrupt Source
Interrupt Status Register Flag
Reset
—
SWI instruction
—
IRQ pin
IF1
CGM (PLL)
IF2
TIM1 channel 0
IF3
TIM1 channel 1
IF4
TIM1 overflow
IF5
TIM2 channel 0
IF6
Reserved
IF7
TIM2 overflow
IF8
SPI receive
IF9
SPI transmit
IF10
SCI error
IF11
SCI receive
IF12
SCI transmit
IF13
Keyboard
IF14
ADC conversion complete
IF15
Timebase
IF16
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4.4.3.1 Interrupt Status Register 1
Address:
$FE04
Bit 7
6
5
4
3
2
1
Bit 0
Read:
IF6
IF5
IF4
IF3
IF2
IF1
0
0
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
R = Reserved
Figure 4-7. Interrupt Status Register 1 (INT1)
IF6–IF1 — Interrupt Flags 6–1
These flags indicate the presence of interrupt requests from the
sources shown in Table 4-2.
1 = Interrupt request present
0 = No interrupt request present
Bit 1 and Bit 0 — Always read 0
4.4.3.2 Interrupt Status Register 2
Address:
$FE05
Bit 7
6
5
4
3
2
1
Bit 0
Read:
IF14
IF13
IF12
IF11
IF10
IF9
IF8
IF7
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
R = Reserved
Figure 4-8. Interrupt Status Register 2 (INT2)
IF14–IF7 — Interrupt Flags 14–7
These flags indicate the presence of interrupt requests from the
sources shown in Table 4-2.
1 = Interrupt request present
0 = No interrupt request present
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4.4.3.3 Interrupt Status Register 3
Address:
$FE06
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
0
IF16
IF15
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
R = Reserved
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Figure 4-9. Interrupt Status Register 3 (INT3)
IF16–IF15 — Interrupt Flags 16–15
This flag indicates the presence of an interrupt request from the
source shown in Table 4-2.
1 = Interrupt request present
0 = No interrupt request present
Bits 7–2 — Always read 0
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Section 5. Analog-to-Digital Converter (ADC)
5.1 Contents
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.5
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.6
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
5.7
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.8
I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.2 Introduction
This section describes the 8-bit analog-to-digital converter (ADC).
For further information regarding analog-to-digital converters on
Motorola microcontrollers, please consult the HC08 ADC Reference
Manual, ADCRM/AD.
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Analog-to-Digital Converter (ADC)
5.3 Features
Features of the ADC module include:
•
Six channels with multiplexed input
•
Linear successive approximation with monotonicity
•
8-bit resolution
•
Single or continuous conversion
•
Conversion complete flag or conversion complete interrupt
•
Selectable ADC clock
5.4 Functional Description
The ADC provides six pins for sampling external sources at pins
PTB5/ATD5–PTB0/ATD0. An analog multiplexer allows the single ADC
converter to select one of six ADC channels as ADC voltage in (VADIN).
VADIN is converted by the successive approximation register-based
analog-to-digital converter. When the conversion is completed, ADC
places the result in the ADC data register and sets a flag or generates
an interrupt. See Figure 5-1.
NOTE:
References to DMA (direct-memory access) and associated functions
are only valid if the MCU has a DMA module. If the MCU has no DMA,
any DMA-related register bits should be left in their reset state for
expected MCU operation.
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Functional Description
INTERNAL
DATA BUS
READ DDRBx
WRITE DDRBx
DISABLE
DDRBx
RESET
WRITE PTBx
PTBx
PTBx
ADC CHANNEL x
READ PTBx
DISABLE
ADC DATA REGISTER
CONVERSION
INTERRUPT COMPLETE
LOGIC
AIEN
ADC
ADC
VOLTAGE IN
ADCH4–ADCH0
(VADIN)
CHANNEL
SELECT
ADC CLOCK
COCO
CGMXCLK
BUS CLOCK
CLOCK
GENERATOR
ADIV2–ADIV0
ADICLK
Figure 5-1. ADC Block Diagram
5.4.1 ADC Port I/O Pins
PTB5/ATD5–PTB0/ATD0 are general-purpose I/O (input/output) pins
that share with the ADC channels. The channel select bits define which
ADC channel/port pin will be used as the input signal. The ADC
overrides the port I/O logic by forcing that pin as input to the ADC. The
remaining ADC channels/port pins are controlled by the port I/O logic
and can be used as general-purpose I/O. Writes to the port register or
DDR will not have any affect on the port pin that is selected by the ADC.
Read of a port pin in use by the ADC will return a logic 0.
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Analog-to-Digital Converter (ADC)
5.4.2 Voltage Conversion
When the input voltage to the ADC equals VREFH, the ADC converts the
signal to $FF (full scale). If the input voltage equals VREFL, the ADC
converts it to $00. Input voltages between VREFH and VREFL are a
straight-line linear conversion. All other input voltages will result in $FF,
if greater than VREFH.
NOTE:
Inside the ADC module, the reference voltage, VREFH is connected to the
ADC analog power VDDAD; and VREFL is connected to the ADC analog
ground VDDAD. Therefore, the ADC input voltage should not exceed the
analog supply voltages
For operation, VDDAD should be tied to the same potential as VDD via
separate traces
5.4.3 Conversion Time
Conversion starts after a write to the ADSCR. One conversion will take
between 16 and 17 ADC clock cycles. The ADIVx and ADICLK bits
should be set to provide a 1 MHz ADC clock frequency.
Conversion time = 16 to17 ADC cycles
ADC frequency
Number of bus cycles = conversion time x bus frequency
5.4.4 Conversion
In continuous conversion mode, the ADC data register will be filled with
new data after each conversion. Data from the previous conversion will
be overwritten whether that data has been read or not. Conversions will
continue until the ADCO bit is cleared. The COCO/IDMAS bit is set after
the first conversion and will stay set until the next write of the ADC status
and control register or the next read of the ADC data register.
In single conversion mode, conversion begins with a write to the
ADSCR. Only one conversion occurs between writes to the ADSCR.
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Interrupts
5.4.5 Accuracy and Precision
The conversion process is monotonic and has no missing codes.
5.5 Interrupts
When the AIEN bit is set, the ADC module is capable of generating CPU
interrupts after each ADC conversion. A CPU interrupt is generated if the
COCO/IDMAS bit is at logic 0. If COCO/IDMAS bit is set, a DMA interrupt
is generated. The COCO/IDMAS bit is not used as a conversion
complete flag when interrupts are enabled.
5.6 Low-Power Modes
The WAIT and STOP instruction can put the MCU in low powerconsumption standby modes.
5.6.1 Wait Mode
The ADC continues normal operation during wait mode. Any enabled
CPU interrupt request from the ADC can bring the MCU out of wait
mode. If the ADC is not required to bring the MCU out of wait mode,
power down the ADC by setting ADCH4–ADCH0 bits in the ADC status
and control register before executing the WAIT instruction.
5.6.2 Stop Mode
The ADC module is inactive after the execution of a STOP instruction.
Any pending conversion is aborted. ADC conversions resume when the
MCU exits stop mode after an external interrupt. Allow one conversion
cycle to stabilize the analog circuitry.
5.7 I/O Signals
The ADC module has six pins shared with port B,
PTB5/AD5–PTB0/ATD0.
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5.7.1 ADC Analog Power Pin (VDDAD)/ADC Voltage Reference High Pin (VREFH)
The ADC analog portion uses VDDAD as its power pin. Connect the
VDDAD pin to the same voltage potential as VDD. External filtering may be
necessary to ensure clean VDDAD for good results.
NOTE:
For maximum noise immunity, route VDDAD carefully and place bypass
capacitors as close as possible to the package.
5.7.2 ADC Analog Ground Pin (VSSAD)/ADC Voltage Reference Low Pin (VREFL)
The ADC analog portion uses VSSAD as its ground pin. Connect the
VSSAD pin to the same voltage potential as VSS.
NOTE:
Route VSSAD cleanly to avoid any offset errors.
5.7.3 ADC Voltage In (VADIN)
VADIN is the input voltage signal from one of the six ADC channels to the
ADC module.
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I/O Registers
5.8 I/O Registers
These I/O registers control and monitor ADC operation:
•
ADC status and control register (ADSCR)
•
ADC data register (ADR)
•
ADC clock register (ADCLK)
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5.8.1 ADC Status and Control Register
Function of the ADC status and control register (ADSCR) is described
here.
Address:
$0003C
Bit 7
6
5
4
3
2
1
Bit 0
AIEN
ADCO
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
Write:
COCO/
IDMAS
Reset:
0
0
0
1
1
1
1
1
Read:
Figure 5-2. ADC Status and Control Register (ADSCR)
COCO/IDMAS — Conversions Complete/Interrupt DMA Select Bit
When the AIEN bit is a logic 0, the COCO/IDMAS is a read-only bit
which is set each time a conversion is completed except in the
continuous conversion mode where it is set after the first conversion.
This bit is cleared whenever the ADSCR is written or whenever the
ADR is read.
If the AIEN bit is a logic 1, the COCO/IDMAS is a read/write bit which
selects either CPU or DMA to service the ADC interrupt request.
Reset clears this bit.
1 = Conversion completed (AIEN = 0)/DMA interrupt (AIEN = 1)
0 = Conversion not completed (AIEN = 0)/CPU interrupt (AIEN = 1)
CAUTION:
Because the MC68HC908GR8 does NOT have a DMA module, the
IDMAS bit should NEVER be set when AIEN is set. Doing so will mask
ADC interrupts and cause unwanted results.
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AIEN — ADC Interrupt Enable Bit
When this bit is set, an interrupt is generated at the end of an ADC
conversion. The interrupt signal is cleared when the data register is
read or the status/control register is written. Reset clears the AIEN bit.
1 = ADC interrupt enabled
0 = ADC interrupt disabled
ADCO — ADC Continuous Conversion Bit
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When this bit is set, the ADC will convert samples continuously and
update the ADR register at the end of each conversion. Only one
conversion is completed between writes to the ADSCR when this bit
is cleared. Reset clears the ADCO bit.
1 = Continuous ADC conversion
0 = One ADC conversion
ADCH4–ADCH0 — ADC Channel Select Bits
ADCH4–ADCH0 form a 5-bit field which is used to select one of 16
ADC channels. Only six channels, AD5–AD0, are available on this
MCU. The channels are detailed in Table 5-1. Care should be taken
when using a port pin as both an analog and digital input
simultaneously to prevent switching noise from corrupting the analog
signal. See Table 5-1.
The ADC subsystem is turned off when the channel select bits are all
set to 1. This feature allows for reduced power consumption for the
MCU when the ADC is not being used.
NOTE:
Recovery from the disabled state requires one conversion cycle to
stabilize.
The voltage levels supplied from internal reference nodes, as specified
in Table 5-1, are used to verify the operation of the ADC converter both
in production test and for user applications.
Table 5-1. Mux Channel Select
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
Input Select
0
0
0
0
0
PTB0/ATD0
0
0
0
0
1
PTB1/ATD1
0
0
0
1
0
PTB2/ATD2
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I/O Registers
Table 5-1. Mux Channel Select
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
Input Select
0
0
0
1
1
PTB3/ATD3
0
0
1
0
0
PTB4/ATD4
0
0
1
0
1
PTB5/ATD5
0
0
1
1
0
Reserved
0
0
1
1
1
Reserved
↓
↓
↓
↓
↓
Reserved
1
1
0
1
1
Reserved
1
1
1
0
0
Reserved
1
1
1
0
1
VREFH
1
1
1
1
0
VREFL
1
1
1
1
1
ADC power off
NOTE: If an unknown channel is selected it should be made clear what value the user will read
from the ADC Data Register, unknown or reserved is not specific enough.
5.8.2 ADC Data Register
One 8-bit result register, ADC data register (ADR), is provided. This
register is updated each time an ADC conversion completes.
Address:
Read:
$0003D
Bit 7
6
5
4
3
2
1
Bit 0
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
0
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 5-3. ADC Data Register (ADR)
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5.8.3 ADC Clock Register
The ADC clock register (ADCLK) selects the clock frequency for the
ADC.
Address:
$0003E
Bit 7
6
5
4
ADIV2
ADIV1
ADIV0
ADICLK
0
0
0
0
Read:
3
2
1
Bit 0
0
0
0
0
0
0
0
0
Write:
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Reset:
= Unimplemented
Figure 5-4. ADC Clock Register (ADCLK)
ADIV2–ADIV0 — ADC Clock Prescaler Bits
ADIV2–ADIV0 form a 3-bit field which selects the divide ratio used by
the ADC to generate the internal ADC clock. Table 5-2 shows the
available clock configurations. The ADC clock should be set to
approximately 1 MHz.
Table 5-2. ADC Clock Divide Ratio
ADIV2
ADIV1
ADIV0
ADC Clock Rate
0
0
0
ADC input clock ÷ 1
0
0
1
ADC input clock ÷ 2
0
1
0
ADC input clock ÷ 4
0
1
1
ADC input clock ÷ 8
1
X
X
ADC input clock ÷ 16
X = don’t care
ADICLK — ADC Input Clock Select Bit
ADICLK selects either the bus clock or CGMXCLK as the input clock
source to generate the internal ADC clock. Reset selects CGMXCLK
as the ADC clock source.
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I/O Registers
If the external clock (CGMXCLK) is equal to or greater than 1 MHz,
CGMXCLK can be used as the clock source for the ADC. If
CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as
the clock source. As long as the internal ADC clock is at
approximately 1 MHz, correct operation can be guaranteed.
1 = Internal bus clock
0 = External clock (CGMXCLK)
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ADC input clock frequency
----------------------------------------------------------------------- = 1MHz
ADIV2 –ADIV0
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Section 6. Break Module (BRK)
6.1 Contents
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.5
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
6.6
Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
6.2 Introduction
This section describes the break module. The break module can
generate a break interrupt that stops normal program flow at a defined
address to enter a background program.
6.3 Features
Features of the break module include:
•
Accessible input/output (I/O) registers during the break interrupt
•
CPU-generated break interrupts
•
Software-generated break interrupts
•
COP disabling during break interrupts
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6.4 Functional Description
When the internal address bus matches the value written in the break
address registers, the break module issues a breakpoint signal to the
CPU. The CPU then loads the instruction register with a software
interrupt instruction (SWI) after completion of the current CPU
instruction. The program counter vectors to $FFFC and $FFFD ($FEFC
and $FEFD in monitor mode).
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The following events can cause a break interrupt to occur:
•
A CPU-generated address (the address in the program counter)
matches the contents of the break address registers.
•
Software writes a logic 1 to the BRKA bit in the break status and
control register.
When a CPU-generated address matches the contents of the break
address registers, the break interrupt begins after the CPU completes its
current instruction. A return-from-interrupt instruction (RTI) in the break
routine ends the break interrupt and returns the MCU to normal
operation. Figure 6-1 shows the structure of the break module.
IAB15–IAB8
BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
IAB15–IAB0
CONTROL
BREAK
8-BIT COMPARATOR
BREAK ADDRESS REGISTER LOW
IAB7–IAB0
Figure 6-1. Break Module Block Diagram
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Break Module (BRK)
Functional Description
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SIM Break Status Register
$FE00
Write:
(SBSR)
Reset:
0
0
0
1
0
0
BW
0
R
R
R
R
R
R
NOTE
R
0
0
0
1
0
0
0
0
BCFE
R
R
R
R
R
R
R
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
BRKE
BRKA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
= Reserved
$FE03
$FE09
$FE0A
Read:
SIM Break Flag Control
Write:
Register (SBFCR)
Reset:
Read:
Break Address Register
Write:
High (BRKH)
Reset:
Read:
Break Address Register
Write:
Low (BRKL)
Reset:
Read:
Break Status and Control
$FE0B
Write:
Register (BRKSCR)
Reset:
0
Note: Writing a logic 0 clears BW.
= Unimplemented
Figure 6-2. I/O Register Summary
6.4.1 Flag Protection During Break Interrupts
The BCFE bit in the SIM break flag control register (SBFCR) enables
software to clear status bits during the break state.
6.4.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
•
Loading the instruction register with the SWI instruction
•
Loading the program counter with $FFFC and $FFFD ($FEFC and
$FEFD in monitor mode)
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The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
6.4.3 TIMI and TIM2 During Break Interrupts
A break interrupt stops the timer counters.
6.4.4 COP During Break Interrupts
The COP is disabled during a break interrupt when VTST is present on
the RST pin.
6.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low powerconsumption standby modes.
6.5.1 Wait Mode
If enabled, the break module is active in wait mode. In the break routine,
the user can subtract one from the return address on the stack if SBSW
is set. See Low Power Modes. Clear the BW bit by writing logic 0 to it.
6.5.2 Stop Mode
A break interrupt causes exit from stop mode and sets the SBSW bit in
the break status register.
6.6 Break Module Registers
These registers control and monitor operation of the break module:
•
Break status and control register (BRKSCR)
•
Break address register high (BRKH)
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Break Module Registers
•
Break address register low (BRKL)
•
SIM break status register (SBSR)
•
SIM break flag control register (SBFCR)
6.6.1 Break Status and Control Register
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The break status and control register (BRKSCR) contains break module
enable and status bits.
Address:
$FE0E
Bit 7
6
BRKE
BRKA
0
0
Read:
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 6-3. Break Status and Control Register (BRKSCR)
BRKE — Break Enable Bit
This read/write bit enables breaks on break address register matches.
Clear BRKE by writing a logic 0 to bit 7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled on 16-bit address match
BRKA — Break Active Bit
This read/write status and control bit is set when a break address
match occurs. Writing a logic 1 to BRKA generates a break interrupt.
Clear BRKA by writing a logic 0 to it before exiting the break routine.
Reset clears the BRKA bit.
1 = (When read) Break address match
0 = (When read) No break address match
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6.6.2 Break Address Registers
The break address registers (BRKH and BRKL) contain the high and low
bytes of the desired breakpoint address. Reset clears the break address
registers.
Address:
$FE09
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 6-4. Break Address Register High (BRKH)
Address:
$FE0A
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 6-5. Break Address Register Low (BRKL)
6.6.3 Break Status Register
The break status register (SBSR) contains a flag to indicate that a break
caused an exit from wait mode. The flag is useful in applications
requiring a return to wait mode after exiting from a break interrupt.
Address:
$FE00
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
1
0
0
BW
0
Write:
R
R
R
R
R
R
NOTE
R
Reset:
0
0
0
1
0
0
0
0
R
= Reserved
Note: Writing a logic 0 clears BW.
Figure 6-6. SIM Break Status Register (SBSR)
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Break Module Registers
BW — Break Wait Bit
This read/write bit is set when a break interrupt causes an exit from
wait mode. Clear BW by writing a logic 0 to it. Reset clears BW.
1 = Break interrupt during wait mode
0 = No break interrupt during wait mode
BW can be read within the break interrupt routine. The user can modify
the return address on the stack by subtracting 1 from it. The following
code is an example.
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This code works if the H register was stacked in the break interrupt
routine. Execute this code at the end of the break interrupt routine.
HIBYTE
EQU
5
LOBYTE
EQU
6
;
If not BW, do RTI
BRCLR
BW,BSR, RETURN
; See if wait mode or stop mode
; was exited by break.
TST
LOBYTE,SP
; If RETURNLO is not 0,
BNE
DOLO
; then just decrement low byte.
DEC
HIBYTE,SP
; Else deal with high byte also.
DOLO
DEC
LOBYTE,SP
; Point to WAIT/STOP opcode.
RETURN
PULH
RTI
; Restore H register.
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6.6.4 Break Flag Control Register
The break flag control register (SBFCR) contains a bit that enables
software to clear status bits while the MCU is in a break state.
Address:
$FE03
Bit 7
6
5
4
3
2
1
Bit 0
BCFE
R
R
R
R
R
R
R
Read:
Write:
Freescale Semiconductor, Inc...
Reset:
0
R
= Reserved
Figure 6-7. SIM Break Flag Control Register (SBFCR)
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing
status registers while the MCU is in a break state. To clear status bits
during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
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Technical Data — MC68HC908GR8
Section 7. Clock Generator Module (CGMC)
7.1 Contents
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.5
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
7.6
CGMC Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
7.7
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
7.8
Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
7.9
Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . .125
7.2 Introduction
This section describes the clock generator module. The CGMC
generates the crystal clock signal, CGMXCLK, which operates at the
frequency of the crystal. The CGMC also generates the base clock
signal, CGMOUT, which is based on either the crystal clock divided by
two or the phase-locked loop (PLL) clock, CGMVCLK, divided by two. In
user mode, CGMOUT is the clock from which the SIM derives the
system clocks, including the bus clock, which is at a frequency of
CGMOUT/2. In monitor mode, PTC3 determines the bus clock. The PLL
is a fully functional frequency generator designed for use with crystals or
ceramic resonators. The PLL can generate an 8-MHz bus frequency
using a 32-kHz crystal.
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7.3 Features
Features of the CGMC include:
•
Phase-locked loop with output frequency in integer multiples of an
integer dividend of the crystal reference
•
Low-frequency crystal operation with low-power operation and
high-output frequency resolution
•
Programmable prescaler for power-of-two increases in frequency
•
Programmable hardware voltage-controlled oscillator (VCO) for
low-jitter operation
•
Automatic bandwidth control mode for low-jitter operation
•
Automatic frequency lock detector
•
CPU interrupt on entry or exit from locked condition
•
Configuration register bit to allow oscillator operation during stop
mode
7.4 Functional Description
The CGMC consists of three major submodules:
•
Crystal oscillator circuit — The crystal oscillator circuit generates
the constant crystal frequency clock, CGMXCLK.
•
Phase-locked loop (PLL) — The PLL generates the
programmable VCO frequency clock, CGMVCLK.
•
Base clock selector circuit — This software-controlled circuit
selects either CGMXCLK divided by two or the VCO clock,
CGMVCLK, divided by two as the base clock, CGMOUT. The SIM
derives the system clocks from either CGMOUT or CGMXCLK.
Figure 7-1 shows the structure of the CGMC.
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Functional Description
OSCILLATOR (OSC)
OSC2
CGMXCLK
(TO: SIM, TIMTB15A, ADC)
OSC1
SIMOSCEN (FROM SIM)
OSCSTOPENB
(FROM CONFIG)
PHASE-LOCKED LOOP (PLL)
CGMRDV
CGMRCLK
REFERENCE
DIVIDER
CLOCK
SELECT
CIRCUIT
BCS
RDS3–RDS0
VDDA
CGMXFC
÷2
CGMOUT
(TO SIM)
VSSA
VPR1–VPR0
VRS7–VRS0
PHASE
DETECTOR
VOLTAGE
CONTROLLED
OSCILLATOR
LOOP
FILTER
CGMVCLK
PLL ANALOG
LOCK
DETECTOR
LOCK
CGMVDV
AUTOMATIC
MODE
CONTROL
AUTO
ACQ
INTERRUPT
CONTROL
PLLIE
MUL11–MUL0
PRE1–PRE0
FREQUENCY
DIVIDER
FREQUENCY
DIVIDER
PLLIREQ
(TO SIM)
PLLF
Figure 7-1. CGMC Block Diagram
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7.4.1 Crystal Oscillator Circuit
The crystal oscillator circuit consists of an inverting amplifier and an
external crystal. The OSC1 pin is the input to the amplifier and the OSC2
pin is the output. The SIMOSCEN signal from the system integration
module (SIM) or the OSCSTOPENB bit in the CONFIG register enable
the crystal oscillator circuit.
The CGMXCLK signal is the output of the crystal oscillator circuit and
runs at a rate equal to the crystal frequency. CGMXCLK is then buffered
to produce CGMRCLK, the PLL reference clock.
CGMXCLK can be used by other modules which require precise timing
for operation. The duty cycle of CGMXCLK is not guaranteed to be 50%
and depends on external factors, including the crystal and related
external components. An externally generated clock also can feed the
OSC1 pin of the crystal oscillator circuit. Connect the external clock to
the OSC1 pin and let the OSC2 pin float.
7.4.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition
mode or tracking mode, depending on the accuracy of the output
frequency. The PLL can change between acquisition and tracking
modes either automatically or manually.
7.4.3 PLL Circuits
The PLL consists of these circuits:
•
Voltage-controlled oscillator (VCO)
•
Reference divider
•
Frequency prescaler
•
Modulo VCO frequency divider
•
Phase detector
•
Loop filter
•
Lock detector
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Functional Description
The operating range of the VCO is programmable for a wide range of
frequencies and for maximum immunity to external noise, including
supply and CGM/XFC noise. The VCO frequency is bound to a range
from roughly one-half to twice the center-of-range frequency, fVRS.
Modulating the voltage on the CGM/XFC pin changes the frequency
within this range. By design, fVRS is equal to the nominal center-of-range
frequency, fNOM, (38.4 kHz) times a linear factor, L, and a power-of-two
factor, E, or (L × 2E)fNOM.
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CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK.
CGMRCLK runs at a frequency, fRCLK, and is fed to the PLL through a
programmable modulo reference divider, which divides fRCLK by a
factor, R. The divider’s output is the final reference clock, CGMRDV,
running at a frequency, fRDV = fRCLK/R. With an external crystal
(30 kHz–100 kHz), always set R = 1 for specified performance. With an
external high-frequency clock source, use R to divide the external
frequency to between 30 kHz and 100 kHz.
The VCO’s output clock, CGMVCLK, running at a frequency, fVCLK, is
fed back through a programmable prescale divider and a programmable
modulo divider. The prescaler divides the VCO clock by a power-of-two
factor P and the modulo divider reduces the VCO clock by a factor, N.
The dividers’ output is the VCO feedback clock, CGMVDV, running at a
frequency, fVDV = fVCLK/(N × 2P). (See Programming the PLL for more
information.)
The phase detector then compares the VCO feedback clock, CGMVDV,
with the final reference clock, CGMRDV. A correction pulse is generated
based on the phase difference between the two signals. The loop filter
then slightly alters the DC voltage on the external capacitor connected
to CGM/XFC based on the width and direction of the correction pulse.
The filter can make fast or slow corrections depending on its mode,
described in Acquisition and Tracking Modes. The value of the external
capacitor and the reference frequency determine the speed of the
corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock,
CGMVDV, and the final reference clock, CGMRDV. Therefore, the
speed of the lock detector is directly proportional to the final reference
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frequency, fRDV. The circuit determines the mode of the PLL and the lock
condition based on this comparison.
7.4.4 Acquisition and Tracking Modes
The PLL filter is manually or automatically configurable into one of two
operating modes:
•
Acquisition mode — In acquisition mode, the filter can make large
frequency corrections to the VCO. This mode is used at PLL
startup or when the PLL has suffered a severe noise hit and the
VCO frequency is far off the desired frequency. When in
acquisition mode, the ACQ bit is clear in the PLL bandwidth control
register. (See PLL Bandwidth Control Register.)
•
Tracking mode — In tracking mode, the filter makes only small
corrections to the frequency of the VCO. PLL jitter is much lower
in tracking mode, but the response to noise is also slower. The
PLL enters tracking mode when the VCO frequency is nearly
correct, such as when the PLL is selected as the base clock
source. (See Base Clock Selector Circuit.) The PLL is
automatically in tracking mode when not in acquisition mode or
when the ACQ bit is set.
7.4.5 Manual and Automatic PLL Bandwidth Modes
The PLL can change the bandwidth or operational mode of the loop filter
manually or automatically. Automatic mode is recommended for most
users.
In automatic bandwidth control mode (AUTO = 1), the lock detector
automatically switches between acquisition and tracking modes.
Automatic bandwidth control mode also is used to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock,
CGMOUT. (See PLL Bandwidth Control Register.) If PLL interrupts are
enabled, the software can wait for a PLL interrupt request and then
check the LOCK bit. If interrupts are disabled, software can poll the
LOCK bit continuously (during PLL startup, usually) or at periodic
intervals. In either case, when the LOCK bit is set, the VCO clock is safe
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Functional Description
to use as the source for the base clock. (See Base Clock Selector
Circuit.) If the VCO is selected as the source for the base clock and the
LOCK bit is clear, the PLL has suffered a severe noise hit and the
software must take appropriate action, depending on the application.
(See Interrupts for information and precautions on using interrupts.)
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The following conditions apply when the PLL is in automatic bandwidth
control mode:
•
The ACQ bit (see PLL Bandwidth Control Register) is a read-only
indicator of the mode of the filter. (See Acquisition and Tracking
Modes.)
•
The ACQ bit is set when the VCO frequency is within a certain
tolerance and is cleared when the VCO frequency is out of a
certain tolerance. (See Acquisition/Lock Time Specifications for
more information.)
•
The LOCK bit is a read-only indicator of the locked state of the PLL.
•
The LOCK bit is set when the VCO frequency is within a certain
tolerance and is cleared when the VCO frequency is out of a
certain tolerance. (See Acquisition/Lock Time Specifications for
more information.)
•
CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s
lock condition changes, toggling the LOCK bit. (See PLL Control
Register.)
The PLL also may operate in manual mode (AUTO = 0). Manual mode is
used by systems that do not require an indicator of the lock condition for
proper operation. Such systems typically operate well below fBUSMAX.
The following conditions apply when in manual mode:
•
ACQ is a writable control bit that controls the mode of the filter.
Before turning on the PLL in manual mode, the ACQ bit must be
clear.
•
Before entering tracking mode (ACQ = 1), software must wait a
given time, tACQ (see Acquisition/Lock Time Specifications), after
turning on the PLL by setting PLLON in the PLL control register
(PCTL).
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•
Software must wait a given time, tAL, after entering tracking mode
before selecting the PLL as the clock source to CGMOUT
(BCS = 1).
•
The LOCK bit is disabled.
•
CPU interrupts from the CGMC are disabled.
7.4.6 Programming the PLL
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The following procedure shows how to program the PLL.
NOTE:
The round function in the following equations means that the real
number should be rounded to the nearest integer number.
1. Choose the desired bus frequency, fBUSDES.
2. Calculate the desired VCO frequency (four times the desired bus
frequency).
f VCLKDES = 4 × f BUSDES
3. Choose a practical PLL (crystal) reference frequency, fRCLK, and
the reference clock divider, R. Typically, the reference crystal is
32.768 kHz and R = 1.
Frequency errors to the PLL are corrected at a rate of fRCLK/R. For
stability and lock time reduction, this rate must be as fast as
possible. The VCO frequency must be an integer multiple of this
rate. The relationship between the VCO frequency, fVCLK, and the
reference frequency, fRCLK, is
P
2 N
f VCLK = ----------- ( f RCLK )
R
P, the power of two multiplier, and N, the range multiplier, are
integers.
In cases where desired bus frequency has some tolerance,
choose fRCLK to a value determined either by other module
requirements (such as modules which are clocked by CGMXCLK),
cost requirements, or ideally, as high as the specified range
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Functional Description
allows. See Electrical Specifications. Choose the reference
divider, R = 1. After choosing N and P, the actual bus frequency
can be determined using equation in 2 above.
When the tolerance on the bus frequency is tight, choose fRCLK to
an integer divisor of fBUSDES, and R = 1. If fRCLK cannot meet this
requirement, use the following equation to solve for R with
practical choices of fRCLK, and choose the fRCLK that gives the
lowest R.
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 f VCLKDES 
  f VCLKDES
R = round R MAX ×   -------------------------- – integer  -------------------------- 
 f RCLK  
  f RCLK 
4. Select a VCO frequency multiplier, N.
 R × fVCLKDES
N = round  -------------------------------------
f RCLK


Reduce N/R to the lowest possible R.
5. If N is < Nmax, use P = 0. If N > Nmax, choose P using this table:
Current N Value
P
0 < N ≤ N max
0
N max < N ≤ N max × 2
1
N max × 2 < N ≤ N max × 4
2
N max × 4 < N ≤ N max × 8
3
Then recalculate N:
 R × f VCLKDES
N = round  -------------------------------------
P
 f
×2 
RCLK
6. Calculate and verify the adequacy of the VCO and bus
frequencies fVCLK and fBUS.
P
f VCLK = ( 2 × N ⁄ R ) × f RCLK
f BUS = ( f VCLK ) ⁄ 4
7. Select the VCO’s power-of-two range multiplier E, according to
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this table:
Frequency Range
E
0 < fVCLK < 9,830,400
0
9,830,400 ≤ fVCLK < 19,660,800
1
19,660,800 ≤ fVCLK < 39,321,600
2
NOTE: Do not program E to a value of 3.
8. Select a VCO linear range multiplier, L, where fNOM = 38.4 kHz
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 f VCLK 
L = round  --------------------------
 2E × f

NOM
9. Calculate and verify the adequacy of the VCO programmed
center-of-range frequency, fVRS. The center-of-range frequency is
the midpoint between the minimum and maximum frequencies
attainable by the PLL.
E
f VRS = ( L × 2 ) f NOM
For proper operation,
E
f NOM × 2
f VRS – f VCLK ≤ -------------------------2
10. Verify the choice of P, R, N, E, and L by comparing fVCLK to fVRS
and fVCLKDES. For proper operation, fVCLK must be within the
application’s tolerance of fVCLKDES, and fVRS must be as close as
possible to fVCLK.
NOTE:
Exceeding the recommended maximum bus frequency or VCO
frequency can crash the MCU.
11. Program the PLL registers accordingly:
a. In the PRE bits of the PLL control register (PCTL), program
the binary equivalent of P.
b. In the VPR bits of the PLL control register (PCTL), program
the binary equivalent of E.
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Functional Description
c. In the PLL multiplier select register low (PMSL) and the PLL
multiplier select register high (PMSH), program the binary
equivalent of N.
d. In the PLL VCO range select register (PMRS), program the
binary coded equivalent of L.
e. In the PLL reference divider select register (PMDS), program
the binary coded equivalent of R.
Table 7-1 provides numeric examples (numbers are in hexadecimal
notation):
Table 7-1. Numeric Example
fBUS
fRCLK
R
N
P
E
L
2.0 MHz
32.768 kHz
1
F5
0
0
D1
2.4576 MHz
32.768 kHz
1
12C
0
1
80
2.5 MHz
32.768 kHz
1
132
0
1
83
4.0 MHz
32.768 kHz
1
1E9
0
1
D1
4.9152 MHz
32.768 kHz
1
258
0
2
80
5.0 MHz
32.768 kHz
1
263
0
2
82
7.3728 MHz
32.768 kHz
1
384
0
2
C0
8.0 MHz
32.768 kHz
1
3D1
0
2
D0
7.4.7 Special Programming Exceptions
The programming method described in Programming the PLL does not
account for three possible exceptions. A value of 0 for R, N, or L is
meaningless when used in the equations given. To account for these
exceptions:
•
A 0 value for R or N is interpreted exactly the same as a value of 1.
•
A 0 value for L disables the PLL and prevents its selection as the
source for the base clock.
(See Base Clock Selector Circuit.)
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7.4.8 Base Clock Selector Circuit
This circuit is used to select either the crystal clock, CGMXCLK, or the
VCO clock, CGMVCLK, as the source of the base clock, CGMOUT. The
two input clocks go through a transition control circuit that waits up to
three CGMXCLK cycles and three CGMVCLK cycles to change from
one clock source to the other. During this time, CGMOUT is held in
stasis. The output of the transition control circuit is then divided by two
to correct the duty cycle. Therefore, the bus clock frequency, which is
one-half of the base clock frequency, is one-fourth the frequency of the
selected clock (CGMXCLK or CGMVCLK).
The BCS bit in the PLL control register (PCTL) selects which clock drives
CGMOUT. The VCO clock cannot be selected as the base clock source
if the PLL is not turned on. The PLL cannot be turned off if the VCO clock
is selected. The PLL cannot be turned on or off simultaneously with the
selection or deselection of the VCO clock. The VCO clock also cannot
be selected as the base clock source if the factor L is programmed to a
0. This value would set up a condition inconsistent with the operation of
the PLL, so that the PLL would be disabled and the crystal clock would
be forced as the source of the base clock.
7.4.9 CGMC External Connections
In its typical configuration, the CGMC requires up to nine external
components. Five of these are for the crystal oscillator and two or four
are for the PLL.
The crystal oscillator is normally connected in a Pierce oscillator
configuration, as shown in Figure 7-2. Figure 7-2 shows only the logical
representation of the internal components and may not represent actual
circuitry. The oscillator configuration uses five components:
•
Crystal, X1
•
Fixed capacitor, C1
•
Tuning capacitor, C2 (can also be a fixed capacitor)
•
Feedback resistor, RB
•
Series resistor, RS
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Functional Description
The series resistor (RS) is included in the diagram to follow strict Pierce
oscillator guidelines. Refer to the crystal manufacturer’s data for more
information regarding values for C1 and C2.
Figure 7-2 also shows the external components for the PLL:
•
Bypass capacitor, CBYP
•
Filter network
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Routing should be done with great care to minimize signal cross talk and
noise.
See CGM Component Specifications for capacitor and resistor values.
SIMOSCEN
OSCSTOPENB
(FROM CONFIG)
CGMXCLK
OSC1
CGMXFC
OSC2
VSSA
VDDA
VDD
RB
10 k
RS
0.01 µF
CBYP
0.1 µF
0.033 µF
X1
C1
C2
Note: Filter network in box can be replaced with a 0.47 µF capacitor, but will degrade stability.
Figure 7-2. CGMC External Connections
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7.5 I/O Signals
The following paragraphs describe the CGMC I/O signals.
7.5.1 Crystal Amplifier Input Pin (OSC1)
The OSC1 pin is an input to the crystal oscillator amplifier.
7.5.2 Crystal Amplifier Output Pin (OSC2)
The OSC2 pin is the output of the crystal oscillator inverting amplifier.
7.5.3 External Filter Capacitor Pin (CGMXFC)
The CGMXFC pin is required by the loop filter to filter out phase
corrections. An external filter network is connected to this pin. (See
Figure 7-2.)
NOTE:
To prevent noise problems, the filter network should be placed as close
to the CGMXFC pin as possible, with minimum routing distances and no
routing of other signals across the network.
7.5.4 PLL Analog Power Pin (VDDA)
VDDA is a power pin used by the analog portions of the PLL. Connect the
VDDA pin to the same voltage potential as the VDD pin.
NOTE:
Route VDDA carefully for maximum noise immunity and place bypass
capacitors as close as possible to the package.
7.5.5 PLL Analog Ground Pin (VSSA)
VSSA is a ground pin used by the analog portions of the PLL. Connect
the VSSA pin to the same voltage potential as the VSS pin.
NOTE:
Route VSSA carefully for maximum noise immunity and place bypass
capacitors as close as possible to the package.
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I/O Signals
7.5.6 Oscillator Enable Signal (SIMOSCEN)
The SIMOSCEN signal comes from the system integration module (SIM)
and enables the oscillator and PLL.
7.5.7 Oscillator Stop Mode Enable Bit (OSCSTOPENB)
OSCSTOPENB is a bit in the CONFIG register that enables the oscillator
to continue operating during stop mode. If this bit is set, the Oscillator
continues running during stop mode. If this bit is not set (default), the
oscillator is controlled by the SIMOSCEN signal which will disable the
oscillator during stop mode.
7.5.8 Crystal Output Frequency Signal (CGMXCLK)
CGMXCLK is the crystal oscillator output signal. It runs at the full speed
of the crystal (fXCLK) and comes directly from the crystal oscillator circuit.
Figure 7-2 shows only the logical relation of CGMXCLK to OSC1 and
OSC2 and may not represent the actual circuitry. The duty cycle of
CGMXCLK is unknown and may depend on the crystal and other
external factors. Also, the frequency and amplitude of CGMXCLK can be
unstable at startup.
7.5.9 CGMC Base Clock Output (CGMOUT)
CGMOUT is the clock output of the CGMC. This signal goes to the SIM,
which generates the MCU clocks. CGMOUT is a 50 percent duty cycle
clock running at twice the bus frequency. CGMOUT is software
programmable to be either the oscillator output, CGMXCLK, divided by
two or the VCO clock, CGMVCLK, divided by two.
7.5.10 CGMC CPU Interrupt (CGMINT)
CGMINT is the interrupt signal generated by the PLL lock detector.
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7.6 CGMC Registers
These registers control and monitor operation of the CGMC:
•
PLL control register (PCTL)
(See PLL Control Register.)
•
PLL bandwidth control register (PBWC)
(See PLL Bandwidth Control Register.)
•
PLL multiplier select register high (PMSH)
(See PLL Multiplier Select Register High.)
•
PLL multiplier select register low (PMSL)
(See PLL Multiplier Select Register Low.)
•
PLL VCO range select register (PMRS)
(See PLL VCO Range Select Register.)
•
PLL reference divider select register (PMDS)
(See PLL Reference Divider Select Register.)
Figure 7-3 is a summary of the CGMC registers.
Addr.
$0036
$0037
Register Name
Bit 7
Read:
PLL Control Register
Write:
(PCTL)
Reset:
Read:
PLL Bandwidth Control
Write:
Register (PBWC)
Reset:
Read:
PLL Multiplier Select High
$0038
Write:
Register (PMSH)
Reset:
Read:
PLL Multiplier Select Low
$0039
Write:
Register (PMSL)
Reset:
PLLIE
0
AUTO
6
PLLF
0
LOCK
5
4
3
2
1
Bit 0
PLLON
BCS
PRE1
PRE0
VPR1
VPR0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
MUL11
MUL10
MUL9
MUL8
ACQ
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MUL7
MUL6
MUL5
MUL4
MUL3
MUL2
MUL1
MUL0
0
1
0
0
0
0
0
0
Figure 7-3. CGMC I/O Register Summary
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CGMC Registers
$003A
$003B
Read:
PLL VCO Select Range
Write:
Register (PMRS)
Reset:
Read:
PLL Reference Divider
Write:
Select Register (PMDS)
Reset:
VRS7
VRS6
VRS5
VRS4
VRS3
VRS2
VRS1
VRS0
0
1
0
0
0
0
0
0
0
0
0
0
RDS3
RDS2
RDS1
RDS0
0
0
0
0
0
0
0
1
= Unimplemented
R
= Reserved
NOTES:
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
Figure 7-3. CGMC I/O Register Summary
7.6.1 PLL Control Register
The PLL control register (PCTL) contains the interrupt enable and flag
bits, the on/off switch, the base clock selector bit, the prescaler bits, and
the VCO power-of-two range selector bits.
Address:
$0036
Bit 7
Read:
6
5
4
3
2
1
Bit 0
PLLON
BCS
PRE1
PRE0
VPR1
VPR0
1
0
0
0
0
0
PLLF
PLLIE
Write:
Reset:
0
0
= Unimplemented
Figure 7-4. PLL Control Register (PCTL)
PLLIE — PLL Interrupt Enable Bit
This read/write bit enables the PLL to generate an interrupt request
when the LOCK bit toggles, setting the PLL flag, PLLF. When the
AUTO bit in the PLL bandwidth control register (PBWC) is clear,
PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE
bit.
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1 = PLL interrupts enabled
0 = PLL interrupts disabled
PLLF — PLL Interrupt Flag Bit
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This read-only bit is set whenever the LOCK bit toggles. PLLF
generates an interrupt request if the PLLIE bit also is set. PLLF
always reads as logic 0 when the AUTO bit in the PLL bandwidth
control register (PBWC) is clear. Clear the PLLF bit by reading the
PLL control register. Reset clears the PLLF bit.
1 = Change in lock condition
0 = No change in lock condition
NOTE:
Do not inadvertently clear the PLLF bit. Any read or read-modify-write
operation on the PLL control register clears the PLLF bit.
PLLON — PLL On Bit
This read/write bit activates the PLL and enables the VCO clock,
CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the
base clock, CGMOUT (BCS = 1). (See Base Clock Selector Circuit.)
Reset sets this bit so that the loop can stabilize as the MCU is
powering up.
1 = PLL on
0 = PLL off
BCS — Base Clock Select Bit
This read/write bit selects either the crystal oscillator output,
CGMXCLK, or the VCO clock, CGMVCLK, as the source of the
CGMC output, CGMOUT. CGMOUT frequency is one-half the
frequency of the selected clock. BCS cannot be set while the PLLON
bit is clear. After toggling BCS, it may take up to three CGMXCLK and
three CGMVCLK cycles to complete the transition from one source
clock to the other. During the transition, CGMOUT is held in stasis.
(See Base Clock Selector Circuit.) Reset clears the BCS bit.
1 = CGMVCLK divided by two drives CGMOUT
0 = CGMXCLK divided by two drives CGMOUT
NOTE:
PLLON and BCS have built-in protection that prevents the base clock
selector circuit from selecting the VCO clock as the source of the base
clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS
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CGMC Registers
is set, and BCS cannot be set when PLLON is clear. If the PLL is off
(PLLON = 0), selecting CGMVCLK requires two writes to the PLL control
register. (See Base Clock Selector Circuit.)
PRE1 and PRE0 — Prescaler Program Bits
These read/write bits control a prescaler that selects the prescaler
power-of-two multiplier, P. (See PLL Circuits and Programming the
PLL.) PRE1 and PRE0 cannot be written when the PLLON bit is set.
Reset clears these bits.
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NOTE:
The value of P is normally 0 when using a 32.768-kHz crystal as the
reference.
Table 7-2. PRE 1 and PRE0 Programming
PRE1 and PRE0
P
Prescaler Multiplier
00
0
1
01
1
2
10
2
4
11
3
8
VPR1 and 0 — VCO Power-of-Two Range Select Bits
These read/write bits control the VCO’s hardware power-of-two range
multiplier E that, in conjunction with L (See PLL Circuits,
Programming the PLL, and PLL VCO Range Select Register.)
controls the hardware center-of-range frequency, fVRS. VPR1:VPR0
cannot be written when the PLLON bit is set. Reset clears these bits.
Table 7-3. VPR1 and VPR0 Programming
VPR1 and VPR0
E
VCO Power-of-Two
Range Multiplier
00
0
1
01
1
2
10
2
4
11
3(1)
8
1. Do not program E to a value of 3.
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7.6.2 PLL Bandwidth Control Register
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The PLL bandwidth control register (PBWC):
•
Selects automatic or manual (software-controlled) bandwidth
control mode
•
Indicates when the PLL is locked
•
In automatic bandwidth control mode, indicates when the PLL is in
acquisition or tracking mode
•
In manual operation, forces the PLL into acquisition or tracking
mode
Address:
$0037
Bit 7
Read:
6
5
LOCK
AUTO
4
3
2
1
0
0
0
0
Bit 0
ACQ
R
Write:
Reset:
0
0
0
0
= Unimplemented
R
0
0
0
0
= Reserved
Figure 7-5. PLL Bandwidth Control Register (PBWC)
AUTO — Automatic Bandwidth Control Bit
This read/write bit selects automatic or manual bandwidth control.
When initializing the PLL for manual operation (AUTO = 0), clear the
ACQ bit before turning on the PLL. Reset clears the AUTO bit.
1 = Automatic bandwidth control
0 = Manual bandwidth control
LOCK — Lock Indicator Bit
When the AUTO bit is set, LOCK is a read-only bit that becomes set
when the VCO clock, CGMVCLK, is locked (running at the
programmed frequency). When the AUTO bit is clear, LOCK reads as
logic 0 and has no meaning. The write one function of this bit is
reserved for test, so this bit must always be written a 0. Reset clears
the LOCK bit.
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CGMC Registers
1 = VCO frequency correct or locked
0 = VCO frequency incorrect or unlocked
ACQ — Acquisition Mode Bit
When the AUTO bit is set, ACQ is a read-only bit that indicates
whether the PLL is in acquisition mode or tracking mode. When the
AUTO bit is clear, ACQ is a read/write bit that controls whether the
PLL is in acquisition or tracking mode.
In automatic bandwidth control mode (AUTO = 1), the last-written
value from manual operation is stored in a temporary location and is
recovered when manual operation resumes. Reset clears this bit,
enabling acquisition mode.
1 = Tracking mode
0 = Acquisition mode
7.6.3 PLL Multiplier Select Register High
The PLL multiplier select register high (PMSH) contains the
programming information for the high byte of the modulo feedback
divider.
Address:
Read:
$0038
Bit 7
6
5
4
0
0
0
0
3
2
1
Bit 0
MUL11
MUL10
MUL9
MUL8
0
0
0
0
Write:
Reset:
0
0
0
0
= Unimplemented
Figure 7-6. PLL Multiplier Select Register High (PMSH)
MUL11–MUL8 — Multiplier Select Bits
These read/write bits control the high byte of the modulo feedback
divider that selects the VCO frequency multiplier N. (See PLL Circuits
and Programming the PLL.) A value of $0000 in the multiplier select
registers configures the modulo feedback divider the same as a value
of $0001. Reset initializes the registers to $0040 for a default multiply
value of 64.
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NOTE:
The multiplier select bits have built-in protection such that they cannot
be written when the PLL is on (PLLON = 1).
PMSH[7:4] — Unimplemented Bits
These bits have no function and always read as logic 0s.
7.6.4 PLL Multiplier Select Register Low
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The PLL multiplier select register low (PMSL) contains the programming
information for the low byte of the modulo feedback divider.
Address:
$0038
Bit 7
6
5
4
3
2
1
Bit 0
MUL7
MUL6
MUL5
MUL4
MUL3
MUL2
MUL1
MUL0
0
1
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 7-7. PLL Multiplier Select Register Low (PMSL)
MUL7–MUL0 — Multiplier Select Bits
These read/write bits control the low byte of the modulo feedback
divider that selects the VCO frequency multiplier, N. (See PLL Circuits
and Programming the PLL.) MUL7–MUL0 cannot be written when the
PLLON bit in the PCTL is set. A value of $0000 in the multiplier select
registers configures the modulo feedback divider the same as a value
of $0001. Reset initializes the register to $40 for a default multiply
value of 64.
NOTE:
The multiplier select bits have built-in protection such that they cannot
be written when the PLL is on (PLLON = 1).
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CGMC Registers
7.6.5 PLL VCO Range Select Register
NOTE:
PMRS may be called PVRS on other HC08 derivatives.
The PLL VCO range select register (PMRS) contains the programming
information required for the hardware configuration of the VCO.
Address:
$003A
Bit 7
6
5
4
3
2
1
Bit 0
VRS7
VRS6
VRS5
VRS4
VRS3
VRS2
VRS1
VRS0
0
1
0
0
0
0
0
0
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Read:
Write:
Reset:
Figure 7-8. PLL VCO Range Select Register (PMRS)
VRS7–VRS0 — VCO Range Select Bits
These read/write bits control the hardware center-of-range linear
multiplier L which, in conjunction with E (see PLL Circuits,
Programming the PLL, and PLL Control Register), controls the
hardware center-of-range frequency, fVRS. VRS7–VRS0 cannot be
written when the PLLON bit in the PCTL is set. (See Special
Programming Exceptions.) A value of $00 in the VCO range select
register disables the PLL and clears the BCS bit in the PLL control
register (PCTL). (See Base Clock Selector Circuit and Special
Programming Exceptions.). Reset initializes the register to $40 for a
default range multiply value of 64.
NOTE:
The VCO range select bits have built-in protection such that they cannot
be written when the PLL is on (PLLON = 1) and such that the VCO clock
cannot be selected as the source of the base clock (BCS = 1) if the VCO
range select bits are all clear.
The PLL VCO range select register must be programmed correctly.
Incorrect programming can result in failure of the PLL to achieve lock.
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7.6.6 PLL Reference Divider Select Register
NOTE:
PMDS may be called PRDS on other HC08 derivatives.
The PLL reference divider select register (PMDS) contains the
programming information for the modulo reference divider.
Address:
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Read:
$003B
Bit 7
6
5
4
0
0
0
0
3
2
1
Bit 0
RDS3
RDS2
RDS1
RDS0
0
0
0
1
Write:
Reset:
0
0
0
0
= Unimplemented
Figure 7-9. PLL Reference Divider Select Register (PMDS)
RDS3–RDS0 — Reference Divider Select Bits
These read/write bits control the modulo reference divider that selects
the reference division factor, R. (See PLL Circuits and Programming
the PLL.) RDS7–RDS0 cannot be written when the PLLON bit in the
PCTL is set. A value of $00 in the reference divider select register
configures the reference divider the same as a value of $01. (See
Special Programming Exceptions.) Reset initializes the register to
$01 for a default divide value of 1.
NOTE:
The reference divider select bits have built-in protection such that they
cannot be written when the PLL is on (PLLON = 1).
NOTE:
The default divide value of 1 is recommended for all applications.
PMDS7–PMDS4 — Unimplemented Bits
These bits have no function and always read as logic 0s.
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Interrupts
7.7 Interrupts
When the AUTO bit is set in the PLL bandwidth control register (PBWC),
the PLL can generate a CPU interrupt request every time the LOCK bit
changes state. The PLLIE bit in the PLL control register (PCTL) enables
CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL,
becomes set whether interrupts are enabled or not. When the AUTO bit
is clear, CPU interrupts from the PLL are disabled and PLLF reads as
logic 0.
Software should read the LOCK bit after a PLL interrupt request to see
if the request was due to an entry into lock or an exit from lock. When the
PLL enters lock, the VCO clock, CGMVCLK, divided by two can be
selected as the CGMOUT source by setting BCS in the PCTL. When the
PLL exits lock, the VCO clock frequency is corrupt, and appropriate
precautions should be taken. If the application is not frequency sensitive,
interrupts should be disabled to prevent PLL interrupt service routines
from impeding software performance or from exceeding stack
limitations.
NOTE:
Software can select the CGMVCLK divided by two as the CGMOUT
source even if the PLL is not locked (LOCK = 0). Therefore, software
should make sure the PLL is locked before setting the BCS bit.
7.8 Special Modes
The WAIT instruction puts the MCU in low power-consumption standby
modes.
7.8.1 Wait Mode
The WAIT instruction does not affect the CGMC. Before entering wait
mode, software can disengage and turn off the PLL by clearing the BCS
and PLLON bits in the PLL control register (PCTL) to save power. Less
power-sensitive applications can disengage the PLL without turning it
off, so that the PLL clock is immediately available at WAIT exit. This
would be the case also when the PLL is to wake the MCU from wait
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mode, such as when the PLL is first enabled and waiting for LOCK or
LOCK is lost.
7.8.2 Stop Mode
If the OSCSTOPENB bit in the CONFIG register is cleared (default),
then the STOP instruction disables the CGMC (oscillator and phase
locked loop) and holds low all CGMC outputs (CGMXCLK, CGMOUT,
and CGMINT).
If the STOP instruction is executed with the VCO clock, CGMVCLK,
divided by two driving CGMOUT, the PLL automatically clears the BCS
bit in the PLL control register (PCTL), thereby selecting the crystal clock,
CGMXCLK, divided by two as the source of CGMOUT. When the MCU
recovers from STOP, the crystal clock divided by two drives CGMOUT
and BCS remains clear.
If the OSCSTOPENB bit in the CONFIG register is set, then the phase
locked loop is shut off but the oscillator will continue to operate in stop
mode.
7.8.3 CGMC During Break Interrupts
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. (See SIM Break Flag Control
Register.)
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect the PLLF bit during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
the PLL control register during the break state without affecting the PLLF
bit.
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Acquisition/Lock Time Specifications
7.9 Acquisition/Lock Time Specifications
The acquisition and lock times of the PLL are, in many applications, the
most critical PLL design parameters. Proper design and use of the PLL
ensures the highest stability and lowest acquisition/lock times.
7.9.1 Acquisition/Lock Time Definitions
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Typical control systems refer to the acquisition time or lock time as the
reaction time, within specified tolerances, of the system to a step input.
In a PLL, the step input occurs when the PLL is turned on or when it
suffers a noise hit. The tolerance is usually specified as a percentage of
the step input or when the output settles to the desired value plus or
minus a percentage of the frequency change. Therefore, the reaction
time is constant in this definition, regardless of the size of the step input.
For example, consider a system with a 5 percent acquisition time
tolerance. If a command instructs the system to change from 0 Hz to
1 MHz, the acquisition time is the time taken for the frequency to reach
1 MHz ±50 kHz. Fifty kHz = 5% of the 1-MHz step input. If the system is
operating at 1 MHz and suffers a –100-kHz noise hit, the acquisition time
is the time taken to return from 900 kHz to 1 MHz ±5 kHz. Five kHz = 5%
of the 100-kHz step input.
Other systems refer to acquisition and lock times as the time the system
takes to reduce the error between the actual output and the desired
output to within specified tolerances. Therefore, the acquisition or lock
time varies according to the original error in the output. Minor errors may
not even be registered. Typical PLL applications prefer to use this
definition because the system requires the output frequency to be within
a certain tolerance of the desired frequency regardless of the size of the
initial error.
7.9.2 Parametric Influences on Reaction Time
Acquisition and lock times are designed to be as short as possible while
still providing the highest possible stability. These reaction times are not
constant, however. Many factors directly and indirectly affect the
acquisition time.
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The most critical parameter which affects the reaction times of the PLL
is the reference frequency, fRDV. This frequency is the input to the phase
detector and controls how often the PLL makes corrections. For stability,
the corrections must be small compared to the desired frequency, so
several corrections are required to reduce the frequency error.
Therefore, the slower the reference the longer it takes to make these
corrections. This parameter is under user control via the choice of crystal
frequency fXCLK and the R value programmed in the reference divider.
(See PLL Circuits, Programming the PLL, and PLL Reference Divider
Select Register.)
Another critical parameter is the external filter network. The PLL
modifies the voltage on the VCO by adding or subtracting charge from
capacitors in this network. Therefore, the rate at which the voltage
changes for a given frequency error (thus change in charge) is
proportional to the capacitance. The size of the capacitor also is related
to the stability of the PLL. If the capacitor is too small, the PLL cannot
make small enough adjustments to the voltage and the system cannot
lock. If the capacitor is too large, the PLL may not be able to adjust the
voltage in a reasonable time. (See Choosing a Filter.)
Also important is the operating voltage potential applied to VDDA. The
power supply potential alters the characteristics of the PLL. A fixed value
is best. Variable supplies, such as batteries, are acceptable if they vary
within a known range at very slow speeds. Noise on the power supply is
not acceptable, because it causes small frequency errors which
continually change the acquisition time of the PLL.
Temperature and processing also can affect acquisition time because
the electrical characteristics of the PLL change. The part operates as
specified as long as these influences stay within the specified limits.
External factors, however, can cause drastic changes in the operation of
the PLL. These factors include noise injected into the PLL through the
filter capacitor, filter capacitor leakage, stray impedances on the circuit
board, and even humidity or circuit board contamination.
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Acquisition/Lock Time Specifications
7.9.3 Choosing a Filter
As described in Parametric Influences on Reaction Time, the external
filter network is critical to the stability and reaction time of the PLL. The
PLL is also dependent on reference frequency and supply voltage.
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Either of the filter networks in Figure 7-10 is recommended when using
a 32.768-kHz reference crystal. In low-cost applications, where stability
and reaction time of the PLL is not critical, this filter network can be
replaced by a single capacitor.
CGMXFC
10 k
0.01 µF
0.033 µF
VSSA
Figure 7-10. PLL Filter
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Section 8. Configuration Register (CONFIG)
8.1 Contents
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
8.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
8.2 Introduction
This section describes the configuration registers, CONFIG1 and
CONFIG2. The configuration registers enable or disable these options:
•
Stop mode recovery time (32 CGMXCLK cycles or 4096
CGMXCLK cycles)
•
COP timeout period (218 – 24 or 213 – 24 CGMXCLK cycles)
•
STOP instruction
•
Computer operating properly module (COP)
•
Low-voltage inhibit (LVI) module control and voltage trip point
selection
•
Enable/disable the oscillator (OSC) during stop mode
8.3 Functional Description
The configuration registers are used in the initialization of various
options. The configuration registers can be written once after each reset.
All of the configuration register bits are cleared during reset. Since the
various options affect the operation of the MCU, it is recommended that
these registers be written immediately after reset. The configuration
registers are located at $001E and $001F. The configuration register
may be read at anytime.
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Configuration Register (CONFIG)
NOTE:
To ensure correct operation of the MCU under all operating conditions,
the user must write data $1C to address $0033 immediately after reset.
This is to ensure proper termination of an unused module within the
MCU.
NOTE:
On a FLASH device, the options except LVI5OR3 are one-time writeable
by the user after each reset. The LVI5OR3 bit is one-time writeable by
the user only after each POR (power-on reset). The CONFIG registers
are not in the FLASH memory but are special registers containing onetime writeable latches after each reset. Upon a reset, the CONFIG
registers default to predetermined settings as shown in Figure 8-1 and
Figure 8-2.
Address:
Read:
$001E
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
OSCSTOPEN
B
SCIBDSRC
0
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 8-1. Configuration Register 2 (CONFIG2)
Address:
$001F
Bit 7
6
5
Read:
COPRS
LVISTOP LVIRSTD
Write:
Reset:
0
0
0
4
3
2
1
Bit 0
LVIPWRD
LVI5OR3
SSREC
STOP
COPD
0
See Note
0
0
0
Note: LVI5OR3 bit is only reset via POR (power-on reset)
Figure 8-2. Configuration Register 1 (CONFIG1)
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Configuration Register (CONFIG)
Functional Description
OSCSTOPENB— Oscillator Stop Mode Enable Bar Bit
OSCSTOPENB enables the oscillator to continue operating during stop
mode. Setting the OSCSTOPENB bit allows the oscillator to operate
continuously even during stop mode. This is useful for driving the
timebase module to allow it to generate periodic wakeup while in stop
mode. (See Clock Generator Module (CGM) subsection Stop Mode.)
1 = Oscillator enabled to operate during stop mode
0 = Oscillator disabled during stop mode (default)
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SCIBDSRC — SCI Baud Rate Clock Source Bit
SCIBDSRC controls the clock source used for the SCI. The setting of
this bit affects the frequency at which the SCI operates.
1 = Internal data bus clock used as clock source for SCI
0 = External oscillator used as clock source for SCI
COPRS — COP Rate Select Bit
COPRS selects the COP timeout period. Reset clears COPRS. See
Computer Operating Properly (COP).
1 = COP timeout period = 213 – 24 CGMXCLK cycles
0 = COP timeout period = 218 – 24 CGMXCLK cycles
LVISTOP — LVI Enable in Stop Mode Bit
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the
LVI to operate during stop mode. Reset clears LVISTOP. See Stop
Mode.
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
LVIRSTD — LVI Reset Disable Bit
LVIRSTD disables the reset signal from the LVI module. See LowVoltage Inhibit (LVI).
1 = LVI module resets disabled
0 = LVI module resets enabled
LVIPWRD — LVI Power Disable Bit
LVIPWRD disables the LVI module. See Low-Voltage Inhibit (LVI).
1 = LVI module power disabled
0 = LVI module power enabled
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Configuration Register (CONFIG)
LVI5OR3 — LVI 5V or 3V Operating Mode Bit
LVI5OR3 selects the voltage operating mode of the LVI module. See
Low-Voltage Inhibit (LVI). The voltage mode selected for the LVI
should match the operating VDD. See Electrical Specifications for the
LVI’s voltage trip points for each of the modes.
1 = LVI operates in 5V mode.
0 = LVI operates in 3V mode.
SSREC — Short Stop Recovery Bit
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SSREC enables the CPU to exit stop mode with a delay of 32
CGMXCLK cycles instead of a 4096-CGMXCLK cycle delay.
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLKC cycles
NOTE:
Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal oscillator, do not set the SSREC bit.
NOTE:
When the LVISTOP is enabled, the system stabilization time for power
on reset and long stop recovery (both 4096 CGMXCLK cycles) gives a
delay longer than the enable time for the LVI. There is no period where
the MCU is not protected from a low power condition. However, when
using the short stop recovery configuration option, the 32-CGMXCLK
delay is less than the LVI’s turn-on time and there exists a period in
startup where the LVI is not protecting the MCU.
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. See Computer Operating Properly
(COP).
1 = COP module disabled
0 = COP module enabled
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Section 9. Computer Operating Properly (COP)
9.1 Contents
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
9.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
9.4
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
9.5
COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
9.6
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
9.7
Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
9.8
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
9.9
COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . .137
9.2 Introduction
The computer operating properly (COP) module contains a free-running
counter that generates a reset if allowed to overflow. The COP module
helps software recover from runaway code. Prevent a COP reset by
clearing the COP counter periodically. The COP module can be disabled
through the COPD bit in the CONFIG register.
9.3 Functional Description
Figure 9-1 shows the structure of the COP module.
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Computer Operating Properly (COP)
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RESET STATUS REGISTER
COP TIMEOUT
CLEAR STAGES 5–12
STOP INSTRUCTION
INTERNAL RESET SOURCES
RESET VECTOR FETCH
RESET CIRCUIT
12-BIT COP PRESCALER
CLEAR ALL STAGES
CGMXCLK
COPCTL WRITE
COP CLOCK
COP MODULE
6-BIT COP COUNTER
COPEN (FROM SIM)
COP DISABLE
(FROM CONFIG)
RESET
COPCTL WRITE
CLEAR
COP COUNTER
COP RATE SEL
(FROM CONFIG)
Figure 9-1. COP Block Diagram
The COP counter is a free-running 6-bit counter preceded by a 12-bit
prescaler counter. If not cleared by software, the COP counter overflows
and generates an asynchronous reset after 218 – 24 or 213 – 24
CGMXCLK cycles, depending on the state of the COP rate select bit,
COPRS, in the configuration register. With a 213 – 24 CGMXCLK cycle
overflow option, a 32.768-kHz crystal gives a COP timeout period of
250 ms. Writing any value to location $FFFF before an overflow occurs
prevents a COP reset by clearing the COP counter and stages 12
through 5 of the prescaler.
NOTE:
Service the COP immediately after reset and before entering or after
exiting stop mode to guarantee the maximum time before the first COP
counter overflow.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the
COP bit in the reset status register (RSR).
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Computer Operating Properly (COP)
I/O Signals
In monitor mode, the COP is disabled if the RST pin or the IRQ1 is held
at VTST. During the break state, VTST on the RST pin disables the COP.
NOTE:
Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
9.4 I/O Signals
The following paragraphs describe the signals shown in Figure 9-1.
9.4.1 CGMXCLK
CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency
is equal to the crystal frequency.
9.4.2 STOP Instruction
The STOP instruction clears the COP prescaler.
9.4.3 COPCTL Write
Writing any value to the COP control register (COPCTL) (see COP
Control Register) clears the COP counter and clears bits 12 through 5 of
the prescaler. Reading the COP control register returns the low byte of
the reset vector.
9.4.4 Power-On Reset
The power-on reset (POR) circuit clears the COP prescaler 4096
CGMXCLK cycles after power-up.
9.4.5 Internal Reset
An internal reset clears the COP prescaler and the COP counter.
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Computer Operating Properly (COP)
9.4.6 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data
bus. A reset vector fetch clears the COP prescaler.
9.4.7 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the
configuration register. See Configuration Register (CONFIG).
9.4.8 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS)
in the configuration register. See Configuration Register (CONFIG).
9.5 COP Control Register
The COP control register is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and
starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Address: $FFFF
Bit 7
6
5
4
3
2
Read:
Low byte of reset vector
Write:
Clear COP counter
Reset:
Unaffected by reset
1
Bit 0
Figure 9-2. COP Control Register (COPCTL)
9.6 Interrupts
The COP does not generate CPU interrupt requests.
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Computer Operating Properly (COP)
Monitor Mode
9.7 Monitor Mode
When monitor mode is entered with VTST on the IRQ pin, the COP is
disabled as long as VTST remains on the IRQ pin or the RST pin. When
monitor mode is entered by having blank reset vectors and not having
VTST on the IRQ pin, the COP is automatically disabled until a POR
occurs.
9.8 Low-Power Modes
The WAIT and STOP instructions put the MCU in low powerconsumption standby modes.
9.8.1 Wait Mode
The COP remains active during wait mode. To prevent a COP reset
during wait mode, periodically clear the COP counter in a CPU interrupt
routine.
9.8.2 Stop Mode
Stop mode turns off the CGMXCLK input to the COP and clears the COP
prescaler. Service the COP immediately before entering or after exiting
stop mode to ensure a full COP timeout period after entering or exiting
stop mode.
To prevent inadvertently turning off the COP with a STOP instruction, a
configuration option is available that disables the STOP instruction.
When the STOP bit in the configuration register has the STOP
instruction disabled, execution of a STOP instruction results in an illegal
opcode reset.
9.9 COP Module During Break Mode
The COP is disabled during a break interrupt when VTST is present on
the RST pin.
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Section 10. Central Processing Unit (CPU)
10.1 Contents
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
10.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
10.4
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
10.5
Arithmetic/logic unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
10.6
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
10.7
CPU during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 146
10.8
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
10.9
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
10.2 Introduction
The M68HC08 CPU (central processor unit) is an enhanced and fully
object-code-compatible version of the M68HC05 CPU. The CPU08
Reference Manual (Motorola document order number CPU08RM/AD)
contains a description of the CPU instruction set, addressing modes,
and architecture.
10.3 Features
•
Object code fully upward-compatible with M68HC05 Family
•
16-bit stack pointer with stack manipulation instructions
•
16-bit index register with x-register manipulation instructions
•
8-MHz CPU internal bus frequency
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Central Processing Unit (CPU)
•
64K byte program/data memory space
•
16 addressing modes
•
Memory-to-memory data moves without using accumulator
•
Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
•
Enhanced binary-coded decimal (BCD) data handling
•
Modular architecture with expandable internal bus definition for
extension of addressing range beyond 64K bytes
•
Low-power stop and wait modes
10.4 CPU registers
Figure 10-1 shows the five CPU registers. CPU registers are not part of
the memory map.
7
0
ACCUMULATOR (A)
15
0
H
15
X
INDEX REGISTER (H:X)
0
STACK POINTER (SP)
15
0
PROGRAM COUNTER (PC)
7
0
V 1 1 H I N Z C
CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
Figure 10-1. CPU registers
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Central Processing Unit (CPU)
CPU registers
10.4.1 Accumulator (A)
The accumulator is a general-purpose 8-bit register. The CPU uses the
accumulator to hold operands and the results of arithmetic/logic
operations.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
A
Write:
Reset:
Unaffected by reset
Figure 10-2. Accumulator (A)
10.4.2 Index register (H:X)
The 16-bit index register allows indexed addressing of a 64K byte
memory space. H is the upper byte of the index register and X is the
lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the
index register to determine the conditional address of the operand.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit
0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
Read:
H:X
Write:
Reset:
X = Indeterminate
Figure 10-3. Index register (H:X)
The index register can also be used as a temporary data storage
location.
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Central Processing Unit (CPU)
10.4.3 Stack pointer (SP)
The stack pointer is a 16-bit register that contains the address of the next
location on the stack. During a reset, the stack pointer is preset to
$00FF. The reset stack pointer (RSP) instruction sets the least
significant byte to $FF and does not affect the most significant byte. The
stack pointer decrements as data is pushed onto the stack and
increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the
stack pointer can function as an index register to access data on the
stack. The CPU uses the contents of the stack pointer to determine the
conditional address of the operand.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Read:
SP
Write:
Reset:
Figure 10-4. Stack pointer (SP)
NOTE:
The location of the stack is arbitrary and may be relocated anywhere in
RAM. Moving the SP out of page zero ($0000 to $00FF) frees direct
address (page zero) space. For correct operation, the stack pointer must
point only to RAM locations.
10.4.4 Program counter (PC)
The program counter is a 16-bit register that contains the address of the
next instruction or operand to be fetched.
Normally, the program counter automatically increments to the next
sequential memory location every time an instruction or operand is
fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
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Central Processing Unit (CPU)
CPU registers
During reset, the program counter is loaded with the reset vector
address located at $FFFE and $FFFF. The vector address is the
address of the first instruction to be executed after exiting the reset state.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Bit
0
1
Read:
PC
Write:
Reset:
Loaded with vector from $FFFE and $FFFF
Figure 10-5. Program counter (PC)
10.4.5 Condition code register (CCR)
The 8-bit condition code register contains the interrupt mask and five
flags that indicate the results of the instruction just executed. Bits 6 and
5 are set permanently to ‘1’. The following paragraphs describe the
functions of the condition code register.
Bit 7
6
5
4
3
2
1
Bit 0
V
1
1
H
I
N
Z
C
X
1
1
X
1
X
X
X
Read:
CCR
Write:
Reset:
X = Indeterminate
Figure 10-6. Condition code register (CCR)
V — Overflow flag
The CPU sets the overflow flag when a two's complement overflow
occurs. The signed branch instructions BGT, BGE, BLE, and BLT use
the overflow flag.
1 = Overflow
0 = No overflow
H — Half-carry flag
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The CPU sets the half-carry flag when a carry occurs between
accumulator bits 3 and 4 during an ADD or ADC operation. The halfcarry flag is required for binary-coded decimal (BCD) arithmetic
operations. The DAA instruction uses the states of the H and C flags
to determine the appropriate correction factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
I — Interrupt mask
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When the interrupt mask is set, all maskable CPU interrupts are
disabled. CPU interrupts are enabled when the interrupt mask is
cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but
before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
NOTE:
To maintain M6805 compatibility, the upper byte of the index register (H)
is not stacked automatically. If the interrupt service routine modifies H,
then the user must stack and unstack H using the PSHH and PULH
instructions.
After the I bit is cleared, the highest-priority interrupt request is
serviced first.
A return from interrupt (RTI) instruction pulls the CPU registers from the
stack and restores the interrupt mask from the stack. After any reset, the
interrupt mask is set and can only be cleared by the clear interrupt mask
software instruction (CLI).
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Arithmetic/logic unit (ALU)
N — Negative flag
The CPU sets the negative flag when an arithmetic operation, logic
operation, or data manipulation produces a negative result, setting bit
7 of the result.
1 = Negative result
0 = Non-negative result
Z — Zero flag
The CPU sets the zero flag when an arithmetic operation, logic
operation, or data manipulation produces a result of $00.
1 = Zero result
0 = Non-zero result
C — Carry/borrow flag
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some instructions - such as bit test and
branch, shift, and rotate - also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
10.5 Arithmetic/logic unit (ALU)
The ALU performs the arithmetic and logic operations defined by the
instruction set.
Refer to the CPU08 Reference Manual (Motorola document number
CPU08RM/AD) for a description of the instructions and addressing
modes and more detail about CPU architecture.
10.6 Low-power modes
The WAIT and STOP instructions put the MCU in low--power
consumption standby modes.
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10.6.1 WAIT mode
The WAIT instruction:
•
clears the interrupt mask (I bit) in the condition code register,
enabling interrupts. After exit from WAIT mode by interrupt, the I
bit remains clear. After exit by reset, the I bit is set.
•
Disables the CPU clock
10.6.2 STOP mode
The STOP instruction:
•
clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from STOP mode by
external interrupt, the I bit remains clear. After exit by reset, the I
bit is set.
•
Disables the CPU clock
After exiting STOP mode, the CPU clock begins running after the
oscillator stabilization delay.
10.7 CPU during break interrupts
If the break module is enabled, a break interrupt causes the CPU to
execute the software interrupt instruction (SWI) at the completion of the
current CPU instruction. See Break Module (BRK). The program counter
vectors to $FFFC–$FFFD ($FEFC–$FEFD in monitor mode).
A return-from-interrupt instruction (RTI) in the break routine ends the
break interrupt and returns the MCU to normal operation if the break
interrupt has been deasserted.
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Central Processing Unit (CPU)
Instruction Set Summary
10.8 Instruction Set Summary
Table 10-1 provides a summary of the M68HC08 instruction set.
V H I N Z C
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
ADC opr,SP
ADC opr,SP
A ← (A) + (M) + (C)
Add with Carry
IMM
DIR
EXT
↕ ↕ – ↕ ↕ ↕ IX2
IX1
IX
SP1
SP2
A9
B9
C9
D9
E9
F9
9EE9
9ED9
ii
dd
hh ll
ee ff
ff
IMM
DIR
EXT
IX2
↕ ↕ – ↕ ↕ ↕
IX1
IX
SP1
SP2
AB
BB
CB
DB
EB
FB
9EEB
9EDB
ii
dd
hh ll
ee ff
ff
ff
ee ff
A7
ii
2
– – – – – – IMM
AF
ii
2
IMM
DIR
EXT
IX2
0 – – ↕ ↕ –
IX1
IX
SP1
SP2
A4
B4
C4
D4
E4
F4
9EE4
9ED4
ii
dd
hh ll
ee ff
ff
2
3
4
4
3
2
4
5
0
DIR
INH
INH
↕ – – ↕ ↕ ↕
IX1
IX
SP1
38 dd
48
58
68 ff
78
9E68 ff
4
1
1
4
3
5
C
DIR
INH
INH
↕ – – ↕ ↕ ↕ IX1
IX
SP1
37 dd
47
57
67 ff
77
9E67 ff
4
1
1
4
3
5
Add without Carry
AIS #opr
Add Immediate Value (Signed) to SP
SP ← (SP) + (16 « M)
– – – – – – IMM
AIX #opr
Add Immediate Value (Signed) to H:X
H:X ← (H:X) + (16 « M)
A ← (A) & (M)
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
ASL opr,SP
A ← (A) + (M)
Logical AND
Arithmetic Shift Left
(Same as LSL)
C
b7
ASR opr
ASRA
ASRX
ASR opr,X
ASR opr,X
ASR opr,SP
Arithmetic Shift Right
BCC rel
Branch if Carry Bit Clear
b7
b0
b0
PC ← (PC) + 2 + rel ? (C) = 0
– – – – – – REL
MC68HC908GR8 — Rev 4.0
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2
3
4
4
3
2
4
5
2
3
4
4
3
2
4
5
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
ADD opr,SP
ADD opr,SP
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
AND opr,SP
AND opr,SP
ff
ee ff
Cycles
Description
Operand
Operation
Effect on
CCR
Opcode
Source
Form
Address
Mode
Table 10-1. Instruction Set Summary
24
ff
ee ff
rr
3
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V H I N Z C
Mn ← 0
Cycles
Description
Operand
Operation
Effect on
CCR
Opcode
Source
Form
Address
Mode
Table 10-1. Instruction Set Summary (Continued)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
– – – – – – DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
BCLR n, opr
Clear Bit n in M
BCS rel
Branch if Carry Bit Set (Same as BLO)
PC ← (PC) + 2 + rel ? (C) = 1
– – – – – – REL
25
rr
3
BEQ rel
Branch if Equal
PC ← (PC) + 2 + rel ? (Z) = 1
– – – – – – REL
27
rr
3
BGE opr
Branch if Greater Than or Equal To
(Signed Operands)
PC ← (PC) + 2 + rel ? (N ⊕ V) = 0
– – – – – – REL
90
rr
3
BGT opr
Branch if Greater Than (Signed
Operands)
PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 0 – – – – – – REL
92
rr
3
BHCC rel
Branch if Half Carry Bit Clear
PC ← (PC) + 2 + rel ? (H) = 0
– – – – – – REL
28
rr
3
BHCS rel
Branch if Half Carry Bit Set
PC ← (PC) + 2 + rel ? (H) = 1
– – – – – – REL
29
rr
BHI rel
Branch if Higher
PC ← (PC) + 2 + rel ? (C) | (Z) = 0
– – – – – – REL
22
rr
3
BHS rel
Branch if Higher or Same
(Same as BCC)
PC ← (PC) + 2 + rel ? (C) = 0
– – – – – – REL
24
rr
3
BIH rel
Branch if IRQ Pin High
PC ← (PC) + 2 + rel ? IRQ = 1
– – – – – – REL
2F
rr
3
BIL rel
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 0
– – – – – – REL
2E
rr
3
(A) & (M)
IMM
DIR
EXT
0 – – ↕ ↕ – IX2
IX1
IX
SP1
SP2
A5
B5
C5
D5
E5
F5
9EE5
9ED5
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
93
rr
3
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
BIT opr,SP
BIT opr,SP
Bit Test
BLE opr
Branch if Less Than or Equal To
(Signed Operands)
BLO rel
Branch if Lower (Same as BCS)
BLS rel
PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 1 – – – – – – REL
3
PC ← (PC) + 2 + rel ? (C) = 1
– – – – – – REL
25
rr
3
Branch if Lower or Same
PC ← (PC) + 2 + rel ? (C) | (Z) = 1
– – – – – – REL
23
rr
3
BLT opr
Branch if Less Than (Signed Operands)
PC ← (PC) + 2 + rel ? (N ⊕ V) =1
– – – – – – REL
91
rr
3
BMC rel
Branch if Interrupt Mask Clear
PC ← (PC) + 2 + rel ? (I) = 0
– – – – – – REL
2C
rr
3
BMI rel
Branch if Minus
PC ← (PC) + 2 + rel ? (N) = 1
– – – – – – REL
2B
rr
3
BMS rel
Branch if Interrupt Mask Set
PC ← (PC) + 2 + rel ? (I) = 1
– – – – – – REL
2D
rr
3
Technical Data
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Instruction Set Summary
V H I N Z C
Cycles
Description
Operand
Operation
Effect on
CCR
Opcode
Source
Form
Address
Mode
Table 10-1. Instruction Set Summary (Continued)
BNE rel
Branch if Not Equal
PC ← (PC) + 2 + rel ? (Z) = 0
– – – – – – REL
26
rr
3
BPL rel
Branch if Plus
PC ← (PC) + 2 + rel ? (N) = 0
– – – – – – REL
2A
rr
3
BRA rel
Branch Always
PC ← (PC) + 2 + rel
– – – – – – REL
20
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
– – – – – ↕ DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
– – – – – – REL
21
rr
3
PC ← (PC) + 3 + rel ? (Mn) = 1
DIR (b0)
DIR (b1)
DIR (b2)
– – – – – ↕ DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
Mn ← 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
– – – – – –
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
– – – – – – REL
AD
rr
4
DIR
IMM
IMM
– – – – – – IX1+
IX+
SP1
31
41
51
61
71
9E61
dd rr
ii rr
ii rr
ff rr
rr
ff rr
5
4
4
5
4
6
BRCLR n,opr,rel Branch if Bit n in M Clear
BRN rel
PC ← (PC) + 3 + rel ? (Mn) = 0
PC ← (PC) + 2
Branch Never
BRSET n,opr,rel Branch if Bit n in M Set
BSET n,opr
Set Bit n in M
BSR rel
Branch to Subroutine
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
CBEQ opr,rel
CBEQA #opr,rel
CBEQX #opr,rel
Compare and Branch if Equal
CBEQ opr,X+,rel
CBEQ X+,rel
CBEQ opr,SP,rel
PC ←
PC ←
PC ←
PC ←
PC ←
PC ←
(PC) + 3 + rel ? (A) – (M) = $00
(PC) + 3 + rel ? (A) – (M) = $00
(PC) + 3 + rel ? (X) – (M) = $00
(PC) + 3 + rel ? (A) – (M) = $00
(PC) + 2 + rel ? (A) – (M) = $00
(PC) + 4 + rel ? (A) – (M) = $00
CLC
Clear Carry Bit
C←0
– – – – – 0 INH
98
1
CLI
Clear Interrupt Mask
I←0
– – 0 – – – INH
9A
2
M ← $00
A ← $00
X ← $00
H ← $00
M ← $00
M ← $00
M ← $00
DIR
INH
INH
0 – – 0 1 – INH
IX1
IX
SP1
CLR opr
CLRA
CLRX
CLRH
CLR opr,X
CLR ,X
CLR opr,SP
Clear
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3F dd
4F
5F
8C
6F ff
7F
9E6F ff
3
1
1
1
3
2
4
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V H I N Z C
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
CMP opr,SP
CMP opr,SP
Compare A with M
(A) – (M)
COM opr
COMA
COMX
COM opr,X
COM ,X
COM opr,SP
Complement (One’s Complement)
CPHX #opr
CPHX opr
Compare H:X with M
CPX #opr
CPX opr
CPX opr
CPX ,X
CPX opr,X
CPX opr,X
CPX opr,SP
CPX opr,SP
Compare X with M
DAA
Decimal Adjust A
(H:X) – (M:M + 1)
(X) – (M)
(A)10
DBNZ opr,rel
DBNZA rel
DBNZX rel
Decrement and Branch if Not Zero
DBNZ opr,X,rel
DBNZ X,rel
DBNZ opr,SP,rel
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
DEC opr,SP
Decrement
DIV
Divide
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
EOR opr,SP
EOR opr,SP
Exclusive OR M with A
M ← (M) = $FF – (M)
A ← (A) = $FF – (M)
X ← (X) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
IMM
DIR
EXT
IX2
↕ – – ↕ ↕ ↕ IX1
IX
SP1
SP2
A1
B1
C1
D1
E1
F1
9EE1
9ED1
DIR
INH
INH
0 – – ↕ ↕ 1 IX1
IX
SP1
33 dd
43
53
63 ff
73
9E63 ff
4
1
1
4
3
5
ii ii+1
dd
3
4
IMM
DIR
EXT
↕ – – ↕ ↕ ↕ IX2
IX1
IX
SP1
SP2
A3
B3
C3
D3
E3
F3
9EE3
9ED3
ii
dd
hh ll
ee ff
ff
2
3
4
4
3
2
4
5
U – – ↕ ↕ ↕ INH
72
A ← (A) – 1 or M ← (M) – 1 or X ← (X) – 1
DIR
PC ← (PC) + 3 + rel ? (result) ≠ 0
INH
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
– – – – – – INH
IX1
PC ← (PC) + 3 + rel ? (result) ≠ 0
IX
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 4 + rel ? (result) ≠ 0
SP1
3B
4B
5B
6B
7B
9E6B
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
M ← (M) – 1
DIR
INH
INH
↕ – – ↕ ↕ –
IX1
IX
SP1
A ← (H:A)/(X)
H ← Remainder
– – – – ↕ ↕ INH
52
A ← (A ⊕ M)
IMM
DIR
EXT
0 – – ↕ ↕ – IX2
IX1
IX
SP1
SP2
A8
B8
C8
D8
E8
F8
9EE8
9ED8
Technical Data
150
ff
ee ff
2
3
4
4
3
2
4
5
65
75
↕ – – ↕ ↕ ↕
IMM
DIR
ii
dd
hh ll
ee ff
ff
Cycles
Description
Operand
Operation
Effect on
CCR
Opcode
Source
Form
Address
Mode
Table 10-1. Instruction Set Summary (Continued)
ff
ee ff
2
dd rr
rr
rr
ff rr
rr
ff rr
3A dd
4A
5A
6A ff
7A
9E6A ff
5
3
3
5
4
6
4
1
1
4
3
5
7
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
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Instruction Set Summary
V H I N Z C
INC opr
INCA
INCX
INC opr,X
INC ,X
INC opr,SP
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
Increment
Jump to Subroutine
Load A from M
LDHX #opr
LDHX opr
Load H:X from M
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
LSL opr,SP
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
LSR opr,SP
Logical Shift Right
MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr
Move
MUL
Unsigned multiply
4
1
1
4
3
5
PC ← Jump Address
dd
hh ll
ee ff
ff
2
3
4
3
2
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Unconditional Address
DIR
EXT
– – – – – – IX2
IX1
IX
BD
CD
DD
ED
FD
dd
hh ll
ee ff
ff
4
5
6
5
4
A ← (M)
IMM
DIR
EXT
0 – – ↕ ↕ – IX2
IX1
IX
SP1
SP2
A6
B6
C6
D6
E6
F6
9EE6
9ED6
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
ii jj
dd
3
4
ii
dd
hh ll
ee ff
ff
2
3
4
4
3
2
4
5
H:X ← (M:M + 1)
0 – – ↕ ↕ –
b7
0
DIR
INH
INH
↕ – – ↕ ↕ ↕
IX1
IX
SP1
38 dd
48
58
68 ff
78
9E68 ff
4
1
1
4
3
5
C
DIR
INH
INH
↕ – – 0 ↕ ↕ IX1
IX
SP1
34 dd
44
54
64 ff
74
9E64 ff
4
1
1
4
3
5
b0
0
b7
b0
(M)Destination ← (M)Source
H:X ← (H:X) + 1 (IX+D, DIX+)
X:A ← (X) × (A)
45
55
AE
BE
CE
DE
EE
FE
9EEE
9EDE
X ← (M)
C
IMM
DIR
IMM
DIR
EXT
IX2
0 – – ↕ ↕ –
IX1
IX
SP1
SP2
0 – – ↕ ↕ –
DD
DIX+
IMD
IX+D
– 0 – – – 0 INH
MC68HC908GR8 — Rev 4.0
MOTOROLA
3C dd
4C
5C
6C ff
7C
9E6C ff
BC
CC
DC
EC
FC
Load X from M
Logical Shift Left
(Same as ASL)
DIR
INH
INH
↕ – – ↕ ↕ – IX1
IX
SP1
(M) + 1
(A) + 1
(X) + 1
(M) + 1
(M) + 1
(M) + 1
DIR
EXT
– – – – – – IX2
IX1
IX
Jump
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDA opr,SP
LDA opr,SP
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LDX opr,SP
LDX opr,SP
M←
A←
X←
M←
M←
M←
Cycles
Description
Operand
Operation
Effect on
CCR
Opcode
Source
Form
Address
Mode
Table 10-1. Instruction Set Summary (Continued)
4E
5E
6E
7E
42
ff
ee ff
dd dd
dd
ii dd
dd
5
4
4
4
5
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V H I N Z C
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NEG opr,SP
Negate (Two’s Complement)
NOP
No Operation
NSA
Nibble Swap A
30 dd
40
50
60 ff
70
9E60 ff
Cycles
Description
Operand
Operation
Effect on
CCR
Opcode
Source
Form
Address
Mode
Table 10-1. Instruction Set Summary (Continued)
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
DIR
INH
INH
↕ – – ↕ ↕ ↕
IX1
IX
SP1
4
1
1
4
3
5
None
– – – – – – INH
9D
1
A ← (A[3:0]:A[7:4])
– – – – – – INH
62
3
A ← (A) | (M)
IMM
DIR
EXT
0 – – ↕ ↕ – IX2
IX1
IX
SP1
SP2
AA
BA
CA
DA
EA
FA
9EEA
9EDA
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ORA opr,SP
ORA opr,SP
Inclusive OR A and M
PSHA
Push A onto Stack
Push (A); SP ← (SP) – 1
– – – – – – INH
87
2
PSHH
Push H onto Stack
Push (H); SP ← (SP) – 1
– – – – – – INH
8B
2
PSHX
Push X onto Stack
Push (X); SP ← (SP) – 1
– – – – – – INH
89
2
PULA
Pull A from Stack
SP ← (SP + 1); Pull (A)
– – – – – – INH
86
2
PULH
Pull H from Stack
SP ← (SP + 1); Pull (H)
– – – – – – INH
8A
2
PULX
Pull X from Stack
SP ← (SP + 1); Pull (X)
– – – – – – INH
88
2
C
DIR
INH
INH
↕ – – ↕ ↕ ↕ IX1
IX
SP1
39 dd
49
59
69 ff
79
9E69 ff
4
1
1
4
3
5
DIR
INH
↕ – – ↕ ↕ ↕ INH
IX1
IX
SP1
36 dd
46
56
66 ff
76
9E66 ff
4
1
1
4
3
5
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
ROL opr,SP
Rotate Left through Carry
b7
b0
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
ROR opr,SP
Rotate Right through Carry
RSP
Reset Stack Pointer
SP ← $FF
– – – – – – INH
9C
1
RTI
Return from Interrupt
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
↕ ↕ ↕ ↕ ↕ ↕ INH
80
7
RTS
Return from Subroutine
SP ← SP + 1; Pull (PCH)
SP ← SP + 1; Pull (PCL)
– – – – – – INH
81
4
C
b7
b0
Technical Data
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Central Processing Unit (CPU)
Instruction Set Summary
V H I N Z C
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
SBC opr,SP
SBC opr,SP
Subtract with Carry
SEC
Set Carry Bit
SEI
Set Interrupt Mask
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
STA opr,SP
STA opr,SP
Store A in M
STHX opr
Store H:X in M
STOP
Enable IRQ Pin; Stop Oscillator
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
STX opr,SP
STX opr,SP
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
Store X in M
Subtract
IMM
DIR
EXT
IX2
↕ – – ↕ ↕ ↕ IX1
IX
SP1
SP2
A2
B2
C2
D2
E2
F2
9EE2
9ED2
C←1
– – – – – 1 INH
99
1
I←1
– – 1 – – – INH
9B
2
M ← (A)
DIR
EXT
IX2
0 – – ↕ ↕ – IX1
IX
SP1
SP2
B7
C7
D7
E7
F7
9EE7
9ED7
(M:M + 1) ← (H:X)
0 – – ↕ ↕ – DIR
35
I ← 0; Stop Oscillator
– – 0 – – – INH
8E
M ← (X)
DIR
EXT
IX2
0 – – ↕ ↕ – IX1
IX
SP1
SP2
BF
CF
DF
EF
FF
9EEF
9EDF
dd
hh ll
ee ff
ff
IMM
DIR
EXT
↕ – – ↕ ↕ ↕ IX2
IX1
IX
SP1
SP2
A0
B0
C0
D0
E0
F0
9EE0
9ED0
ii
dd
hh ll
ee ff
ff
– – 1 – – – INH
83
9
A ← (A) – (M) – (C)
A ← (A) – (M)
ii
dd
hh ll
ee ff
ff
Cycles
Description
Operand
Operation
Effect on
CCR
Opcode
Source
Form
Address
Mode
Table 10-1. Instruction Set Summary (Continued)
ff
ee ff
dd
hh ll
ee ff
ff
2
3
4
4
3
2
4
5
ff
ee ff
3
4
4
3
2
4
5
dd
4
1
ff
ee ff
ff
ee ff
3
4
4
3
2
4
5
2
3
4
4
3
2
4
5
SWI
Software Interrupt
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
TAP
Transfer A to CCR
CCR ← (A)
↕ ↕ ↕ ↕ ↕ ↕ INH
84
2
TAX
Transfer A to X
X ← (A)
– – – – – – INH
97
1
TPA
Transfer CCR to A
A ← (CCR)
– – – – – – INH
85
1
MC68HC908GR8 — Rev 4.0
MOTOROLA
Technical Data
Central Processing Unit (CPU)
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V H I N Z C
TST opr
TSTA
TSTX
TST opr,X
TST ,X
TST opr,SP
Test for Negative or Zero
TSX
Transfer SP to H:X
TXA
Transfer X to A
TXS
Transfer H:X to SP
(A) – $00 or (X) – $00 or (M) – $00
DIR
INH
INH
0 – – ↕ ↕ – IX1
IX
SP1
H:X ← (SP) + 1
– – – – – – INH
95
2
A ← (X)
– – – – – – INH
9F
1
(SP) ← (H:X) – 1
– – – – – – INH
94
2
A Accumulatorn
C Carry/borrow bitopr
CCRCondition code registerPC
ddDirect address of operandPCH
dd rrDirect address of operand and relative offset of branch instructionPCL
DDDirect to direct addressing modeREL
DIRDirect addressing moderel
DIX+Direct to indexed with post increment addressing moderr
ee ffHigh and low bytes of offset in indexed, 16-bit offset addressingSP1
EXTExtended addressing modeSP2
ff Offset byte in indexed, 8-bit offset addressingSP
H Half-carry bitU
H Index register high byteV
hh llHigh and low bytes of operand address in extended addressingX
I Interrupt maskZ
ii Immediate operand byte&
IMDImmediate source to direct destination addressing mode|
IMMImmediate addressing mode⊕
INHInherent addressing mode( )
IXIndexed, no offset addressing mode–( )
IX+Indexed, no offset, post increment addressing mode#
IX+DIndexed with post increment to direct addressing mode«
IX1Indexed, 8-bit offset addressing mode←
IX1+Indexed, 8-bit offset, post increment addressing mode?
IX2Indexed, 16-bit offset addressing mode:
MMemory location↕
N Negative bit—
3D dd
4D
5D
6D ff
7D
9E6D ff
Cycles
Description
Operand
Operation
Effect on
CCR
Opcode
Source
Form
Address
Mode
Table 10-1. Instruction Set Summary (Continued)
3
1
1
3
2
4
Any bit
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer, 8-bit offset addressing mode
Stack pointer 16-bit offset addressing mode
Stack pointer
Undefined
Overflow bit
Index register low byte
Zero bit
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Immediate value
Sign extend
Loaded with
If
Concatenated with
Set or cleared
Not affected
10.9 Opcode Map
See Table 10-2.
Technical Data
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155
Technical Data
Central Processing Unit (CPU)
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5
BRSET0
3 DIR
5
BRCLR0
3 DIR
5
BRSET1
3 DIR
5
BRCLR1
3 DIR
5
BRSET2
3 DIR
5
BRCLR2
3 DIR
5
BRSET3
3 DIR
5
BRCLR3
3 DIR
5
BRSET4
3 DIR
5
BRCLR4
3 DIR
5
BRSET5
3 DIR
5
BRCLR5
3 DIR
5
BRSET6
3 DIR
5
BRCLR6
3 DIR
5
BRSET7
3 DIR
5
BRCLR7
3 DIR
0
4
BSET0
2 DIR
4
BCLR0
2 DIR
4
BSET1
2 DIR
4
BCLR1
2 DIR
4
BSET2
2 DIR
4
BCLR2
2 DIR
4
BSET3
2 DIR
4
BCLR3
2 DIR
4
BSET4
2 DIR
4
BCLR4
2 DIR
4
BSET5
2 DIR
4
BCLR5
2 DIR
4
BSET6
2 DIR
4
BCLR6
2 DIR
4
BSET7
2 DIR
4
BCLR7
2 DIR
1
3
BRA
REL
3
BRN
2 REL
3
BHI
2 REL
3
BLS
2 REL
3
BCC
2 REL
3
BCS
2 REL
3
BNE
2 REL
3
BEQ
2 REL
3
BHCC
2 REL
3
BHCS
2 REL
3
BPL
2 REL
3
BMI
2 REL
3
BMC
2 REL
3
BMS
2 REL
3
BIL
2 REL
3
BIH
2 REL
2
2
Branch
REL
4
INH
1
NEGX
1 INH
4
CBEQX
3 IMM
7
DIV
1 INH
1
COMX
1 INH
1
LSRX
1 INH
4
LDHX
2 DIR
1
RORX
1 INH
1
ASRX
1 INH
1
LSLX
1 INH
1
ROLX
1 INH
1
DECX
1 INH
3
DBNZX
2 INH
1
INCX
1 INH
1
TSTX
1 INH
4
MOV
2 DIX+
1
CLRX
1 INH
5
4
NEG
IX1
5
CBEQ
3 IX1+
3
NSA
1 INH
4
COM
2 IX1
4
LSR
2 IX1
3
CPHX
3 IMM
4
ROR
2 IX1
4
ASR
2 IX1
4
LSL
2 IX1
4
ROL
2 IX1
4
DEC
2 IX1
5
DBNZ
3 IX1
4
INC
2 IX1
3
TST
2 IX1
4
MOV
3 IMD
3
CLR
2 IX1
2
6
Read-Modify-Write
INH
IX1
7
IX
9
7
3
RTI
BGE
INH 2 REL
4
3
RTS
BLT
1 INH 2 REL
3
BGT
2 REL
9
3
SWI
BLE
1 INH 2 REL
2
2
TAP
TXS
1 INH 1 INH
1
2
TPA
TSX
1 INH 1 INH
2
PULA
1 INH
2
1
PSHA
TAX
1 INH 1 INH
2
1
PULX
CLC
1 INH 1 INH
2
1
PSHX
SEC
1 INH 1 INH
2
2
PULH
CLI
1 INH 1 INH
2
2
PSHH
SEI
1 INH 1 INH
1
1
CLRH
RSP
1 INH 1 INH
1
NOP
1 INH
1
STOP
*
1 INH
1
1
WAIT
TXA
1 INH 1 INH
1
8
Control
INH
INH
2
2
2
2
2
2
2
2
2
2
2
2
Table 10-2. Opcode Map
0
MSB
3
SUB
DIR
3
CMP
DIR
3
SBC
DIR
3
CPX
DIR
3
AND
DIR
3
BIT
DIR
3
LDA
DIR
3
STA
DIR
3
EOR
DIR
3
ADC
DIR
3
ORA
DIR
3
ADD
DIR
2
JMP
DIR
4
JSR
DIR
3
LDX
DIR
3
STX
DIR
B
DIR
LSB
2
4
BSR
2 REL 2
2
LDX
2 IMM 2
2
AIX
2 IMM 2
2
SUB
IMM
2
CMP
2 IMM
2
SBC
2 IMM
2
CPX
2 IMM
2
AND
2 IMM
2
BIT
2 IMM
2
LDA
2 IMM
2
AIS
2 IMM
2
EOR
2 IMM
2
ADC
2 IMM
2
ORA
2 IMM
2
ADD
2 IMM
2
A
IMM
Low Byte of Opcode in Hexadecimal
5
3
NEG
NEG
SP1 1 IX
6
4
CBEQ
CBEQ
4 SP1 2 IX+
2
DAA
1 INH
5
3
COM
COM
3 SP1 1 IX
5
3
LSR
LSR
3 SP1 1 IX
4
CPHX
2 DIR
5
3
ROR
ROR
3 SP1 1 IX
5
3
ASR
ASR
3 SP1 1 IX
5
3
LSL
LSL
3 SP1 1 IX
5
3
ROL
ROL
3 SP1 1 IX
5
3
DEC
DEC
3 SP1 1 IX
6
4
DBNZ
DBNZ
4 SP1 2 IX
5
3
INC
INC
3 SP1 1 IX
4
2
TST
TST
3 SP1 1 IX
4
MOV
2 IX+D
4
2
CLR
CLR
3 SP1 1 IX
3
9E6
SP1
SP1 Stack Pointer, 8-Bit Offset
SP2 Stack Pointer, 16-Bit Offset
IX+ Indexed, No Offset with
Post Increment
IX1+ Indexed, 1-Byte Offset with
Post Increment
4
1
NEG
NEGA
DIR 1 INH
5
4
CBEQ CBEQA
3 DIR 3 IMM
5
MUL
1 INH
4
1
COM
COMA
2 DIR 1 INH
4
1
LSR
LSRA
2 DIR 1 INH
4
3
STHX
LDHX
2 DIR 3 IMM
4
1
ROR
RORA
2 DIR 1 INH
4
1
ASR
ASRA
2 DIR 1 INH
4
1
LSL
LSLA
2 DIR 1 INH
4
1
ROL
ROLA
2 DIR 1 INH
4
1
DEC
DECA
2 DIR 1 INH
5
3
DBNZ DBNZA
3 DIR 2 INH
4
1
INC
INCA
2 DIR 1 INH
3
1
TST
TSTA
2 DIR 1 INH
5
MOV
3 DD
3
1
CLR
CLRA
2 DIR 1 INH
2
3
DIR
INH Inherent
REL Relative
IMM Immediate
IX
Indexed, No Offset
DIR Direct
IX1 Indexed, 8-Bit Offset
EXT Extended
IX2 Indexed, 16-Bit Offset
DD Direct-Direct
IMD Immediate-Direct
IX+D Indexed-Direct DIX+ Direct-Indexed
*Pre-byte for stack pointer indexed instructions
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
LSB
MSB
Bit Manipulation
DIR
DIR
2
E
3
SUB
IX1
3
CMP
2 IX1
3
SBC
2 IX1
3
CPX
2 IX1
3
AND
2 IX1
3
BIT
2 IX1
3
LDA
2 IX1
3
STA
2 IX1
3
EOR
2 IX1
3
ADC
2 IX1
3
ORA
2 IX1
3
ADD
2 IX1
3
JMP
2 IX1
5
JSR
2 IX1
5
3
LDX
LDX
4 SP2 2 IX1
5
3
STX
STX
4 SP2 2 IX1
5
SUB
SP2
5
CMP
4 SP2
5
SBC
4 SP2
5
CPX
4 SP2
5
AND
4 SP2
5
BIT
4 SP2
5
LDA
4 SP2
5
STA
4 SP2
5
EOR
4 SP2
5
ADC
4 SP2
5
ORA
4 SP2
5
ADD
4 SP2
4
9ED
IX1
4
SUB
SP1
4
CMP
SP1
4
SBC
SP1
4
CPX
SP1
4
AND
SP1
4
BIT
SP1
4
LDA
SP1
4
STA
SP1
4
EOR
SP1
4
ADC
SP1
4
ORA
SP1
4
ADD
SP1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
LDX
3 SP1 1
4
STX
3 SP1 1
3
3
3
3
3
3
3
3
3
3
3
3
9EE
SP1
High Byte of Opcode in Hexadecimal
4
SUB
IX2
4
CMP
3 IX2
4
SBC
3 IX2
4
CPX
3 IX2
4
AND
3 IX2
4
BIT
3 IX2
4
LDA
3 IX2
4
STA
3 IX2
4
EOR
3 IX2
4
ADC
3 IX2
4
ORA
3 IX2
4
ADD
3 IX2
4
JMP
3 IX2
6
JSR
3 IX2
4
LDX
3 IX2
4
STX
3 IX2
3
D
Register/Memory
IX2
SP2
5
Cycles
BRSET0 Opcode Mnemonic
3 DIR Number of Bytes / Addressing Mode
0
4
SUB
EXT
4
CMP
3 EXT
4
SBC
3 EXT
4
CPX
3 EXT
4
AND
3 EXT
4
BIT
3 EXT
4
LDA
3 EXT
4
STA
3 EXT
4
EOR
3 EXT
4
ADC
3 EXT
4
ORA
3 EXT
4
ADD
3 EXT
3
JMP
3 EXT
5
JSR
3 EXT
4
LDX
3 EXT
4
STX
3 EXT
3
C
EXT
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2
SUB
IX
2
CMP
IX
2
SBC
IX
2
CPX
IX
2
AND
IX
2
BIT
IX
2
LDA
IX
2
STA
IX
2
EOR
IX
2
ADC
IX
2
ORA
IX
2
ADD
IX
2
JMP
IX
4
JSR
IX
2
LDX
IX
2
STX
IX
F
IX
Freescale Semiconductor, Inc.
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MC68HC908GR8 — Rev 4.0
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Technical Data — MC68HC908GR8
Section 11. Flash Memory
11.1 Contents
11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
11.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
11.4
FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
11.5
FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . 160
11.6
FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . 161
11.7
FLASH Program/Read Operation . . . . . . . . . . . . . . . . . . . . . .162
11.8
FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
11.9
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
11.10 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
11.2 Introduction
This section describes the operation of the embedded FLASH memory.
This memory can be read, programmed, and erased from a single
external supply. The program, erase, and read operations are enabled
through the use of an internal charge pump.
11.3 Functional Description
The FLASH memory is an array of 7,680 bytes for the MC68HC908GR8
or 4,096 bytes for the MC68HC908GR4 with an additional 36 bytes of
user vectors and one byte used for block protection. An erased bit reads
as logic 1 and a programmed bit reads as a logic 0. The program and
erase operations are facilitated through control bits in the Flash Control
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Flash Memory
Register (FLCR). Details for these operations appear later in this
section.
The FLASH is organized internally as a 8192-word by 8-bit CMOS page
erase, byte (8-bit) program Embedded Flash Memory. Each page
consists of 64 bytes. The page erase operation erases all words within
a page. A page is composed of two adjacent rows.
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The address ranges for the user memory and vectors are as follows:
•
$E000–$FDFF; user memory for the MC68HC908GR8
$EE00–$FDFF; user memory for the MC68HC908GR4.
•
$FF7E; FLASH block protect register.
•
$FE08; FLASH control register.
•
$FFDC–$FFFF; these locations are reserved for user-defined
interrupt and reset vectors.
Programming tools are available from Motorola. Contact your local
Motorola representative for more information.
NOTE:
A security feature prevents viewing of the FLASH contents.(1)
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
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Flash Memory
FLASH Control Register
11.4 FLASH Control Register
The FLASH control register (FLCR) controls FLASH program and erase
operations.
Address:
Read:
$FE08
Bit 7
6
5
4
0
0
0
0
3
2
1
Bit 0
HVEN
MASS
ERASE
PGM
0
0
0
0
Write:
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Reset:
0
0
0
0
Figure 11-1. FLASH Control Register (FLCR)
HVEN — High-Voltage Enable Bit
This read/write bit enables the charge pump to drive high voltages for
program and erase operations in the array. HVEN can only be set if
either PGM = 1 or ERASE = 1 and the proper sequence for program
or erase is followed.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
MASS — Mass Erase Control Bit
Setting this read/write bit configures the 8K byte FLASH array for
mass erase operation.
1 = MASS erase operation selected
0 = MASS erase operation unselected
ERASE — Erase Control Bit
This read/write bit configures the memory for erase operation.
ERASE is interlocked with the PGM bit such that both bits cannot be
equal to 1 or set to 1 at the same time.
1 = Erase operation selected
0 = Erase operation unselected
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Flash Memory
PGM — Program Control Bit
This read/write bit configures the memory for program operation.
PGM is interlocked with the ERASE bit such that both bits cannot be
equal to 1 or set to 1 at the same time.
1 = Program operation selected
0 = Program operation unselected
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11.5 FLASH Page Erase Operation
Use this step-by-step procedure to erase a page (64 bytes) of FLASH
memory to read as logic 1:
1. Set the ERASE bit, and clear the MASS bit in the FLASH control
register.
2. Read the FLASH block protect register.
3. Write any data to any FLASH address within the page address
range desired.
4. Wait for a time, tnvs (min. 10µs)
5. Set the HVEN bit.
6. Wait for a time, tErase (min. 1ms)
7. Clear the ERASE bit.
8. Wait for a time, tnvh (min. 5µs)
9. Clear the HVEN bit.
10. After a time, trcv (typ. 1µs), the memory can be accessed again in
read mode.
NOTE:
While these operations must be performed in the order shown, other
unrelated operations may occur between the steps.
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Flash Memory
FLASH Mass Erase Operation
11.6 FLASH Mass Erase Operation
Use this step-by-step procedure to erase entire FLASH memory to read
as logic 1:
1. Set both the ERASE bit, and the MASS bit in the FLASH control
register.
2. Read from the FLASH block protect register.
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3. Write any data to any FLASH address* within the FLASH memory
address range.
4. Wait for a time, tnvs (min. 10µs)
5. Set the HVEN bit.
6. Wait for a time, tMErase (min. 4ms)
7. Clear the ERASE bit.
8. Wait for a time, tnvhl (min. 100µs)
9. Clear the HVEN bit.
10. After a time, trcv (min. 1µs), the memory can be accessed again in
read mode.
* When in Monitor mode, with security sequence failed Monitor ROM (MON), write to the FLASH
block protect register instead of any FLASH address.
NOTE:
Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order shown, other unrelated operations may
occur between the steps.
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Flash Memory
11.7 FLASH Program/Read Operation
Programming of the FLASH memory is done on a row basis. A row
consists of 32 consecutive bytes starting from addresses $XX00,
$XX20, $XX40, $XX60, $XX80, $XXA0, $XXC0, and $XXE0. Use this
step-by-step procedure to program a row of FLASH memory (Figure 112 is a flowchart representation):
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1. Set the PGM bit. This configures the memory for program
operation and enables the latching of address and data for
programming.
2. Read from the FLASH block protect register.
3. Write any data to any FLASH address within the row address
range desired.
4. Wait for a time, tnvs (min. 10µs).
5. Set the HVEN bit.
6. Wait for a time, tpgs (min. 5µs).
7. Write data to the FLASH address to be programmed.*
8. Wait for a time, tPROG (min. 30µs).
9. Repeat step 7 and 8 until all the bytes within the row are
programmed.
10. Clear the PGM bit.*
11. Wait for a time, tnvh (min. 5µs).
12. Clear the HVEN bit.
13. After time, trcv (min. 1µs), the memory can be accessed in read
mode again.
* The time between each FLASH address change, or the time between the last FLASH address
programmed to clearing PGM bit, must not exceed the maximum programming time, tPROG max.
This program sequence is repeated throughout the memory until all data
is programmed.
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Flash Memory
FLASH Block Protection
NOTE:
Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order shown, other unrelated operations may
occur between the steps. Do not exceed tPROG maximum. See Memory
Characteristics.
11.8 FLASH Block Protection
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Due to the ability of the on-board charge pump to erase and program the
FLASH memory in the target application, provision is made for protecting
a block of memory from unintentional erase or program operations due
to system malfunction. This protection is done by using of a FLASH
Block Protect Register (FLBPR). The FLBPR determines the range of
the FLASH memory which is to be protected. The range of the protected
area starts from a location defined by FLBPR and ends at the bottom of
the FLASH memory ($FFFF). When the memory is protected, the HVEN
bit cannot be set in either ERASE or PROGRAM operations.
NOTE:
In performing a program or erase operation, the FLASH block protect
register must be read after setting the PGM or ERASE bit and before
asserting the HVEN bit
When the FLBPR is programmed with all 0s, the entire memory is
protected from being programmed and erased. When all the bits are
erased (all 1s), the entire memory is accessible for program and erase.
When bits within the FLBPR are programmed, they lock a block of
memory with address ranges as shown in FLASH Block Protect
Register. Once the FLBPR is programmed with a value other than $FF,
any erase or program of the FLBPR or the protected block of FLASH
memory is prohibited. The FLBPR itself can be erased or programmed
only with an external voltage, VTST, present on the IRQ pin. This voltage
also allows entry from reset into the monitor mode.
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Flash Memory
1
Algorithm for programming
a row (32 bytes) of FLASH memory
2
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3
Set PGM bit
Read the FLASH block protect register
Write any data to any FLASH address
within the row address range desired
4
Wait for a time, tnvs
5
Set HVEN bit
6
Wait for a time, tpgs
7
8
Write data to the FLASH address
to be programmed
Wait for a time, tPROG
Completed
programming
this row?
Y
N
NOTE:
The time between each FLASH address change (step 7 to step 7), or
the time between the last FLASH address programmed
to clearing PGM bit (step 7 to step 10)
must not exceed the maximum programming
time, tPROG max.
10
Clear PGM bit
11
Wait for a time, tnvh
12
Clear HVEN bit
13
Wait for a time, trcv
This row program algorithm assumes the row/s
to be programmed are initially erased.
End of programming
Figure 11-2. FLASH Programming Flowchart
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Flash Memory
FLASH Block Protection
11.8.1 FLASH Block Protect Register
The FLASH block protect register (FLBPR) is implemented as a byte
within the FLASH memory, and therefore can only be written during a
programming sequence of the FLASH memory. The value in this register
determines the starting location of the protected range within the FLASH
memory.
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Address:
$FF7E
Bit 7
6
5
4
3
2
1
Bit 0
BPR7
BPR6
BPR5
BPR4
BPR3
BPR2
BPR1
BPR0
U
U
U
U
U
U
U
U
Read:
Write:
Reset:
U = Unaffected by reset. Initial value from factory is 1.
Write to this register is by a programming sequence to the FLASH memory.
Figure 11-3. FLASH Block Protect Register (FLBPR)
BPR[7:0] — FLASH Block Protect Bits
These eight bits represent bits [13:6] of a 16-bit memory address.
Bits [15:14] are logic 1s and bits [5:0] are logic 0s.
The resultant 16-bit address is used for specifying the start address
of the FLASH memory for block protection. The FLASH is protected
from this start address to the end of FLASH memory, at $FFFF. With
this mechanism, the protect start address can be $XX00, $XX40,
$XX80, and $XXC0 (64 bytes page boundaries) within the FLASH
memory.
16-bit memory address
Start address of FLASH block protect
1 1
FLBPR value
0
0
0
0
0
0
Figure 11-4. FLASH Block Protect Start Address
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Flash Memory
Examples of protect start address:
Table 11-1. Examples of protect start address:
BPR[7:0]
Start of Address of Protect Range
$80
The entire FLASH memory is protected.
$81 (1000 0001)
$E040 (1110 0000 0100 0000)
$82 (1000 0010)
$E080 (1110 0000 1000 0000)
and so on...
$FE (1111 1110)
$FF80 (1111 1111 1000 0000)
$FF
The entire FLASH memory is not protected.
Note:
The end address of the protected range is always $FFFF.
11.9 Wait Mode
Putting the MCU into wait mode while the FLASH is in read mode does
not affect the operation of the FLASH memory directly, but there will not
be any memory activity since the CPU is inactive.
The WAIT instruction should not be executed while performing a
program or erase operation on the FLASH, otherwise the operation will
discontinue, and the FLASH will be on Standby Mode.
11.10 STOP Mode
Putting the MCU into stop mode while the FLASH is in read mode does
not affect the operation of the FLASH memory directly, but there will not
be any memory activity since the CPU is inactive.
The STOP instruction should not be executed while performing a
program or erase operation on the FLASH, otherwise the operation will
discontinue, and the FLASH will be on Standby Mode
NOTE:
Standby Mode is the power saving mode of the FLASH module in which
all internal control signals to the FLASH are inactive and the current
consumption of the FLASH is at a minimum.
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Technical Data — MC68HC908GR8
Section 12. External Interrupt (IRQ)
12.1 Contents
12.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
12.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
12.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
12.5
IRQ1 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
12.6
IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .171
12.7
IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . 172
12.2 Introduction
The IRQ (external interrupt) module provides a maskable interrupt input.
12.3 Features
Features of the IRQ module include:
•
A dedicated external interrupt pin (IRQ1)
•
IRQ interrupt control bits
•
Hysteresis buffer
•
Programmable edge-only or edge and level interrupt sensitivity
•
Automatic interrupt acknowledge
•
Internal pullup resistor
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External Interrupt (IRQ)
12.4 Functional Description
A logic 0 applied to the external interrupt pin can latch a CPU interrupt
request. Figure 12-1 shows the structure of the IRQ module.
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Interrupt signals on the IRQ1 pin are latched into the IRQ latch. An
interrupt latch remains set until one of the following actions occurs:
•
Vector fetch — A vector fetch automatically generates an interrupt
acknowledge signal that clears the latch that caused the vector
fetch.
•
Software clear — Software can clear an interrupt latch by writing
to the appropriate acknowledge bit in the interrupt status and
control register (INTSCR). Writing a logic 1 to the ACK bit clears
the IRQ latch.
•
Reset — A reset automatically clears the interrupt latch.
The external interrupt pin is falling-edge-triggered and is softwareconfigurable to be either falling-edge or falling-edge and low-leveltriggered. The MODE bit in the INTSCR controls the triggering sensitivity
of the IRQ1 pin.
When an interrupt pin is edge-triggered only, the interrupt remains set
until a vector fetch, software clear, or reset occurs.
When an interrupt pin is both falling-edge and low-level-triggered, the
interrupt remains set until both of the following occur:
•
Vector fetch or software clear
•
Return of the interrupt pin to logic 1
The vector fetch or software clear may occur before or after the interrupt
pin returns to logic 1. As long as the pin is low, the interrupt request
remains pending. A reset will clear the latch and the MODE control bit,
thereby clearing the interrupt even if the pin stays low.
When set, the IMASK bit in the INTSCR mask all external interrupt
requests. A latched interrupt request is not presented to the interrupt
priority logic unless the IMASK bit is clear.
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External Interrupt (IRQ)
Functional Description
NOTE:
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests.
ACK
RESET
INTERNAL ADDRESS BUS
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TO CPU FOR
BIL/BIH
INSTRUCTIONS
VECTOR
FETCH
DECODER
VDD
INTERNAL
PULLUP
DEVICE
VDD
IRQF
D
IRQ1
CLR
Q
SYNCHRONIZER
CK
IRQ
INTERRUPT
REQUEST
IRQ
FF
IMASK
MODE
TO MODE
SELECT
LOGIC
HIGH
VOLTAGE
DETECT
Figure 12-1. IRQ Module Block Diagram
Addr.
Register Name
$001D
Read:
IRQ Status and Control
Write:
Register (INTSCR)
Reset:
Bit 7
6
5
4
3
2
0
0
0
0
IRQF
0
ACK
0
0
0
0
0
0
1
Bit 0
IMASK
MODE
0
0
= Unimplemented
Figure 12-2. IRQ I/O Register Summary
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External Interrupt (IRQ)
12.5 IRQ1 Pin
A logic 0 on the IRQ1 pin can latch an interrupt request into the IRQ
latch. A vector fetch, software clear, or reset clears the IRQ latch.
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If the MODE bit is set, the IRQ1 pin is both falling-edge-sensitive and
low-level-sensitive. With MODE set, both of the following actions must
occur to clear IRQ:
•
Vector fetch or software clear — A vector fetch generates an
interrupt acknowledge signal to clear the latch. Software may
generate the interrupt acknowledge signal by writing a logic 1 to
the ACK bit in the interrupt status and control register (INTSCR).
The ACK bit is useful in applications that poll the IRQ1 pin and
require software to clear the IRQ latch. Writing to the ACK bit prior
to leaving an interrupt service routine can also prevent spurious
interrupts due to noise. Setting ACK does not affect subsequent
transitions on the IRQ1 pin. A falling edge that occurs after writing
to the ACK bit another interrupt request. If the IRQ mask bit,
IMASK, is clear, the CPU loads the program counter with the
vector address at locations $FFFA and $FFFB.
•
Return of the IRQ1 pin to logic 1 — As long as the IRQ1 pin is at
logic 0, IRQ remains active.
The vector fetch or software clear and the return of the IRQ1 pin to logic
1 may occur in any order. The interrupt request remains pending as long
as the IRQ1 pin is at logic 0. A reset will clear the latch and the MODE
control bit, thereby clearing the interrupt even if the pin stays low.
If the MODE bit is clear, the IRQ1 pin is falling-edge-sensitive only. With
MODE clear, a vector fetch or software clear immediately clears the IRQ
latch.
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External Interrupt (IRQ)
IRQ Module During Break Interrupts
The IRQF bit in the INTSCR register can be used to check for pending
interrupts. The IRQF bit is not affected by the IMASK bit, which makes it
useful in applications where polling is preferred.
Use the BIH or BIL instruction to read the logic level on the IRQ1 pin.
NOTE:
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
12.6 IRQ Module During Break Interrupts
The BCFE bit in the SIM break flag control register (SBFCR) enables
software to clear the latch during the break state. See Break Module
(BRK).
To allow software to clear the IRQ latch during a break interrupt, write a
logic 1 to the BCFE bit. If a latch is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect CPU interrupt flags during the break state, write a logic 0 to
the BCFE bit. With BCFE at logic 0 (its default state), writing to the ACK
bit in the IRQ status and control register during the break state has no
effect on the IRQ interrupt flags.
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External Interrupt (IRQ)
12.7 IRQ Status and Control Register
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The IRQ status and control register (INTSCR) controls and monitors
operation of the IRQ module. The INTSCR:
•
Shows the state of the IRQ flag
•
Clears the IRQ latch
•
Masks IRQ interrupt request
•
Controls triggering sensitivity of the IRQ1 interrupt pin
Address:
$001D
Bit 7
6
5
4
Read:
3
2
IRQF
0
Write:
Reset:
1
Bit 0
IMASK
MODE
0
0
ACK
0
0
0
0
0
0
= Unimplemented
Figure 12-3. IRQ Status and Control Register (INTSCR)
IRQF — IRQ Flag Bit
This read-only status bit is high when the IRQ interrupt is pending.
1 = IRQ interrupt pending
0 = IRQ interrupt not pending
ACK — IRQ Interrupt Request Acknowledge Bit
Writing a logic 1 to this write-only bit clears the IRQ latch. ACK always
reads as logic 0. Reset clears ACK.
IMASK — IRQ Interrupt Mask Bit
Writing a logic 1 to this read/write bit disables IRQ interrupt requests.
Reset clears IMASK.
1 = IRQ interrupt requests disabled
0 = IRQ interrupt requests enabled
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External Interrupt (IRQ)
IRQ Status and Control Register
MODE — IRQ Edge/Level Select Bit
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This read/write bit controls the triggering sensitivity of the IRQ1 pin.
Reset clears MODE.
1 = IRQ1 interrupt requests on falling edges and low levels
0 = IRQ1 interrupt requests on falling edges only
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External Interrupt (IRQ)
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Section 13. Keyboard Interrupt (KBI)
13.1 Contents
13.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
13.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
13.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
13.5
Keyboard Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
13.6
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
13.7
Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .180
13.8
I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
13.2 Introduction
The keyboard interrupt module (KBI) provides four independently
maskable external interrupts.
13.3 Features
•
Four keyboard interrupt pins with separate keyboard interrupt
enable bits and one keyboard interrupt mask
•
Hysteresis buffers
•
Programmable edge-only or edge- and level- interrupt sensitivity
•
Exit from low-power modes
•
I/O (input/output) port bit(s) software configurable with pullup
device(s) if configured as input port bit(s)
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Keyboard Interrupt (KBI)
13.4 Functional Description
Writing to the KBIE3–KBIE0 bits in the keyboard interrupt enable register
independently enables or disables each port A pin as a keyboard
interrupt pin. Enabling a keyboard interrupt pin also enables its internal
pullup device. A logic 0 applied to an enabled keyboard interrupt pin
latches a keyboard interrupt request.
Freescale Semiconductor, Inc...
A keyboard interrupt is latched when one or more keyboard pins goes
low after all were high. The MODEK bit in the keyboard status and
control register controls the triggering mode of the keyboard interrupt.
•
If the keyboard interrupt is edge-sensitive only, a falling edge on a
keyboard pin does not latch an interrupt request if another
keyboard pin is already low. To prevent losing an interrupt request
on one pin because another pin is still low, software can disable
the latter pin while it is low.
•
If the keyboard interrupt is falling-edge and low-level sensitive, an
interrupt request is present as long as any keyboard interrupt pin
is low and the pin is keyboard interrupt enabled.
Technical Data
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Keyboard Interrupt (KBI)
Functional Description
INTERNAL BUS
KBD0
ACKK
VDD
VECTOR FETCH
DECODER
KEYF
RESET
.
TO PULLUP
ENABLE
D
CLR
Q
SYNCHRONIZER
.
CK
KB0IE
KEYBOARD
INTERRUPT
REQUEST
.
KEYBOARD
INTERRUPT FF
KBD3
IMASKK
MODEK
TO PULLUP
ENABLE
KB3IE
Figure 13-1. Keyboard Module Block Diagram
Addr.
$001A
Register Name
Read:
Keyboard Status
and Control Register Write:
(INTKBSCR)
Reset:
Bit 7
6
5
4
3
2
0
0
0
0
KEYF
0
1
Bit 0
IMASKK
MODEK
ACKK
0
0
0
0
0
0
0
0
KBIE3
KBIE2
KBIE1
KBIE0
0
0
0
0
Read:
$001B
Keyboard Interrupt Enable
Write:
Register (INTKBIER)
Reset:
= Unimplemented
Figure 13-2. I/O Register Summary
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Keyboard Interrupt (KBI)
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If the MODEK bit is set, the keyboard interrupt pins are both falling edgeand low-level sensitive, and both of the following actions must occur to
clear a keyboard interrupt request:
•
Vector fetch or software clear — A vector fetch generates an
interrupt acknowledge signal to clear the interrupt request.
Software may generate the interrupt acknowledge signal by
writing a logic 1 to the ACKK bit in the keyboard status and control
register (INTKBSCR). The ACKK bit is useful in applications that
poll the keyboard interrupt pins and require software to clear the
keyboard interrupt request. Writing to the ACKK bit prior to leaving
an interrupt service routine can also prevent spurious interrupts
due to noise. Setting ACKK does not affect subsequent transitions
on the keyboard interrupt pins. A falling edge that occurs after
writing to the ACKK bit latches another interrupt request. If the
keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the
program counter with the vector address at locations $FFDE and
$FFDF.
•
Return of all enabled keyboard interrupt pins to logic 1 — As long
as any enabled keyboard interrupt pin is at logic 0, the keyboard
interrupt remains set.
The vector fetch or software clear and the return of all enabled keyboard
interrupt pins to logic 1 may occur in any order.
If the MODEK bit is clear, the keyboard interrupt pin is falling-edgesensitive only. With MODEK clear, a vector fetch or software clear
immediately clears the keyboard interrupt request.
Reset clears the keyboard interrupt request and the MODEK bit, clearing
the interrupt request even if a keyboard interrupt pin stays at logic 0.
The keyboard flag bit (KEYF) in the keyboard status and control register
can be used to see if a pending interrupt exists. The KEYF bit is not
affected by the keyboard interrupt mask bit (IMASKK) which makes it
useful in applications where polling is preferred.
To determine the logic level on a keyboard interrupt pin, use the data
direction register to configure the pin as an input and read the data
register.
Technical Data
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Keyboard Interrupt (KBI)
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Keyboard Interrupt (KBI)
Keyboard Initialization
NOTE:
Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding
keyboard interrupt pin to be an input, overriding the data direction
register. However, the data direction register bit must be a logic 0 for
software to read the pin.
13.5 Keyboard Initialization
Freescale Semiconductor, Inc...
When a keyboard interrupt pin is enabled, it takes time for the internal
pullup to reach a logic 1. Therefore, a false interrupt can occur as soon
as the pin is enabled.
To prevent a false interrupt on keyboard initialization:
1. Mask keyboard interrupts by setting the IMASKK bit in the
keyboard status and control register.
2. Enable the KBI pins by setting the appropriate KBIEx bits in the
keyboard interrupt enable register.
3. Write to the ACKK bit in the keyboard status and control register
to clear any false interrupts.
4. Clear the IMASKK bit.
An interrupt signal on an edge-triggered pin can be acknowledged
immediately after enabling the pin. An interrupt signal on an edge- and
level-triggered interrupt pin must be acknowledged after a delay that
depends on the external load.
Another way to avoid a false interrupt is:
1. Configure the keyboard pins as outputs by setting the appropriate
DDRA bits in data direction register A.
2. Write logic 1s to the appropriate port A data register bits.
3. Enable the KBI pins by setting the appropriate KBIEx bits in the
keyboard interrupt enable register.
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Keyboard Interrupt (KBI)
13.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low powerconsumption standby modes.
13.6.1 Wait Mode
The keyboard module remains active in wait mode. Clearing the
IMASKK bit in the keyboard status and control register enables keyboard
interrupt requests to bring the MCU out of wait mode.
13.6.2 Stop Mode
The keyboard module remains active in stop mode. Clearing the
IMASKK bit in the keyboard status and control register enables keyboard
interrupt requests to bring the MCU out of stop mode.
13.7 Keyboard Module During Break Interrupts
The system integration module (SIM) controls whether the keyboard
interrupt latch can be cleared during the break state. The BCFE bit in the
SIM break flag control register (SBFCR) enables software to clear status
bits during the break state.
To allow software to clear the keyboard interrupt latch during a break
interrupt, write a logic 1 to the BCFE bit. If a latch is cleared during the
break state, it remains cleared when the MCU exits the break state.
To protect the latch during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), writing to the keyboard
acknowledge bit (ACKK) in the keyboard status and control register
during the break state has no effect. See Keyboard Status and Control
Register.
Technical Data
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Keyboard Interrupt (KBI)
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Keyboard Interrupt (KBI)
I/O Registers
13.8 I/O Registers
These registers control and monitor operation of the keyboard module:
•
Keyboard status and control register (INTKBSCR)
•
Keyboard interrupt enable register (INTKBIER)
13.8.1 Keyboard Status and Control Register
Freescale Semiconductor, Inc...
The keyboard status and control register:
•
Flags keyboard interrupt requests
•
Acknowledges keyboard interrupt requests
•
Masks keyboard interrupt requests
•
Controls keyboard interrupt triggering sensitivity
Address: $001A
Read:
Bit 7
6
5
4
3
2
0
0
0
0
KEYF
0
Write:
Reset:
1
Bit 0
IMASKK
MODEK
0
0
ACKK
0
0
0
0
0
0
= Unimplemented
Figure 13-3. Keyboard Status and Control Register (INTKBSCR)
Bits 7–4 — Not used
These read-only bits always read as logic 0s.
KEYF — Keyboard Flag Bit
This read-only bit is set when a keyboard interrupt is pending. Reset
clears the KEYF bit.
1 = Keyboard interrupt pending
0 = No keyboard interrupt pending
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Keyboard Interrupt (KBI)
ACKK — Keyboard Acknowledge Bit
Writing a logic 1 to this write-only bit clears the keyboard interrupt
request. ACKK always reads as logic 0. Reset clears ACKK.
IMASKK — Keyboard Interrupt Mask Bit
Writing a logic 1 to this read/write bit prevents the output of the
keyboard interrupt mask from generating interrupt requests. Reset
clears the IMASKK bit.
1 = Keyboard interrupt requests masked
0 = Keyboard interrupt requests not masked
MODEK — Keyboard Triggering Sensitivity Bit
This read/write bit controls the triggering sensitivity of the keyboard
interrupt pins. Reset clears MODEK.
1 = Keyboard interrupt requests on falling edges and low levels
0 = Keyboard interrupt requests on falling edges only
13.8.2 Keyboard Interrupt Enable Register
The keyboard interrupt enable register enables or disables each port A
pin to operate as a keyboard interrupt pin.
Address: $001B
Bit 7
6
5
4
3
2
1
Bit 0
KBIE3
KBIE2
KBIE1
KBIE0
0
0
0
0
Read:
Write:
Reset:
Figure 13-4. Keyboard Interrupt Enable Register (INTKBIER)
KBIE3–KBIE0 — Keyboard Interrupt Enable Bits
Each of these read/write bits enables the corresponding keyboard
interrupt pin to latch interrupt requests. Reset clears the keyboard
interrupt enable register.
1 = PTAx pin enabled as keyboard interrupt pin
0 = PTAx pin not enabled as keyboard interrupt pin
Technical Data
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MC68HC908GR8 — Rev 4.0
Keyboard Interrupt (KBI)
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Technical Data — MC68HC908GR8
Section 14. Low-Voltage Inhibit (LVI)
14.1 Contents
14.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
14.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
14.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
14.5
LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
14.6
LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
14.7
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
14.2 Introduction
This section describes the low-voltage inhibit (LVI) module, which
monitors the voltage on the VDD pin and can force a reset when the VDD
voltage falls below the LVI trip falling voltage, VTRIPF.
14.3 Features
Features of the LVI module include:
•
Programmable LVI reset
•
Selectable LVI trip voltage
•
Programmable stop mode operation
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Low-Voltage Inhibit (LVI)
14.4 Functional Description
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Figure 14-1 shows the structure of the LVI module. The LVI is enabled
out of reset. The LVI module contains a bandgap reference circuit and
comparator. Clearing the LVI power disable bit, LVIPWRD, enables the
LVI to monitor VDD voltage. Clearing the LVI reset disable bit, LVIRSTD,
enables the LVI module to generate a reset when VDD falls below the trip
point voltage, VTRIPF. Setting the LVI enable in stop mode bit, LVISTOP,
enables the LVI to operate in stop mode. Setting the LVI 5V or 3V trip
point bit, LVI5OR3, enables VTRIPF to be configured for 5V operation.
Clearing the LVI5OR3 bit enables VTRIPF to be configured for 3V
operation. The actual trip points are shown in Electrical Specifications.
NOTE:
After a power-on reset (POR) the LVI’s default mode of operation is 3 V.
If a 5V system is used, the user must set the LVI5OR3 bit to raise the trip
point to 5V operation. Note that this must be done after every POR since
the default will revert back to 3V mode after each POR. If the VDD supply
is below the 5V mode trip voltage but above the 3V mode trip voltage
when POR is released, the part will operate because VTRIPF defaults to
3V mode after a POR. So, in a 5V system care must be taken to ensure
that VDD is above the 5V mode trip voltage after POR is released.
NOTE:
If the user requires 5V mode and sets the LVI5OR3 bit after a POR while
the VDD supply is not above the VTRIPR for 5V mode, the MCU will
immediately go into reset. The LVI in this case will hold the part in reset
until either VDD goes above the rising 5V trip point, VTRIPR, which will
release reset or VDD decreases to approximately 0 V which will re-trigger
the POR and reset the trip point to 3V operation.
Technical Data
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MC68HC908GR8 — Rev 4.0
Low-Voltage Inhibit (LVI)
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Low-Voltage Inhibit (LVI)
Functional Description
LVISTOP, LVIPWRD, LVI5OR3, and LVIRSTD are in the configuration
register (MOR1). See Configuration Register (CONFIG) for details of the
LVI’s configuration bits. Once an LVI reset occurs, the MCU remains in
reset until VDD rises above a voltage, VTRIPR, which causes the MCU to
exit reset. See Low-Voltage Inhibit (LVI) Reset for details of the
interaction between the SIM and the LVI. The output of the comparator
controls the state of the LVIOUT flag in the LVI status register (LVISR).
Freescale Semiconductor, Inc...
An LVI reset also drives the RST pin low to provide low-voltage
protection to external peripheral devices.
VDD
STOP INSTRUCTION
LVISTOP
FROM CONFIG
FROM CONFIG
LVIRSTD
LVIPWRD
FROM CONFIG
LOW VDD
DETECTOR
VDD > LVITrip = 0
LVI RESET
VDD ≤ LVITrip = 1
LVIOUT
LVI5OR3
FROM CONFIG
Figure 14-1. LVI Module Block Diagram
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Low-Voltage Inhibit (LVI)
Addr.
$FE0C
Register Name
Bit 7
Read: LVIOUT
LVI Status Register
Write:
(LVISR)
Reset:
0
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-2. LVI I/O Register Summary
14.4.1 Polled LVI Operation
In applications that can operate at VDD levels below the VTRIPF level,
software can monitor VDD by polling the LVIOUT bit. In the configuration
register, the LVIPWRD bit must be at logic 0 to enable the LVI module,
and the LVIRSTD bit must be at logic 1 to disable LVI resets.
14.4.2 Forced Reset Operation
In applications that require VDD to remain above the VTRIPF level,
enabling LVI resets allows the LVI module to reset the MCU when VDD
falls below the VTRIPF level. In the configuration register, the LVIPWRD
and LVIRSTD bits must be at logic 0 to enable the LVI module and to
enable LVI resets.
14.4.3 Voltage Hysteresis Protection
Once the LVI has triggered (by having VDD fall below VTRIPF), the LVI
will maintain a reset condition until VDD rises above the rising trip point
voltage, VTRIPR. This prevents a condition in which the MCU is
continually entering and exiting reset if VDD is approximately equal to
VTRIPF. VTRIPR is greater than VTRIPF by the hysteresis voltage, VHYS.
Technical Data
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Low-Voltage Inhibit (LVI)
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Low-Voltage Inhibit (LVI)
LVI Status Register
14.4.4 LVI Trip Selection
The LVI5OR3 bit in the configuration register selects whether the LVI is
configured for 5V or 3V protection.
NOTE:
The microcontroller is guaranteed to operate at a minimum supply
voltage. The trip point (VTRIPF [5 V] or VTRIPF [3 V]) may be lower than
this. (See Electrical Specifications for the actual trip point voltages.)
14.5 LVI Status Register
The LVI status register (LVISR) indicates if the VDD voltage was
detected below the VTRIPF level.
Address:
$FE0C
Bit 7
Read: LVIOUT
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Write:
Reset:
0
= Unimplemented
Figure 14-3. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when the VDD voltage falls below the
VTRIPF trip voltage. See Table 14-1. Reset clears the LVIOUT bit.
Table 14-1. LVIOUT Bit Indication
VDD
LVIOUT
VDD > VTRIPR
0
VDD < VTRIPF
1
VTRIPF < VDD < VTRIPR
Previous value
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Low-Voltage Inhibit (LVI)
14.6 LVI Interrupts
The LVI module does not generate interrupt requests.
14.7 Low-Power Modes
The STOP and WAIT instructions put the MCU in low powerconsumption standby modes.
14.7.1 Wait Mode
If enabled, the LVI module remains active in wait mode. If enabled to
generate resets, the LVI module can generate a reset and bring the MCU
out of wait mode.
14.7.2 Stop Mode
If enabled in stop mode (LVISTOP set), the LVI module remains active
in stop mode. If enabled to generate resets, the LVI module can
generate a reset and bring the MCU out of stop mode.
Technical Data
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Low-Voltage Inhibit (LVI)
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Technical Data — MC68HC908GR8
Section 15. Monitor ROM (MON)
15.1 Contents
15.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
15.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
15.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
15.5
Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
15.2 Introduction
This section describes the monitor ROM (MON) and the monitor mode
entry methods. The monitor ROM allows complete testing of the MCU
through a single-wire interface with a host computer. Monitor mode entry
can be achieved without use of the higher test voltage, VTST, as long as
vector addresses $FFFE and $FFFF are blank, thus reducing the
hardware requirements for in-circuit programming.
15.3 Features
Features of the monitor ROM include:
•
Normal user-mode pin functionality
•
One pin dedicated to serial communication between monitor ROM
and host computer
•
Standard mark/space non-return-to-zero (NRZ) communication
with host computer
•
Execution of code in RAM or FLASH
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Monitor ROM (MON)
•
FLASH memory security feature(1)
•
FLASH memory programming interface
•
Enhanced PLL (phase-locked loop) option to allow use of external
32.768-kHz crystal to generate internal frequency of 2.4576 MHz
•
310 byte monitor ROM code size ($FE20 to $FF55)
•
Monitor mode entry without high voltage, VTST, if reset vector is
blank ($FFFE and $FFFF contain $FF)
•
Standard monitor mode entry if high voltage, VTST, is applied to
IRQ
15.4 Functional Description
The monitor ROM receives and executes commands from a host
computer. Figure 15-1 shows an example circuit used to enter monitor
mode and communicate with a host computer via a standard RS-232
interface.
Simple monitor commands can access any memory address. In monitor
mode, the MCU can execute code downloaded into RAM by a host
computer while most MCU pins retain normal operating mode functions.
All communication between the host computer and the MCU is through
the PTA0 pin. A level-shifting and multiplexing interface is required
between PTA0 and the host computer. PTA0 is used in a wired-OR
configuration and requires a pullup resistor.
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
Technical Data
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Monitor ROM (MON)
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Monitor ROM (MON)
Functional Description
68HC08
RST
0.1 µF
VTST
(SEE NOTE 3)
RESET VECTORS
$FFFE
10 kΩ
(SEE NOTES 2
SW2 AND 3)
C
VDDA
D
$FFFF
IRQ
VDDA
0.033 µF
SW3
(SEE NOTE 2)
C
1
10 µF
+
MC145407
3
6–30 pF
20
+
10 µF
18
D
C
32.768 kHz XTAL
4
10 µF
17
330 kΩ
+
+
2
19
DB-25
2
5
16
3
6
15
10 µF
VDD
0.01 µF
CGMXFC
10 k
10 MΩ
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D
SW4
(SEE NOTE 2)
OSC1
OSC2
PTA1
10 kΩ
VSS
6–30 pF
VSSAD/VREFL
VSSA
VDD
VDD
VDDAD/VREFH
0.1 µF
7
VDD
1
MC74HC125
14
2
3
6
5
VDD
10 kΩ
PTA0
4
VDD
7
10 kΩ
PTB0
PTB1
10 kΩ
Notes:
1. SW2, SW3, and SW4: Position C — Enter monitor mode using external oscillator.
SW2, SW3, and SW4: Position D — Enter monitor mode using external XTAL and internal PLL.
2. See . Monitor Mode Signal Requirements and Options for IRQ voltage level requirements.
Figure 15-1. Monitor Mode Circuit
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Monitor ROM (MON)
The monitor code has been updated from previous versions to allow
enabling the PLL to generate the internal clock, provided the reset vector
is blank, when the device is being clocked by a low-frequency crystal.
This addition, which is enabled when IRQ is held low out of rest, is
intended to support serial communication/ programming at 9600 baud in
monitor mode by stepping up the external frequency (assumed to be
32.768 kHz) by a fixed amount to generate the desired internal
frequency (2.4576 MHz). Since this feature is enabled only when IRQ is
held low out of reset, it cannot be used when the reset vector is not blank
because entry into monitor mode in this case requires VTST on IRQ.
15.4.1 Entering Monitor Mode
Table 15-1 shows the pin conditions for entering monitor mode. As
specified in the table, monitor mode may be entered after a power-on
reset (POR) and will allow communication at 9600 baud provided one of
the following sets of conditions is met:
1. If $FFFE and $FFFF contain values not cared:
– The external clock is 9.8304 MHz
– IRQ = VTST (PLL off)
2. If $FFFE and $FFFF contain $FF, blank state:
– The external clock is 9.8304 MHz
– IRQ = VDD (this can be implemented through the internal IRQ
pullup; PLL off)
3. If $FFFE and $FFFF contain $FF, blank state:
– The external clock is 32.768 kHz (crystal)
– IRQ = VSS (this setting initiates the PLL to boost the external
32.768 kHz to an internal bus frequency of 2.4576 MHz)
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Monitor ROM (MON)
Functional Description
Table 15-1. Monitor Mode Signal Requirements and Options
IRQ
RESET
$FFFE/
$FFFF
X
GND
X
VTST
VDD
or
VTST
X
VDD
VDD
$FFFF
GND
VDD
$FFFF
PLL PTB0 PTB1
X
X
OFF
1
OFF
X
ON
Bus
Freq
COP
0
Disabled
X
X
0
0
9.8304
MHz
4.9152
MHz
2.4576
Disabled
MHz
9.8304
MHz
4.9152
MHz
2.4576
Disabled
MHz
32.768
kHz
4.9152
MHz
2.4576
Disabled
MHz
X
X
External
CGMOUT
Clock(1)
For Serial
Communication
X
Baud
PTA0 PTA1
Rate(2) (3)
X
X
0
1
0
9600
X
1
DNA
1
0
9600
X
1
DNA
1
0
9600
X
1
DNA
Comment
No operation until
reset goes high
PTB0 and PTB1
voltages only
required if
IRQ = VTST
External frequency
always divided by
4
PLL enabled (BCS
set) in monitor
code
VDD
or
GND
VTST
$FFFF
OFF
X
X
X
—
—
Enabled
X
X
—
Enters user mode
— will encounter
an illegal address
reset
VDD
or
GND
VDD
or
VTST
Not
$FFFF
OFF
X
X
X
—
—
Enabled
X
X
—
Enters user mode
Notes:
1. External clock is derived by a 32.768 kHz crystal or a 9.8304 MHz off-chip oscillator
2. PTA0 = 1 if serial communication; PTA0 = X if parallel communication
3. PTA1 = 0 → serial, PTA1 = 1 → parallel communication for security code entry
4. DNA = does not apply, X = don’t care
If entering monitor mode with VTST applied on IRQ (condition set 1), the
CGMOUT frequency is equal to the CGMXCLK frequency and the OSC1
input directly generates internal bus clocks. In this case, the OSC1
signal must have a 50% duty cycle at maximum bus frequency.
If entering monitor mode without high voltage applied on IRQ (condition
set 2 or 3, where applied voltage is either VDD or VSS), then all port B pin
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requirements and conditions, are not in effect. This is to reduce circuit
requirements when performing in-circuit programming.
NOTE:
If the reset vector is blank and monitor mode is entered, the chip will see
an additional reset cycle after the initial POR reset. Once the part has
been programmed, the traditional method of applying a voltage, VTST, to
IRQ must be used to enter monitor mode.
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The COP module is disabled in monitor mode based on these
conditions:
•
If monitor mode was entered as a result of the reset vector being
blank (condition set 2 or 3), the COP is always disabled regardless
of the state of IRQ or RST.
•
If monitor mode was entered with VTST on IRQ (condition set 1),
then the COP is disabled as long as VTST is applied to either IRQ
or RST.
The second condition states that as long as VTST is maintained on the
IRQ pin after entering monitor mode, or if VTST is applied to RST after
the initial reset to get into monitor mode (when VTST was applied to IRQ),
then the COP will be disabled. In the latter situation, after VTST is applied
to the RST pin, VTST can be removed from the IRQ pin in the interest of
freeing the IRQ for normal functionality in monitor mode.
Figure 15-2 shows a simplified diagram of the monitor mode entry when
the reset vector is blank and just 1 x VDD voltage is applied to the IRQ
pin. An external oscillator of 9.8304 MHz is required for a baud rate of
9600, as the internal bus frequency is automatically set to the external
frequency divided by four.
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Functional Description
POR RESET
IS VECTOR
BLANK?
NO
NORMAL USER
MODE
YES
MONITOR MODE
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EXECUTE
MONITOR
CODE
POR
TRIGGERED?
NO
YES
Figure 15-2. Low-Voltage Monitor Mode Entry Flowchart
Enter monitor mode with pin configuration shown in Figure 15-1 by
pulling RST low and then high. The rising edge of RST latches monitor
mode. Once monitor mode is latched, the values on the specified pins
can change.
Once out of reset, the MCU waits for the host to send eight security
bytes. (See Security.) After the security bytes, the MCU sends a break
signal (10 consecutive logic 0s) to the host, indicating that it is ready to
receive a command.
NOTE:
The PTA1 pin must remain at logic 0 for 24 bus cycles after the RST pin
goes high to enter monitor mode properly.
In monitor mode, the MCU uses different vectors for reset, SWI
(software interrupt), and break interrupt than those for user mode. The
alternate vectors are in the $FE page instead of the $FF page and allow
code execution from the internal monitor firmware instead of user code.
NOTE:
Exiting monitor mode after it has been initiated by having a blank reset
vector requires a power-on reset. Pulling RST low will not exit monitor
mode in this situation.
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Monitor ROM (MON)
Table 15-2 summarizes the differences between user mode and monitor
mode.
Table 15-2. Mode Differences
Functions
Modes
Reset
Vector
High
Reset
Vector
Low
Break
Vector
High
Break
Vector
Low
SWI
Vector
High
SWI
Vector
Low
User
$FFFE
$FFFF
$FFFC
$FFFD
$FFFC
$FFFD
Monitor
$FEFE
$FEFF
$FEFC
$FEFD
$FEFC
$FEFD
15.4.2 Data Format
Communication with the monitor ROM is in standard non-return-to-zero
(NRZ) mark/space data format. Transmit and receive baud rates must
be identical.
START
BIT 0
BIT
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
NEXT
START
STOP
BIT
BIT
Figure 15-3. Monitor Data Format
15.4.3 Break Signal
A start bit (logic 0) followed by nine logic 0 bits is a break signal. When
the monitor receives a break signal, it drives the PTA0 pin high for the
duration of two bits and then echoes back the break signal.
MISSING STOP BIT
2-STOP BIT DELAY BEFORE ZERO ECHO
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Figure 15-4. Break Transaction
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Monitor ROM (MON)
Functional Description
15.4.4 Baud Rate
The communication baud rate is controlled by the crystal frequency upon
entry into monitor mode. The divide by ratio is 1024.
If monitor mode was entered with VDD on IRQ, then the divide by ratio is
also set at 1024. If monitor mode was entered with VSS on IRQ, then the
internal PLL steps up the external frequency, presumed to be 32.768
kHz, to 2.4576 MHz. These latter two conditions for monitor mode entry
require that the reset vector is blank.
Table 15-3 lists external frequencies required to achieve a standard
baud rate of 9600 BPS. Other standard baud rates can be accomplished
using proportionally higher or lower frequency generators. If using a
crystal as the clock source, be aware of the upper frequency limit that the
internal clock module can handle. See 5.0 V Control Timing and 3.0 V
Control Timing for this limit.
Table 15-3. Monitor Baud Rate Selection
External
Frequency
IRQ
Internal
Frequency
Baud Rate
(BPS)
9.8304 MHz
VTST
2.4576 MHz
9600
9.8304 MHz
VDD
2.4576 MHz
9600
32.768 kHz
VSS
2.4576 MHz
9600
15.4.5 Commands
The monitor ROM firmware uses these commands:
•
READ (read memory)
•
WRITE (write memory)
•
IREAD (indexed read)
•
IWRITE (indexed write)
•
READSP (read stack pointer)
•
RUN (run user program)
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The monitor ROM firmware echoes each received byte back to the PTA0
pin for error checking. An 11-bit delay at the end of each command
allows the host to send a break character to cancel the command. A
delay of two bit times occurs before each echo and before READ,
IREAD, or READSP data is returned. The data returned by a read
command appears after the echo of the last byte of the command.
NOTE:
Wait one bit time after each echo before sending the next byte.
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FROM
HOST
READ
4
ADDRESS
HIGH
READ
4
1
ADDRESS
HIGH
1
ADDRESS
LOW
4
ADDRESS
LOW
DATA
1
3, 2
4
ECHO
RETURN
Notes:
1 = Echo delay, 2 bit times
2 = Data return delay, 2 bit times
3 = Cancel command delay, 11 bit times
4 = Wait 1 bit time before sending next byte.
Figure 15-5. Read Transaction
FROM
HOST
3
ADDRESS
HIGH
WRITE
WRITE
1
3
ADDRESS
HIGH
1
ADDRESS
LOW
3
ADDRESS
LOW
1
DATA
DATA
3
1
2, 3
ECHO
Notes:
1 = Echo delay, 2 bit times
2 = Cancel command delay, 11 bit times
3 = Wait 1 bit time before sending next byte.
Figure 15-6. Write Transaction
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Functional Description
A brief description of each monitor mode command is given in Table 154 through Table 15-9.
Table 15-4. READ (Read Memory) Command
Description
Operand
2-byte address in high-byte:low-byte order
Data
Returned
Returns contents of specified address
Opcode
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Read byte from memory
$4A
Command Sequence
SENT TO
MONITOR
READ
ADDRESS
HIGH
READ
ADDRESS
HIGH
ADDRESS
LOW
ADDRESS
LOW
DATA
ECHO
RETURN
Table 15-5. WRITE (Write Memory) Command
Description
Write byte to memory
Operand
2-byte address in high-byte:low-byte order; low byte followed by
data byte
Data
Returned
None
Opcode
$49
Command Sequence
FROM
HOST
WRITE
WRITE
ADDRESS
HIGH
ADDRESS
HIGH
ADDRESS
LOW
ADDRESS
LOW
DATA
DATA
ECHO
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Table 15-6. IREAD (Indexed Read) Command
Description
Read next 2 bytes in memory from last address accessed
Operand
2-byte address in high byte:low byte order
Data
Returned
Returns contents of next two addresses
Opcode
$1A
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Command Sequence
FROM
HOST
IREAD
IREAD
DATA
ECHO
DATA
RETURN
Table 15-7. IWRITE (Indexed Write) Command
Description
Write to last address accessed + 1
Operand
Single data byte
Data
Returned
None
Opcode
$19
Command Sequence
FROM
HOST
IWRITE
IWRITE
DATA
DATA
ECHO
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Functional Description
A sequence of IREAD or IWRITE commands can access a block of
memory sequentially over the full 64K byte memory map.
Table 15-8. READSP (Read Stack Pointer) Command
Description
Operand
None
Data
Returned
Returns incremented stack pointer value (SP + 1) in high-byte:lowbyte order
Opcode
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Reads stack pointer
$0C
Command Sequence
FROM
HOST
READSP
SP
HIGH
READSP
ECHO
SP
LOW
RETURN
Table 15-9. RUN (Run User Program) Command
Description
Executes PULH and RTI instructions
Operand
None
Data
Returned
None
Opcode
$28
Command Sequence
FROM
HOST
RUN
RUN
ECHO
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Monitor ROM (MON)
The MCU executes the SWI and PSHH instructions when it enters
monitor mode. The RUN command tells the MCU to execute the PULH
and RTI instructions. Before sending the RUN command, the host can
modify the stacked CPU registers to prepare to run the host program.
The READSP command returns the incremented stack pointer value,
SP + 1. The high and low bytes of the program counter are at addresses
SP + 5 and SP + 6.
SP
HIGH BYTE OF INDEX REGISTER
SP + 1
CONDITION CODE REGISTER
SP + 2
ACCUMULATOR
SP + 3
LOW BYTE OF INDEX REGISTER
SP + 4
HIGH BYTE OF PROGRAM COUNTER SP + 5
LOW BYTE OF PROGRAM COUNTER SP + 6
SP + 7
Figure 15-7. Stack Pointer at Monitor Mode Entry
15.5 Security
A security feature discourages unauthorized reading of FLASH locations
while in monitor mode. The host can bypass the security feature at
monitor mode entry by sending eight security bytes that match the bytes
at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain userdefined data.
NOTE:
Do not leave locations $FFF6–$FFFD blank. For security reasons, they
should be programmed even if they are not used for vectors.
During monitor mode entry, the MCU waits after the power-on reset for
the host to send the eight security bytes on pin PTA0. If the received
bytes match those at locations $FFF6–$FFFD, the host bypasses the
security feature and can read all FLASH locations and execute code
from FLASH. Security remains bypassed until a power-on reset occurs.
If the reset was not a power-on reset, security remains bypassed and
security code entry is not required. (See Figure 15-8.)
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Security
VDD
4096 + 32 CGMXCLK CYCLES
RST
24 BUS CYCLES
COMMAND
PA1
BYTE 8
BYTE 2
BYTE 1
256 BUS CYCLES (MINIMUM)
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FROM HOST
PA0
4
BREAK
2
NOTES:
1 = Echo delay, 2 bit times
2 = Data return delay, 2 bit times
4 = Wait 1 bit time before sending next byte.
1
COMMAND ECHO
1
BYTE 8 ECHO
BYTE 1 ECHO
FROM MCU
1
BYTE 2 ECHO
4
1
Figure 15-8. Monitor Mode Entry Timing
Upon power-on reset, if the received bytes of the security code do not
match the data at locations $FFF6–$FFFD, the host fails to bypass the
security feature. The MCU remains in monitor mode, but reading a
FLASH location returns an invalid value and trying to execute code from
FLASH causes an illegal address reset. After receiving the eight security
bytes from the host, the MCU transmits a break character, signifying that
it is ready to receive a command.
NOTE:
The MCU does not transmit a break character until after the host sends
the eight security bytes.
To determine whether the security code entered is correct, check to see
if bit 6 of RAM address $40 is set. If it is, then the correct security code
has been entered and FLASH can be accessed.
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If the security sequence fails, the device can be reset and brought up in
monitor mode to attempt another entry. After failing the security
sequence, the FLASH mode can also be bulk erased by executing an
erase routine that was downloaded into internal RAM. The bulk erase
operation clears the security code locations so that all eight security
bytes become $FF (blank).
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Technical Data — MC68HC908GR8
Section 16. Input/Output Ports (I/O)
16.1 Contents
16.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
16.3
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
16.4
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
16.5
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
16.6
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
16.7
Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
16.2 Introduction
Twenty one (21) bidirectional input-output (I/O) pins form five parallel
ports. All I/O pins are programmable as inputs or outputs. All individual
bits within port A, port C, and port D are software configurable with pullup
devices if configured as input port bits. The pullup devices are
automatically and dynamically disabled when a port bit is switched to
output mode.
NOTE:
Connect any unused I/O pins to an appropriate logic level, either VDD or
VSS. Although the I/O ports do not require termination for proper
operation, termination reduces excess current consumption and the
possibility of electrostatic damage.
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Input/Output Ports (I/O)
Addr.
Bit 7
6
5
4
Read:
Port A Data Register
Write:
(PTA)
Reset:
0
0
0
0
Read:
Port B Data Register
Write:
(PTB)
Reset:
0
Read:
Port C Data Register
Write:
(PTC)
Reset:
0
Read:
Port D Data Register
Write:
(PTD)
Reset:
0
Read:
Data Direction Register A
$0004
Write:
(DDRA)
Reset:
0
0
0
Read:
Data Direction Register B
$0005
Write:
(DDRB)
Reset:
0
0
$0000
$0001
$0002
$0003
Register Name
3
2
1
Bit 0
PTA3
PTA2
PTA1
PTA0
PTB2
PTB1
PTB0
PTC1
PTC0
PTD2
PTD1
PTD0
DDRA3
DDRA2
DDRA1
DDRA0
Unaffected by reset
0
PTB5
PTB4
PTB3
Unaffected by reset
0
0
0
0
0
Unaffected by reset
PTD6
PTD5
PTD4
PTD3
Unaffected by reset
0
0
0
0
0
0
0
0
0
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
DDRC1
DDRC0
0
0
0
0
0
0
Read:
Data Direction Register C
$0006
Write:
(DDRC)
Reset:
0
0
0
0
0
0
Read:
Data Direction Register D
$0007
Write:
(DDRD)
Reset:
0
0
0
0
0
0
0
0
0
0
DDRD6
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
DDRD0
0
0
0
0
0
0
0
= Unimplemented
Figure 16-1. I/O Port Register Summary
Technical Data
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Input/Output Ports (I/O)
Introduction
Addr.
Register Name
Read:
$0008
$000D
$000E
$000F
6
5
4
3
2
0
0
0
0
0
0
Port E Data Register
Write:
(PTE)
Reset:
Read:
$000C
Bit 7
Bit 0
PTE1
PTE0
DDRE1
DDRE0
0
0
Unaffected by reset
0
0
0
0
Data Direction Register E
Write:
(DDRE)
Reset:
0
0
0
0
Read:
0
0
0
0
0
0
0
0
PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
Port A Input Pullup Enable
Write:
Register (PTAPUE)
Reset:
0
0
0
0
0
0
Read:
0
0
0
0
0
0
0
0
PTCPUE1 PTCPUE0
Port C Input Pullup Enable
Write:
Register (PTCPUE)
Reset:
0
Read:
0
Port D Input Pullup Enable
Write:
Register (PTDPUE)
Reset:
1
0
0
0
0
0
0
0
PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 16-1. I/O Port Register Summary (Continued)
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Table 16-1. Port Control Register Bits Summary
Port
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A
B
C
D
E
Bit
DDR
Module Control
0
DDRA0
KBIE0
PTA0/KBD0
1
DDRA1
KBIE1
PTA1/KBD1
2
DDRA2
KBIE2
PTA2/KBD2
3
DDRA3
KBIE3
PTA3/KBD3
-
--
-
--
-
--
-
--
-
--
-
--
-
--
-
--
0
DDRB0
CH0
PTB0/ATD0
1
DDRB1
CH1
PTB1/ATD1
2
DDRB2
CH2
PTB2/ATD2
3
DDRB3
CH3
PTB3/ATD3
4
DDRB4
CH4
PTB4/ATD4
5
DDRB5
CH5
PTB5/ATD5
-
--
-
--
-
--
-
--
0
DDRC0
PTC0
1
DDRC1
PTC1
-
--
--
-
--
--
-
--
--
-
--
--
-
--
--
0
DDRD0
PTD0/SS
1
DDRD1
2
DDRD2
3
DDRD3
4
DDRD4
5
DDRD5
6
DDRD6
-
--
0
DDRE0
1
DDRE1
KBD
ADC
SPI
PTD1/MISO
PTD2/MOSI
PTD3/SPSCK
TIM1
TIM2
SCI
Technical Data
208
Pin
PTD4/T1CH0
PTD5/T1CH1
PTD6/T2CH0
-PTE0/TxD
PTE1/RxD
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Port A
16.3 Port A
Port A is an 4-bit special-function port that shares all four of its pins with
the keyboard interrupt (KBI) module. Port A also has software
configurable pullup devices if configured as an input port.
16.3.1 Port A Data Register
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The port A data register (PTA) contains a data latch for each of the four
port A pins.
Address:
Read:
$0000
Bit 7
6
5
4
0
0
0
0
3
2
1
Bit 0
PTA3
PTA2
PTA1
PTA0
KBD2
KBD1
KBD0
Write:
Reset:
Unaffected by reset
Alternate
Function:
KBD3
Figure 16-2. Port A Data Register (PTA)
PTA3–PTA0 — Port A Data Bits
These read/write bits are software programmable. Data direction of
each port A pin is under the control of the corresponding bit in data
direction register A. Reset has no effect on port A data.
KBD3–KBD0 — Keyboard Inputs
The keyboard interrupt enable bits, KBIE3–KBIE0, in the keyboard
interrupt control register (KBICR) enable the port A pins as external
interrupt pins. See Keyboard Interrupt (KBI).
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16.3.2 Data Direction Register A
Data direction register A (DDRA) determines whether each port A pin is
an input or an output. Writing a logic 1 to a DDRA bit enables the output
buffer for the corresponding port A pin; a logic 0 disables the output
buffer.
Address:
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Read:
$0004
Bit 7
6
5
4
0
0
0
0
3
2
1
Bit 0
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
Write:
Reset:
0
0
0
0
Figure 16-3. Data Direction Register A (DDRA)
DDRA3–DDRA0 — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears
DDRA3–DDRA0, configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE:
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 16-4 shows the port A I/O logic.
Technical Data
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Input/Output Ports (I/O)
Port A
READ DDRA ($0004)
INTERNAL DATA BUS
WRITE DDRA ($0004)
DDRAx
RESET
WRITE PTA ($0000)
PTAx
PTAx
VDD
PTAPUEx
READ PTA ($0000)
INTERNAL
PULLUP
DEVICE
Figure 16-4. Port A I/O Circuit
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx
data latch. When bit DDRAx is a logic 0, reading address $0000 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 16-2 summarizes
the operation of the port A pins.
Table 16-2. Port A Pin Functions
Accesses to DDRA
PTAPUE Bit
DDRA Bit
PTA Bit
Accesses to PTA
I/O Pin Mode
Read/Write
Read
Write
1
0
X(1)
Input, VDD(4)
DDRA3–DDRA0
Pin
PTA3–PTA0(3
0
0
X
Input, Hi-Z(2)
DDRA3–DDRA0
Pin
PTA3–PTA0(3
X
1
X
Output
DDRA3–DDRA0
PTA3–PTA0
PTA3–PTA0
)
)
NOTES:
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
4. I/O pin pulled up to VDD by internal pullup device
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16.3.3 Port A Input Pullup Enable Register
The port A input pullup enable register (PTAPUE) contains a software
configurable pullup device for each of the four port A pins. Each bit is
individually configurable and requires that the data direction register,
DDRA, bit be configured as an input. Each pullup is automatically and
dynamically disabled when a port bit’s DDRA is configured for output
mode.
Freescale Semiconductor, Inc...
Address:
Read:
$000D
Bit 7
6
5
4
0
0
0
0
3
2
1
Bit 0
PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
Write:
Reset:
0
0
0
0
0
0
0
0
Figure 16-5. Port A Input Pullup Enable Register (PTAPUE)
PTAPUE3–PTAPUE0 — Port A Input Pullup Enable Bits
These writeable bits are software programmable to enable pullup
devices on an input port bit.
1 = Corresponding port A pin configured to have internal pullup
0 = Corresponding port A pin has internal pullup disconnected
Technical Data
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Port B
16.4 Port B
Port B is an 6-bit special-function port that shares all six of its pins with
the analog-to-digital converter (ADC) module.
16.4.1 Port B Data Register
Freescale Semiconductor, Inc...
The port B data register (PTB) contains a data latch for each of the six
port pins.
Address:
Read:
Write:
$0001
Bit 7
6
0
0
5
4
3
2
1
Bit 0
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
AD2
AD1
AD0
Reset:
Alternate
Function:
Unaffected by reset
AD5
AD4
AD3
Figure 16-6. Port B Data Register (PTB)
PTB5–PTB0 — Port B Data Bits
These read/write bits are software-programmable. Data direction of
each port B pin is under the control of the corresponding bit in data
direction register B. Reset has no effect on port B data.
AD5–AD0 — Analog-to-Digital Input Bits
AD5–AD0 are pins used for the input channels to the analog-to-digital
converter module. The channel select bits in the ADC status and
control register define which port B pin will be used as an ADC input
and overrides any control from the port I/O logic by forcing that pin as
the input to the analog circuitry.
NOTE:
Care must be taken when reading port B while applying analog voltages
to AD5–AD0 pins. If the appropriate ADC channel is not enabled,
excessive current drain may occur if analog voltages are applied to the
PTBx/ADx pin, while PTB is read as a digital input. Those ports not
selected as analog input channels are considered digital I/O ports.
NOTE:
PTB4 and 5 are not available in a 28-pin DIP and SOIC package
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16.4.2 Data Direction Register B
Data direction register B (DDRB) determines whether each port B pin is
an input or an output. Writing a logic 1 to a DDRB bit enables the output
buffer for the corresponding port B pin; a logic 0 disables the output
buffer.
Address:
Freescale Semiconductor, Inc...
Read:
$0005
Bit 7
6
0
0
5
4
3
2
1
Bit 0
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
Write:
Reset:
0
0
Figure 16-7. Data Direction Register B (DDRB)
DDRB5–DDRB0 — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears
DDRB5–DDRB0], configuring all port B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE:
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
NOTE:
For those devices packaged in a 28-pin DIP and SOIC package, PTB5,4
are not connected. Set DDRB5,4 to a 1 to configure PTB5,4 as outputs.
Figure 16-8 shows the port B I/O logic.
Technical Data
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Input/Output Ports (I/O)
Port B
INTERNAL DATA BUS
READ DDRB ($0005)
WRITE DDRB ($0005)
RESET
DDRBx
WRITE PTB ($0001)
PTBx
PTBx
READ PTB ($0001)
Figure 16-8. Port B I/O Circuit
When bit DDRBx is a logic 1, reading address $0001 reads the PTBx
data latch. When bit DDRBx is a logic 0, reading address $0001 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 16-3 summarizes
the operation of the port B pins.
Table 16-3. Port B Pin Functions
DDRB Bit
PTB Bit
I/O Pin Mode
Accesses
to DDRB
Accesses to PTB
Read/Write
Read
Write
0
X(1)
Input, Hi-Z(2)
DDRB5–DDRB0
Pin
PTB5–PTB0(3)
1
X
Output
DDRB5–DDRB0
PTB5–PTB0
PTB5–PTB0
Notes:
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
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16.5 Port C
Port C is a 2-bit, general-purpose bidirectional I/O port. Port C also has
software configurable pullup devices if configured as an input port.
16.5.1 Port C Data Register
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The port C data register (PTC) contains a data latch for each of the two
port C pins.
Address:
Read:
$0002
Bit 7
6
5
4
3
2
0
0
0
0
0
0
1
Bit 0
PTC1
PTC0
Write:
Reset:
Unaffected by reset
= Unimplemented
Figure 16-9. Port C Data Register (PTC)
PTC1–PTC0 — Port C Data Bits
These read/write bits are software-programmable. Data direction of
each port C pin is under the control of the corresponding bit in data
direction register C. Reset has no effect on port C data.
NOTE:
PTC is not available in a 28-pin DIP and SOIC package
Technical Data
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Port C
16.5.2 Data Direction Register C
Data direction register C (DDRC) determines whether each port C pin is
an input or an output. Writing a logic 1 to a DDRC bit enables the output
buffer for the corresponding port C pin; a logic 0 disables the output
buffer.
Freescale Semiconductor, Inc...
Address:
Read:
$0006
Bit 7
6
5
4
3
2
0
0
0
0
0
0
1
Bit 0
DDRC1
DDRC0
0
0
Write:
Reset:
0
0
0
0
0
0
= Unimplemented
Figure 16-10. Data Direction Register C (DDRC)
DDRC1–DDRC0 — Data Direction Register C Bits
These read/write bits control port C data direction. Reset clears
DDRC1–DDRC0, configuring all port C pins as inputs.
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
NOTE:
Avoid glitches on port C pins by writing to the port C data register before
changing data direction register C bits from 0 to 1.
Figure 16-11 shows the port C I/O logic.
NOTE:
For those devices packaged in a 28-pin DIP and SOIC package, PTC1,0
are not connected. Set DDRC1,0 to a 1 to configure PTC1,0 as outputs.
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Input/Output Ports (I/O)
READ DDRC ($0006)
INTERNAL DATA BUS
WRITE DDRC ($0006)
DDRCx
RESET
WRITE PTC ($0002)
PTCx
PTCx
VDD
PTCPUEx
READ PTC ($0002)
INTERNAL
PULLUP
DEVICE
Figure 16-11. Port C I/O Circuit
When bit DDRCx is a logic 1, reading address $0002 reads the PTCx
data latch. When bit DDRCx is a logic 0, reading address $0002 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 16-4 summarizes
the operation of the port C pins.
Table 16-4. Port C Pin Functions
Accesses to DDRC
PTCPUE Bit
DDRC Bit
PTC Bit
Accesses to PTC
I/O Pin Mode
Read/Write
Read
Write
1
0
X(1)
Input, VDD(4)
DDRC1–DDRC0
Pin
PTC1–PTC0(3)
0
0
X
Input, Hi-Z(2)
DDRC1–DDRC0
Pin
PTC1–PTC0(3)
X
1
X
Output
DDRC1–DDRC0
PTC1–PTC0
PTC1–PTC0
Notes:
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
4. I/O pin pulled up to VDD by internal pullup device.
Technical Data
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Port C
16.5.3 Port C Input Pullup Enable Register
The port C input pullup enable register (PTCPUE) contains a software
configurable pullup device for each of the two port C pins. Each bit is
individually configurable and requires that the data direction register,
DDRC, bit be configured as an input. Each pullup is automatically and
dynamically disabled when a port bit’s DDRC is configured for output
mode.
Freescale Semiconductor, Inc...
Address:
Read:
$000E
Bit 7
6
5
4
3
2
0
0
0
0
0
0
1
Bit 0
PTCPUE1 PTCPUE0
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 16-12. Port C Input Pullup Enable Register (PTCPUE)
PTCPUE1–PTCPUE0 — Port C Input Pullup Enable Bits
These writeable bits are software programmable to enable pullup
devices on an input port bit.
1 = Corresponding port C pin configured to have internal pullup
0 = Corresponding port C pin internal pullup disconnected
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16.6 Port D
Port D is an 7-bit special-function port that shares four of its pins with the
serial peripheral interface (SPI) module and three of its pins with two
timer interface (TIM1 and TIM2) modules. Port D also has software
configurable pullup devices if configured as an input port.
16.6.1 Port D Data Register
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The port D data register (PTD) contains a data latch for each of the
seven port D pins.
.
Address:
$0003
Bit 7
Read:
6
5
4
3
2
1
Bit 0
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
MOSI
MISO
SS
0
Write:
Reset:
Alternate
Function:
Unaffected by reset
T2CH0
T1CH1
T1CH0
SPSCK
Figure 16-13. Port D Data Register (PTD)
PTD6–PTD0 — Port D Data Bits
These read/write bits are software-programmable. Data direction of
each port D pin is under the control of the corresponding bit in data
direction register D. Reset has no effect on port D data.
T2CH0 — Timer 2 Channel I/O Bits
The PTD6/T2CH0 pin is the TIM2 input capture/output compare pin.
The edge/level select bits, ELSxB:ELSxA, determine whether the
PTD6/T2CH0 pin is a timer channel I/O pin or a general-purpose I/O
pin. See Timer Interface Module (TIM).
Technical Data
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Port D
T1CH1 and T1CH0 — Timer 1 Channel I/O Bits
The PTD5/T1CH1–PTD4/T1CH0 pins are the TIM1 input
capture/output compare pins. The edge/level select bits, ELSxB and
ELSxA, determine whether the PTD5/T1CH1–PTD4/T1CH0 pins are
timer channel I/O pins or general-purpose I/O pins. See Timer
Interface Module (TIM).
SPSCK — SPI Serial Clock
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The PTD3/SPSCK pin is the serial clock input of the SPI module.
When the SPE bit is clear, the PTD3/SPSCK pin is available for
general-purpose I/O.
MOSI — Master Out/Slave In
The PTD2/MOSI pin is the master out/slave in terminal of the SPI
module. When the SPE bit is clear, the PTD2/MOSI pin is available
for general-purpose I/O.
MISO — Master In/Slave Out
The PTD1/MISO pin is the master in/slave out terminal of the SPI
module. When the SPI enable bit, SPE, is clear, the SPI module is
disabled, and the PTD0/SS pin is available for general-purpose I/O.
Data direction register D (DDRD) does not affect the data direction of
port D pins that are being used by the SPI module. However, the
DDRD bits always determine whether reading port D returns the
states of the latches or the states of the pins. See Table 16-5.
SS — Slave Select
The PTD0/SS pin is the slave select input of the SPI module. When
the SPE bit is clear, or when the SPI master bit, SPMSTR, is set, the
PTD0/SS pin is available for general-purpose I/O. When the SPI is
enabled, the DDRB0 bit in data direction register B (DDRB) has no
effect on the PTD0/SS pin.
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16.6.2 Data Direction Register D
Data direction register D (DDRD) determines whether each port D pin is
an input or an output. Writing a logic 1 to a DDRD bit enables the output
buffer for the corresponding port D pin; a logic 0 disables the output
buffer.
Address:
$0007
Freescale Semiconductor, Inc...
Bit 7
Read:
6
5
4
3
2
1
Bit 0
DDRD6
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
DDRD0
0
0
0
0
0
0
0
0
Write:
Reset:
0
Figure 16-14. Data Direction Register D (DDRD)
DDRD6–DDRD0 — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears
DDRD6–DDRD0, configuring all port D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE:
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Figure 16-15 shows the port D I/O logic.
Technical Data
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Port D
READ DDRD ($0007)
INTERNAL DATA BUS
WRITE DDRD ($0007)
DDRDx
RESET
WRITE PTD ($0003)
PTDx
PTDx
VDD
PTDPUEx
READ PTD ($0003)
INTERNAL
PULLUP
DEVICE
Figure 16-15. Port D I/O Circuit
When bit DDRDx is a logic 1, reading address $0003 reads the PTDx
data latch. When bit DDRDx is a logic 0, reading address $0003 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 16-5 summarizes
the operation of the port D pins.
Table 16-5. Port D Pin Functions
Accesses to DDRD
PTDPUE Bit
DDRD Bit
PTD Bit
Accesses to PTD
I/O Pin Mode
Read/Write
Read
Write
1
0
X(1)
Input, VDD(4)
DDRD6–DDRD0
Pin
PTD6–PTD0(3)
0
0
X
Input, Hi-Z(2)
DDRD6–DDRD0
Pin
PTD6–PTD0(3)
X
1
X
Output
DDRD6–DDRD0
PTD6–PTD0
PTD6–PTD0
Notes:
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
4. I/O pin pulled up to VDD by internal pullup device.
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16.6.3 Port D Input Pullup Enable Register
The port D input pullup enable register (PTDPUE) contains a software
configurable pullup device for each of the seven port D pins. Each bit is
individually configurable and requires that the data direction register,
DDRD, bit be configured as an input. Each pullup is automatically and
dynamically disabled when a port bit’s DDRD is configured for output
mode.
Freescale Semiconductor, Inc...
Address:
$000F
Bit 7
Read:
6
5
4
3
2
1
Bit 0
0
PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0
Write:
Reset:
0
0
0
0
0
0
0
0
Figure 16-16. Port D Input Pullup Enable Register (PTDPUE)
PTDPUE6–PTDPUE0 — Port D Input Pullup Enable Bits
These writeable bits are software programmable to enable pullup
devices on an input port bit.
1 = Corresponding port D pin configured to have internal pullup
0 = Corresponding port D pin has internal pullup disconnected
Technical Data
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Port E
16.7 Port E
Port E is a 2-bit special-function port that shares two of its pins with the
serial communications interface (SCI) module.
16.7.1 Port E Data Register
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The port E data register contains a data latch for each of the two port E
pins.
Address:
Read:
$0008
Bit 7
6
5
4
3
2
0
0
0
0
0
0
1
Bit 0
PTE1
PTE0
RxD
TxD
Write:
Reset:
Unaffected by reset
Alternate
Function:
= Unimplemented
Figure 16-17. Port E Data Register (PTE)
PTE1 and PTE0 — Port E Data Bits
PTE1 and PTE0 are read/write, software programmable bits. Data
direction of each port E pin is under the control of the corresponding
bit in data direction register E.
NOTE:
Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the SCI module. However, the DDRE
bits always determine whether reading port E returns the states of the
latches or the states of the pins. See Table 16-6.
RxD — SCI Receive Data Input
The PTE1/RxD pin is the receive data input for the SCI module. When
the enable SCI bit, ENSCI, is clear, the SCI module is disabled, and
the PTE1/RxD pin is available for general-purpose I/O. See Serial
Communications Interface (SCI).
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TxD — SCI Transmit Data Output
The PTE0/TxD pin is the transmit data output for the SCI module.
When the enable SCI bit, ENSCI, is clear, the SCI module is disabled,
and the PTE0/TxD pin is available for general-purpose I/O. See Serial
Communications Interface (SCI).
16.7.2 Data Direction Register E
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Data direction register E (DDRE) determines whether each port E pin is
an input or an output. Writing a logic 1 to a DDRE bit enables the output
buffer for the corresponding port E pin; a logic 0 disables the output
buffer.
Address:
Read:
$000C
Bit 7
6
5
4
3
2
0
0
0
0
0
0
1
Bit 0
DDRE1
DDRE0
0
0
Write:
Reset:
0
0
0
0
0
0
= Unimplemented
Figure 16-18. Data Direction Register E (DDRE)
DDRE1 and DDRE0 — Data Direction Register E Bits
These read/write bits control port E data direction. Reset clears
DDRE1 and DDRE0, configuring all port E pins as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
NOTE:
Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
Figure 16-19 shows the port E I/O logic.
Technical Data
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Input/Output Ports (I/O)
Port E
INTERNAL DATA BUS
READ DDRE ($000C)
WRITE DDRE ($000C)
RESET
DDREx
WRITE PTE ($0008)
PTEx
PTEx
READ PTE ($0008)
Figure 16-19. Port E I/O Circuit
When bit DDREx is a logic 1, reading address $0008 reads the PTEx
data latch. When bit DDREx is a logic 0, reading address $0008 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 16-6 summarizes
the operation of the port E pins.
Table 16-6. Port E Pin Functions
Accesses to DDRE
DDRE Bit
PTE Bit
Accesses to PTE
I/O Pin Mode
Read/Write
Read
Write
0
X(1)
Input, Hi-Z(2)
DDRE1–DDRE0
Pin
PTE1–PTE0(3)
1
X
Output
DDRE1–DDRE0]
PTE1–PTE0
PTE1–PTE0
Notes:
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
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Technical Data — MC68HC908GR8
Section 17. RAM
17.1 Contents
17.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
17.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
17.2 Introduction
This section describes the 384 bytes of RAM (random-access memory).
17.3 Functional Description
Addresses $0040 through $01BF are RAM locations. The location of the
stack RAM is programmable. The 16-bit stack pointer allows the stack to
be anywhere in the 64K byte memory space.
NOTE:
For correct operation, the stack pointer must point only to RAM
locations.
Within page zero are 192 bytes of RAM. Because the location of the
stack RAM is programmable, all page zero RAM locations can be used
for I/O control and user data or code. When the stack pointer is moved
from its reset location at $00FF out of page zero, direct addressing mode
instructions can efficiently access all page zero RAM locations. Page
zero RAM, therefore, provides ideal locations for frequently accessed
global variables.
Before processing an interrupt, the CPU uses five bytes of the stack to
save the contents of the CPU registers.
NOTE:
For M6805 compatibility, the H register is not stacked.
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RAM
During a subroutine call, the CPU uses two bytes of the stack to store
the return address. The stack pointer decrements during pushes and
increments during pulls.
Be careful when using nested subroutines. The CPU may overwrite data
in the RAM during a subroutine or during the interrupt stacking
operation.
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NOTE:
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Section 18. Serial Communications Interface (SCI)
18.1 Contents
18.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
18.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
18.4
Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
18.5
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
18.6
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
18.7
SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . . 251
18.8
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
18.9
I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
18.2 Introduction
This section describes the serial communications interface (SCI)
module, which allows high-speed asynchronous communications with
peripheral devices and other MCUs.
NOTE:
References to DMA (direct-memory access) and associated functions
are only valid if the MCU has a DMA module. This MCU does not have
the DMA function. Any DMA-related register bits should be left in their
reset state for normal MCU operation.
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18.3 Features
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Features of the SCI module include:
•
Full-duplex operation
•
Standard mark/space non-return-to-zero (NRZ) format
•
32 programmable baud rates
•
Programmable 8-bit or 9-bit character length
•
Separately enabled transmitter and receiver
•
Separate receiver and transmitter CPU interrupt requests
•
Programmable transmitter output polarity
•
Two receiver wakeup methods:
– Idle line wakeup
– Address mark wakeup
•
Interrupt-driven operation with eight interrupt flags:
– Transmitter empty
– Transmission complete
– Receiver full
– Idle receiver input
– Receiver overrun
– Noise error
– Framing error
– Parity error
•
Receiver framing error detection
•
Hardware parity checking
•
1/16 bit-time noise detection
•
Configuration register bit, SCIBDSRC, to allow selection of baud
rate clock source
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Serial Communications Interface (SCI)
Pin Name Conventions
18.4 Pin Name Conventions
The generic names of the SCI I/O pins are:
•
RxD (receive data)
•
TxD (transmit data)
SCI I/O (input/output) lines are implemented by sharing parallel I/O port
pins. The full name of an SCI input or output reflects the name of the
shared port pin. Table 18-1 shows the full names and the generic names
of the SCI I/O pins.
The generic pin names appear in the text of this section.
Table 18-1. Pin Name Conventions
Generic Pin Names:
RxD
TxD
Full Pin Names:
PE1/RxD
PE0/TxD
18.5 Functional Description
Figure 18-1 shows the structure of the SCI module. The SCI allows fullduplex, asynchronous, NRZ serial communication among the MCU and
remote devices, including other MCUs. The transmitter and receiver of
the SCI operate independently, although they use the same baud rate
generator. During normal operation, the CPU monitors the status of the
SCI, writes the data to be transmitted, and processes received data.
The baud rate clock source for the SCI can be selected via the
configuration bit, SCIBDSRC, of the CONFIG2 register ($001E). Source
selection values are shown in Figure 18-1.
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Serial Communications Interface (SCI)
INTERNAL BUS
SCI DATA
REGISTER
ERROR
INTERRUPT
CONTROL
RECEIVER
INTERRUPT
CONTROL
DMA
INTERRUPT
CONTROL
RECEIVE
SHIFT REGISTER
PE1/RxD
TRANSMITTER
INTERRUPT
CONTROL
SCI DATA
REGISTER
TRANSMIT
SHIFT REGISTER
PE2/TxD
TXINV
SCTIE
R8
TCIE
T8
SCRIE
ILIE
DMARE
TE
SCTE
RE
DMATE
TC
RWU
SBK
SCRF
OR
ORIE
IDLE
NF
NEIE
FE
FEIE
PE
PEIE
LOOPS
LOOPS
RECEIVE
CONTROL
WAKEUP
CONTROL
SCIBDSRC
FROM
CONFIG
ENSCI
ENSCI
FLAG
CONTROL
TRANSMIT
CONTROL
BKF
M
RPF
WAKE
ILTY
SL
A
CGMXCLK
X
B
IT12
SL = 0 => X = A
SL = 1 => X = B
÷4
PRESCALER
BAUD
DIVIDER
∏ ÷ 16
PEN
PTY
DATA SELECTION
CONTROL
Figure 18-1. SCI Module Block Diagram
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Serial Communications Interface (SCI)
Functional Description
Addr.
$0013
$0014
$0015
$0016
$0017
Register Name
6
5
4
3
2
1
Bit 0
ENSCI
TXINV
M
WAKE
ILTY
PEN
PTY
0
0
0
0
0
0
0
SCTIE
TCIE
SCRIE
ILIE
TE
RE
RWU
SBK
0
0
0
0
0
0
0
0
T8
DMARE
DMATE
ORIE
NEIE
FEIE
PEIE
Read:
LOOPS
SCI Control Register 1
Write:
(SCC1)
Reset:
0
Read:
SCI Control Register 2
Write:
(SCC2)
Reset:
Read:
SCI Control Register 3
Write:
(SCC3)
Reset:
R8
U
U
0
0
0
0
0
0
Read:
SCI Status Register 1
Write:
(SCS1)
Reset:
SCTE
TC
SCRF
IDLE
OR
NF
FE
PE
1
1
0
0
0
0
0
0
BKF
RPF
Read:
SCI Status Register 2
Write:
(SCS2)
Reset:
Read:
SCI Data Register
Write:
(SCDR)
Reset:
$0018
$0019
Bit 7
Read:
SCI Baud Rate Register
Write:
(SCBR)
Reset:
0
0
0
0
0
0
0
0
R7
R6
R5
R4
R3
R2
R1
R0
T7
T6
T5
T4
T3
T2
T1
T0
Unaffected by reset
0
0
SCP1
SCP0
R
SCR2
SCR1
SCR0
0
0
0
0
0
0
= Unimplemented
R = Reserved
U = Unaffected
Figure 18-2. SCI I/O Register Summary
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Serial Communications Interface (SCI)
18.5.1 Data Format
The SCI uses the standard non-return-to-zero mark/space data format
illustrated in Figure 18-3.
8-BIT DATA FORMAT
BIT M IN SCC1 CLEAR
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
PARITY
BIT
BIT 6
BIT 7
9-BIT DATA FORMAT
BIT M IN SCC1 SET
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
STOP
BIT
NEXT
START
BIT
PARITY
BIT
BIT 6
BIT 7
BIT 8
STOP
BIT
NEXT
START
BIT
Figure 18-3. SCI Data Formats
18.5.2 Transmitter
Figure 18-4 shows the structure of the SCI transmitter.
The baud rate clock source for the SCI can be selected via the
configuration bit, SCIBDSRC. Source selection values are shown in
Figure 18-4.
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Functional Description
SCIBDSRC
FROM
CONFIG2
SL
A
CGMXCLK
X
B
IT12
SL = 0 => X = A
SL = 1 => X = B
INTERNAL BUS
BAUD
DIVIDER
÷ 16
SCI DATA REGISTER
11-BIT
TRANSMIT
SHIFT REGISTER
STOP
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SCP1
SCP0
SCR1
H
SCR2
8
7
6
5
4
3
2
START
PRESCALER
÷4
1
0
L
PE2/TxD
MSB
TXINV
PARITY
GENERATION
T8
DMATE
DMATE
SCTIE
SCTE
DMATE
SCTE
SCTIE
TC
TCIE
BREAK
ALL 0s
PTY
PREAMBLE
ALL 1s
PEN
SHIFT ENABLE
M
LOAD FROM SCDR
TRANSMITTER DMA SERVICE REQUEST
TRANSMITTER CPU INTERRUPT REQUEST
SCR0
TRANSMITTER
CONTROL LOGIC
SCTE
SBK
LOOPS
SCTIE
ENSCI
TC
TE
TCIE
Figure 18-4. SCI Transmitter
18.5.2.1 Character Length
The transmitter can accommodate either 8-bit or 9-bit data. The state of
the M bit in SCI control register 1 (SCC1) determines character length.
When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3) is
the ninth bit (bit 8).
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18.5.2.2 Character Transmission
During an SCI transmission, the transmit shift register shifts a character
out to the PE2/TxD pin. The SCI data register (SCDR) is the write-only
buffer between the internal data bus and the transmit shift register. To
initiate an SCI transmission:
1. Enable the SCI by writing a logic 1 to the enable SCI bit (ENSCI)
in SCI control register 1 (SCC1).
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2. Enable the transmitter by writing a logic 1 to the transmitter enable
bit (TE) in SCI control register 2 (SCC2).
3. Clear the SCI transmitter empty bit by first reading SCI status
register 1 (SCS1) and then writing to the SCDR.
4. Repeat step 3 for each subsequent transmission.
At the start of a transmission, transmitter control logic automatically
loads the transmit shift register with a preamble of logic 1s. After the
preamble shifts out, control logic transfers the SCDR data into the
transmit shift register. A logic 0 start bit automatically goes into the least
significant bit position of the transmit shift register. A logic 1 stop bit goes
into the most significant bit position.
The SCI transmitter empty bit, SCTE, in SCS1 becomes set when the
SCDR transfers a byte to the transmit shift register. The SCTE bit
indicates that the SCDR can accept new data from the internal data bus.
If the SCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the
SCTE bit generates a transmitter CPU interrupt request.
When the transmit shift register is not transmitting a character, the
PE2/TxD pin goes to the idle condition, logic 1. If at any time software
clears the ENSCI bit in SCI control register 1 (SCC1), the transmitter and
receiver relinquish control of the port E pins.
18.5.2.3 Break Characters
Writing a logic 1 to the send break bit, SBK, in SCC2 loads the transmit
shift register with a break character. A break character contains all logic
0s and has no start, stop, or parity bit. Break character length depends
on the M bit in SCC1. As long as SBK is at logic 1, transmitter logic
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Functional Description
continuously loads break characters into the transmit shift register. After
software clears the SBK bit, the shift register finishes transmitting the
last break character and then transmits at least one logic 1. The
automatic logic 1 at the end of a break character guarantees the
recognition of the start bit of the next character.
The SCI recognizes a break character when a start bit is followed by
eight or nine logic 0 data bits and a logic 0 where the stop bit should be.
Receiving a break character has these effects on SCI registers:
•
Sets the framing error bit (FE) in SCS1
•
Sets the SCI receiver full bit (SCRF) in SCS1
•
Clears the SCI data register (SCDR)
•
Clears the R8 bit in SCC3
•
Sets the break flag bit (BKF) in SCS2
•
May set the overrun (OR), noise flag (NF), parity error (PE), or
reception in progress flag (RPF) bits
18.5.2.4 Idle Characters
An idle character contains all logic 1s and has no start, stop, or parity bit.
Idle character length depends on the M bit in SCC1. The preamble is a
synchronizing idle character that begins every transmission.
If the TE bit is cleared during a transmission, the PE2/TxD pin becomes
idle after completion of the transmission in progress. Clearing and then
setting the TE bit during a transmission queues an idle character to be
sent after the character currently being transmitted.
NOTE:
When queueing an idle character, return the TE bit to logic 1 before the
stop bit of the current character shifts out to the TxD pin. Setting TE after
the stop bit appears on TxD causes data previously written to the SCDR
to be lost.
Toggle the TE bit for a queued idle character when the SCTE bit
becomes set and just before writing the next byte to the SCDR.
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18.5.2.5 Inversion of Transmitted Output
The transmit inversion bit (TXINV) in SCI control register 1 (SCC1)
reverses the polarity of transmitted data. All transmitted values, including
idle, break, start, and stop bits, are inverted when TXINV is at logic 1.
See SCI Control Register 1.
18.5.2.6 Transmitter Interrupts
These conditions can generate CPU interrupt requests from the SCI
transmitter:
•
SCI transmitter empty (SCTE) — The SCTE bit in SCS1 indicates
that the SCDR has transferred a character to the transmit shift
register. SCTE can generate a transmitter CPU interrupt request.
Setting the SCI transmit interrupt enable bit, SCTIE, in SCC2
enables the SCTE bit to generate transmitter CPU interrupt
requests.
•
Transmission complete (TC) — The TC bit in SCS1 indicates that
the transmit shift register and the SCDR are empty and that no
break or idle character has been generated. The transmission
complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to
generate transmitter CPU interrupt requests.
18.5.3 Receiver
Figure 18-5 shows the structure of the SCI receiver.
18.5.3.1 Character Length
The receiver can accommodate either 8-bit or 9-bit data. The state of the
M bit in SCI control register 1 (SCC1) determines character length.
When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2) is the
ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth
bit (bit 7).
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Functional Description
18.5.3.2 Character Reception
During an SCI reception, the receive shift register shifts characters in
from the PE1/RxD pin. The SCI data register (SCDR) is the read-only
buffer between the internal data bus and the receive shift register.
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After a complete character shifts into the receive shift register, the data
portion of the character transfers to the SCDR. The SCI receiver full bit,
SCRF, in SCI status register 1 (SCS1) becomes set, indicating that the
received byte can be read. If the SCI receive interrupt enable bit, SCRIE,
in SCC2 is also set, the SCRF bit generates a receiver CPU interrupt
request.
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INTERNAL BUS
SCIBDSRC
FROM
CONFIG2
SCR1
SCR0
PRESCALER
BAUD
DIVIDER
÷ 16
DATA
RECOVERY
PE1/RxD
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ALL 1s
RPF
CPU INTERRUPT REQUEST
H
11-BIT
RECEIVE SHIFT REGISTER
8
7
6
5
M
WAKE
ILTY
PEN
PTY
4
3
2
1
0
L
ALL 0s
BKF
ERROR CPU INTERRUPT REQUEST
DMA SERVICE REQUEST
STOP
÷4
SCI DATA REGISTER
START
SCR2
SCP0
MSB
SL
CGMXCLK
A
X
B
IT12
SL = 0 => X = A
SL = 1 => X = B
SCP1
SCRF
WAKEUP
LOGIC
PARITY
CHECKING
IDLE
ILIE
DMARE
SCRF
SCRIE
DMARE
SCRF
SCRIE
DMARE
OR
ORIE
NF
NEIE
FE
FEIE
PE
PEIE
RWU
IDLE
R8
ILIE
SCRIE
DMARE
OR
ORIE
NF
NEIE
FE
FEIE
PE
PEIE
Figure 18-5. SCI Receiver Block Diagram
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18.5.3.3 Data Sampling
The receiver samples the PE1/RxD pin at the RT clock rate. The RT
clock is an internal signal with a frequency 16 times the baud rate. To
adjust for baud rate mismatch, the RT clock is resynchronized at the
following times (see Figure 18-6):
•
After every start bit
•
After the receiver detects a data bit change from logic 1 to logic 0
(after the majority of data bit samples at RT8, RT9, and RT10
returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
To locate the start bit, data recovery logic does an asynchronous search
for a logic 0 preceded by three logic 1s. When the falling edge of a
possible start bit occurs, the RT clock begins to count to 16.
START BIT
LSB
START BIT
VERIFICATION
DATA
SAMPLING
RT8
START BIT
QUALIFICATION
SAMPLES
RT3
PE1/RxD
RT4
RT3
RT2
RT1
RT16
RT15
RT14
RT13
RT12
RT11
RT10
RT9
RT7
RT6
RT5
RT4
RT2
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT CLOCK
STATE
RT1
RT
CLOCK
RT1
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RT CLOCK
RESET
Figure 18-6. Receiver Data Sampling
To verify the start bit and to detect noise, data recovery logic takes
samples at RT3, RT5, and RT7. Table 18-2 summarizes the results of
the start bit verification samples.
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Table 18-2. Start Bit Verification
RT3, RT5, and RT7 Samples
Start Bit
Verification
Noise Flag
000
Yes
0
001
Yes
1
010
Yes
1
011
No
0
100
Yes
1
101
No
0
110
No
0
111
No
0
Start bit verification is not successful if any two of the three verification
samples are logic 1s. If start bit verification is not successful, the RT
clock is reset and a new search for a start bit begins.
To determine the value of a data bit and to detect noise, recovery logic
takes samples at RT8, RT9, and RT10. Table 18-3 summarizes the
results of the data bit samples.
Table 18-3. Data Bit Recovery
RT8, RT9, and RT10 Samples
Data Bit Determination
Noise Flag
000
0
0
001
0
1
010
0
1
011
1
1
100
0
1
101
1
1
110
1
1
111
1
0
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Functional Description
NOTE:
The RT8, RT9, and RT10 samples do not affect start bit verification. If
any or all of the RT8, RT9, and RT10 start bit samples are logic 1s
following a successful start bit verification, the noise flag (NF) is set and
the receiver assumes that the bit is a start bit.
To verify a stop bit and to detect noise, recovery logic takes samples at
RT8, RT9, and RT10. Table 18-4 summarizes the results of the stop bit
samples.
Table 18-4. Stop Bit Recovery
RT8, RT9, and RT10
Samples
Framing
Error Flag
Noise Flag
000
1
0
001
1
1
010
1
1
011
0
1
100
1
1
101
0
1
110
0
1
111
0
0
18.5.3.4 Framing Errors
If the data recovery logic does not detect a logic 1 where the stop bit
should be in an incoming character, it sets the framing error bit, FE, in
SCS1. A break character also sets the FE bit because a break character
has no stop bit. The FE bit is set at the same time that the SCRF bit is
set.
18.5.3.5 Baud Rate Tolerance
A transmitting device may be operating at a baud rate below or above
the receiver baud rate. Accumulated bit time misalignment can cause
one of the three stop bit data samples to fall outside the actual stop bit.
Then a noise error occurs. If more than one of the samples is outside the
stop bit, a framing error occurs. In most applications, the baud rate
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tolerance is much more than the degree of misalignment that is likely to
occur.
As the receiver samples an incoming character, it resynchronizes the RT
clock on any valid falling edge within the character. Resynchronization
within characters corrects misalignments between transmitter bit times
and receiver bit times.
18.5.3.6 Slow Data Tolerance
RT16
RT15
RT14
RT13
RT11
RT10
RT9
RT8
RT7
RT6
STOP
RT5
RT4
RT3
RT2
RECEIVER
RT CLOCK
RT1
MSB
RT12
Freescale Semiconductor, Inc...
Figure 18-7 shows how much a slow received character can be
misaligned without causing a noise error or a framing error. The slow
stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit
data samples at RT8, RT9, and RT10.
DATA
SAMPLES
Figure 18-7. Slow Data
For an 8-bit character, data sampling of the stop bit takes the receiver
9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles.
With the misaligned character shown in Figure 18-7, the receiver counts
154 RT cycles at the point when the count of the transmitting device is
9 bit times × 16 RT cycles + 3 RT cycles = 147 RT cycles.
The maximum percent difference between the receiver count and the
transmitter count of a slow 8-bit character with no errors is
154 – 147 × 100 = 4.54%
-------------------------154
For a 9-bit character, data sampling of the stop bit takes the receiver
10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles.
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With the misaligned character shown in Figure 18-7, the receiver counts
170 RT cycles at the point when the count of the transmitting device is
10 bit times × 16 RT cycles + 3 RT cycles = 163 RT cycles.
The maximum percent difference between the receiver count and the
transmitter count of a slow 9-bit character with no errors is
170 – 163 × 100 = 4.12%
-------------------------170
18.5.3.7 Fast Data Tolerance
Figure 18-8 shows how much a fast received character can be
misaligned without causing a noise error or a framing error. The fast stop
bit ends at RT10 instead of RT16 but is still there for the stop bit data
samples at RT8, RT9, and RT10.
RT16
RT15
RT14
RT13
RT12
RT11
RT10
RT9
RT8
RT7
IDLE OR NEXT CHARACTER
RT6
RT5
RT4
RT3
RECEIVER
RT CLOCK
RT2
STOP
RT1
Freescale Semiconductor, Inc...
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DATA
SAMPLES
Figure 18-8. Fast Data
For an 8-bit character, data sampling of the stop bit takes the receiver
9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles.
With the misaligned character shown in Figure 18-8, the receiver counts
154 RT cycles at the point when the count of the transmitting device is
10 bit times × 16 RT cycles = 160 RT cycles.
The maximum percent difference between the receiver count and the
transmitter count of a fast 8-bit character with no errors is
·
154 – 160 × 100 = 3.90%
-------------------------154
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Serial Communications Interface (SCI)
For a 9-bit character, data sampling of the stop bit takes the receiver
10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles.
With the misaligned character shown in Figure 18-8, the receiver counts
170 RT cycles at the point when the count of the transmitting device is
11 bit times × 16 RT cycles = 176 RT cycles.
The maximum percent difference between the receiver count and the
transmitter count of a fast 9-bit character with no errors is
170 – 176 × 100 = 3.53%
-------------------------170
18.5.3.8 Receiver Wakeup
So that the MCU can ignore transmissions intended only for other
receivers in multiple-receiver systems, the receiver can be put into a
standby state. Setting the receiver wakeup bit, RWU, in SCC2 puts the
receiver into a standby state during which receiver interrupts are
disabled.
Depending on the state of the WAKE bit in SCC1, either of two
conditions on the PE1/RxD pin can bring the receiver out of the standby
state:
•
Address mark — An address mark is a logic 1 in the most
significant bit position of a received character. When the WAKE bit
is set, an address mark wakes the receiver from the standby state
by clearing the RWU bit. The address mark also sets the SCI
receiver full bit, SCRF. Software can then compare the character
containing the address mark to the user-defined address of the
receiver. If they are the same, the receiver remains awake and
processes the characters that follow. If they are not the same,
software can set the RWU bit and put the receiver back into the
standby state.
•
Idle input line condition — When the WAKE bit is clear, an idle
character on the PE1/RxD pin wakes the receiver from the
standby state by clearing the RWU bit. The idle character that
wakes the receiver does not set the receiver idle bit, IDLE, or the
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Serial Communications Interface (SCI)
Functional Description
SCI receiver full bit, SCRF. The idle line type bit, ILTY, determines
whether the receiver begins counting logic 1s as idle character bits
after the start bit or after the stop bit.
NOTE:
With the WAKE bit clear, setting the RWU bit after the RxD pin has been
idle may cause the receiver to wake up immediately.
18.5.3.9 Receiver Interrupts
The following sources can generate CPU interrupt requests from the SCI
receiver:
•
SCI receiver full (SCRF) — The SCRF bit in SCS1 indicates that
the receive shift register has transferred a character to the SCDR.
SCRF can generate a receiver CPU interrupt request. Setting the
SCI receive interrupt enable bit, SCRIE, in SCC2 enables the
SCRF bit to generate receiver CPU interrupts.
•
Idle input (IDLE) — The IDLE bit in SCS1 indicates that 10 or 11
consecutive logic 1s shifted in from the PE1/RxD pin. The idle line
interrupt enable bit, ILIE, in SCC2 enables the IDLE bit to generate
CPU interrupt requests.
18.5.3.10 Error Interrupts
The following receiver error flags in SCS1 can generate CPU interrupt
requests:
•
Receiver overrun (OR) — The OR bit indicates that the receive
shift register shifted in a new character before the previous
character was read from the SCDR. The previous character
remains in the SCDR, and the new character is lost. The overrun
interrupt enable bit, ORIE, in SCC3 enables OR to generate SCI
error CPU interrupt requests.
•
Noise flag (NF) — The NF bit is set when the SCI detects noise on
incoming data or break characters, including start, data, and stop
bits. The noise error interrupt enable bit, NEIE, in SCC3 enables
NF to generate SCI error CPU interrupt requests.
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Serial Communications Interface (SCI)
•
Framing error (FE) — The FE bit in SCS1 is set when a logic 0
occurs where the receiver expects a stop bit. The framing error
interrupt enable bit, FEIE, in SCC3 enables FE to generate SCI
error CPU interrupt requests.
•
Parity error (PE) — The PE bit in SCS1 is set when the SCI
detects a parity error in incoming data. The parity error interrupt
enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU
interrupt requests.
18.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low powerconsumption standby modes.
18.6.1 Wait Mode
The SCI module remains active after the execution of a WAIT
instruction. In wait mode, the SCI module registers are not accessible by
the CPU. Any enabled CPU interrupt request from the SCI module can
bring the MCU out of wait mode.
If SCI module functions are not required during wait mode, reduce power
consumption by disabling the module before executing the WAIT
instruction.
Refer to Low Power Modes for information on exiting wait mode.
18.6.2 Stop Mode
The SCI module is inactive after the execution of a STOP instruction.
The STOP instruction does not affect SCI register states. SCI module
operation resumes after an external interrupt.
Because the internal clock is inactive during stop mode, entering stop
mode during an SCI transmission or reception results in invalid data.
Refer to Low Power Modes for information on exiting stop mode.
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Serial Communications Interface (SCI)
SCI During Break Module Interrupts
18.7 SCI During Break Module Interrupts
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state.
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a 2-step read/write clearing procedure. If software does
the first step on such a bit before the break, the bit cannot change during
the break state as long as BCFE is at logic 0. After the break, doing the
second step clears the status bit.
18.8 I/O Signals
Port E shares two of its pins with the SCI module. The two SCI I/O pins
are:
•
PE2/TxD — Transmit data
•
PE1/RxD — Receive data
18.8.1 PE2/TxD (Transmit Data)
The PE2/TxD pin is the serial data output from the SCI transmitter. The
SCI shares the PE2/TxD pin with port E. When the SCI is enabled, the
PE2/TxD pin is an output regardless of the state of the DDRE0 bit in data
direction register E (DDRE).
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Serial Communications Interface (SCI)
18.8.2 PE1/RxD (Receive Data)
The PE1/RxD pin is the serial data input to the SCI receiver. The SCI
shares the PE1/RxD pin with port E. When the SCI is enabled, the
PE1/RxD pin is an input regardless of the state of the DDRE1 bit in data
direction register E (DDRE).
18.9 I/O Registers
These I/O registers control and monitor SCI operation:
•
SCI control register 1 (SCC1)
•
SCI control register 2 (SCC2)
•
SCI control register 3 (SCC3)
•
SCI status register 1 (SCS1)
•
SCI status register 2 (SCS2)
•
SCI data register (SCDR)
•
SCI baud rate register (SCBR)
18.9.1 SCI Control Register 1
SCI control register 1:
•
Enables loop mode operation
•
Enables the SCI
•
Controls output polarity
•
Controls character length
•
Controls SCI wakeup method
•
Controls idle character detection
•
Enables parity function
•
Controls parity type
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I/O Registers
Address:
$0013
Bit 7
6
5
4
3
2
1
Bit 0
LOOPS
ENSCI
TXINV
M
WAKE
ILTY
PEN
PTY
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Freescale Semiconductor, Inc...
Figure 18-9. SCI Control Register 1 (SCC1)
LOOPS — Loop Mode Select Bit
This read/write bit enables loop mode operation. In loop mode the
PE1/RxD pin is disconnected from the SCI, and the transmitter output
goes into the receiver input. Both the transmitter and the receiver
must be enabled to use loop mode. Reset clears the LOOPS bit.
1 = Loop mode enabled
0 = Normal operation enabled
ENSCI — Enable SCI Bit
This read/write bit enables the SCI and the SCI baud rate generator.
Clearing ENSCI sets the SCTE and TC bits in SCI status register 1
and disables transmitter interrupts. Reset clears the ENSCI bit.
1 = SCI enabled
0 = SCI disabled
TXINV — Transmit Inversion Bit
This read/write bit reverses the polarity of transmitted data. Reset
clears the TXINV bit.
1 = Transmitter output inverted
0 = Transmitter output not inverted
NOTE:
Setting the TXINV bit inverts all transmitted values, including idle, break,
start, and stop bits.
M — Mode (Character Length) Bit
This read/write bit determines whether SCI characters are eight or
nine bits long. See Table 18-5. The ninth bit can serve as an extra
stop bit, as a receiver wakeup signal, or as a parity bit. Reset clears
the M bit.
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1 = 9-bit SCI characters
0 = 8-bit SCI characters
WAKE — Wakeup Condition Bit
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This read/write bit determines which condition wakes up the SCI: a
logic 1 (address mark) in the most significant bit position of a received
character or an idle condition on the PE1/RxD pin. Reset clears the
WAKE bit.
1 = Address mark wakeup
0 = Idle line wakeup
ILTY — Idle Line Type Bit
This read/write bit determines when the SCI starts counting logic 1s
as idle character bits. The counting begins either after the start bit or
after the stop bit. If the count begins after the start bit, then a string of
logic 1s preceding the stop bit may cause false recognition of an idle
character. Beginning the count after the stop bit avoids false idle
character recognition, but requires properly synchronized
transmissions. Reset clears the ILTY bit.
1 = Idle character bit count begins after stop bit
0 = Idle character bit count begins after start bit
PEN — Parity Enable Bit
This read/write bit enables the SCI parity function. See Table 18-5.
When enabled, the parity function inserts a parity bit in the most
significant bit position. See Figure 18-3. Reset clears the PEN bit.
1 = Parity function enabled
0 = Parity function disabled
PTY — Parity Bit
This read/write bit determines whether the SCI generates and checks
for odd parity or even parity. See Table 18-5. Reset clears the PTY bit.
1 = Odd parity
0 = Even parity
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Serial Communications Interface (SCI)
I/O Registers
NOTE:
Changing the PTY bit in the middle of a transmission or reception can
generate a parity error.
Table 18-5. Character Format Selection
Control Bits
Character Format
M
PEN and
PTY
Start
Bits
Data
Bits
Parity
Stop
Bits
Character
Length
0
0X
1
8
None
1
10 bits
1
0X
1
9
None
1
11 bits
0
10
1
7
Even
1
10 bits
0
11
1
7
Odd
1
10 bits
1
10
1
8
Even
1
11 bits
1
11
1
8
Odd
1
11 bits
18.9.2 SCI Control Register 2
SCI control register 2:
•
Enables the following CPU interrupt requests:
– Enables the SCTE bit to generate transmitter CPU interrupt
requests
– Enables the TC bit to generate transmitter CPU interrupt
requests
– Enables the SCRF bit to generate receiver CPU interrupt
requests
– Enables the IDLE bit to generate receiver CPU interrupt
requests
•
Enables the transmitter
•
Enables the receiver
•
Enables SCI wakeup
•
Transmits SCI break characters
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Address:
$0014
Bit 7
6
5
4
3
2
1
Bit 0
SCTIE
TCIE
SCRIE
ILIE
TE
RE
RWU
SBK
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Freescale Semiconductor, Inc...
Figure 18-10. SCI Control Register 2 (SCC2)
SCTIE — SCI Transmit Interrupt Enable Bit
This read/write bit enables the SCTE bit to generate SCI transmitter
CPU interrupt requests. Reset clears the SCTIE bit.
1 = SCTE enabled to generate CPU interrupt
0 = SCTE not enabled to generate CPU interrupt
TCIE — Transmission Complete Interrupt Enable Bit
This read/write bit enables the TC bit to generate SCI transmitter CPU
interrupt requests. Reset clears the TCIE bit.
1 = TC enabled to generate CPU interrupt requests
0 = TC not enabled to generate CPU interrupt requests
SCRIE — SCI Receive Interrupt Enable Bit
This read/write bit enables the SCRF bit to generate SCI receiver
CPU interrupt requests. Reset clears the SCRIE bit.
1 = SCRF enabled to generate CPU interrupt
0 = SCRF not enabled to generate CPU interrupt
ILIE — Idle Line Interrupt Enable Bit
This read/write bit enables the IDLE bit to generate SCI receiver CPU
interrupt requests. Reset clears the ILIE bit.
1 = IDLE enabled to generate CPU interrupt requests
0 = IDLE not enabled to generate CPU interrupt requests
TE — Transmitter Enable Bit
Setting this read/write bit begins the transmission by sending a
preamble of 10 or 11 logic 1s from the transmit shift register to the
PE2/TxD pin. If software clears the TE bit, the transmitter completes
any transmission in progress before the PE2/TxD returns to the idle
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I/O Registers
condition (logic 1). Clearing and then setting TE during a transmission
queues an idle character to be sent after the character currently being
transmitted. Reset clears the TE bit.
1 = Transmitter enabled
0 = Transmitter disabled
NOTE:
Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is
clear. ENSCI is in SCI control register 1.
RE — Receiver Enable Bit
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Setting this read/write bit enables the receiver. Clearing the RE bit
disables the receiver but does not affect receiver interrupt flag bits.
Reset clears the RE bit.
1 = Receiver enabled
0 = Receiver disabled
NOTE:
Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is
clear. ENSCI is in SCI control register 1.
RWU — Receiver Wakeup Bit
This read/write bit puts the receiver in a standby state during which
receiver interrupts are disabled. The WAKE bit in SCC1 determines
whether an idle input or an address mark brings the receiver out of the
standby state and clears the RWU bit. Reset clears the RWU bit.
1 = Standby state
0 = Normal operation
SBK — Send Break Bit
Setting and then clearing this read/write bit transmits a break
character followed by a logic 1. The logic 1 after the break character
guarantees recognition of a valid start bit. If SBK remains set, the
transmitter continuously transmits break characters with no logic 1s
between them. Reset clears the SBK bit.
1 = Transmit break characters
0 = No break characters being transmitted
NOTE:
Do not toggle the SBK bit immediately after setting the SCTE bit.
Toggling SBK before the preamble begins causes the SCI to send a
break character instead of a preamble.
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18.9.3 SCI Control Register 3
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SCI control register 3:
•
Stores the ninth SCI data bit received and the ninth SCI data bit to
be transmitted
•
Enables these interrupts:
– Receiver overrun interrupts
– Noise error interrupts
– Framing error interrupts
•
Parity error interrupts
Address:
$0015
Bit 7
Read:
6
5
4
3
2
1
Bit 0
T8
DMARE
DMATE
ORIE
NEIE
FEIE
PEIE
U
0
0
0
0
0
0
R8
Write:
Reset:
U
= Unimplemented
U = Unaffected
Figure 18-11. SCI Control Register 3 (SCC3)
R8 — Received Bit 8
When the SCI is receiving 9-bit characters, R8 is the read-only ninth
bit (bit 8) of the received character. R8 is received at the same time
that the SCDR receives the other 8 bits.
When the SCI is receiving 8-bit characters, R8 is a copy of the eighth
bit (bit 7). Reset has no effect on the R8 bit.
T8 — Transmitted Bit 8
When the SCI is transmitting 9-bit characters, T8 is the read/write
ninth bit (bit 8) of the transmitted character. T8 is loaded into the
transmit shift register at the same time that the SCDR is loaded into
the transmit shift register. Reset has no effect on the T8 bit.
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I/O Registers
DMARE — DMA Receive Enable Bit
CAUTION:
The DMA module is not included on this MCU. Writing a logic 1 to
DMARE or DMATE may adversely affect MCU performance.
1 = DMA not enabled to service SCI receiver DMA service requests
generated by the SCRF bit (SCI receiver CPU interrupt
requests enabled)
0 = DMA not enabled to service SCI receiver DMA service requests
generated by the SCRF bit (SCI receiver CPU interrupt
requests enabled)
DMATE — DMA Transfer Enable Bit
CAUTION:
The DMA module is not included on this MCU. Writing a logic 1 to
DMARE or DMATE may adversely affect MCU performance.
1 = SCTE DMA service requests enabled; SCTE CPU interrupt
requests disabled
0 = SCTE DMA service requests disabled; SCTE CPU interrupt
requests enabled
ORIE — Receiver Overrun Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests
generated by the receiver overrun bit, OR.
1 = SCI error CPU interrupt requests from OR bit enabled
0 = SCI error CPU interrupt requests from OR bit disabled
NEIE — Receiver Noise Error Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests
generated by the noise error bit, NE. Reset clears NEIE.
1 = SCI error CPU interrupt requests from NE bit enabled
0 = SCI error CPU interrupt requests from NE bit disabled
FEIE — Receiver Framing Error Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests
generated by the framing error bit, FE. Reset clears FEIE.
1 = SCI error CPU interrupt requests from FE bit enabled
0 = SCI error CPU interrupt requests from FE bit disabled
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PEIE — Receiver Parity Error Interrupt Enable Bit
This read/write bit enables SCI receiver CPU interrupt requests
generated by the parity error bit, PE. See SCI Status Register 1.
Reset clears PEIE.
1 = SCI error CPU interrupt requests from PE bit enabled
0 = SCI error CPU interrupt requests from PE bit disabled
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18.9.4 SCI Status Register 1
SCI status register 1 (SCS1) contains flags to signal these conditions:
•
Transfer of SCDR data to transmit shift register complete
•
Transmission complete
•
Transfer of receive shift register data to SCDR complete
•
Receiver input idle
•
Receiver overrun
•
Noisy data
•
Framing error
•
Parity error
Address:
Read:
$0016
Bit 7
6
5
4
3
2
1
Bit 0
SCTE
TC
SCRF
IDLE
OR
NF
FE
PE
1
1
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 18-12. SCI Status Register 1 (SCS1)
SCTE — SCI Transmitter Empty Bit
This clearable, read-only bit is set when the SCDR transfers a
character to the transmit shift register. SCTE can generate an SCI
transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set,
SCTE generates an SCI transmitter CPU interrupt request. In normal
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operation, clear the SCTE bit by reading SCS1 with SCTE set and
then writing to SCDR. Reset sets the SCTE bit.
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
TC — Transmission Complete Bit
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This read-only bit is set when the SCTE bit is set, and no data,
preamble, or break character is being transmitted. TC generates an
SCI transmitter CPU interrupt request if the TCIE bit in SCC2 is also
set. TC is automatically cleared when data, preamble or break is
queued and ready to be sent. There may be up to 1.5 transmitter
clocks of latency between queueing data, preamble, and break and
the transmission actually starting. Reset sets the TC bit.
1 = No transmission in progress
0 = Transmission in progress
SCRF — SCI Receiver Full Bit
This clearable, read-only bit is set when the data in the receive shift
register transfers to the SCI data register. SCRF can generate an SCI
receiver CPU interrupt request. When the SCRIE bit in SCC2 is set,
SCRF generates a CPU interrupt request. In normal operation, clear
the SCRF bit by reading SCS1 with SCRF set and then reading the
SCDR. Reset clears SCRF.
1 = Received data available in SCDR
0 = Data not available in SCDR
IDLE — Receiver Idle Bit
This clearable, read-only bit is set when 10 or 11 consecutive logic 1s
appear on the receiver input. IDLE generates an SCI error CPU
interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE bit
by reading SCS1 with IDLE set and then reading the SCDR. After the
receiver is enabled, it must receive a valid character that sets the
SCRF bit before an idle condition can set the IDLE bit. Also, after the
IDLE bit has been cleared, a valid character must again set the SCRF
bit before an idle condition can set the IDLE bit. Reset clears the IDLE
bit.
1 = Receiver input idle
0 = Receiver input active (or idle since the IDLE bit was cleared)
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OR — Receiver Overrun Bit
This clearable, read-only bit is set when software fails to read the
SCDR before the receive shift register receives the next character.
The OR bit generates an SCI error CPU interrupt request if the ORIE
bit in SCC3 is also set. The data in the shift register is lost, but the data
already in the SCDR is not affected. Clear the OR bit by reading SCS1
with OR set and then reading the SCDR. Reset clears the OR bit.
1 = Receive shift register full and SCRF = 1
0 = No receiver overrun
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Software latency may allow an overrun to occur between reads of
SCS1 and SCDR in the flag-clearing sequence. Figure 18-13 shows
the normal flag-clearing sequence and an example of an overrun
caused by a delayed flag-clearing sequence. The delayed read of
SCDR does not clear the OR bit because OR was not set when SCS1
was read. Byte 2 caused the overrun and is lost. The next flagclearing sequence reads byte 3 in the SCDR instead of byte 2.
In applications that are subject to software latency or in which it is
important to know which byte is lost due to an overrun, the flagclearing routine can check the OR bit in a second read of SCS1 after
reading the data register.
NF — Receiver Noise Flag Bit
This clearable, read-only bit is set when the SCI detects noise on the
PE1/RxD pin. NF generates an NF CPU interrupt request if the NEIE
bit in SCC3 is also set. Clear the NF bit by reading SCS1 and then
reading the SCDR. Reset clears the NF bit.
1 = Noise detected
0 = No noise detected
FE — Receiver Framing Error Bit
This clearable, read-only bit is set when a logic 0 is accepted as the
stop bit. FE generates an SCI error CPU interrupt request if the FEIE
bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set
and then reading the SCDR. Reset clears the FE bit.
1 = Framing error detected
0 = No framing error detected
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BYTE 1
BYTE 2
BYTE 3
SCRF = 0
SCRF = 1
SCRF = 0
SCRF = 1
SCRF = 0
SCRF = 1
NORMAL FLAG CLEARING SEQUENCE
BYTE 4
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 1
READ SCDR
BYTE 2
READ SCDR
BYTE 3
BYTE 1
BYTE 2
BYTE 3
SCRF = 0
OR = 0
SCRF = 1
OR = 1
SCRF = 0
OR = 1
SCRF = 1
SCRF = 1
OR = 1
DELAYED FLAG CLEARING SEQUENCE
BYTE 4
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 1
READ SCDR
BYTE 1
READ SCDR
BYTE 3
Figure 18-13. Flag Clearing Sequence
PE — Receiver Parity Error Bit
This clearable, read-only bit is set when the SCI detects a parity error
in incoming data. PE generates a PE CPU interrupt request if the
PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with
PE set and then reading the SCDR. Reset clears the PE bit.
1 = Parity error detected
0 = No parity error detected
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18.9.5 SCI Status Register 2
SCI status register 2 contains flags to signal the following conditions:
•
Break character detected
•
Incoming data
Address:
$0017
Bit 7
6
5
4
3
2
Read:
1
Bit 0
BKF
RPF
0
0
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Write:
Reset:
0
0
0
0
0
0
= Unimplemented
Figure 18-14. SCI Status Register 2 (SCS2)
BKF — Break Flag Bit
This clearable, read-only bit is set when the SCI detects a break
character on the PE1/RxD pin. In SCS1, the FE and SCRF bits are
also set. In 9-bit character transmissions, the R8 bit in SCC3 is
cleared. BKF does not generate a CPU interrupt request. Clear BKF
by reading SCS2 with BKF set and then reading the SCDR. Once
cleared, BKF can become set again only after logic 1s again appear
on the PE1/RxD pin followed by another break character. Reset
clears the BKF bit.
1 = Break character detected
0 = No break character detected
RPF — Reception in Progress Flag Bit
This read-only bit is set when the receiver detects a logic 0 during the
RT1 time period of the start bit search. RPF does not generate an
interrupt request. RPF is reset after the receiver detects false start bits
(usually from noise or a baud rate mismatch) or when the receiver
detects an idle character. Polling RPF before disabling the SCI
module or entering stop mode can show whether a reception is in
progress.
1 = Reception in progress
0 = No reception in progress
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I/O Registers
18.9.6 SCI Data Register
The SCI data register (SCDR) is the buffer between the internal data bus
and the receive and transmit shift registers. Reset has no effect on data
in the SCI data register.
Address:
$0018
Bit 7
6
5
4
3
2
1
Bit 0
Read:
R7
R6
R5
R4
R3
R2
R1
R0
Write:
T7
T6
T5
T4
T3
T2
T1
T0
Reset:
Unaffected by reset
Figure 18-15. SCI Data Register (SCDR)
R7/T7–R0/T0 — Receive/Transmit Data Bits
Reading address $0018 accesses the read-only received data bits,
R7:R0. Writing to address $0018 writes the data to be transmitted,
T7:T0. Reset has no effect on the SCI data register.
NOTE:
Do not use read/modify/write instructions on the SCI data register.
18.9.7 SCI Baud Rate Register
The baud rate register (SCBR) selects the baud rate for both the receiver
and the transmitter.
Address:
$0019
Bit 7
6
5
4
3
2
1
Bit 0
SCP1
SCP0
R
SCR2
SCR1
SCR0
0
0
0
0
0
0
R
= Reserved
Read:
Write:
Reset:
0
0
= Unimplemented
Figure 18-16. SCI Baud Rate Register (SCBR)
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SCP1 and SCP0 — SCI Baud Rate Prescaler Bits
These read/write bits select the baud rate prescaler divisor as shown
in Table 18-6. Reset clears SCP1 and SCP0.
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Table 18-6. SCI Baud Rate Prescaling
SCP1 and SCP0
Prescaler Divisor (PD)
00
1
01
3
10
4
11
13
SCR2–SCR0 — SCI Baud Rate Select Bits
These read/write bits select the SCI baud rate divisor as shown in
Table 18-7. Reset clears SCR2–SCR0.
Table 18-7. SCI Baud Rate Selection
SCR2, SCR1,
and SCR0
Baud Rate
Divisor (BD)
000
1
001
2
010
4
011
8
100
16
101
32
110
64
111
128
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I/O Registers
Use this formula to calculate the SCI baud rate:
f BUS
baud rate = -----------------------------------64 × PD × BD
where:
fBUS = bus frequency
PD = prescaler divisor
BD = baud rate divisor
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SCI_BDSRC is an input to the SCI. Normally it will be tied off low at the
top level to select the bus clock as the clock source. This makes the
formula:
f BUS
baud rate = -----------------------------------64 × PD × BD
Table 18-8 shows the SCI baud rates that can be generated with a
4.9152-MHz bus clock.
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Table 18-8. SCI Baud Rate Selection Examples
SCP1 and
SCP0
Prescaler
Divisor (PD)
SCR2, SCR1,
and SCR0
Baud Rate
Divisor (BD)
Baud Rate
(fBUS = 4.9152 MHz)
00
1
000
1
76,800
00
1
001
2
38,400
00
1
010
4
19,200
00
1
011
8
9600
00
1
100
16
4800
00
1
101
32
2400
00
1
110
64
1200
00
1
111
128
600
01
3
000
1
25,600
01
3
001
2
12,800
01
3
010
4
6400
01
3
011
8
3200
01
3
100
16
1600
01
3
101
32
800
01
3
110
64
400
01
3
111
128
200
10
4
000
1
19,200
10
4
001
2
9600
10
4
010
4
4800
10
4
011
8
2400
10
4
100
16
1200
10
4
101
32
600
10
4
110
64
300
10
4
111
128
150
11
13
000
1
5908
11
13
001
2
2954
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Table 18-8. SCI Baud Rate Selection Examples
SCP1 and
SCP0
Prescaler
Divisor (PD)
SCR2, SCR1,
and SCR0
Baud Rate
Divisor (BD)
Baud Rate
(fBUS = 4.9152 MHz)
11
13
010
4
1477
11
13
011
8
739
11
13
100
16
369
11
13
101
32
185
11
13
110
64
92
11
13
111
128
46
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Technical Data — MC68HC908GR8
Section 19. System Integration Module (SIM)
19.1 Contents
19.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
19.3
SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . 275
19.4
Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . 276
19.5
SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
19.6
Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
19.7
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290
19.8
SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
19.2 Introduction
This section describes the system integration module (SIM). Together
with the CPU, the SIM controls all MCU activities. A block diagram of the
SIM is shown in Figure 19-1. Table 19-1 is a summary of the SIM
input/output (I/O) registers. The SIM is a system state controller that
coordinates CPU and exception timing. The SIM is responsible for:
•
Bus clock generation and control for CPU and peripherals:
– Stop/wait/reset/break entry and recovery
– Internal clock control
•
Master reset control, including power-on reset (POR) and COP
timeout
•
Interrupt control:
– Acknowledge timing
– Arbitration control timing
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System Integration Module (SIM)
– Vector address generation
•
CPU enable/disable timing
•
Modular architecture expandable to 128 interrupt sources
Table 19-1 shows the internal signal names used in this section.
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
STOP/WAIT
CONTROL
SIMOSCEN (TO CGM)
SIM
COUNTER
COP CLOCK
CGMXCLK (FROM CGM)
CGMOUT (FROM CGM)
÷2
CLOCK
CONTROL
VDD
CLOCK GENERATORS
INTERNAL CLOCKS
INTERNAL
PULLUP
DEVICE
RESET
PIN LOGIC
LVI (FROM LVI MODULE)
POR CONTROL
MASTER
RESET
CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP (FROM COP MODULE)
RESET
INTERRUPT CONTROL
AND PRIORITY DECODE
INTERRUPT SOURCES
CPU INTERFACE
Figure 19-1. SIM Block Diagram
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Introduction
Table 19-1. Signal Name Conventions
Signal Name
Description
CGMXCLK
Buffered version of OSC1 from clock generator module (CGM)
CGMVCLK
PLL output
CGMOUT
PLL-based or OSC1-based clock output from CGM module
(Bus clock = CGMOUT divided by two)
IAB
Internal address bus
IDB
Internal data bus
PORRST
Signal from the power-on reset module to the SIM
IRST
Internal reset signal
R/W
Read/write signal
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Addr.
Register Name
Read:
SIM Break Status Register
$FE00
Write:
(SBSR)
Reset:
Bit 7
6
5
4
3
2
R
R
R
R
R
R
1
Bit 0
SBSW
R
NOTE
0
0
0
0
0
0
0
0
POR
PIN
COP
ILOP
ILAD
MODRST
LVI
0
1
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
BCFE
R
R
R
R
R
R
R
Note: Writing a logic 0 clears SBSW.
Read:
SIM Reset Status Register
$FE01
Write:
(SRSR)
POR:
Read:
SIM Upper Byte Address
$FE02
Write:
Register (SUBAR)
Reset:
$FE03
Read:
SIM Break Flag Control
Write:
Register (SBFCR)
Reset:
0
Read:
Interrupt Status Register 1
$FE09
Write:
(INT1)
Reset:
IF6
IF5
IF4
IF3
IF2
IF1
0
0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Read:
Interrupt Status Register 2
$FE0A
Write:
(INT2)
Reset:
IF14
IF13
IF12
IF11
IF10
IF9
IF8
IF7
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Read:
Interrupt Status Register 3
$FE0B
Write:
(INT3)
Reset:
0
0
0
0
0
0
IF16
IF15
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
= Unimplemented
Figure 19-2. SIM I/O Register Summary
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SIM Bus Clock Control and Generation
19.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, CGMOUT, as shown in Figure 19-3. This clock can
come from either an external oscillator or from the on-chip PLL. See
Clock Generator Module (CGMC).
OSC2
OSCILLATOR (OSC)
CGMXCLK
OSC1
TO TIMTB15A, ADC
SIM
OSCSTOPENB
FROM
CONFIG
SIM COUNTER
CGMRCLK
CGMOUT
÷2
PHASE-LOCKED LOOP (PLL)
BUS CLOCK
GENERATORS
SIMOSCEN
IT12
TO REST
OF CHIP
IT23
TO REST
OF CHIP
Figure 19-3. CGM Clock Signals
19.3.1 Bus Timing
In user mode, the internal bus frequency is either the crystal oscillator
output (CGMXCLK) divided by four or the PLL output (CGMVCLK)
divided by four. See External Interrupt (IRQ).
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19.3.2 Clock Startup from POR or LVI Reset
When the power-on reset module or the low-voltage inhibit module
generates a reset, the clocks to the CPU and peripherals are inactive
and held in an inactive phase until after the 4096 CGMXCLK cycle POR
timeout has completed. The RST pin is driven low by the SIM during this
entire period. The IBUS clocks start upon completion of the timeout.
19.3.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows
CGMXCLK to clock the SIM counter. The CPU and peripheral clocks do
not become active until after the stop delay timeout. This timeout is
selectable as 4096 or 32 CGMXCLK cycles. See Stop Mode.
In wait mode, the CPU clocks are inactive. The SIM also produces two
sets of clocks for other modules. Refer to the wait mode subsection of
each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
19.4 Reset and System Initialization
The MCU has these reset sources:
•
Power-on reset module (POR)
•
External reset pin (RST)
•
Computer operating properly module (COP)
•
Low-voltage inhibit module (LVI)
•
Illegal opcode
•
Illegal address
All of these resets produce the vector $FFFE:$FFFF ($FEFE:$FEFF in
monitor mode) and assert the internal reset signal (IRST). IRST causes
all registers to be returned to their default values and all modules to be
returned to their reset states.
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Reset and System Initialization
An internal reset clears the SIM counter (see SIM Counter), but an
external reset does not. Each of the resets sets a corresponding bit in
the SIM reset status register (SRSR). See SIM Registers.
19.4.1 External Pin Reset
The RST pin circuit includes an internal pullup device. Pulling the
asynchronous RST pin low halts all processing. The PIN bit of the SIM
reset status register (SRSR) is set as long as RST is held low for a
minimum of 67 CGMXCLK cycles, assuming that neither the POR nor
the LVI was the source of the reset. See Table 19-2 for details. Figure
19-4 shows the relative timing.
Table 19-2. PIN Bit Set Timing
Reset Type
Number of Cycles Required to Set PIN
POR/LVI
4163 (4096 + 64 + 3)
All others
67 (64 + 3)
CGMOUT
RST
IAB
VECT H VECT L
PC
Figure 19-4. External Reset Timing
19.4.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK
cycles to allow resetting of external peripherals. The internal reset signal
IRST continues to be asserted for an additional 32 cycles. See Figure
19-5. An internal reset can be caused by an illegal address, illegal
opcode, COP timeout, LVI, or POR. See Figure 19-6.
NOTE:
For LVI or POR resets, the SIM cycles through 4096 CGMXCLK cycles
during which the SIM forces the RST pin low. The internal reset signal
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then follows the sequence from the falling edge of RST shown in Figure
19-5.
IRST
RST
RST PULLED LOW BY MCU
32 CYCLES
32 CYCLES
CGMXCLK
IAB
VECTOR HIGH
Figure 19-5. Internal Reset Timing
The COP reset is asynchronous to the bus clock.
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
LVI
POR
INTERNAL RESET
Figure 19-6. Sources of Internal Reset
The active reset feature allows the part to issue a reset to peripherals
and other chips within a system built around the MCU.
19.4.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module
(POR) generates a pulse to indicate that power-on has occurred. The
external reset pin (RST) is held low while the SIM counter counts out
4096 CGMXCLK cycles. Sixty-four CGMXCLK cycles later, the CPU and
memories are released from reset to allow the reset vector sequence to
occur.
At power-on, these events occur:
•
A POR pulse is generated.
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Reset and System Initialization
•
The internal reset signal is asserted.
•
The SIM enables CGMOUT.
•
Internal clocks to the CPU and modules are held inactive for 4096
CGMXCLK cycles to allow stabilization of the oscillator.
•
The RST pin is driven low during the oscillator stabilization time.
•
The POR bit of the SIM reset status register (SRSR) is set and all
other bits in the register are cleared.
OSC1
PORRST
4096
CYCLES
32
CYCLES
32
CYCLES
CGMXCLK
CGMOUT
RST
$FFFE
IAB
$FFFF
Figure 19-7. POR Recovery
19.4.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of
the COP counter causes an internal reset and sets the COP bit in the
SIM reset status register (SRSR). The SIM actively pulls down the RST
pin for all internal reset sources.
To prevent a COP module timeout, write any value to location $FFFF.
Writing to location $FFFF clears the COP counter and bits 12 through 4
of the SIM counter. The SIM counter output, which occurs at least every
213 – 24 CGMXCLK cycles, drives the COP counter. The COP should be
serviced as soon as possible out of reset to guarantee the maximum
amount of time before the first timeout.
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The COP module is disabled if the RST pin or the IRQ pin is held at Vtst
while the MCU is in monitor mode. The COP module can be disabled
only through combinational logic conditioned with the high voltage signal
on the RST or the IRQ pin. This prevents the COP from becoming
disabled as a result of external noise. During a break state, Vtst on the
RST pin disables the COP module.
19.4.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the SIM reset status register
(SRSR) and causes a reset.
If the stop enable bit, STOP, in the mask option register is logic 0, the
SIM treats the STOP instruction as an illegal opcode and causes an
illegal opcode reset. The SIM actively pulls down the RST pin for all
internal reset sources.
19.4.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal
address reset. The SIM verifies that the CPU is fetching an opcode prior
to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address does not
generate a reset. The SIM actively pulls down the RST pin for all internal
reset sources.
19.4.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when
the VDD voltage falls to the LVITRIPF voltage. The LVI bit in the SIM reset
status register (SRSR) is set, and the external reset pin (RST) is held low
while the SIM counter counts out 4096 CGMXCLK cycles. Sixty-four
CGMXCLK cycles later, the CPU is released from reset to allow the reset
vector sequence to occur. The SIM actively pulls down the RST pin for
all internal reset sources.
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SIM Counter
19.4.2.6 Monitor Mode Entry Module Reset (MODRST)
The monitor mode entry module reset (MODRST) asserts its output to
the SIM when monitor mode is entered in the condition where the reset
vectors are blank ($00). (See Entering Monitor Mode.) When MODRST
gets asserted, an internal reset occurs. The SIM actively pulls down the
RST pin for all internal reset sources.
19.5 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in
stop mode recovery to allow the oscillator time to stabilize before
enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly module (COP). The SIM
counter overflow supplies the clock for the COP module. The SIM
counter is 13 bits long and is clocked by the falling edge of CGMXCLK.
19.5.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU.
At power-on, the POR circuit asserts the signal PORRST. Once the SIM
is initialized, it enables the clock generation module (CGM) to drive the
bus clock state machine.
19.5.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP
instruction clears the SIM counter. After an interrupt, break, or reset, the
SIM senses the state of the short stop recovery bit, SSREC, in the mask
option register. If the SSREC bit is a logic 1, then the stop recovery is
reduced from the normal delay of 4096 CGMXCLK cycles down to 32
CGMXCLK cycles. This is ideal for applications using canned oscillators
that do not require long startup times from stop mode. External crystal
applications should use the full stop recovery time, that is, with SSREC
cleared.
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19.5.3 SIM Counter and Reset States
External reset has no effect on the SIM counter. (See Stop Mode for
details.) The SIM counter is free-running after all reset states. (See
Active Resets from Internal Sources for counter control and internal
reset recovery sequences.)
19.6 Exception Control
Normal, sequential program execution can be changed in three different
ways:
•
Interrupts:
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
•
Reset
•
Break interrupts
19.6.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume. Figure 19-8 shows interrupt entry timing. Figure
19-9 shows interrupt recovery timing.
Interrupts are latched, and arbitration is performed in the SIM at the start
of interrupt processing. The arbitration result is a constant that the CPU
uses to determine which vector to fetch. Once an interrupt is latched by
the SIM, no other interrupt can take precedence, regardless of priority,
until the latched interrupt is serviced (or the I bit is cleared). See Figure
19-10.
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Exception Control
MODULE
INTERRUPT
I BIT
IAB
IDB
SP
DUMMY
DUMMY
SP – 1
PC – 1[7:0]
SP – 2
PC–1[15:8]
SP – 3
X
SP – 4
A
VECT H
CCR
VECT L
V DATA H
START ADDR
V DATA L
OPCODE
R/W
Figure 19-8. Interrupt Entry Timing
MODULE
INTERRUPT
I BIT
IAB
SP – 4
IDB
SP – 3
CCR
SP – 2
A
SP – 1
X
SP
PC – 1 [7:0]
PC
PC–1[15:8]
PC + 1
OPCODE
OPERAND
R/W
Figure 19-9. Interrupt Recovery Timing
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FROM RESET
BREAK
I BIT
SET?
INTERRUPT?
YES
NO
YES
I BIT SET?
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NO
IRQ0
INTERRUPT?
YES
NO
IRQ
INTERRUPT?
NO
AS MANY INTERRUPTS
AS EXIST ON CHIP
YES
STACK CPU REGISTERS
SET I BIT
LOAD PC WITH INTERRUPT VECTOR
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION?
YES
NO
RTI
INSTRUCTION?
YES
UNSTACK CPU REGISTERS
NO
EXECUTE INSTRUCTION
Figure 19-10. Interrupt Processing
19.6.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of
a hardware interrupt begins after completion of the current instruction.
When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the
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condition code register) and if the corresponding interrupt enable bit is
set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
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If more than one interrupt is pending at the end of an instruction
execution, the highest priority interrupt is serviced first. Figure 19-11
demonstrates what happens when two interrupts are pending. If an
interrupt is pending upon exit from the original interrupt service routine,
the pending interrupt is serviced before the LDA instruction is executed.
CLI
BACKGROUND
ROUTINE
LDA #$FF
INT1
PSHH
INT1 INTERRUPT SERVICE ROUTINE
PULH
RTI
INT2
PSHH
INT2 INTERRUPT SERVICE ROUTINE
PULH
RTI
Figure 19-11. Interrupt Recognition Example
The LDA opcode is prefetched by both the INT1 and INT2 RTI
instructions. However, in the case of the INT1 RTI prefetch, this is a
redundant operation.
NOTE:
To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, software
should save the H register and then restore it prior to exiting the routine.
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19.6.1.2 SWI Instruction
The SWI instruction is a non-maskable instruction that causes an
interrupt regardless of the state of the interrupt mask (I bit) in the
condition code register.
NOTE:
A software interrupt pushes PC onto the stack. A software interrupt does
not push PC – 1, as a hardware interrupt does.
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19.6.1.3 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt
sources. Table 19-3 summarizes the interrupt sources and the interrupt
status register flags that they set. The interrupt status registers can be
useful for debugging.
Table 19-3. Interrupt Sources
Priority
Interrupt Source
Interrupt Status
Register Flag
Highest
Reset
—
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Table 19-3. Interrupt Sources
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Priority
Lowest
Interrupt Source
Interrupt Status
Register Flag
SWI instruction
—
IRQ pin
I1
PLL
I2
TIM1 channel 0
I3
TIM1 channel 1
I4
TIM1 overflow
I5
TIM2 channel 0
I6
Reserved
I7
TIM2 overflow
I8
SPI receiver full
I9
SPI transmitter empty
I10
SCI receive error
I11
SCI receive
I12
SCI transmit
I13
Keyboard
I14
ADC conversion complete
I15
Timebase module
I16
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19.6.1.4 Interrupt Status Register 1
Address:
$FE04
Bit 7
6
5
4
3
2
1
Bit 0
Read:
I6
I5
I4
I3
I2
I1
0
0
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
R
= Reserved
Figure 19-12. Interrupt Status Register 1 (INT1)
I6–I1 — Interrupt Flags 1–6
These flags indicate the presence of interrupt requests from the
sources shown in Table 19-3.
1 = Interrupt request present
0 = No interrupt request present
Bit 0 and Bit 1 — Always read 0
19.6.1.5 Interrupt Status Register 2
Address:
$FE05
Bit 7
6
5
4
3
2
1
Bit 0
Read:
I14
I13
I12
I11
I10
I9
I8
I7
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
R
= Reserved
Figure 19-13. Interrupt Status Register 2 (INT2)
I14–I7 — Interrupt Flags 14–7
These flags indicate the presence of interrupt requests from the
sources shown in Table 19-3.
1 = Interrupt request present
0 = No interrupt request present
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19.6.1.6 Interrupt Status Register 3
Address:
$FE06
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
0
I16
I15
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
R
= Reserved
Figure 19-14. Interrupt Status Register 3 (INT3)
Bits 7–2 — Always read 0
I16–I15 — Interrupt Flags 16–15
These flags indicate the presence of an interrupt request from the
source shown in Table 19-3.
1 = Interrupt request present
0 = No interrupt request present
19.6.2 Reset
All reset sources always have equal and highest priority and cannot be
arbitrated.
19.6.3 Break Interrupts
The break module can stop normal program flow at a softwareprogrammable break point by asserting its break interrupt output. See
Timer Interface Module (TIM). The SIM puts the CPU into the break state
by forcing it to the SWI vector location. Refer to the break interrupt
subsection of each module to see how each module is affected by the
break state.
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19.6.4 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can
be cleared during break mode. The user can select whether flags are
protected from being cleared by properly initializing the break clear flag
enable bit (BCFE) in the SIM break flag control register (SBFCR).
Protecting flags in break mode ensures that set flags will not be cleared
while in break mode. This protection allows registers to be freely read
and written during break mode without losing status flag information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in
break mode, a flag remains cleared even when break mode is exited.
Status flags with a 2-step clearing mechanism — for example, a read of
one register followed by the read or write of another — are protected,
even when the first step is accomplished prior to entering break mode.
Upon leaving break mode, execution of the second step will clear the flag
as normal.
19.7 Low-Power Modes
Executing the WAIT or STOP instruction puts the MCU in a low powerconsumption mode for standby situations. The SIM holds the CPU in a
non-clocked state. The operation of each of these modes is described in
the following subsections. Both STOP and WAIT clear the interrupt mask
(I) in the condition code register, allowing interrupts to occur.
19.7.1 Wait Mode
In wait mode, the CPU clocks are inactive while the peripheral clocks
continue to run. Figure 19-15 shows the timing for wait mode entry.
A module that is active during wait mode can wake up the CPU with an
interrupt if the interrupt is enabled. Stacking for the interrupt begins one
cycle after the WAIT instruction during which the interrupt occurred. In
wait mode, the CPU clocks are inactive. Refer to the wait mode
subsection of each module to see if the module is active or inactive in
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wait mode. Some modules can be programmed to be active in wait
mode.
Wait mode also can be exited by a reset or break. A break interrupt
during wait mode sets the SIM break stop/wait bit, SBSW, in the SIM
break status register (SBSR). If the COP disable bit, COPD, in the mask
option register is logic 0, then the computer operating properly module
(COP) is enabled and remains active in wait mode.
WAIT ADDR
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IAB
WAIT ADDR + 1
PREVIOUS DATA
IDB
SAME
NEXT OPCODE
SAME
SAME
SAME
R/W
Note:
Previous data can be operand data or the WAIT opcode, depending on the
last instruction.
Figure 19-15. Wait Mode Entry Timing
Figure 19-16 and Figure 19-17 show the timing for WAIT recovery.
IAB
IDB
$6E0B
$A6
$A6
$6E0C
$A6
$01
$00FF
$0B
$00FE
$00FD
$00FC
$6E
EXITSTOPWAIT
Note: EXITSTOPWAIT = RST pin, CPU interrupt, or break interrupt
Figure 19-16. Wait Recovery from Interrupt or Break
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32
CYCLES
IAB
IDB
32
CYCLES
$6E0B
$A6
$A6
RST VCT H RST VCT L
$A6
RST
CGMXCLK
Figure 19-17. Wait Recovery from Internal Reset
19.7.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are
disabled. An interrupt request from a module can cause an exit from stop
mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the clock generator module outputs (CGMOUT and
CGMXCLK) in stop mode, stopping the CPU and peripherals. Stop
recovery time is selectable using the SSREC bit in the mask option
register (MOR). If SSREC is set, stop recovery is reduced from the
normal delay of 4096 CGMXCLK cycles down to 32. This is ideal for
applications using canned oscillators that do not require long startup
times from stop mode.
NOTE:
External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
A break interrupt during stop mode sets the SIM break stop/wait bit
(SBSW) in the SIM break status register (SBSR).
The SIM counter is held in reset from the execution of the STOP
instruction until the beginning of stop recovery. It is then used to time the
recovery period. Figure 19-18 shows stop mode entry timing.
NOTE:
To minimize stop current, all pins configured as inputs should be driven
to a logic 1 or logic 0.
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SIM Registers
CPUSTOP
IAB
IDB
STOP ADDR
STOP ADDR + 1
PREVIOUS DATA
SAME
NEXT OPCODE
SAME
SAME
SAME
R/W
Note : Previous data can be operand data or the STOP opcode, depending
on the last instruction.
Figure 19-18. Stop Mode Entry Timing
STOP RECOVERY PERIOD
CGMXCLK
INT/BREAK
IAB
STOP +1
STOP + 2
STOP + 2
SP
SP – 1
SP – 2
SP – 3
Figure 19-19. Stop Mode Recovery from Interrupt or Break
19.8 SIM Registers
The SIM has three memory-mapped registers. Table 19-4 shows the
mapping of these registers.
Table 19-4. SIM Registers
Address
Register
Access Mode
$FE00
SBSR
User
$FE01
SRSR
User
$FE03
SBFCR
User
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19.8.1 SIM Break Status Register
The SIM break status register (SBSR) contains a flag to indicate that a
break caused an exit from stop mode or wait mode.
Address:
$FE00
Bit 7
6
5
4
3
2
R
R
R
R
R
R
0
0
0
0
0
0
Read:
Bit 0
SBSW
Write:
Reset:
1
R
Note(1)
0
R
0
= Reserved
Note: 1. Writing a logic 0 clears SBSW.
Figure 19-20. SIM Break Status Register (SBSR)
SBSW — SIM Break Stop/Wait
This status bit is useful in applications requiring a return to wait or stop
mode after exiting from a break interrupt. Clear SBSW by writing a
logic 0 to it. Reset clears SBSW.
1 = Stop mode or wait mode was exited by break interrupt.
0 = Stop mode or wait mode was not exited by break interrupt.
SBSW can be read within the break state SWI routine. The user can
modify the return address on the stack by subtracting one from it. The
following code is an example of this. Writing 0 to the SBSW bit clears it.
This code works if the H register has been pushed onto the stack in the break
service routine software. This code should be executed at the end of the break
service routine software.
HIBYTE
EQU
5
;
LOBYTE
EQU
6
;
If not SBSW, do RTI
;
BRCLR
SBSW,SBSR, RETURN
; See if wait mode or stop mode was exited by
; break.
TST
LOBYTE,SP
;If RETURNLO is not zero,
BNE
DOLO
;then just decrement low byte.
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DEC
HIBYTE,SP
;Else deal with high byte, too.
DOLO
DEC
LOBYTE,SP
;Point to WAIT/STOP opcode.
RETURN
PULH
RTI
;Restore H register.
19.8.2 SIM Reset Status Register
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This register contains six flags that show the source of the last reset
provided all previous reset status bits have been cleared. Clear the SIM
reset status register by reading it. A power-on reset sets the POR bit and
clears all other bits in the register.
Address:
Read:
$FE01
Bit 7
6
5
4
3
2
1
Bit 0
POR
PIN
COP
ILOP
ILAD
MODRST
LVI
0
1
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 19-21. SIM Reset Status Register (SRSR)
POR — Power-On Reset Bit
1 = Last reset caused by POR circuit
0 = Read of SRSR
PIN — External Reset Bit
1 = Last reset caused by external reset pin (RST)
0 = POR or read of SRSR
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by COP counter
0 = POR or read of SRSR
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR
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ILAD — Illegal Address Reset Bit (opcode fetches only)
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
MODRST — Monitor Mode Entry Module Reset Bit
1 = Last reset caused by monitor mode entry when vector locations
$FFFE and $FFFF are $00 after POR while IRQ = VDD
0 = POR or read of SRSR
LVI — Low-Voltage Inhibit Reset Bit
1 = Last reset caused by the LVI circuit
0 = POR or read of SRSR
19.8.3 SIM Break Flag Control Register
The SIM break control register contains a bit that enables software to
clear status bits while the MCU is in a break state.
Address:
$FE03
Bit 7
6
5
4
3
2
1
Bit 0
BCFE
R
R
R
R
R
R
R
Read:
Write:
Reset:
0
R
= Reserved
Figure 19-22. SIM Break Flag Control Register (SBFCR)
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing
status registers while the MCU is in a break state. To clear status bits
during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
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Section 20. Serial Peripheral Interface (SPI)
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20.1 Contents
20.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
20.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
20.4
Pin Name Conventions and I/O Register Addresses . . . . . . . 298
20.5
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
20.6
Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
20.7
Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . 309
20.8
Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
20.9
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
20.10 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
20.11 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317
20.12 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .318
20.13 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
20.14 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
20.2 Introduction
This section describes the serial peripheral interface (SPI) module,
which allows full-duplex, synchronous, serial communications with
peripheral devices.
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Serial Peripheral Interface (SPI)
20.3 Features
Features of the SPI module include:
•
Full-duplex operation
•
Master and slave modes
•
Double-buffered operation with separate transmit and receive
registers
•
Four master mode frequencies (maximum = bus frequency ÷ 2)
•
Maximum slave mode frequency = bus frequency
•
Serial clock with programmable polarity and phase
•
Two separately enabled interrupts:
– SPRF (SPI receiver full)
– SPTE (SPI transmitter empty)
•
Mode fault error flag with CPU interrupt capability
•
Overflow error flag with CPU interrupt capability
•
Programmable wired-OR mode
•
I2C (inter-integrated circuit) compatibility
•
I/O (input/output) port bit(s) software configurable with pullup
device(s) if configured as input port bit(s)
20.4 Pin Name Conventions and I/O Register Addresses
The text that follows describes the SPI. The SPI I/O pin names are SS
(slave select), SPSCK (SPI serial clock), CGND (clock ground), MOSI
(master out slave in), and MISO (master in/slave out). The SPI shares
four I/O pins with four parallel I/O ports.
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Serial Peripheral Interface (SPI)
Functional Description
The full names of the SPI I/O pins are shown in Table 20-1. The generic
pin names appear in the text that follows.
Table 20-1. Pin Name Conventions
SPI Generic
Pin Names:
Full SPI
Pin Names:
SPI
MISO
MOSI
SS
SPSCK
CGND
PTD1/ATD9
PTD2/ATD1
0
PTD0/AT
D8
PTD3/ATD11
VSS
20.5 Functional Description
Figure 20-1 summarizes the SPI I/O registers and Figure 20-2 shows the
structure of the SPI module.
Addr.
$0010
$0011
Register Name
Bit 7
Read:
SPI Control Register
Write:
(SPCR)
Reset:
Read:
SPI Status and Control
Write:
Register (SPSCR)
Reset:
$0012
Read:
SPI Data Register
Write:
(SPDR)
Reset:
6
5
4
3
2
1
Bit 0
SPMSTR
CPOL
CPHA
SPWOM
SPE
SPTIE
1
0
1
0
0
0
OVRF
MODF
SPTE
MODFEN
SPR1
SPR0
DMAS
SPRIE
0
0
SPRF
ERRIE
0
0
0
0
1
0
0
0
R7
R6
R5
R4
R3
R2
R1
R0
T7
T6
T5
T4
T3
T2
T1
T0
Unaffected by reset
= Unimplemented
Figure 20-1. SPI I/O Register Summary
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INTERNAL BUS
TRANSMIT DATA REGISTER
CGMOUT ÷ 2
FROM SIM
SHIFT REGISTER
7
6
5
4
3
2
1
MISO
0
÷2
MOSI
÷8
CLOCK
DIVIDER ÷ 32
RECEIVE DATA REGISTER
PIN
CONTROL
LOGIC
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÷ 128
SPMSTR
SPE
CLOCK
SELECT
SPR1
SPSCK
M
CLOCK
LOGIC
S
SS
SPR0
SPMSTR
RESERVED
MODFEN
TRANSMITTER CPU INTERRUPT REQUEST
RESERVED
CPHA
CPOL
SPWOM
ERRIE
SPI
CONTROL
SPTIE
SPRIE
RECEIVER/ERROR CPU INTERRUPT REQUEST
DMAS
SPE
SPRF
SPTE
OVRF
MODF
Figure 20-2. SPI Module Block Diagram
The SPI module allows full-duplex, synchronous, serial communication
between the MCU and peripheral devices, including other MCUs.
Software can poll the SPI status flags or SPI operation can be interruptdriven.
If a port bit is configured for input, then an internal pullup device may be
enabled for that port bit. See Port D Input Pullup Enable Register.
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Serial Peripheral Interface (SPI)
Functional Description
The following paragraphs describe the operation of the SPI module.
20.5.1 Master Mode
The SPI operates in master mode when the SPI master bit, SPMSTR, is
set.
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NOTE:
Configure the SPI modules as master or slave before enabling them.
Enable the master SPI before enabling the slave SPI. Disable the slave
SPI before disabling the master SPI. See SPI Control Register.
Only a master SPI module can initiate transmissions. Software begins
the transmission from a master SPI module by writing to the transmit
data register. If the shift register is empty, the byte immediately transfers
to the shift register, setting the SPI transmitter empty bit, SPTE. The byte
begins shifting out on the MOSI pin under the control of the serial clock.
See Figure 20-3.
MASTER MCU
SHIFT REGISTER
SLAVE MCU
MISO
MISO
MOSI
MOSI
SPSCK
BAUD RATE
GENERATOR
SS
SHIFT REGISTER
SPSCK
VDD
SS
Figure 20-3. Full-Duplex Master-Slave Connections
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Serial Peripheral Interface (SPI)
The SPR1 and SPR0 bits control the baud rate generator and determine
the speed of the shift register. See SPI Status and Control Register.
Through the SPSCK pin, the baud rate generator of the master also
controls the shift register of the slave peripheral.
As the byte shifts out on the MOSI pin of the master, another byte shifts
in from the slave on the master’s MISO pin. The transmission ends when
the receiver full bit, SPRF, becomes set. At the same time that SPRF
becomes set, the byte from the slave transfers to the receive data
register. In normal operation, SPRF signals the end of a transmission.
Software clears SPRF by reading the SPI status and control register with
SPRF set and then reading the SPI data register. Writing to the SPI data
register clears the SPTE bit.
20.5.2 Slave Mode
The SPI operates in slave mode when the SPMSTR bit is clear. In slave
mode, the SPSCK pin is the input for the serial clock from the master
MCU. Before a data transmission occurs, the SS pin of the slave SPI
must be at logic 0. SS must remain low until the transmission is
complete. See Mode Fault Error.
In a slave SPI module, data enters the shift register under the control of
the serial clock from the master SPI module. After a byte enters the shift
register of a slave SPI, it transfers to the receive data register, and the
SPRF bit is set. To prevent an overflow condition, slave software then
must read the receive data register before another full byte enters the
shift register.
The maximum frequency of the SPSCK for an SPI configured as a slave
is the bus clock speed (which is twice as fast as the fastest master
SPSCK clock that can be generated). The frequency of the SPSCK for
an SPI configured as a slave does not have to correspond to any SPI
baud rate. The baud rate only controls the speed of the SPSCK
generated by an SPI configured as a master. Therefore, the frequency
of the SPSCK for an SPI configured as a slave can be any frequency
less than or equal to the bus speed.
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Serial Peripheral Interface (SPI)
Transmission Formats
When the master SPI starts a transmission, the data in the slave shift
register begins shifting out on the MISO pin. The slave can load its shift
register with a new byte for the next transmission by writing to its transmit
data register. The slave must write to its transmit data register at least
one bus cycle before the master starts the next transmission. Otherwise,
the byte already in the slave shift register shifts out on the MISO pin.
Data written to the slave shift register during a transmission remains in
a buffer until the end of the transmission.
When the clock phase bit (CPHA) is set, the first edge of SPSCK starts
a transmission. When CPHA is clear, the falling edge of SS starts a
transmission. See Transmission Formats.
NOTE:
SPSCK must be in the proper idle state before the slave is enabled to
prevent SPSCK from appearing as a clock edge.
20.6 Transmission Formats
During an SPI transmission, data is simultaneously transmitted (shifted
out serially) and received (shifted in serially). A serial clock synchronizes
shifting and sampling on the two serial data lines. A slave select line
allows selection of an individual slave SPI device; slave devices that are
not selected do not interfere with SPI bus activities. On a master SPI
device, the slave select line can optionally be used to indicate multiplemaster bus contention.
20.6.1 Clock Phase and Polarity Controls
Software can select any of four combinations of serial clock (SPSCK)
phase and polarity using two bits in the SPI control register (SPCR). The
clock polarity is specified by the CPOL control bit, which selects an
active high or low clock and has no significant effect on the transmission
format.
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Serial Peripheral Interface (SPI)
The clock phase (CPHA) control bit selects one of two fundamentally
different transmission formats. The clock phase and polarity should be
identical for the master SPI device and the communicating slave device.
In some cases, the phase and polarity are changed between
transmissions to allow a master device to communicate with peripheral
slaves having different requirements.
NOTE:
Before writing to the CPOL bit or the CPHA bit, disable the SPI by
clearing the SPI enable bit (SPE).
20.6.2 Transmission Format When CPHA = 0
Figure 20-4 shows an SPI transmission in which CPHA is logic 0. The
figure should not be used as a replacement for data sheet parametric
information.
Two waveforms are shown for SPSCK: one for CPOL = 0 and another
for CPOL = 1. The diagram may be interpreted as a master or slave
timing diagram since the serial clock (SPSCK), master in/slave out
(MISO), and master out/slave in (MOSI) pins are directly connected
between the master and the slave. The MISO signal is the output from
the slave, and the MOSI signal is the output from the master. The SS line
is the slave select input to the slave. The slave SPI drives its MISO
output only when its slave select input (SS) is at logic 0, so that only the
selected slave drives to the master. The SS pin of the master is not
shown but is assumed to be inactive. The SS pin of the master must be
high or must be reconfigured as general-purpose I/O not affecting the
SPI. See Mode Fault Error. When CPHA = 0, the first SPSCK edge is the
MSB capture strobe. Therefore, the slave must begin driving its data
before the first SPSCK edge, and a falling edge on the SS pin is used to
start the slave data transmission. The slave’s SS pin must be toggled
back to high and then low again between each byte transmitted as
shown in Figure 20-5.
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Serial Peripheral Interface (SPI)
Transmission Formats
SPSCK CYCLE #
FOR REFERENCE
1
2
3
4
5
6
7
8
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
SPSCK; CPOL = 0
SPSCK; CPOL =1
MOSI
FROM MASTER
MISO
FROM SLAVE
MSB
SS; TO SLAVE
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CAPTURE STROBE
Figure 20-4. Transmission Format (CPHA = 0)
MISO/MOSI
BYTE 1
BYTE 2
BYTE 3
MASTER SS
SLAVE SS
CPHA = 0
SLAVE SS
CPHA = 1
Figure 20-5. CPHA/SS Timing
When CPHA = 0 for a slave, the falling edge of SS indicates the
beginning of the transmission. This causes the SPI to leave its idle state
and begin driving the MISO pin with the MSB of its data. Once the
transmission begins, no new data is allowed into the shift register from
the transmit data register. Therefore, the SPI data register of the slave
must be loaded with transmit data before the falling edge of SS. Any data
written after the falling edge is stored in the transmit data register and
transferred to the shift register after the current transmission.
20.6.3 Transmission Format When CPHA = 1
Figure 20-6 shows an SPI transmission in which CPHA is logic 1. The
figure should not be used as a replacement for data sheet parametric
information. Two waveforms are shown for SPSCK: one for CPOL = 0
and another for CPOL = 1. The diagram may be interpreted as a master
or slave timing diagram since the serial clock (SPSCK), master in/slave
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out (MISO), and master out/slave in (MOSI) pins are directly connected
between the master and the slave. The MISO signal is the output from
the slave, and the MOSI signal is the output from the master. The SS line
is the slave select input to the slave. The slave SPI drives its MISO
output only when its slave select input (SS) is at logic 0, so that only the
selected slave drives to the master. The SS pin of the master is not
shown but is assumed to be inactive. The SS pin of the master must be
high or must be reconfigured as general-purpose I/O not affecting the
SPI. See Mode Fault Error. When CPHA = 1, the master begins driving
its MOSI pin on the first SPSCK edge. Therefore, the slave uses the first
SPSCK edge as a start transmission signal. The SS pin can remain low
between transmissions. This format may be preferable in systems
having only one master and only one slave driving the MISO data line.
SPSCK CYCLE #
FOR REFERENCE
1
2
3
4
5
6
7
8
MOSI
FROM MASTER
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
MISO
FROM SLAVE
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
SPSCK; CPOL = 0
SPSCK; CPOL =1
LSB
SS; TO SLAVE
CAPTURE STROBE
Figure 20-6. Transmission Format (CPHA = 1)
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Serial Peripheral Interface (SPI)
Transmission Formats
When CPHA = 1 for a slave, the first edge of the SPSCK indicates the
beginning of the transmission. This causes the SPI to leave its idle state
and begin driving the MISO pin with the MSB of its data. Once the
transmission begins, no new data is allowed into the shift register from
the transmit data register. Therefore, the SPI data register of the slave
must be loaded with transmit data before the first edge of SPSCK. Any
data written after the first edge is stored in the transmit data register and
transferred to the shift register after the current transmission.
20.6.4 Transmission Initiation Latency
When the SPI is configured as a master (SPMSTR = 1), writing to the
SPDR starts a transmission. CPHA has no effect on the delay to the start
of the transmission, but it does affect the initial state of the SPSCK
signal. When CPHA = 0, the SPSCK signal remains inactive for the first
half of the first SPSCK cycle. When CPHA = 1, the first SPSCK cycle
begins with an edge on the SPSCK line from its inactive to its active
level. The SPI clock rate (selected by SPR1:SPR0) affects the delay
from the write to SPDR and the start of the SPI transmission. See Figure
20-7. The internal SPI clock in the master is a free-running derivative of
the internal MCU clock. To conserve power, it is enabled only when both
the SPE and SPMSTR bits are set. SPSCK edges occur halfway through
the low time of the internal MCU clock. Since the SPI clock is freerunning, it is uncertain where the write to the SPDR occurs relative to the
slower SPSCK. This uncertainty causes the variation in the initiation
delay shown in Figure 20-7. This delay is no longer than a single SPI bit
time. That is, the maximum delay is two MCU bus cycles for DIV2, eight
MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU
bus cycles for DIV128.
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Serial Peripheral Interface (SPI)
WRITE
TO SPDR
INITIATION DELAY
BUS
CLOCK
MOSI
MSB
BIT 6
1
2
BIT 5
SPSCK
CPHA = 1
SPSCK
CPHA = 0
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SPSCK CYCLE
NUMBER
3
INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN








WRITE
TO SPDR
BUS
CLOCK
EARLIEST
LATEST
WRITE
TO SPDR
SPSCK = INTERNAL CLOCK ÷ 2;
2 POSSIBLE START POINTS
BUS
CLOCK
EARLIEST
WRITE
TO SPDR
SPSCK = INTERNAL CLOCK ÷ 8;
8 POSSIBLE START POINTS
LATEST
SPSCK = INTERNAL CLOCK ÷ 32;
32 POSSIBLE START POINTS
LATEST
SPSCK = INTERNAL CLOCK ÷ 128;
128 POSSIBLE START POINTS
LATEST
BUS
CLOCK
EARLIEST
WRITE
TO SPDR
BUS
CLOCK
EARLIEST
Figure 20-7. Transmission Start Delay (Master)
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Serial Peripheral Interface (SPI)
Queuing Transmission Data
20.7 Queuing Transmission Data
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The double-buffered transmit data register allows a data byte to be
queued and transmitted. For an SPI configured as a master, a queued
data byte is transmitted immediately after the previous transmission has
completed. The SPI transmitter empty flag (SPTE) indicates when the
transmit data buffer is ready to accept new data. Write to the transmit
data register only when the SPTE bit is high. Figure 20-8 shows the
timing associated with doing back-to-back transmissions with the SPI
(SPSCK has CPHA: CPOL = 1:0).
WRITE TO SPDR
SPTE
1
3
8
5
2
10
SPSCK
CPHA:CPOL = 1:0
MOSI
MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT
6 5 4 3 2 1
6 5 4 3 2 1
6 5 4
BYTE 1
BYTE 2
BYTE 3
9
4
SPRF
6
READ SPSCR
11
7
READ SPDR
12
1 CPU WRITES BYTE 1 TO SPDR, CLEARING SPTE BIT.
7 CPU READS SPDR, CLEARING SPRF BIT.
2 BYTE 1 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
8
3 CPU WRITES BYTE 2 TO SPDR, QUEUEING BYTE 2
AND CLEARING SPTE BIT.
FIRST INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
5 BYTE 2 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
6 CPU READS SPSCR WITH SPRF BIT SET.
4
CPU WRITES BYTE 3 TO SPDR, QUEUEING BYTE
3 AND CLEARING SPTE BIT.
9 SECOND INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
10 BYTE 3 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
11 CPU READS SPSCR WITH SPRF BIT SET.
12 CPU READS SPDR, CLEARING SPRF BIT.
Figure 20-8. .SPRF/SPTE CPU Interrupt Timing
The transmit data buffer allows back-to-back transmissions without the
slave precisely timing its writes between transmissions as in a system
with a single data buffer. Also, if no new data is written to the data buffer,
the last value contained in the shift register is the next data word to be
transmitted.
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Serial Peripheral Interface (SPI)
For an idle master or idle slave that has no data loaded into its transmit
buffer, the SPTE is set again no more than two bus cycles after the
transmit buffer empties into the shift register. This allows the user to
queue up a 16-bit value to send. For an already active slave, the load of
the shift register cannot occur until the transmission is completed. This
implies that a back-to-back write to the transmit data register is not
possible. The SPTE indicates when the next write can occur.
20.8 Error Conditions
The following flags signal SPI error conditions:
•
Overflow (OVRF) — Failing to read the SPI data register before
the next full byte enters the shift register sets the OVRF bit. The
new byte does not transfer to the receive data register, and the
unread byte still can be read. OVRF is in the SPI status and control
register.
•
Mode fault error (MODF) — The MODF bit indicates that the
voltage on the slave select pin (SS) is inconsistent with the mode
of the SPI. MODF is in the SPI status and control register.
20.8.1 Overflow Error
The overflow flag (OVRF) becomes set if the receive data register still
has unread data from a previous transmission when the capture strobe
of bit 1 of the next transmission occurs. The bit 1 capture strobe occurs
in the middle of SPSCK cycle 7. (See Figure 20-4 and Figure 20-6.) If an
overflow occurs, all data received after the overflow and before the
OVRF bit is cleared does not transfer to the receive data register and
does not set the SPI receiver full bit (SPRF). The unread data that
transferred to the receive data register before the overflow occurred can
still be read. Therefore, an overflow error always indicates the loss of
data. Clear the overflow flag by reading the SPI status and control
register and then reading the SPI data register.
OVRF generates a receiver/error CPU interrupt request if the error
interrupt enable bit (ERRIE) is also set. The SPRF, MODF, and OVRF
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Error Conditions
interrupts share the same CPU interrupt vector. See Figure 20-11. It is
not possible to enable MODF or OVRF individually to generate a
receiver/error CPU interrupt request. However, leaving MODFEN low
prevents MODF from being set.
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If the CPU SPRF interrupt is enabled and the OVRF interrupt is not,
watch for an overflow condition. Figure 20-9 shows how it is possible to
miss an overflow. The first part of Figure 20-9 shows how it is possible
to read the SPSCR and SPDR to clear the SPRF without problems.
However, as illustrated by the second transmission example, the OVRF
bit can be set in between the time that SPSCR and SPDR are read.
BYTE 1
BYTE 2
BYTE 3
BYTE 4
1
4
6
8
SPRF
OVRF
READ
SPSCR
2
READ
SPDR
5
3
1
BYTE 1 SETS SPRF BIT.
2
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
BYTE 2 SETS SPRF BIT.
3
4
7
5
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
6
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
7
CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT,
BUT NOT OVRF BIT.
8
BYTE 4 FAILS TO SET SPRF BIT BECAUSE
OVRF BIT IS NOT CLEARED. BYTE 4 IS LOST.
Figure 20-9. Missed Read of Overflow Condition
In this case, an overflow can be missed easily. Since no more SPRF
interrupts can be generated until this OVRF is serviced, it is not obvious
that bytes are being lost as more transmissions are completed. To
prevent this, either enable the OVRF interrupt or do another read of the
SPSCR following the read of the SPDR. This ensures that the OVRF
was not set before the SPRF was cleared and that future transmissions
can set the SPRF bit. Figure 20-10 illustrates this process. Generally, to
avoid this second SPSCR read, enable the OVRF to the CPU by setting
the ERRIE bit.
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Serial Peripheral Interface (SPI)
BYTE 1
SPI RECEIVE
COMPLETE
BYTE 2
5
1
BYTE 3
7
BYTE 4
11
SPRF
OVRF
READ
SPSCR
2
READ
SPDR
4
3
1
BYTE 1 SETS SPRF BIT.
2
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
3
6
9
8
12
14
10
13
8
CPU READS BYTE 2 IN SPDR,
CLEARING SPRF BIT.
9
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
10 CPU READS BYTE 2 SPDR,
CLEARING OVRF BIT.
4
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
11 BYTE 4 SETS SPRF BIT.
5
BYTE 2 SETS SPRF BIT.
12 CPU READS SPSCR.
6
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
13 CPU READS BYTE 4 IN SPDR,
CLEARING SPRF BIT.
7
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
14 CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
Figure 20-10. Clearing SPRF When OVRF Interrupt Is Not Enabled
20.8.2 Mode Fault Error
Setting the SPMSTR bit selects master mode and configures the
SPSCK and MOSI pins as outputs and the MISO pin as an input.
Clearing SPMSTR selects slave mode and configures the SPSCK and
MOSI pins as inputs and the MISO pin as an output. The mode fault bit,
MODF, becomes set any time the state of the slave select pin, SS, is
inconsistent with the mode selected by SPMSTR.
To prevent SPI pin contention and damage to the MCU, a mode fault
error occurs if:
•
The SS pin of a slave SPI goes high during a transmission
•
The SS pin of a master SPI goes low at any time
For the MODF flag to be set, the mode fault error enable bit (MODFEN)
must be set. Clearing the MODFEN bit does not clear the MODF flag but
does prevent MODF from being set again after MODF is cleared.
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Error Conditions
MODF generates a receiver/error CPU interrupt request if the error
interrupt enable bit (ERRIE) is also set. The SPRF, MODF, and OVRF
interrupts share the same CPU interrupt vector. See Figure 20-11. It is
not possible to enable MODF or OVRF individually to generate a
receiver/error CPU interrupt request. However, leaving MODFEN low
prevents MODF from being set.
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In a master SPI with the mode fault enable bit (MODFEN) set, the mode
fault flag (MODF) is set if SS goes to logic 0. A mode fault in a master
SPI causes the following events to occur:
NOTE:
•
If ERRIE = 1, the SPI generates an SPI receiver/error CPU
interrupt request.
•
The SPE bit is cleared.
•
The SPTE bit is set.
•
The SPI state counter is cleared.
•
The data direction register of the shared I/O port regains control of
port drivers.
To prevent bus contention with another master SPI after a mode fault
error, clear all SPI bits of the data direction register of the shared I/O port
before enabling the SPI.
When configured as a slave (SPMSTR = 0), the MODF flag is set if SS
goes high during a transmission. When CPHA = 0, a transmission begins
when SS goes low and ends once the incoming SPSCK goes back to its
idle level following the shift of the eighth data bit. When CPHA = 1, the
transmission begins when the SPSCK leaves its idle level and SS is
already low. The transmission continues until the SPSCK returns to its
idle level following the shift of the last data bit. See Transmission
Formats.
NOTE:
Setting the MODF flag does not clear the SPMSTR bit. The SPMSTR bit
has no function when SPE = 0. Reading SPMSTR when MODF = 1
shows the difference between a MODF occurring when the SPI is a
master and when it is a slave.
When CPHA = 0, a MODF occurs if a slave is selected (SS is at logic 0)
and later unselected (SS is at logic 1) even if no SPSCK is sent to that
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slave. This happens because SS at logic 0 indicates the start of the
transmission (MISO driven out with the value of MSB) for CPHA = 0.
When CPHA = 1, a slave can be selected and then later unselected with
no transmission occurring. Therefore, MODF does not occur since a
transmission was never begun.
In a slave SPI (MSTR = 0), the MODF bit generates an SPI
receiver/error CPU interrupt request if the ERRIE bit is set. The MODF
bit does not clear the SPE bit or reset the SPI in any way. Software can
abort the SPI transmission by clearing the SPE bit of the slave.
NOTE:
A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high
impedance state. Also, the slave SPI ignores all incoming SPSCK
clocks, even if it was already in the middle of a transmission.
To clear the MODF flag, read the SPSCR with the MODF bit set and then
write to the SPCR register. This entire clearing mechanism must occur
with no MODF condition existing or else the flag is not cleared.
20.9 Interrupts
Four SPI status flags can be enabled to generate CPU interrupt
requests.
Table 20-2. SPI Interrupts
Flag
Request
SPTE
Transmitter empty
SPI transmitter CPU interrupt request
(DMAS = 0, SPTIE = 1, SPE = 1)
SPRF
Receiver full
SPI receiver CPU interrupt request
(DMAS = 0, SPRIE = 1)
OVRF
Overflow
SPI receiver/error interrupt request (ERRIE = 1)
MODF
Mode fault
SPI receiver/error interrupt request (ERRIE = 1)
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Interrupts
Reading the SPI status and control register with SPRF set and then
reading the receive data register clears SPRF. The clearing mechanism
for the SPTE flag is always just a write to the transmit data register.
The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag
to generate transmitter CPU interrupt requests, provided that the SPI is
enabled (SPE = 1).
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The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to
generate receiver CPU interrupt requests, regardless of the state of the
SPE bit. See Figure 20-11.
The error interrupt enable bit (ERRIE) enables both the MODF and
OVRF bits to generate a receiver/error CPU interrupt request.
The mode fault enable bit (MODFEN) can prevent the MODF flag from
being set so that only the OVRF bit is enabled by the ERRIE bit to
generate receiver/error CPU interrupt requests.
NOT AVAILABLE
SPTE
SPTIE
SPE
SPI TRANSMITTER
CPU INTERRUPT REQUEST
DMAS
NOT AVAILABLE
SPRIE
SPRF
SPI RECEIVER/ERROR
CPU INTERRUPT REQUEST
ERRIE
MODF
OVRF
Figure 20-11. SPI Interrupt Request Generation
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The following sources in the SPI status and control register can generate
CPU interrupt requests:
•
SPI receiver full bit (SPRF) — The SPRF bit becomes set every
time a byte transfers from the shift register to the receive data
register. If the SPI receiver interrupt enable bit, SPRIE, is also set,
SPRF generates an SPI receiver/error CPU interrupt request.
•
SPI transmitter empty (SPTE) — The SPTE bit becomes set every
time a byte transfers from the transmit data register to the shift
register. If the SPI transmit interrupt enable bit, SPTIE, is also set,
SPTE generates an SPTE CPU interrupt request.
20.10 Resetting the SPI
Any system reset completely resets the SPI. Partial resets occur
whenever the SPI enable bit (SPE) is low. Whenever SPE is low, the
following occurs:
•
The SPTE flag is set.
•
Any transmission currently in progress is aborted.
•
The shift register is cleared.
•
The SPI state counter is cleared, making it ready for a new
complete transmission.
•
All the SPI port logic is defaulted back to being general-purpose
I/O.
These items are reset only by a system reset:
•
All control bits in the SPCR register
•
All control bits in the SPSCR register (MODFEN, ERRIE, SPR1,
and SPR0)
•
The status flags SPRF, OVRF, and MODF
By not resetting the control bits when SPE is low, the user can clear SPE
between transmissions without having to set all control bits again when
SPE is set back high for the next transmission.
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Low-Power Modes
By not resetting the SPRF, OVRF, and MODF flags, the user can still
service these interrupts after the SPI has been disabled. The user can
disable the SPI by writing 0 to the SPE bit. The SPI can also be disabled
by a mode fault occurring in an SPI that was configured as a master with
the MODFEN bit set.
20.11 Low-Power Modes
The WAIT and STOP instructions put the MCU in low powerconsumption standby modes.
20.11.1 Wait Mode
The SPI module remains active after the execution of a WAIT instruction.
In wait mode the SPI module registers are not accessible by the CPU.
Any enabled CPU interrupt request from the SPI module can bring the
MCU out of wait mode.
If SPI module functions are not required during wait mode, reduce power
consumption by disabling the SPI module before executing the WAIT
instruction.
To exit wait mode when an overflow condition occurs, enable the OVRF
bit to generate CPU interrupt requests by setting the error interrupt
enable bit (ERRIE). See Interrupts.
20.11.2 Stop Mode
The SPI module is inactive after the execution of a STOP instruction.
The STOP instruction does not affect register conditions. SPI operation
resumes after an external interrupt. If stop mode is exited by reset, any
transfer in progress is aborted, and the SPI is reset.
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20.12 SPI During Break Interrupts
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. See System Integration Module (SIM).
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a 2-step read/write clearing procedure. If software does
the first step on such a bit before the break, the bit cannot change during
the break state as long as BCFE is at logic 0. After the break, doing the
second step clears the status bit.
Since the SPTE bit cannot be cleared during a break with the BCFE bit
cleared, a write to the transmit data register in break mode does not
initiate a transmission nor is this data transferred into the shift register.
Therefore, a write to the SPDR in break mode with the BCFE bit cleared
has no effect.
20.13 I/O Signals
The SPI module has five I/O pins and shares four of them with a parallel
I/O port. They are:
•
MISO — Data received
•
MOSI — Data transmitted
•
SPSCK — Serial clock
•
SS — Slave select
•
CGND — Clock ground (internally connected to VSS)
The SPI has limited inter-integrated circuit (I2C) capability (requiring
software support) as a master in a single-master environment. To
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I/O Signals
communicate with I2C peripherals, MOSI becomes an open-drain output
when the SPWOM bit in the SPI control register is set. In I2C
communication, the MOSI and MISO pins are connected to a
bidirectional pin from the I2C peripheral and through a pullup resistor to
VDD.
20.13.1 MISO (Master In/Slave Out)
MISO is one of the two SPI module pins that transmits serial data. In full
duplex operation, the MISO pin of the master SPI module is connected
to the MISO pin of the slave SPI module. The master SPI simultaneously
receives data on its MISO pin and transmits data from its MOSI pin.
Slave output data on the MISO pin is enabled only when the SPI is
configured as a slave. The SPI is configured as a slave when its
SPMSTR bit is logic 0 and its SS pin is at logic 0. To support a multipleslave system, a logic 1 on the SS pin puts the MISO pin in a highimpedance state.
When enabled, the SPI controls data direction of the MISO pin
regardless of the state of the data direction register of the shared I/O
port.
20.13.2 MOSI (Master Out/Slave In)
MOSI is one of the two SPI module pins that transmits serial data. In fullduplex operation, the MOSI pin of the master SPI module is connected
to the MOSI pin of the slave SPI module. The master SPI simultaneously
transmits data from its MOSI pin and receives data on its MISO pin.
When enabled, the SPI controls data direction of the MOSI pin
regardless of the state of the data direction register of the shared I/O
port.
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20.13.3 SPSCK (Serial Clock)
The serial clock synchronizes data transmission between master and
slave devices. In a master MCU, the SPSCK pin is the clock output. In a
slave MCU, the SPSCK pin is the clock input. In full-duplex operation,
the master and slave MCUs exchange a byte of data in eight serial clock
cycles.
When enabled, the SPI controls data direction of the SPSCK pin
regardless of the state of the data direction register of the shared I/O
port.
20.13.4 SS (Slave Select)
The SS pin has various functions depending on the current state of the
SPI. For an SPI configured as a slave, the SS is used to select a slave.
For CPHA = 0, the SS is used to define the start of a transmission. See
Transmission Formats. Since it is used to indicate the start of a
transmission, the SS must be toggled high and low between each byte
transmitted for the CPHA = 0 format. However, it can remain low
between transmissions for the CPHA = 1 format. See Figure 20-12.
MISO/MOSI
BYTE 1
BYTE 2
BYTE 3
MASTER SS
SLAVE SS
CPHA = 0
SLAVE SS
CPHA = 1
Figure 20-12CPHA/SS Timing
When an SPI is configured as a slave, the SS pin is always configured
as an input. It cannot be used as a general-purpose I/O regardless of the
state of the MODFEN control bit. However, the MODFEN bit can still
prevent the state of the SS from creating a MODF error. See SPI Status
and Control Register.
NOTE:
A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a highimpedance state. The slave SPI ignores all incoming SPSCK clocks,
even if it was already in the middle of a transmission.
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Serial Peripheral Interface (SPI)
I/O Signals
When an SPI is configured as a master, the SS input can be used in
conjunction with the MODF flag to prevent multiple masters from driving
MOSI and SPSCK. See Mode Fault Error. For the state of the SS pin to
set the MODF flag, the MODFEN bit in the SPSCK register must be set.
If the MODFEN bit is low for an SPI master, the SS pin can be used as
a general-purpose I/O under the control of the data direction register of
the shared I/O port. With MODFEN high, it is an input-only pin to the SPI
regardless of the state of the data direction register of the shared I/O
port.
The CPU can always read the state of the SS pin by configuring the
appropriate pin as an input and reading the port data register. See Table
20-3.
Table 20-3. SPI Configuration
SPE
SPMSTR
MODFEN
SPI Configuration
State of SS Logic
0
X(1)
X
Not enabled
General-purpose I/O;
SS ignored by SPI
1
0
X
Slave
Input-only to SPI
1
1
0
Master without MODF
General-purpose I/O;
SS ignored by SPI
1
1
1
Master with MODF
Input-only to SPI
Note 1. X = Don’t care
20.13.5 CGND (Clock Ground)
CGND is the ground return for the serial clock pin, SPSCK, and the
ground for the port output buffers. It is internally connected to VSS as
shown in Table 20-1.
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20.14 I/O Registers
Three registers control and monitor SPI operation:
•
SPI control register (SPCR)
•
SPI status and control register (SPSCR)
•
SPI data register (SPDR)
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20.14.1 SPI Control Register
The SPI control register:
•
Enables SPI module interrupt requests
•
Configures the SPI module as master or slave
•
Selects serial clock polarity and phase
•
Configures the SPSCK, MOSI, and MISO pins as open-drain
outputs
•
Enables the SPI module
Address: $0010
Bit 7
6
Read:
5
4
3
2
1
Bit 0
SPMSTR
CPOL
CPHA
SPWOM
SPE
SPTIE
1
0
1
0
0
0
DMAS
SPRIE
Write:
Reset:
0
0
= Unimplemented
Figure 20-13. SPI Control Register (SPCR)
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I/O Registers
SPRIE — SPI Receiver Interrupt Enable Bit
This read/write bit enables CPU interrupt requests generated by the
SPRF bit. The SPRF bit is set when a byte transfers from the shift
register to the receive data register. Reset clears the SPRIE bit.
1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled
DMAS —DMA Select Bit
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This read only bit has no effect on this version of the SPI. This bit
always reads as a 0.
0 = SPRF DMA and SPTE DMA service requests disabled
(SPRF CPU and SPTE CPU interrupt requests enabled)
SPMSTR — SPI Master Bit
This read/write bit selects master mode operation or slave mode
operation. Reset sets the SPMSTR bit.
1 = Master mode
0 = Slave mode
CPOL — Clock Polarity Bit
This read/write bit determines the logic state of the SPSCK pin
between transmissions. (See Figure 20-4 and Figure 20-6.) To
transmit data between SPI modules, the SPI modules must have
identical CPOL values. Reset clears the CPOL bit.
CPHA — Clock Phase Bit
This read/write bit controls the timing relationship between the serial
clock and SPI data. (See Figure 20-4 and Figure 20-6.) To transmit
data between SPI modules, the SPI modules must have identical
CPHA values. When CPHA = 0, the SS pin of the slave SPI module
must be set to logic 1 between bytes. See Figure 20-12. Reset sets
the CPHA bit.
SPWOM — SPI Wired-OR Mode Bit
This read/write bit disables the pullup devices on pins SPSCK, MOSI,
and MISO so that those pins become open-drain outputs.
1 = Wired-OR SPSCK, MOSI, and MISO pins
0 = Normal push-pull SPSCK, MOSI, and MISO pins
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SPE — SPI Enable
This read/write bit enables the SPI module. Clearing SPE causes a
partial reset of the SPI. See Resetting the SPI. Reset clears the SPE
bit.
1 = SPI module enabled
0 = SPI module disabled
SPTIE— SPI Transmit Interrupt Enable
This read/write bit enables CPU interrupt requests generated by the
SPTE bit. SPTE is set when a byte transfers from the transmit data
register to the shift register. Reset clears the SPTIE bit.
1 = SPTE CPU interrupt requests enabled
0 = SPTE CPU interrupt requests disabled
20.14.2 SPI Status and Control Register
The SPI status and control register contains flags to signal these
conditions:
•
Receive data register full
•
Failure to clear SPRF bit before next byte is received (overflow
error)
•
Inconsistent logic level on SS pin (mode fault error)
•
Transmit data register empty
The SPI status and control register also contains bits that perform these
functions:
•
Enable error interrupts
•
Enable mode fault error detection
•
Select master SPI baud rate
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I/O Registers
Address: $0011
Bit 7
Read:
6
SPRF
5
4
3
OVRF
MODF
SPTE
ERRIE
2
1
Bit 0
MODFEN
SPR1
SPR0
0
0
0
Write:
Reset:
0
0
0
0
1
= Unimplemented
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Figure 20-14. SPI Status and Control Register (SPSCR)
SPRF — SPI Receiver Full Bit
This clearable, read-only flag is set each time a byte transfers from
the shift register to the receive data register. SPRF generates a CPU
interrupt request if the SPRIE bit in the SPI control register is set also.
During an SPRF CPU interrupt, the CPU clears SPRF by reading the
SPI status and control register with SPRF set and then reading the
SPI data register.
Reset clears the SPRF bit.
1 = Receive data register full
0 = Receive data register not full
ERRIE — Error Interrupt Enable Bit
This read/write bit enables the MODF and OVRF bits to generate
CPU interrupt requests. Reset clears the ERRIE bit.
1 = MODF and OVRF can generate CPU interrupt requests
0 = MODF and OVRF cannot generate CPU interrupt requests
OVRF — Overflow Bit
This clearable, read-only flag is set if software does not read the byte
in the receive data register before the next full byte enters the shift
register. In an overflow condition, the byte already in the receive data
register is unaffected, and the byte that shifted in last is lost. Clear the
OVRF bit by reading the SPI status and control register with OVRF set
and then reading the receive data register. Reset clears the OVRF bit.
1 = Overflow
0 = No overflow
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MODF — Mode Fault Bit
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This clearable, read-only flag is set in a slave SPI if the SS pin goes
high during a transmission with the MODFEN bit set. In a master SPI,
the MODF flag is set if the SS pin goes low at any time with the
MODFEN bit set. Clear the MODF bit by reading the SPI status and
control register (SPSCR) with MODF set and then writing to the SPI
control register (SPCR). Reset clears the MODF bit.
1 = SS pin at inappropriate logic level
0 = SS pin at appropriate logic level
SPTE — SPI Transmitter Empty Bit
This clearable, read-only flag is set each time the transmit data
register transfers a byte into the shift register. SPTE generates an
SPTE CPU interrupt request or an SPTE DMA service request if the
SPTIE bit in the SPI control register is set also.
NOTE:
Do not write to the SPI data register unless the SPTE bit is high.
During an SPTE CPU interrupt, the CPU clears the SPTE bit by
writing to the transmit data register.
Reset sets the SPTE bit.
1 = Transmit data register empty
0 = Transmit data register not empty
MODFEN — Mode Fault Enable Bit
This read/write bit, when set to 1, allows the MODF flag to be set. If
the MODF flag is set, clearing the MODFEN does not clear the MODF
flag. If the SPI is enabled as a master and the MODFEN bit is low,
then the SS pin is available as a general-purpose I/O.
If the MODFEN bit is set, then this pin is not available as a generalpurpose I/O. When the SPI is enabled as a slave, the SS pin is not
available as a general-purpose I/O regardless of the value of
MODFEN. See SS (Slave Select).
If the MODFEN bit is low, the level of the SS pin does not affect the
operation of an enabled SPI configured as a master. For an enabled
SPI configured as a slave, having MODFEN low only prevents the
MODF flag from being set. It does not affect any other part of SPI
operation. See Mode Fault Error.
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I/O Registers
SPR1 and SPR0 — SPI Baud Rate Select Bits
In master mode, these read/write bits select one of four baud rates as
shown in Table 20-4. SPR1 and SPR0 have no effect in slave mode.
Reset clears SPR1 and SPR0.
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Table 20-4. SPI Master Baud Rate Selection
SPR1 and SPR0
Baud Rate Divisor (BD)
00
2
01
8
10
32
11
128
Use this formula to calculate the SPI baud rate:
CGMOUT
Baud rate = -------------------------2 × BD
where:
CGMOUT = base clock output of the clock generator module (CGM)
BD = baud rate divisor
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20.14.3 SPI Data Register
The SPI data register consists of the read-only receive data register and
the write-only transmit data register. Writing to the SPI data register
writes data into the transmit data register. Reading the SPI data register
reads data from the receive data register. The transmit data and receive
data registers are separate registers that can contain different values.
See Figure 20-2.
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Address: $0012
Bit 7
6
5
4
3
2
1
Bit 0
Read:
R7
R6
R5
R4
R3
R2
R1
R0
Write:
T7
T6
T5
T4
T3
T2
T1
T0
Reset:
Indeterminate after reset
Figure 20-15. SPI Data Register (SPDR)
R7–R0/T7–T0 — Receive/Transmit Data Bits
NOTE:
Do not use read-modify-write instructions on the SPI data register since
the register read is not the same as the register written.
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Section 21. Timebase Module (TBM)
21.1 Contents
21.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
21.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
21.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
21.5
Timebase Register Description. . . . . . . . . . . . . . . . . . . . . . . . 331
21.6
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
21.7
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
21.2 Introduction
This section describes the timebase module (TBM). The TBM will
generate periodic interrupts at user selectable rates using a counter
clocked by the external crystal clock. This TBM version uses 15 divider
stages, eight of which are user selectable.
For further information regarding timers on M68HC08 family devices,
please consult the HC08 Timer Reference Manual, TIM08RM/AD.
21.3 Features
Features of the TBM module include:
•
Software programmable 1 Hz, 4 Hz, 16 Hz, 256 Hz, 512 Hz, 1024
Hz, 2048 Hz, and 4096 Hz periodic interrupt using external 32.768
kHz crystal
•
User selectable oscillator clock source enable during stop mode to
allow periodic wakeup from stop
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21.4 Functional Description
NOTE:
This module is designed for a 32.768 kHz oscillator.
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This module can generate a periodic interrupt by dividing the crystal
frequency, CGMXCLK. The counter is initialized to all 0s when TBON bit
is cleared. The counter, shown in Figure 21-1, starts counting when the
TBON bit is set. When the counter overflows at the tap selected by
TBR2:TBR0, the TBIF bit gets set. If the TBIE bit is set, an interrupt
request is sent to the CPU. The TBIF flag is cleared by writing a 1 to the
TACK bit. The first time the TBIF flag is set after enabling the timebase
module, the interrupt is generated at approximately half of the overflow
period. Subsequent events occur at the exact period.
TBON
÷2
÷2
÷ 128
÷2
÷ 64
÷2
÷ 32
÷2
÷8
÷2
÷ 16
÷2
CGMXCLK
÷2
÷2
TACK
÷2
TBR0
÷2
TBR1
÷2
÷ 32,768
÷2
÷ 8192
÷2
÷ 2048
÷2
TBR2
TBMINT
TBIF
000
TBIE
R
001
010
100
SEL
011
101
110
111
Figure 21-1. Timebase Block Diagram
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Timebase Register Description
21.5 Timebase Register Description
The timebase has one register, the TBCR, which is used to enable the
timebase interrupts and set the rate.
Address:
$001C
Bit 7
Read:
6
5
4
TBR2
TBR1
TBR0
TBIF
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2
1
Bit 0
TBIE
TBON
Reserved
0
0
0
0
Write:
Reset:
3
TACK
0
0
0
0
0
= Unimplemented
Figure 21-2. Timebase Control Register (TBCR)
TBIF — Timebase Interrupt Flag
This read-only flag bit is set when the timebase counter has rolled
over.
1 = Timebase interrupt pending
0 = Timebase interrupt not pending
TBR2:TBR0 — Timebase Rate Selection
These read/write bits are used to select the rate of timebase interrupts
as shown in Table 21-1.
Table 21-1. Timebase Rate Selection for OSC1 = 32.768 kHz
TBR2
TBR1
TBR0
Divider
0
0
0
0
0
0
Hz
ms
32,768
1
1000
1
8192
4
250
1
0
2048
16
62.5
0
1
1
128
256
~ 3.9
1
0
0
64
512
~2
1
0
1
32
1024
~1
1
1
0
16
2048
~0.5
1
1
1
8
4096
~0.24
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NOTE:
Do not change TBR2–TBR0 bits while the timebase is enabled
(TBON = 1).
TACK— Timebase ACKnowledge
The TACK bit is a write-only bit and always reads as 0. Writing a logic
1 to this bit clears TBIF, the timebase interrupt flag bit. Writing a logic
0 to this bit has no effect.
1 = Clear timebase interrupt flag
0 = No effect
TBIE — Timebase Interrupt Enabled
This read/write bit enables the timebase interrupt when the TBIF bit
becomes set. Reset clears the TBIE bit.
1 = Timebase interrupt enabled
0 = Timebase interrupt disabled
TBON — Timebase Enabled
This read/write bit enables the timebase. Timebase may be turned off
to reduce power consumption when its function is not necessary. The
counter can be initialized by clearing and then setting this bit. Reset
clears the TBON bit.
1 = Timebase enabled
0 = Timebase disabled and the counter initialized to 0s
21.6 Interrupts
The timebase module can interrupt the CPU on a regular basis with a
rate defined by TBR2:TBR0. When the timebase counter chain rolls
over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase
interrupt, the counter chain overflow will generate a CPU interrupt
request.
Interrupts must be acknowledged by writing a logic 1 to the TACK bit.
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Low-Power Modes
21.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low powerconsumption standby modes.
21.7.1 Wait Mode
The timebase module remains active after execution of the WAIT
instruction. In wait mode, the timebase register is not accessible by the
CPU.
If the timebase functions are not required during wait mode, reduce the
power consumption by stopping the timebase before enabling the WAIT
instruction.
21.7.2 Stop Mode
The timebase module may remain active after execution of the STOP
instruction if the oscillator has been enabled to operate during stop mode
through the OSCSTOPEN bit in the CONFIG register. The timebase
module can be used in this mode to generate a periodic wakeup from
stop mode.
If the oscillator has not been enabled to operate in stop mode, the
timebase module will not be active during STOP mode. In stop mode, the
timebase register is not accessible by the CPU.
If the timebase functions are not required during stop mode, reduce the
power consumption by stopping the timebase before enabling the STOP
instruction.
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Technical Data — MC68HC908GR8
Section 22. Timer Interface Module (TIM)
22.1 Contents
22.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
22.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
22.4
Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
22.5
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
22.6
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
22.7
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347
22.8
TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 348
22.9
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
22.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
22.2 Introduction
This section describes the timer interface (TIM) module. The TIM on this
part is a 2-channel and a1-channel timer that provides a timing reference
with input capture, output compare, and pulse-width-modulation
functions. Figure 22-1 is a block diagram of the TIM. This particular MCU
has two timer interface modules which are denoted as TIM1 and TIM2.
For further information regarding timers on M68HC08 family devices,
please consult the HC08 Timer Reference Manual, TIM08RM/AD.
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Timer Interface Module (TIM)
22.3 Features
Features of the TIM include:
•
Three input capture/output compare channels:
– Rising-edge, falling-edge, or any-edge input capture trigger
– Set, clear, or toggle output compare action
•
Buffered and unbuffered pulse-width-modulation (PWM) signal
generation
•
Programmable TIM clock input with 7-frequency internal bus clock
prescaler selection
•
Free-running or modulo up-count operation
•
Toggle any channel pin on overflow
•
TIM counter stop and reset bits
•
I/O port bit(s) software configurable with pullup device(s) if
configured as input port bit(s)
22.4 Pin Name Conventions
The text that follows describes both timers, TIM1 and TIM2. The TIM
input/output (I/O) pin names are T[1,2]CH0 (timer 1 channel 0, timer 2
channel 0) and T[1]CH1 (timer channel 1), where “1” is used to indicate
TIM1 and “2” is used to indicate TIM2. The two TIMs share three I/O pins
with three port D I/O port pins. The full names of the TIM I/O pins are
listed in Table 22-1. The generic pin names appear in the text that
follows.
Table 22-1. Pin Name Conventions
TIM Generic Pin Names:
Full TIM
Pin Names:
T[1,2]CH0
T[1,2]CH1
TIM1
PTD4/ATD12/TBLCK
PTD5/T1CH1
TIM2
PTD6/ATD14/TACLK
--
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Functional Description
NOTE:
References to either timer 1 or timer 2 may be made in the following text
by omitting the timer number. For example, TCH0 may refer generically
to T1CH0 and T2CH0, and TCH1 will refer to T1CH1.
NOTE:
The Timer Interface Module in MC68HC908GR8 is constructed by TIM1
which is contained channel 0 and 1, and TIM2 which is contained
channel 0 only.
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22.5 Functional Description
NOTE:
References to TCLK and external TIM clock input are only valid if the
MCU has an external TCLK pin. If the MCU has no external TCLK pin,
the TIM module must use the internal bus clock prescaler selections.
Figure 22-1 shows the structure of the TIM. The central component of
the TIM is the 16-bit TIM counter that can operate as a free-running
counter or a modulo up-counter. The TIM counter provides the timing
reference for the input capture and output compare functions. The TIM
counter modulo registers, TMODH:TMODL, control the modulo value of
the TIM counter. Software can read the TIM counter value at any time
without affecting the counting sequence.
The TIM channels (per timer) are programmable independently as input
capture or output compare channels. If a channel is configured as input
capture, then an internal pullup device may be enabled for that channel.
See Port D Input Pullup Enable Register.
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INTERNAL
TCLK
PRESCALER SELECT
INTERNAL
BUS CLOCK
PRESCALER
TSTOP
PS2
TRST
PS1
PS0
16-BIT COUNTER
TOF
TOIE
INTERRUPT
LOGIC
16-BIT COMPARATOR
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TMODH:TMODL
TOV0
ELS0B
CHANNEL 0
ELS0A
CH0MAX
PORT
LOGIC
T[1,2]CH0
16-BIT COMPARATOR
TCH0H:TCH0L
CH0F
16-BIT LATCH
MS0A
CH0IE
INTERRUPT
LOGIC
MS0B
INTERNAL BUS
TOV1
ELS1B
CHANNEL 1
ELS1A
CH1MAX
PORT
LOGIC
T[1]CH1
16-BIT COMPARATOR
TCH1H:TCH1L
CH1F
16-BIT LATCH
MS1A
CH1IE
INTERRUPT
LOGIC
Figure 22-1. TIM Block Diagram
NOTE:
References to either timer 1 or timer 2 may be made in the following text
by omitting the timer number. For example, TSC may generically refer to
both T1SC and T2SC.
NOTE:
In Figure 22-1, channel1 will only be available in TIM1 while channel 0
will be available in both TIM1 and TIM2
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Timer Interface Module (TIM)
Functional Description
Figure 22-2 summarizes the timer registers.
Addr.
$0020
$0021
$0022
$0023
$0024
Register Name
Timer 1 Status and Control
Register (T1SC)
Timer 1 Counter Register
High (T1CNTH)
Timer 1 Counter Register
Low (T1CNTL)
Timer 1 Counter Modulo
Register High (T1MODH)
Timer 1 Counter Modulo
Register Low (T1MODL)
Timer 1 Channel 0 Status
$0025
and Control Register
(T1SC0)
$0026
$0027
$0028
$0029
$002A
$002B
$002C
Timer 1 Channel 0
Register High (T1CH0H)
Timer 1 Channel 0
Register Low (T1CH0L)
Timer 1 Channel 1 Status
and Control Register
(T1SC1)
Timer 1 Channel 1
Register High (T1CH1H)
Timer 1 Channel 1
Register Low (T1CH1L)
Timer 2 Status and Control
Register (T2SC)
Timer 2 Counter Register
High (T2CNTH)
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Bit 7
TOF
0
0
Bit 15
6
5
1
13
4
0
TRST
0
12
TOIE
TSTOP
0
14
0
Bit 7
0
6
0
5
0
0
Bit 15
3
0
2
1
Bit 0
PS2
PS1
PS0
0
11
0
10
0
9
0
Bit 8
0
4
0
3
0
2
0
1
0
Bit 0
0
0
0
0
0
0
14
13
12
11
10
9
Bit 8
1
1
1
1
1
1
1
1
Bit 7
6
5
4
3
2
1
Bit 0
1
CH0F
0
0
1
1
1
1
1
1
1
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
Indeterminate after reset
Bit 7
6
5
4
3
Indeterminate after reset
CH1F
0
0
Bit 15
CH1IE
0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
0
0
0
14
13
12
11
10
9
Bit 8
2
1
Bit 0
PS2
PS1
PS0
0
10
0
9
0
Bit 8
0
0
0
Indeterminate after reset
Bit 7
TOF
0
0
Bit 15
0
6
TOIE
0
14
5
4
3
Indeterminate after reset
0
0
TSTOP
TRST
1
0
0
13
12
11
0
0
= Unimplemented
0
0
Figure 22-2. TIM I/O Register Summary (Sheet 1 of 2)
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Timer Interface Module (TIM)
Addr.
$002D
$002E
$002F
Register Name
Timer 2 Counter Register
Low (T2CNTL)
Timer 2 Counter Modulo
Register High (T2MODH)
Timer 2 Counter Modulo
Register Low (T2MODL)
Timer 2 Channel 0 Status
$0030
and Control Register
(T2SC0)
$0031
$0032
Timer 2 Channel 0
Register High (T2CH0H)
Timer 2 Channel 0
Register Low (T2CH0L)
$0033
$0034
$0035
Unimplemented
Unimplemented
Unimplemented
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Bit 7
Bit 7
6
6
5
5
4
4
3
3
2
2
1
1
Bit 0
Bit 0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
1
1
1
1
1
1
1
1
Bit 7
6
5
4
3
2
1
Bit 0
1
CH0F
0
0
1
1
1
1
1
1
1
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
0
0
0
Indeterminate after reset
Bit 7
6
5
4
3
Indeterminate after reset
0
0
0
0
0
Indeterminate after reset
Indeterminate after reset
= Unimplemented
Figure 22-2. TIM I/O Register Summary (Sheet 2 of 2)
22.5.1 TIM Counter Prescaler
The TIM clock source can be one of the seven prescaler outputs or the
TIM clock pin, TCLK. The prescaler generates seven clock rates from
the internal bus clock. The prescaler select bits, PS[2:0], in the TIM
status and control register select the TIM clock source.
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Functional Description
22.5.2 Input Capture
With the input capture function, the TIM can capture the time at which an
external event occurs. When an active edge occurs on the pin of an input
capture channel, the TIM latches the contents of the TIM counter into the
TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is
programmable. Input captures can generate TIM CPU interrupt
requests.
22.5.3 Output Compare
With the output compare function, the TIM can generate a periodic pulse
with a programmable polarity, duration, and frequency. When the
counter reaches the value in the registers of an output compare channel,
the TIM can set, clear, or toggle the channel pin. Output compares can
generate TIM CPU interrupt requests.
22.5.4 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare
pulses as described in Output Compare. The pulses are unbuffered
because changing the output compare value requires writing the new
value over the old value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change an
output compare value could cause incorrect operation for up to two
counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new
value prevents any compare during that counter overflow period. Also,
using a TIM overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIM may pass
the new value before it is written.
Use the following methods to synchronize unbuffered changes in the
output compare value on channel x:
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•
When changing to a smaller value, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current output compare pulse. The interrupt routine has until
the end of the counter overflow period to write the new value.
•
When changing to a larger output compare value, enable TIM
overflow interrupts and write the new value in the TIM overflow
interrupt routine. The TIM overflow interrupt occurs at the end of
the current counter overflow period. Writing a larger value in an
output compare interrupt routine (at the end of the current pulse)
could cause two output compares to occur in the same counter
overflow period.
22.5.5 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare
channel whose output appears on the TCH0 pin. The TIM channel
registers of the linked pair alternately control the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0)
links channel 0 and channel 1. The output compare value in the TIM
channel 0 registers initially controls the output on the TCH0 pin. Writing
to the TIM channel 1 registers enables the TIM channel 1 registers to
synchronously control the output after the TIM overflows. At each
subsequent overflow, the TIM channel registers (0 or 1) that control the
output are the ones written to last. TSC0 controls and monitors the
buffered output compare function, and TIM channel 1 status and control
register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin,
TCH1, is available as a general-purpose I/O pin.
NOTE:
In buffered output compare operation, do not write new output compare
values to the currently active channel registers. User software should
track the currently active channel to prevent writing a new value to the
active channel. Writing to the active channel registers is the same as
generating unbuffered output compares.
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Functional Description
22.5.6 Pulse Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel,
the TIM can generate a PWM signal. The value in the TIM counter
modulo registers determines the period of the PWM signal. The channel
pin toggles when the counter reaches the value in the TIM counter
modulo registers. The time between overflows is the period of the PWM
signal.
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As Figure 22-3 shows, the output compare value in the TIM channel
registers determines the pulse width of the PWM signal. The time
between overflow and output compare is the pulse width. Program the
TIM to clear the channel pin on output compare if the state of the PWM
pulse is logic 1. Program the TIM to set the pin if the state of the PWM
pulse is logic 0.
The value in the TIM counter modulo registers and the selected
prescaler output determines the frequency of the PWM output. The
frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIM counter modulo registers produces a PWM
period of 256 times the internal bus clock period if the prescaler select
value is $000. See TIM Status and Control Register.
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PULSE
WIDTH
PTEx/TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 22-3. PWM Period and Pulse Width
The value in the TIM channel registers determines the pulse width of the
PWM output. The pulse width of an 8-bit PWM signal is variable in 256
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increments. Writing $0080 (128) to the TIM channel registers produces
a duty cycle of 128/256 or 50%.
22.5.7 Unbuffered PWM Signal Generation
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Any output compare channel can generate unbuffered PWM pulses as
described in Pulse Width Modulation (PWM). The pulses are unbuffered
because changing the pulse width requires writing the new pulse width
value over the old value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change a pulse
width value could cause incorrect operation for up to two PWM periods.
For example, writing a new value before the counter reaches the old
value but after the counter reaches the new value prevents any compare
during that PWM period. Also, using a TIM overflow interrupt routine to
write a new, smaller pulse width value may cause the compare to be
missed. The TIM may pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the
PWM pulse width on channel x:
NOTE:
•
When changing to a shorter pulse width, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current pulse. The interrupt routine has until the end of the
PWM period to write the new value.
•
When changing to a longer pulse width, enable TIM overflow
interrupts and write the new value in the TIM overflow interrupt
routine. The TIM overflow interrupt occurs at the end of the current
PWM period. Writing a larger value in an output compare interrupt
routine (at the end of the current pulse) could cause two output
compares to occur in the same PWM period.
In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to selfcorrect in the event of software error or noise. Toggling on output
compare also can cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
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Functional Description
22.5.8 Buffered PWM Signal Generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose
output appears on the TCH0 pin. The TIM channel registers of the linked
pair alternately control the pulse width of the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0)
links channel 0 and channel 1. The TIM channel 0 registers initially
control the pulse width on the TCH0 pin. Writing to the TIM channel 1
registers enables the TIM channel 1 registers to synchronously control
the pulse width at the beginning of the next PWM period. At each
subsequent overflow, the TIM channel registers (0 or 1) that control the
pulse width are the ones written to last. TSC0 controls and monitors the
buffered PWM function, and TIM channel 1 status and control register
(TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1,
is available as a general-purpose I/O pin.
NOTE:
In buffered PWM signal generation, do not write new pulse width values
to the currently active channel registers. User software should track the
currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as
generating unbuffered PWM signals.
22.5.9 PWM Initialization
To ensure correct operation when generating unbuffered or buffered
PWM signals, use the following initialization procedure:
1. In the TIM status and control register (TSC):
a. Stop the TIM counter by setting the TIM stop bit, TSTOP.
b. Reset the TIM counter and prescaler by setting the TIM reset
bit, TRST.
2. In the TIM counter modulo registers (TMODH:TMODL), write the
value for the required PWM period.
3. In the TIM channel x registers (TCHxH:TCHxL), write the value for
the required pulse width.
4. In TIM channel x status and control register (TSCx):
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a. Write 0:1 (for unbuffered output compare or PWM signals) or
1:0 (for buffered output compare or PWM signals) to the
mode select bits, MSxB:MSxA. See Table 22-3.
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on
compare) to the edge/level select bits, ELSxB:ELSxA. The
output action on compare must force the output to the
complement of the pulse width level. (See Table 22-3.)
Freescale Semiconductor, Inc...
NOTE:
In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to selfcorrect in the event of software error or noise. Toggling on output
compare can also cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
5. In the TIM status control register (TSC), clear the TIM stop bit,
TSTOP.
Setting MS0B links channels 0 and 1 and configures them for buffered
PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially
control the buffered PWM output. TIM status control register 0 (TSCR0)
controls and monitors the PWM signal from the linked channels.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM
overflows. Subsequent output compares try to force the output to a state
it is already in and have no effect. The result is a 0% duty cycle output.
Setting the channel x maximum duty cycle bit (CHxMAX) and setting the
TOVx bit generates a 100% duty cycle output. (See TIM Channel Status
and Control Registers.)
22.6 Interrupts
The following TIM sources can generate interrupt requests:
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Low-Power Modes
•
TIM overflow flag (TOF) — The TOF bit is set when the TIM
counter value reaches the modulo value programmed in the TIM
counter modulo registers. The TIM overflow interrupt enable bit,
TOIE, enables TIM overflow CPU interrupt requests. TOF and
TOIE are in the TIM status and control register.
•
TIM channel flags (CH1F:CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. Channel x
TIM CPU interrupt requests and TIM DMA service requests are
controlled by the channel x interrupt enable bit, CHxIE. Channel x
TIM CPU interrupt requests are enabled when CHxIE = 1. CHxF
and CHxIE are in the TIM channel x status and control register.
DMAxS is in the TIM DMA select register.
22.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low powerconsumption standby modes.
22.7.1 Wait Mode
The TIM remains active after the execution of a WAIT instruction. In wait
mode, the TIM registers are not accessible by the CPU. Any enabled
CPU interrupt request from the TIM can bring the MCU out of wait mode.
If TIM functions are not required during wait mode, reduce power
consumption by stopping the TIM before executing the WAIT instruction.
22.7.2 Stop Mode
The TIM is inactive after the execution of a STOP instruction. The STOP
instruction does not affect register conditions or the state of the TIM
counter. TIM operation resumes when the MCU exits stop mode after an
external interrupt.
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Timer Interface Module (TIM)
22.8 TIM During Break Interrupts
A break interrupt stops the TIM counter.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. See SIM Break Flag Control Register.
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a 2-step read/write clearing procedure. If software does
the first step on such a bit before the break, the bit cannot change during
the break state as long as BCFE is at logic 0. After the break, doing the
second step clears the status bit.
22.9 I/O Signals
Port D shares three of its pins with the TIM. (There is an optional TCLK
which can be used as an external clock input to the TIM prescaler, but is
not available on this MCU.) The three TIM channel I/O pins are T1CH0,
T1CH1 and T2CH0 as described in Pin Name Conventions.
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. T1CH0 and T2CH0 can be
configured as buffered output compare or buffered PWM pins.
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I/O Registers
22.10 I/O Registers
NOTE:
References to either timer 1 or timer 2 may be made in the following text
by omitting the timer number. For example, TSC may generically refer to
both T1SC AND T2SC.
These I/O registers control and monitor operation of the TIM:
•
TIM status and control register (TSC)
•
TIM control registers (TCNTH:TCNTL)
•
TIM counter modulo registers (TMODH:TMODL)
•
TIM channel status and control registers (TSC0, TSC1)
•
TIM channel registers (TCH0H:TCH0L, TCH1H:TCH1L)
22.10.1 TIM Status and Control Register
The TIM status and control register (TSC):
•
Enables TIM overflow interrupts
•
Flags TIM overflows
•
Stops the TIM counter
•
Resets the TIM counter
•
Prescales the TIM counter clock
Address: T1SC, $0020 and T2SC, $002B
Bit 7
Read:
6
5
TOIE
TSTOP
TOF
Write:
0
Reset:
0
4
3
0
0
2
1
Bit 0
PS2
PS1
PS0
0
0
0
TRST
0
1
0
0
= Unimplemented
Figure 22-4. TIM Status and Control Register (TSC)
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TOF — TIM Overflow Flag Bit
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This read/write flag is set when the TIM counter reaches the modulo
value programmed in the TIM counter modulo registers. Clear TOF by
reading the TIM status and control register when TOF is set and then
writing a logic 0 to TOF. If another TIM overflow occurs before the
clearing sequence is complete, then writing logic 0 to TOF has no
effect. Therefore, a TOF interrupt request cannot be lost due to
inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic
1 to TOF has no effect.
1 = TIM counter has reached modulo value
0 = TIM counter has not reached modulo value
TOIE — TIM Overflow Interrupt Enable Bit
This read/write bit enables TIM overflow interrupts when the TOF bit
becomes set. Reset clears the TOIE bit.
1 = TIM overflow interrupts enabled
0 = TIM overflow interrupts disabled
TSTOP — TIM Stop Bit
This read/write bit stops the TIM counter. Counting resumes when
TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM
counter until software clears the TSTOP bit.
1 = TIM counter stopped
0 = TIM counter active
NOTE:
Do not set the TSTOP bit before entering wait mode if the TIM is required
to exit wait mode.
TRST — TIM Reset Bit
Setting this write-only bit resets the TIM counter and the TIM
prescaler. Setting TRST has no effect on any other registers.
Counting resumes from $0000. TRST is cleared automatically after
the TIM counter is reset and always reads as logic 0. Reset clears the
TRST bit.
1 = Prescaler and TIM counter cleared
0 = No effect
NOTE:
Setting the TSTOP and TRST bits simultaneously stops the TIM counter
at a value of $0000.
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I/O Registers
PS2–PS0 — Prescaler Select Bits
These read/write bits select either the TCLK pin or one of the seven
prescaler outputs as the input to the TIM counter as Table 22-2
shows. Reset clears the PS[2:0] bits.
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Table 22-2. Prescaler Selection
PS2–PS0
TIM Clock Source
000
Internal bus clock ÷1
001
Internal bus clock ÷ 2
010
Internal bus clock ÷ 4
011
Internal bus clock ÷ 8
100
Internal bus clock ÷ 16
101
Internal bus clock ÷ 32
110
Internal bus clock ÷ 64
111
Not available
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22.10.2 TIM Counter Registers
The two read-only TIM counter registers contain the high and low bytes
of the value in the TIM counter. Reading the high byte (TCNTH) latches
the contents of the low byte (TCNTL) into a buffer. Subsequent reads of
TCNTH do not affect the latched TCNTL value until TCNTL is read.
Reset clears the TIM counter registers. Setting the TIM reset bit (TRST)
also clears the TIM counter registers.
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NOTE:
If you read TCNTH during a break interrupt, be sure to unlatch TCNTL
by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
Address: T1CNTH, $0021 and T2CNTH, $002C
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 22-5. TIM Counter Registers High (TCNTH)
Address: T1CNTL, $0022 and T2CNTL, $002D
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 22-6. TIM Counter Registers Low (TCNTL)
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I/O Registers
22.10.3 TIM Counter Modulo Registers
The read/write TIM modulo registers contain the modulo value for the
TIM counter. When the TIM counter reaches the modulo value, the
overflow flag (TOF) becomes set, and the TIM counter resumes counting
from $0000 at the next timer clock. Writing to the high byte (TMODH)
inhibits the TOF bit and overflow interrupts until the low byte (TMODL) is
written. Reset sets the TIM counter modulo registers.
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Address: T1MODH, $0023 and T2MODH, $002E
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
1
1
1
1
1
1
1
1
Write:
Reset:
= Unimplemented
Figure 22-7. TIM Counter Modulo Register High (TMODH)
Address: T1MODL, $0024 and T2MODL, $002F
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
1
1
1
1
1
1
1
1
Write:
Reset:
= Unimplemented
Figure 22-8. TIM Counter Modulo Register Low (TMODL)
NOTE:
Reset the TIM counter before writing to the TIM counter modulo registers.
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22.10.4 TIM Counter Registers
The two read-only TIM counter registers contain the high and low bytes
of the value in the TIM counter. Reading the high byte (TCNTH) latches
the contents of the low byte (TCNTL) into a buffer. Subsequent reads of
TCNTH do not affect the latched TCNTL value until TCNTL is read.
Reset clears the TIM counter registers. Setting the TIM reset bit (TRST)
also clears the TIM counter registers.
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NOTE:
If you read TCNTH during a break interrupt, be sure to unlatch TCNTL
by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
Address: T1CNTH, $0021 and T2CNTH, $002C
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 22-9. TIM Counter Register High (TCNTH)
Address: T1CNTL, $0022 and T2CNTL, $002D
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 22-10. TIM Counter Register Low (TCNTL)
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I/O Registers
22.10.5 TIM Channel Status and Control Registers
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Each of the TIM channel status and control registers:
•
Flags input captures and output compares
•
Enables input capture and output compare interrupts
•
Selects input capture, output compare, or PWM operation
•
Selects high, low, or toggling output on output compare
•
Selects rising edge, falling edge, or any edge as the active input
capture trigger
•
Selects output toggling on TIM overflow
•
Selects 0% and 100% PWM duty cycle
•
Selects buffered or unbuffered output compare/PWM operation
Address: T1SC0, $0025 and T2SC0, $0030
Bit 7
Read:
CH0F
Write:
0
Reset:
0
6
5
4
3
2
1
Bit 0
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
0
0
0
0
0
0
0
Figure 22-11. TIM Channel 0 Status and Control Register (TSC0)
Address: T1SC1, $0028
Bit 7
Read:
6
CH1F
5
0
Reset:
0
3
2
1
Bit 0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
0
0
CH1IE
Write:
4
0
0
Figure 22-12. TIM Channel 1 Status and Control Register (TSC1)
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CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set
when an active edge occurs on the channel x pin. When channel x is
an output compare channel, CHxF is set when the value in the TIM
counter registers matches the value in the TIM channel x registers.
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When TIM CPU interrupt requests are enabled (CHxIE = 1), clear
CHxF by reading TIM channel x status and control register with CHxF
set and then writing a logic 0 to CHxF. If another interrupt request
occurs before the clearing sequence is complete, then writing logic 0
to CHxF has no effect. Therefore, an interrupt request cannot be lost
due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIM CPU interrupt service requests on
channel x.
Reset clears the CHxIE bit.
1 = Channel x CPU interrupt service requests enabled
0 = Channel x CPU interrupt service requests disabled
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation.
MSxB exists only in the TIM1 channel 0 and TIM2 channel 0 status
and control registers.
Setting MS0B disables the channel 1 status and control register and
reverts TCH1 to general-purpose I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MSxA — Mode Select Bit A
When ELSxB:A ≠ 00, this read/write bit selects either input capture
operation or unbuffered output compare/PWM operation. See Table
22-3.
1 = Unbuffered output compare/PWM operation
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I/O Registers
0 = Input capture operation
When ELSxB:A = 00, this read/write bit selects the initial output level
of the TCHx pin. See Table 22-3. Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE:
Before changing a channel function by writing to the MSxB or MSxA bit,
set the TSTOP and TRST bits in the TIM status and control register
(TSC).
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ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits
control the active edge-sensing logic on channel x.
When channel x is an output compare channel, ELSxB and ELSxA
control the channel x output behavior when an output compare
occurs.
When ELSxB and ELSxA are both clear, channel x is not connected
to port D, and pin PTDx/TCHx is available as a general-purpose I/O
pin. Table 22-3 shows how ELSxB and ELSxA work. Reset clears the
ELSxB and ELSxA bits.
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Table 22-3. Mode, Edge, and Level Selection
MSxB:MSxA
ELSxB:ELSxA
X0
00
Mode
Configuration
Pin under port control;
initial output level high
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Output preset
NOTE:
X1
00
Pin under port control;
initial output level low
00
01
Capture on rising edge only
00
10
00
11
01
01
01
10
01
11
1X
01
1X
10
1X
11
Input capture
Capture on falling edge only
Capture on rising or
falling edge
Output
compare or
PWM
Buffered
output
compare or
buffered PWM
Toggle output on compare
Clear output on compare
Set output on compare
Toggle output on compare
Clear output on compare
Set output on compare
Before enabling a TIM channel register for input capture operation, make
sure that the PTD/TCHx pin is stable for at least two bus clocks.
TOVx — Toggle On Overflow Bit
When channel x is an output compare channel, this read/write bit
controls the behavior of the channel x output when the TIM counter
overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
1 = Channel x pin toggles on TIM counter overflow.
0 = Channel x pin does not toggle on TIM counter overflow.
NOTE:
When TOVx is set, a TIM counter overflow takes precedence over a
channel x output compare if both occur at the same time.
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I/O Registers
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at logic 1, setting the CHxMAX bit forces the
duty cycle of buffered and unbuffered PWM signals to 100%. As .
CHxMAX Latency shows, the CHxMAX bit takes effect in the cycle
after it is set or cleared. The output stays at the 100% duty cycle level
until the cycle after CHxMAX is cleared.
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PTEx/TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
CHxMAX
Figure 22-13. CHxMAX Latency
22.10.6 TIM Channel Registers
These read/write registers contain the captured TIM counter value of the
input capture function or the output compare value of the output
compare function. The state of the TIM channel registers after reset is
unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the
TIM channel x registers (TCHxH) inhibits input captures until the low
byte (TCHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of
the TIM channel x registers (TCHxH) inhibits output compares until the
low byte (TCHxL) is written.
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Address: T1CH0H, $0026 and T2CH0H, $0031
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Read:
Write:
Reset:
Indeterminate after reset
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Figure 22-14. TIM Channel 0 Register High (TCH0H)
Address: T1CH0L, $0027 and T2CH0L $0032
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Indeterminate after reset
Figure 22-15. TIM Channel 0 Register Low (TCH0L)
Address: T1CH1H, $0029
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Read:
Write:
Reset:
Indeterminate after reset
Figure 22-16. TIM Channel 1 Register High (TCH1H)
Address: T1CH1L, $002A
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Indeterminate after reset
Figure 22-17. TIM Channel 1 Register Low (TCH1L)
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Section 23. Electrical Specifications
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23.1 Contents
23.2
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .362
23.3
Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 363
23.4
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
23.5
5.0 V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . 364
23.6
3.0 V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . 366
23.7
5.0 V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
23.8
3.0 V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
23.9
Output High-Voltage Characteristics . . . . . . . . . . . . . . . . . . .370
23.10 Output Low-Voltage Characteristics . . . . . . . . . . . . . . . . . . . . 373
23.11 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
23.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
23.13 5.0 V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
23.14 3.0 V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
23.15 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . 383
23.16 Clock Generation Module Characteristics . . . . . . . . . . . . . . . 383
23.17 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
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23.2 Absolute Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
NOTE:
This device is not guaranteed to operate properly beyond the maximum
ratings. Refer to 5.0 V DC Electrical Characteristics for guaranteed
operating conditions.
Freescale Semiconductor, Inc...
Table 23-1. Absolute Maximum Ratings
Characteristic(1)
Symbol
Value
Unit
Supply voltage
VDD
–0.3 to + 5.5
V
Input voltage
VIn
VSS – 0.3 to VDD + 0.3
V
Maximum current per pin
excluding VDD , VSS ,
and PTC0–PTC1
I
± 15
mA
Maximum current for pins
PTC0–PTC1
IPTC0–PTC1
± 25
mA
Maximum current into VDD
Imvdd
150
mA
Maximum current out of VSS
Imvss
150
mA
Tstg
–55 to +150
°C
Storage temperature
Note:
1. Voltages referenced to VSS
NOTE:
This device contains circuitry to protect the inputs against damage due
to high static voltages or electric fields; however, it is advised that normal
precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to this high-impedance circuit. For proper
operation, it is recommended that VIn and VOut be constrained to the
range VSS ≤ (VIn or VOut) ≤ VDD. Reliability of operation is enhanced if
unused inputs are connected to an appropriate logic voltage level (for
example, either VSS or VDD).
Technical Data
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Functional Operating Range
23.3 Functional Operating Range
Table 23-2. Functional Operation Range
Characteristic
Operating temperature range
Operating voltage range
NOTE:
Symbol
Value
Unit
TA
–40 to +125
°C
VDD
3.0 ±10%
5.0 ±10%
V
To ensure correct operation of the MCU under all operating conditions,
the user must write data $1C to address $0033 immediately after reset.
This is to ensure proper termination of an unused module within the
MCU.
23.4 Thermal Characteristics
Table 23-3. Thermal Characteristics
Characteristic
Symbol
Value
Unit
Thermal resistance
PDIP (28-pin)
SOIC (28-pin)
QFP (32-pin)
θJA
60
60
95
°C/W
I/O pin power dissipation
PI/O
User-Determined
W
Power dissipation(1)
PD
PD = (IDD × VDD) + PI/O =
K/(TJ + 273 °C)
W
Constant(2)
K
Average junction temperature
TJ
TA + (PD × θJA)
°C
TJM
140
°C
Maximum junction temperature
PD x (TA + 273 °C)
+ PD2 × θJA
W/°C
Notes:
1. Power dissipation is a function of temperature.
2. K is a constant unique to the device. K can be determined for a known TA and measured
PD. With this value of K, PD and TJ can be determined for any value of TA.
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Electrical Specifications
23.5 5.0 V DC Electrical Characteristics
Table 23-4. 5.0V DC Electrical Characteristics
Symbol
Min
Typ(2)
Max
Unit
VOH
VOH
VOH
IOH1
VDD – 0.8
VDD – 1.5
VDD – 0.8
—
—
—
—
—
—
—
—
50
V
V
V
mA
IOH2
—
—
50
mA
IOHT
—
—
100
mA
VOL
VOL
VOL
IOL1
—
—
—
—
—
—
—
—
0.4
1.5
1.0
50
V
V
V
mA
IOL2
—
—
50
mA
IOLT
—
—
100
mA
Input high voltage
All ports, IRQs, RESET
OSC1
VIH
0.7 x VDD
0.8 x VDD
—
VDD
V
Input low voltage
All ports, IRQs, RESET, OSC1
VIL
VSS
—
0.2 x VDD
V
IDD
—
—
15
4
20
8
mA
mA
IDD
—
—
—
—
3
5
20
300
5
10
35
500
µA
µA
µA
µA
I/O ports Hi-Z leakage current(7)
IIL
—
—
±10
µA
Input current
IIn
—
—
1
µA
Characteristic(1)
Output high voltage
(ILoad = –2.0 mA) all I/O pins
(ILoad = –10.0 mA) all I/O pins
(ILoad = –10.0 mA) pins PTC0–PTC1 only
Maximum combined IOH for port C, port E,
port PTD0–PTD3
Maximum combined IOH for port PTD4–PTD6,
port A, port B
Maximum total IOH for all port pins
Output low voltage
(ILoad = 1.6 mA) all I/O pins
(ILoad = 10 mA) all I/O pins
(ILoad = 15 mA) pins PTC0–PTC1 only
Maximum combined IOL for port C, port E,
port PTD0–PTD3
Maximum combined IOL for port PTD4–PTD6,
port A, port B
Maximum total IOL for all port pins
VDD supply current
Run(3)
Wait(4)
Stop(5) (<85 °C)
Stop (>85 °C)
Stop with TBM enabled(6)
Stop with LVI and TBM enabled(6)
Technical Data
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5.0 V DC Electrical Characteristics
Table 23-4. 5.0V DC Electrical Characteristics
Symbol
Min
Typ(2)
Max
Unit
Pullup resistors (as input only)
Ports PTA3/KBD3–PTA0/KBD0, PTC1–PTC0,
PTD6/T2CH0–PTD0/SS
RPU
20
45
65
kΩ
Capacitance
Ports (as input or output)
COut
CIn
—
—
—
—
12
8
pF
Monitor mode entry voltage
VTST
VDD +2.5
—
8
V
Low-voltage inhibit, trip falling voltage – target
VTRIPF
3.85
4.25
4.50
V
Low-voltage inhibit, trip rising voltage – target
VTRIPR
3.95
4.35
4.60
V
Low-voltage inhibit reset/recover hysteresis – target
(VTRIPF + VHYS = VTRIPR)
VHYS
—
100
—
mV
POR rearm voltage(8)
VPOR
0
—
100
mV
POR reset voltage(9)
VPORRST
0
700
800
mV
RPOR
0.035
—
—
V/ms
Characteristic(1)
POR rise time ramp rate(10)
Notes:
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) IDD measured using external square wave clock source (fosc = 32.8 MHz). All inputs 0.2 V from rail. No
dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
affects run IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fosc = 32.8 MHz). All inputs 0.2 V from rail. No dc loads. Less
than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait
IDD. Measured with PLL and LVI enabled.
5. Stop IDD is measured with OSC1 = VSS.
6. Stop IDD with TBM enabled is measured using an external square wave clock source (fOSC = 32.8 KHz). All inputs 0.2 V
from rail. No dc loads. Less than 100 pF on all outputs. All inputs configured as inputs.
7. Pullups and pulldowns are disabled. Port B leakage is specified in ADC Characteristics.
8. Maximum is highest voltage that POR is guaranteed.
9. Maximum is highest voltage that POR is possible.
10. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum
VDD is reached.
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23.6 3.0 V DC Electrical Characteristics
Table 23-5. 3.0 V DC Electrical Characteristics
Symbol
Min
Typ(2)
Max
Unit
VOH
VOH
VOH
IOH1
VDD – 0.3
VDD – 1.0
VDD – 0.5
—
—
—
—
—
—
—
—
30
V
V
V
mA
IOH2
—
—
30
mA
IOHT
—
—
60
mA
VOL
VOL
VOL
IOL1
—
—
—
—
—
—
—
—
0.3
1.0
0.8
30
V
V
V
mA
IOL2
—
—
30
mA
IOLT
—
—
60
mA
Input high voltage
All ports, IRQs, RESET
OSC1
VIH
0.7 x VDD
0.8 x VDD
—
VDD
V
Input low voltage
All ports, IRQs, RESET
OSC1
VIL
VSS
—
0.3 x VDD
0.2 x VDD
V
IDD
—
—
4.5
1.65
8
4
mA
mA
IDD
—
—
—
—
1
3
12
200
3
6
20
300
µA
µA
µA
µA
I/O ports Hi-Z leakage current(7)
IIL
—
—
±10
µA
Input current
IIn
—
—
1
µA
Characteristic(1)
Output high voltage
(ILoad = –0.6 mA) all I/O pins
(ILoad = –4.0 mA) all I/O pins
(ILoad = –4.0 mA) pins PTC0–PTC1 only
Maximum combined IOH for port C, port E,
port PTD0–PTD3
Maximum combined IOH for port PTD4–PTD6,
port A, port B
Maximum total IOH for all port pins
Output low voltage
(ILoad = 0.5 mA) all I/O pins
(ILoad = 6.0 mA) all I/O pins
(ILoad = 10.0 mA) pins PTC0–PTC1 only
Maximum combined IOL for port C, port E,
port PTD0–PTD3
Maximum combined IOL for port PTD4–PTD6,
port A, port B
Maximum total IOL for all port pins
VDD supply current
Run(3)
Wait(4)
Stop(5)(<85 °C)
Stop (>85 °C)
Stop with TBM enabled(6)
Stop with LVI and TBM enabled(6)
Technical Data
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3.0 V DC Electrical Characteristics
Table 23-5. 3.0 V DC Electrical Characteristics
Symbol
Min
Typ(2)
Max
Unit
Pullup resistors (as input only)
Ports PTA3/KBD37–PTA0/KBD0, PTC1–PTC0,
PTD6/T2CH0–PTD0/SS
RPU
20
45
65
kΩ
Capacitance
Ports (as input or output)
COut
CIn
—
—
—
—
12
8
pF
Monitor mode entry voltage
VTST
VDD +2.5
—
8
V
Low-voltage inhibit, trip falling voltage – target
VTRIPF
2.35
2.60
2.70
V
Low-voltage inhibit, trip rising voltage – target
VTRIPR
2.45
2.66
2.80
V
Low-voltage inhibit reset/recover hysteresis – target
(VTRIPF + VHYS = VTRIPR)
VHYS
—
60
—
mV
POR rearm voltage(8)
VPOR
0
—
100
mV
POR reset voltage(9)
VPORRST
0
700
800
mV
RPOR
0.02
—
—
V/ms
Characteristic(1)
POR rise time ramp rate(10)
Notes:
1. VDD = 3.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) IDD measured using external square wave clock source (fosc = 16.4 MHz). All inputs 0.2 V from rail. No
dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
affects run IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fosc = 16.4 MHz). All inputs 0.2 V from rail. No dc loads. Less
than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait
IDD. Measured with PLL and LVI enabled.
5. Stop IDD is measured with OSC1 = VSS.
6. Stop IDD with TBM enabled is measured using an external square wave clock source (fOSC = 32.8 KHz). All inputs 0.2 V
from rail. No dc loads. Less than 100 pF on all outputs. All inputs configured as inputs.
7. Pullups and pulldowns are disabled.
8. Maximum is highest voltage that POR is guaranteed.
9. Maximum is highest voltage that POR is possible.
10. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum
VDD is reached.
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23.7 5.0 V Control Timing
Table 23-6. 5.0 V Control Timing
Freescale Semiconductor, Inc...
Characteristic(1)
Symbol
Min
Max
Unit
Frequency of operation(2)
Crystal option
External clock option(3)
fosc
32
dc(4)
100
32.8
kHz
MHz
Internal operating frequency
fop
—
8.2
MHz
Internal clock period (1/fOP)
tcyc
122
—
ns
RESET input pulse width low(5)
tIRL
50
—
ns
IRQ interrupt pulse width low(6)
(edge-triggered)
tILIH
50
—
ns
IRQ interrupt pulse period
tILIL
Note 8
—
tcyc
16-bit timer(7)
Input capture pulse width
Input capture period
tTH,tTL
tTLTL
Note 8
—
—
ns
tcyc
Notes:
1. VSS = 0 Vdc; timing shown with respect to 20% VDD and 70% VSS unless otherwise noted.
2. See Clock Generation Module Characteristics for more information.
3. No more than 10% duty cycle deviation from 50%
4. Some modules may require a minimum frequency greater than dc for proper operation.
See appropriate table for this information.
5. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse
width to cause a reset.
6. Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to
be recognized.
7. Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to
be recognized.
8. The minimum period, tILIL or tTLTL, should not be less than the number of cycles it takes to
execute the interrupt service routine plus tcyc.
Technical Data
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3.0 V Control Timing
23.8 3.0 V Control Timing
Table 23-7. 3.0 V Control Timing
Freescale Semiconductor, Inc...
Characteristic(1)
Symbol
Min
Max
Unit
Frequency of operation(2)
Crystal option
External clock option(3)
fosc
32
dc(4)
100
16.4
kHz
MHz
Internal operating frequency
fop
—
4.1
MHz
Internal clock period (1/fOP)
tcyc
244
—
ns
RESET input pulse width low(5)
tIRL
125
—
ns
IRQ interrupt pulse width low(6)
(edge-triggered)
tILIH
125
—
ns
IRQ interrupt pulse period
tILIL
Note 8
—
tcyc
16-bit timer(7)
Input capture pulse width
Input capture period
tTH,tTL
tTLTL
Note 8
—
—
ns
tcyc
Notes:
1. VSS = 0 Vdc; timing shown with respect to 20% VDD and 70% VSS unless otherwise noted.
2. See Clock Generation Module Characteristics for more information.
3. No more than 10% duty cycle deviation from 50%
4. Some modules may require a minimum frequency greater than dc for proper operation.
See appropriate table for this information.
5. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse
width to cause a reset.
6. Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to
be recognized.
7. Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to
be recognized.
8. The minimum period, tILIL or tTLTL, should not be less than the number of cycles it takes to
execute the interrupt service routine plus tCYC.
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23.9 Output High-Voltage Characteristics
0
–5
IOH (mA)
–10
–40
0
25
85
–15
–20
–25
–30
Freescale Semiconductor, Inc...
–35
–40
3
3.2
3.4
3.6
VOH (V)
3.8
4.0
4.2
VOH > VDD –0.8 V @ IOH = –2.0 mA
VOH > VDD –1.5 V @ IOH = –10.0 mA
Figure 23-1. Typical High-Side Driver Characteristics –
Port PTA3–PTA0 (VDD = 4.5 Vdc)
0
IOH (mA)
–5
–40
0
25
85
–10
–15
–20
–25
1.3
1.5
1.7
1.9
VOH (V)
2.1
2.3
2.5
VOH > VDD –0.3 V @ IOH = –0.6 mA
VOH > VDD –1.0 V @ IOH = –4.0 mA
Figure 23-2. Typical High-Side Driver Characteristics –
Port PTA3–PTA0 (VDD = 2.7 Vdc)
Technical Data
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Output High-Voltage Characteristics
0
–5
IOH (mA)
–10
–40
0
25
85
–15
–20
–25
–30
–35
–40
Freescale Semiconductor, Inc...
3
3.2
3.4
3.6
VOH (V)
3.8
4.0
4.2
VOH > VDD –0.8 V @ IOH = –10.0 mA
Figure 23-3. Typical High-Side Driver Characteristics –
Port PTC1–PTC0 (VDD = 4.5 Vdc)
0
IOH (mA)
–5
–40
0
25
85
–10
–15
–20
–25
1.3
1.5
1.7
1.9
VOH (V)
2.1
2.3
2.5
VOH > VDD –0.5 V @ IOH = –4.0 mA
Figure 23-4. Typical High-Side Driver Characteristics –
Port PTC1–PTC0 (VDD = 2.7 Vdc)
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0
–10
–20
–40
0
25
85
IOH (mA)
–30
–40
–50
–60
–70
–80
–90
Freescale Semiconductor, Inc...
3
3.2
3.4
3.6
3.8
VOH (V)
4.0
4.2
4.4
4.6
VOH > VDD –0.8 V @ IOH = –2.0 mA
VOH > VDD –1.5 V @ IOH = –10.0 mA
Figure 23-5. Typical High-Side Driver Characteristics –
Ports PTB5–PTB0, PTD6–PTD0, and
PTE1–PTE0 (VDD = 5.5 Vdc)
0
IOH (mA)
–5
–40
0
25
85
–10
–15
–20
–25
1.3
1.5
1.7
1.9
VOH (V)
2.1
2.3
2.5
VOH > VDD –0.3 V @ IOH = –0.6 mA
VOH > VDD –1.0 V @ IOH = –4.0 mA
Figure 23-6. Typical High-Side Driver Characteristics –
Ports PTB5–PTB0, PTD6–PTD0, and
PTE1–PTE0 (VDD = 2.7 Vdc)
Technical Data
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Output Low-Voltage Characteristics
23.10 Output Low-Voltage Characteristics
35
30
–40
0
25
85
IOL (mA)
25
20
15
10
5
Freescale Semiconductor, Inc...
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
VOL (V)
VOL < 0.4 V @ IOL = 1.6 mA
VOL < 1.5 V @ IOL = 10.0 mA
Figure 23-7. Typical Low-Side Driver Characteristics –
Port PTA3–PTA0 (VDD = 5.5 Vdc)
14
12
–40
0
25
85
IOL (mA)
10
8
6
4
2
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
VOL (V)
VOL < 0.3 V @ IOL = 0.5 mA
VOL < 1.0 V @ IOL = 6.0 mA
Figure 23-8. Typical Low-Side Driver Characteristics –
Port PTA3–PTA0 (VDD = 2.7 Vdc)
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60
IOL (mA)
50
40
–40
0
25
85
30
20
10
0
0.4
0.6
0.8
1.0
1.2
1.4
1.6
VOL (V)
Freescale Semiconductor, Inc...
VOL < 1.0 V @ IOL = 15 mA
Figure 23-9. Typical Low-Side Driver Characteristics –
Port PTC1–PTC0 (VDD = 4.5 Vdc)
30
IOL (mA)
25
–40
0
25
85
20
15
10
5
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
VOL (V)
VOL < 0.8 V @ IOL = 10 mA
Figure 23-10. Typical Low-Side Driver Characteristics –
Port PTC1–PTC0 (VDD = 2.7 Vdc)
Technical Data
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Output Low-Voltage Characteristics
35
30
–40
0
25
85
IOL (mA)
25
20
15
10
5
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.6
1.4
VOL (V)
Freescale Semiconductor, Inc...
VOL < 0.4 V @ IOL = 1.6 mA
VOL < 1.5 V @ IOL = 10.0 mA
Figure 23-11. Typical Low-Side Driver Characteristics –
Ports PTB5–PTB0, PTD6–PTD0, and
PTE1–PTE0 (VDD = 5.5 Vdc)
14
12
–40
0
25
85
IOL (mA)
10
8
6
4
2
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
VOL (V)
VOL < 0.3 V @ IOL = 0.5 mA
VOL < 1.0 V @ IOL = 6.0 mA
Figure 23-12. Typical Low-Side Driver Characteristics –
Ports PTB5–PTB0, PTD6–PTD0, and
PTE1–PTE0 (VDD = 2.7 Vdc)
MC68HC908GR8 — Rev 4.0
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23.11 Typical Supply Currents
16
14
12
IDD (mA)
10
8
Freescale Semiconductor, Inc...
6
4
5.5 V
3.6 V
2
0
0
1
2
3
4
5
fbus (MHz)
6
7
8
9
Figure 23-13. Typical Operating IDD, with All Modules
Turned On (–40 °C to 125 °C)
5.0
4.5
4.0
IDD (mA)
3.5
3.0
2.5
2.0
1.5
1.0
5.5 V
3.6 V
0.5
0
0
1
2
3
4
fbus (MHz)
5
6
7
8
Figure 23-14. Typical Wait Mode IDD, with all Modules Disabled
(–40 °C to 125 °C)
Technical Data
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MC68HC908GR8 — Rev 4.0
Electrical Specifications
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Freescale Semiconductor, Inc.
Electrical Specifications
Typical Supply Currents
1.35
1.30
IDD (µA)
1.25
1.20
1.15
Freescale Semiconductor, Inc...
1.10
5.5 V
3.6 V
1.05
1
0
1
2
3
4
5
fbus (MHz)
6
7
8
9
Figure 23-15. Typical Stop Mode IDD, with all Modules Disabled
(–40 °C to 125 °C)
MC68HC908GR8 — Rev 4.0
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Freescale Semiconductor, Inc.
Electrical Specifications
23.12 ADC Characteristics
Characteristic(1)
Symbol
Min
Max
Unit
Comments
Supply voltage
VDDAD
2.7
(VDD
min)
5.5
(VDD
max)
V
VDDAD should be tied
to the same potential
as VDD via separate
traces.
Input voltages
VADIN
0
VDDAD
V
VADIN <= VREFH
Resolution
BAD
8
8
Bits
Absolute accuracy
(VREFL = 0 V, VDDAD = VREFH =
5 V ± 10%)
AAD
−−
±1
LSB
Includes quantization
ADC internal clock
fADIC
0.5
1.048
MHz
tAIC = 1/fADIC, tested
only at 1 MHz
Conversion range
RAD
VREFL
VREFH
V
VREFH = VDDAD
VREFL = VSSAD
Power-up time
tADPU
16
Conversion time
tADC
16
17
tAIC cycles
Sample time(2)
tADS
5
—
tAIC
cycles
Zero input reading(3)
ZADI
00
01
Hex
VIN = VREFL
Full-scale reading(3)
FADI
FE
FF
Hex
VIN = VREFH
Input capacitance
CADI
—
(20) 8
pF
Not tested
—
—
±1
µA
Input leakage(4)
Port B
tAIC cycles
Notes:
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, VDDAD = 5.0 Vdc ± 10%, VSSAD = 0 Vdc, VREFH = 5.0 Vdc ± 10%, VREFL = 0
2. Source impedances greater than 10 kΩ adversely affect internal RC charging time during input sampling.
3. Zero-input/full-scale reading requires sufficient decoupling measures for accurate conversions.
4. The external system error caused by input leakage current is approximately equal to the product of R source and input
current.
Technical Data
378
MC68HC908GR8 — Rev 4.0
Electrical Specifications
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Electrical Specifications
5.0 V SPI Characteristics
23.13 5.0 V SPI Characteristics
Diagram
Number(1)
Characteristic(2)
Symbol
Min
Max
Unit
Operating frequency
Master
Slave
fOP(M)
fOP(S)
fOP/128
DC
fOP/2
fOP
MHz
MHz
1
Cycle time
Master
Slave
tCYC(M)
tCYC(S)
2
1
128
—
tcyc
tcyc
2
Enable lead time
tLead(S)
1
—
tcyc
3
Enable lag time
tLag(S)
1
—
tcyc
4
Clock (SPSCK) high time
Master
Slave
tSCKH(M)
tSCKH(S)
tcyc –25
1/2 tcyc –25
64 tcyc
—
ns
ns
5
Clock (SPSCK) low time
Master
Slave
tSCKL(M)
tSCKL(S)
tcyc –25
1/2 tcyc –25
64 tcyc
—
ns
ns
6
Data setup time (inputs)
Master
Slave
tSU(M)
tSU(S)
30
30
—
—
ns
ns
7
Data hold time (inputs)
Master
Slave
tH(M)
tH(S)
30
30
—
—
ns
ns
8
Access time, slave(3)
CPHA = 0
CPHA = 1
tA(CP0)
tA(CP1)
0
0
40
40
ns
ns
9
Disable time, slave(4)
tDIS(S)
—
40
ns
10
Data valid time, after enable edge
Master
Slave(5)
tV(M)
tV(S)
—
—
50
50
ns
ns
11
Data hold time, outputs, after enable edge
Master
Slave
tHO(M)
tHO(S)
0
0
—
—
ns
ns
Notes:
1. Numbers refer to dimensions in Figure 23-16 and Figure 23-17.
2. All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins.
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
5. With 100 pF on all SPI pins
MC68HC908GR8 — Rev 4.0
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23.14 3.0 V SPI Characteristics
Freescale Semiconductor, Inc...
Diagram
Number(1)
Characteristic(2)
Symbol
Min
Max
Unit
Operating frequency
Master
Slave
fOP(M)
fOP(S)
fOP/128
DC
fOP/2
fOP
MHz
MHz
1
Cycle time
Master
Slave
tCYC(M)
tCYC(S)
2
1
128
—
tcyc
tcyc
2
Enable lead time
tLead(s)
1
—
tcyc
3
Enable lag time
tLag(s)
1
—
tcyc
4
Clock (SPSCK) high time
Master
Slave
tSCKH(M)
tSCKH(S)
tcyc –35
1/2 tcyc –35
64 tcyc
—
ns
ns
5
Clock (SPSCK) low time
Master
Slave
tSCKL(M)
tSCKL(S)
tcyc –35
1/2 tcyc –35
±
64 tcyc
—
ns
ns
6
Data setup time (inputs)
Master
Slave
tSU(M)
tSU(S)
40
40
—
—
ns
ns
7
Data hold time (inputs)
Master
Slave
tH(M)
tH(S)
40
40
—
—
ns
ns
8
Access time, slave(3)
CPHA = 0
CPHA = 1
tA(CP0)
tA(CP1)
0
0
50
50
ns
ns
9
Disable time, slave(4)
tDIS(S)
—
50
ns
10
Data valid time, after enable edge
Master
Slave(5)
tV(M)
tV(S)
—
—
60
60
ns
ns
11
Data hold time, outputs, after enable edge
Master
Slave
tHO(M)
tHO(S)
0
0
—
—
ns
ns
Notes:
1. Numbers refer to dimensions in Figure 23-16 and Figure 23-17.
2. All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins.
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
5. With 100 pF on all SPI pins
Technical Data
380
MC68HC908GR8 — Rev 4.0
Electrical Specifications
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Electrical Specifications
3.0 V SPI Characteristics
SS
INPUT
SS PIN OF MASTER HELD HIGH
1
SPSCK OUTPUT
CPOL = 0
NOTE
SPSCK OUTPUT
CPOL = 1
NOTE
5
4
5
4
6
MISO
INPUT
MSB IN
BITS 6–1
11
MOSI
OUTPUT
7
MASTER MSB OUT
LSB IN
10
11
BITS 6–1
MASTER LSB OUT
Note: This first clock edge is generated internally, but is not seen at the SPSCK pin.
a) SPI Master Timing (CPHA = 0)
SS
INPUT
SS PIN OF MASTER HELD HIGH
1
SPSCK OUTPUT
CPOL = 0
5
NOTE
4
SPSCK OUTPUT
CPOL = 1
5
NOTE
4
6
MISO
INPUT
MSB IN
10
MOSI
OUTPUT
BITS 6–1
11
MASTER MSB OUT
7
LSB IN
10
BITS 6–1
MASTER LSB OUT
Note: This last clock edge is generated internally, but is not seen at the SPSCK pin.
b) SPI Master Timing (CPHA = 1)
Figure 23-16. SPI Master Timing
MC68HC908GR8 — Rev 4.0
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Electrical Specifications
SS
INPUT
3
1
SPSCK INPUT
CPOL = 0
5
4
2
SPSCK INPUT
CPOL = 1
5
4
9
8
Freescale Semiconductor, Inc...
MISO
INPUT
SLAVE
MSB OUT
6
MOSI
OUTPUT
BITS 6–1
7
NOTE
11
11
10
MSB IN
SLAVE LSB OUT
BITS 6–1
LSB IN
Note: Not defined but normally MSB of character just received
a) SPI Slave Timing (CPHA = 0)
SS
INPUT
1
SPSCK INPUT
CPOL = 0
5
4
2
3
SPSCK INPUT
CPOL = 1
8
MISO
OUTPUT
MOSI
INPUT
5
4
10
NOTE
9
SLAVE
MSB OUT
6
7
BITS 6–1
11
10
MSB IN
SLAVE LSB OUT
BITS 6–1
LSB IN
Note: Not defined but normally LSB of character previously transmitted
b) SPI Slave Timing (CPHA = 1)
Figure 23-17. SPI Slave Timing
Technical Data
382
MC68HC908GR8 — Rev 4.0
Electrical Specifications
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Electrical Specifications
Timer Interface Module Characteristics
23.15 Timer Interface Module Characteristics
Table 23-8. Timer Interface Module Characteristics
Characteristic
Input capture pulse width
Symbol
Min
Max
Unit
tTIH, tTIL
1
—
tcyc
23.16 Clock Generation Module Characteristics
23.16.1 CGM Component Specifications
Table 23-9. CGM Component Specifications
Characteristic
Symbol
Min
Typ
Max
Unit
fXCLK
30
32.768
100
kHz
Crystal load capacitance(2)
CL
—
—
—
pF
Crystal fixed capacitance(2)
C1
6
2 × CL
40
pF
Crystal tuning capacitance(2)
C2
6
2 × CL
40
pF
Feedback bias resistor
RB
10
10
22
MΩ
Series resistor
RS
330
330
470
kΩ
Crystal reference frequency(1)
Notes:
1. Fundamental mode crystals only
2. Consult crystal manufacturer’s data.
MC68HC908GR8 — Rev 4.0
MOTOROLA
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Electrical Specifications
23.16.2 CGM Electrical Specifications
Description
Symbol
Min
Typ
Max
Unit
VDD
2.7
—
5.5
V
T
–40
25
125
o
Crystal reference frequency
fRCLK
30
32.768
100
kHz
Range nominal multiplier
fNOM
—
38.4
—
kHz
VCO center-of-range frequency(1)
fVRS
38.4 k
—
40.0 M
Hz
Medium-voltage VCO center-of-range frequency(2)
fVRS
38.4 k
—
40.0 M
Hz
VCO range linear range multiplier
L
1
—
255
VCO power-of-two range multiplier
2E
1
—
4
VCO multiply factor
N
1
—
4095
VCO prescale multiplier
2P
1
1
8
Reference divider factor
R
1
1
15
VCO operating frequency
fVCLK
38.4 k
—
40.0 M
Hz
Bus operating frequency(1)
fBUS
—
—
8.2
MHz
Bus frequency @ medium voltage(2)
fBUS
—
—
4.1
MHz
Manual acquisition time
tLock
—
—
50
ms
Automatic lock time
tLock
—
—
50
ms
Hz
Operating voltage
Operating temperature
C
fJ
0
—
fRCLK x
0.025%
x 2P N/4
External clock input frequency
PLL disabled
fOSC
dc
—
32.8 M
Hz
External clock input frequency
PLL enabled
fOSC
30 k
—
1.5 M
Hz
PLL
jitter(3)
Notes:
1. 5.0 V ± 10% VDD
2. 3.0 V ± 10% VDD
3. Deviation of average bus frequency over 2 ms. N = VCO multiplier.
Technical Data
384
MC68HC908GR8 — Rev 4.0
Electrical Specifications
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Electrical Specifications
Memory Characteristics
23.17 Memory Characteristics
Characteristic
RAM data retention voltage
FLASH program bus clock frequency
Symbol
Min
Typ
Max
Unit
VRDR
1.3
—
—
V
—
1
—
—
MHz
32k
—
8.4M
Hz
(1)
FLASH read bus clock frequency
fRead
FLASH page erase time
tErase(2)
1
—
—
ms
FLASH mass erase time
tMErase(3)
4
—
—
ms
FLASH PGM/ERASE to HVEN set up time
tnvs
10
—
—
µs
FLASH high-voltage hold time
tnvh
5
—
—
µs
FLASH high-voltage hold time (mass erase)
tnvhl
100
—
—
µs
FLASH program hold time
tpgs
5
—
—
µs
FLASH program time
tPROG
30
—
40
µs
FLASH return to read time
trcv(4)
1
—
—
µs
FLASH cumulative program HV period
tHV(5)
—
—
4
ms
FLASH row erase endurance(6)
—
10k
100k(7)
—
Cycles
FLASH row program endurance(8)
—
10k
100k(7)
—
Cycles
FLASH data retention time(9)
—
10
100(10)
—
Years
Notes:
1. fRead is defined as the frequency range for which the FLASH memory can be read.
2. If the page erase time is longer than tErase (Min), there is no erase-disturb, but it reduces the endurance of the FLASH
memory.
3. If the mass erase time is longer than tMErase (Min), there is no erase-disturb, but it reduces the endurance of the FLASH
memory.
4. trcv is defined as the time it needs before the FLASH can be read after turning off the high voltage charge pump, by clearing
HVEN to logic 0.
5. tHV is defined as the cumulative high voltage programming time to the same row before next erase.
tHV must satisfy this condition: tnvs + tnvh + tpgs + (tPROG × 64) ≤ tHV max.
6. The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at
least this many erase / program cycles.
7. FLASH endurance is a function of the temperature at which erasure occurs. Typical endurance degrades when the temperature while erasing is less than 25°C.
8. The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at
least this many erase / program cycles.
9. The FLASH is guaranteed to retain data over the entire operating temperature range for at least the minimum
time specified.
10. Motorola performs reliability testing for data retention. These tests are based on samples tested at elevated temperatures.
Due to the higher activation energy of the elevated test temperature, calculated life tests correspond to more than 100
years of operation/storage at 55°C
MC68HC908GR8 — Rev 4.0
MOTOROLA
Technical Data
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Electrical Specifications
Technical Data
386
MC68HC908GR8 — Rev 4.0
Electrical Specifications
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Technical Data — MC68HC908GR8
Section 24. Mechanical Specifications
24.1 Contents
24.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
24.3
32-Pin LQFP (Case #873A) . . . . . . . . . . . . . . . . . . . . . . . . . .388
24.4
28-Pin PDIP (Case #710) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
24.5
28-Pin SOIC (Case #751F). . . . . . . . . . . . . . . . . . . . . . . . . . . 390
24.2 Introduction
The MC68HC908GR8 is available in these packages:
•
32-pin low-profile quad flat pack (LQFP)
•
28-pin dual in-line package (PDIP)
•
28-pin small outline package (SOIC)
The package information contained in this section is the latest available
at the time of this publication. To make sure that you have the latest
package specifications, contact one of the following:
•
Local Motorola Sales Office
•
World Wide Web at http://www.motorola.com/semiconductors/
Follow World Wide Web on-line instructions to retrieve the current
mechanical specifications.
MC68HC908GR8 — Rev 4.0
MOTOROLA
Technical Data
Mechanical Specifications
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Mechanical Specifications
24.3 32-Pin LQFP (Case #873A)
–T–,–U–,–Z–
4X
A
A1
0.20 (0.008) AB T-U Z
32
25
1
B
AE
V
B1
Freescale Semiconductor, Inc...
AE
P
-U-
-T-
DETAIL Y
DETAIL Y
8
17
9
9
V1
NOTES:
1. DIMENSIONS AND TOLERANCING AS PER ANSI
Y14.5M, 1982
2. CONTROLLING DIMENSION: MILLIMETER
3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF
LEAD AND IS CONSISTENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE
4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT
DATUM PLANE -AB5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE -AC6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE -AB7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020)
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003)
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION
4X
-Z-
0.20 (0.008) AC T-U Z
S1
S
DETAIL AD
G
-ABSeating -ACplane
0.10 (0.004) AC
Base Metal
Z
DIM
D
J
R
C E
K
W
X
DETAIL AD
Q°
0.25 (0.010)
H
Gauge Plane
Section AE–AE
0.20 (0.008) M
F
8x M °
AC T – U
N
A
A1
B
B1
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
S1
V
V1
W
X
Technical Data
388
MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.300
0.450
1.350
1.450
0.300
0.400
0.800 BSC
0.050
0.150
0.090
0.200
0.500
0.700
12° REF
0.090
0.160
0.400 BSC
1°
5°
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
INCHES
MIN
MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055
0.063
0.012
0.018
0.053
0.057
0.012
0.016
0.031 BSC
0.002
0.006
0.004
0.008
0.020
0.028
12° REF
0.004
0.006
0.016 BSC
1°
5°
0.006
0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
MC68HC908GR8 — Rev 4.0
Mechanical Specifications
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Mechanical Specifications
28-Pin PDIP (Case #710)
24.4 28-Pin PDIP (Case #710)
A
B
Freescale Semiconductor, Inc...
1
G
H
L
N
C
K
M
F
J
D
Seating
Plane
Dim.
Min.
Max.
A
36.45
37.21
B
13.72
14.22
C
3.94
5.08
D
0.36
0.56
F
1.02
1.52
G
Notes
1. All dimensions in mm.
2. Positional tolerance of leads (‘D’) shall be within 0.25 mm at
maximum material condition, in relation to seating plane and to
each other.
3. Dimension ‘L’ is to centre of leads when formed parallel.
4. Dimension ‘B’ does not include mould protrusion.
2.54 BSC
MC68HC908GR8 — Rev 4.0
MOTOROLA
Dim.
Min.
Max.
H
1.65
2.16
J
0.20
0.38
K
2.92
3.43
L
15.24 BSC
M
0°
15 °
N
0.51
1.02
Technical Data
Mechanical Specifications
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Freescale Semiconductor, Inc.
Mechanical Specifications
24.5 28-Pin SOIC (Case #751F)
–A–
–B–
P
0.25
M B M
14 PL
1
Freescale Semiconductor, Inc...
R x 45°
G
J
C
0.25
M
T B S
Dim.
Min.
Max.
A
17.80
18.05
B
7.40
7.60
C
2.35
2.65
D
0.35
0.49
F
0.41
0.90
G
Seating
Plane
K
D 28 PL
–T–
F
A S
Notes
1.
2.
3.
4.
5.
Dimensions ‘A’ and ‘B’ are datums and ‘T’ is a datum surface.
Dimensioning and tolerancing per ANSI Y14.5M, 1982.
All dimensions in mm.
Dimensions ‘A’ and ‘B’ do not include mould protrusion.
Maximum mould protrusion is 0.15 mm per side.
1.27 BSC
Technical Data
390
M
Dim.
Min.
Max.
J
0.229
0.317
0.292
K
0.127
M
0°
8°
P
10.05
10.55
R
0.25
0.75
—
—
—
MC68HC908GR8 — Rev 4.0
Mechanical Specifications
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Section 25. Ordering Information
25.1 Contents
25.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
25.3
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
25.4
Development Tools. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
25.2 Introduction
This section contains instructions for ordering the MC68HC908GR8 and
MC68HC908GR4.
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25.3 MC Order Numbers
Table 25-1. MC Order Numbers
MC Order Number(1)
Operating
Temperature Range
(°C)
MC68HC908GR8CP
MC68HC908GR8CFA
MC68HC908GR8CDW
MC68HC908GR8VFA
MC68HC908GR8VP
MC68HC908GR8VDW
MC68HC908GR8MFA
MC68HC908GR8MP
MC68HC908GR8MDW
– 40 to + 85
– 40 to + 85
– 40 to + 85
– 40 to + 105
– 40 to + 105
– 40 to + 105
– 40 to + 125
– 40 to + 125
– 40 to + 125
MC68HC908GR4CP
MC68HC908GR4CFA
MC68HC908GR4CDW
MC68HC908GR4VFA
MC68HC908GR4VP
MC68HC908GR4VDW
MC68HC908GR4MFA
MC68HC908GR4MP
MC68HC908GR4MDW
– 40 to + 85
– 40 to + 85
– 40 to + 85
– 40 to + 105
– 40 to + 105
– 40 to + 105
– 40 to + 125
– 40 to + 125
– 40 to + 125
MC908GR8CFAR2
MC908GR8CDWR2
MC908GR8VFAR2
MC908GR8VDWR2
MC908GR8MFAR2
MC908GR8MDWR2
– 40 to + 85
– 40 to + 85
– 40 to + 105
– 40 to + 105
– 40 to + 125
– 40 to + 125
MC908GR4CFAR2
MC908GR4CDWR2
MC908GR4VFAR2
MC908GR4VDWR2
MC908GR4MFAR2
MC908GR4MDWR2
– 40 to + 85
– 40 to + 85
– 40 to + 105
– 40 to + 105
– 40 to + 125
– 40 to + 125
Production Parts
Tape and Reel
1. FA = quad flat pack
P = plastic dual in line package
DW = Small outline integrated circuit (SOIC) package
Technical Data
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Development Tools
25.4 Development Tools
Table 25-2. Development Tool Kits
Ordering Part Number
Description
M68ICS08GR
HC908GR8 ICS KIT includes: M68ICS08GR programmer board, Windowsbased IDE, 68HC908GR8 sample, ICS Board & IDE documentation, Universal
Power Supply, Serial cable
KITMMEVS08GR
HC908GR8 EVS KIT includes: M68MMPFB0508, M68EML08GP32,
M68CBL05C, M68TC08GR8P28, M68TC08GR8FA32, M68TQS032SAG1,
M68TQP032SA1, M68ICS08GR Kit
KITMMDS08GR
HC908GR8 MMDS KIT includes: M68MMDS0508, M68EML08GP32,
M68CBL05C, M68TC08GR8P28, M68TC08GR8FA32, M68TQS032SAG1,
M68TQP032SA1, M68ICS08GR Kit
Table 25-3. Development Tool Components
Ordering Part Number
Description
M68MMDS0508
High performance emulator
M68MMPFB0508
MMEVS Platform Board
M68EML08GP32
HC908GP32 Emulator Board
M68CBL05C
Used for HC908GR8/GR4 emulation
Low noise flex-cable
M68TC08GR8P28
28-pin DIP target head adapter
M68TC08GR8FA32
32-pin QFP target head adapter
M68TQS032SAG1
32-pin TQ socket with guides
M68TQP032SA1
Comments
32-pin TQPACK
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Glossary
A — See “accumulator (A).”
accumulator (A) — An 8-bit general-purpose register in the CPU08. The CPU08 uses the
accumulator to hold operands and results of arithmetic and logic operations.
acquisition mode — A mode of PLL operation during startup before the PLL locks on a
frequency. Also see "tracking mode."
address bus — The set of wires that the CPU or DMA uses to read and write memory locations.
addressing mode — The way that the CPU determines the operand address for an instruction.
The M68HC08 CPU has 16 addressing modes.
ALU — See “arithmetic logic unit (ALU).”
arithmetic logic unit (ALU) — The portion of the CPU that contains the logic circuitry to perform
arithmetic, logic, and manipulation operations on operands.
asynchronous — Refers to logic circuits and operations that are not synchronized by a common
reference signal.
baud rate — The total number of bits transmitted per unit of time.
BCD — See “binary-coded decimal (BCD).”
binary — Relating to the base 2 number system.
binary number system — The base 2 number system, having two digits, 0 and 1. Binary
arithmetic is convenient in digital circuit design because digital circuits have two
permissible voltage levels, low and high. The binary digits 0 and 1 can be interpreted to
correspond to the two digital voltage levels.
binary-coded decimal (BCD) — A notation that uses 4-bit binary numbers to represent the 10
decimal digits and that retains the same positional structure of a decimal number. For
example,
234 (decimal) = 0010 0011 0100 (BCD)
bit — A binary digit. A bit has a value of either logic 0 or logic 1.
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branch instruction — An instruction that causes the CPU to continue processing at a memory
location other than the next sequential address.
break module — A module in the M68HC08 Family. The break module allows software to halt
program execution at a programmable point in order to enter a background routine.
breakpoint — A number written into the break address registers of the break module. When a
number appears on the internal address bus that is the same as the number in the break
address registers, the CPU executes the software interrupt instruction (SWI).
break interrupt — A software interrupt caused by the appearance on the internal address bus
of the same value that is written in the break address registers.
bus — A set of wires that transfers logic signals.
bus clock — The bus clock is derived from the CGMOUT output from the CGM. The bus clock
frequency, fop, is equal to the frequency of the oscillator output, CGMXCLK, divided by
four.
byte — A set of eight bits.
C — The carry/borrow bit in the condition code register. The CPU08 sets the carry/borrow bit
when an addition operation produces a carry out of bit 7 of the accumulator or when a
subtraction operation requires a borrow. Some logical operations and data manipulation
instructions also clear or set the carry/borrow bit (as in bit test and branch instructions and
shifts and rotates).
CCR — See “condition code register.”
central processor unit (CPU) — The primary functioning unit of any computer system. The
CPU controls the execution of instructions.
CGM — See “clock generator module (CGM).”
clear — To change a bit from logic 1 to logic 0; the opposite of set.
clock — A square wave signal used to synchronize events in a computer.
clock generator module (CGM) — A module in the M68HC08 Family. The CGM generates a
base clock signal from which the system clocks are derived. The CGM may include a
crystal oscillator circuit and or phase-locked loop (PLL) circuit.
comparator — A device that compares the magnitude of two inputs. A digital comparator defines
the equality or relative differences between two binary numbers.
computer operating properly module (COP) — A counter module in the M68HC08 Family that
resets the MCU if allowed to overflow.
Technical Data
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condition code register (CCR) — An 8-bit register in the CPU08 that contains the interrupt
mask bit and five bits that indicate the results of the instruction just executed.
control bit — One bit of a register manipulated by software to control the operation of the
module.
control unit — One of two major units of the CPU. The control unit contains logic functions that
synchronize the machine and direct various operations. The control unit decodes
instructions and generates the internal control signals that perform the requested
operations. The outputs of the control unit drive the execution unit, which contains the
arithmetic logic unit (ALU), CPU registers, and bus interface.
COP — See "computer operating properly module (COP)."
counter clock — The input clock to the TIM counter. This clock is the output of the TIM
prescaler.
CPU — See “central processor unit (CPU).”
CPU08 — The central processor unit of the M68HC08 Family.
CPU clock — The CPU clock is derived from the CGMOUT output from the CGM. The CPU
clock frequency is equal to the frequency of the oscillator output, CGMXCLK, divided by
four.
CPU cycles — A CPU cycle is one period of the internal bus clock, normally derived by dividing
a crystal oscillator source by two or more so the high and low times will be equal. The
length of time required to execute an instruction is measured in CPU clock cycles.
CPU registers — Memory locations that are wired directly into the CPU logic instead of being
part of the addressable memory map. The CPU always has direct access to the
information in these registers. The CPU registers in an M68HC08 are:
•
A (8-bit accumulator)
•
H:X (16-bit index register)
•
SP (16-bit stack pointer)
•
PC (16-bit program counter)
•
CCR (condition code register containing the V, H, I, N, Z, and C
bits)
CSIC — customer-specified integrated circuit
cycle time — The period of the operating frequency: tCYC = 1/fOP.
decimal number system — Base 10 numbering system that uses the digits zero through nine.
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direct memory access module (DMA) — A M68HC08 Family module that can perform data
transfers between any two CPU-addressable locations without CPU intervention. For
transmitting or receiving blocks of data to or from peripherals, DMA transfers are faster
and more code-efficient than CPU interrupts.
DMA — See "direct memory access module (DMA)."
DMA service request — A signal from a peripheral to the DMA module that enables the DMA
module to transfer data.
duty cycle — A ratio of the amount of time the signal is on versus the time it is off. Duty cycle is
usually represented by a percentage.
EEPROM — Electrically erasable, programmable, read-only memory. A nonvolatile type of
memory that can be electrically reprogrammed.
EPROM — Erasable, programmable, read-only memory. A nonvolatile type of memory that can
be erased by exposure to an ultraviolet light source and then reprogrammed.
exception — An event such as an interrupt or a reset that stops the sequential execution of the
instructions in the main program.
external interrupt module (IRQ) — A module in the M68HC08 Family with both dedicated
external interrupt pins and port pins that can be enabled as interrupt pins.
fetch — To copy data from a memory location into the accumulator.
firmware — Instructions and data programmed into nonvolatile memory.
free-running counter — A device that counts from zero to a predetermined number, then rolls
over to zero and begins counting again.
full-duplex transmission — Communication on a channel in which data can be sent and
received simultaneously.
H — The upper byte of the 16-bit index register (H:X) in the CPU08.
H — The half-carry bit in the condition code register of the CPU08. This bit indicates a carry from
the low-order four bits of the accumulator value to the high-order four bits. The half-carry
bit is required for binary-coded decimal arithmetic operations. The decimal adjust
accumulator (DAA) instruction uses the state of the H and C bits to determine the
appropriate correction factor.
hexadecimal — Base 16 numbering system that uses the digits 0 through 9 and the letters A
through F.
high byte — The most significant eight bits of a word.
Technical Data
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illegal address — An address not within the memory map
illegal opcode — A nonexistent opcode.
I — The interrupt mask bit in the condition code register of the CPU08. When I is set, all interrupts
are disabled.
index register (H:X) — A 16-bit register in the CPU08. The upper byte of H:X is called H. The
lower byte is called X. In the indexed addressing modes, the CPU uses the contents of
H:X to determine the effective address of the operand. H:X can also serve as a temporary
data storage location.
input/output (I/O) — Input/output interfaces between a computer system and the external world.
A CPU reads an input to sense the level of an external signal and writes to an output to
change the level on an external signal.
instructions — Operations that a CPU can perform. Instructions are expressed by programmers
as assembly language mnemonics. A CPU interprets an opcode and its associated
operand(s) and instruction.
interrupt — A temporary break in the sequential execution of a program to respond to signals
from peripheral devices by executing a subroutine.
interrupt request — A signal from a peripheral to the CPU intended to cause the CPU to
execute a subroutine.
I/O — See “input/output (I/0).”
IRQ — See "external interrupt module (IRQ)."
jitter — Short-term signal instability.
latch — A circuit that retains the voltage level (logic 1 or logic 0) written to it for as long as power
is applied to the circuit.
latency — The time lag between instruction completion and data movement.
least significant bit (LSB) — The rightmost digit of a binary number.
logic 1 — A voltage level approximately equal to the input power voltage (VDD).
logic 0 — A voltage level approximately equal to the ground voltage (VSS).
low byte — The least significant eight bits of a word.
low voltage inhibit module (LVI) — A module in the M68HC08 Family that monitors power
supply voltage.
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LVI — See "low voltage inhibit module (LVI)."
M68HC08 — A Motorola family of 8-bit MCUs.
mark/space — The logic 1/logic 0 convention used in formatting data in serial communication.
mask — 1. A logic circuit that forces a bit or group of bits to a desired state. 2. A photomask used
in integrated circuit fabrication to transfer an image onto silicon.
mask option — A optional microcontroller feature that the customer chooses to enable or
disable.
mask option register (MOR) — An EPROM location containing bits that enable or disable
certain MCU features.
MCU — Microcontroller unit. See “microcontroller.”
memory location — Each M68HC08 memory location holds one byte of data and has a unique
address. To store information in a memory location, the CPU places the address of the
location on the address bus, the data information on the data bus, and asserts the write
signal. To read information from a memory location, the CPU places the address of the
location on the address bus and asserts the read signal. In response to the read signal,
the selected memory location places its data onto the data bus.
memory map — A pictorial representation of all memory locations in a computer system.
microcontroller — Microcontroller unit (MCU). A complete computer system, including a CPU,
memory, a clock oscillator, and input/output (I/O) on a single integrated circuit.
modulo counter — A counter that can be programmed to count to any number from zero to its
maximum possible modulus.
monitor ROM — A section of ROM that can execute commands from a host computer for testing
purposes.
MOR — See "mask option register (MOR)."
most significant bit (MSB) — The leftmost digit of a binary number.
multiplexer — A device that can select one of a number of inputs and pass the logic level of that
input on to the output.
N — The negative bit in the condition code register of the CPU08. The CPU sets the negative bit
when an arithmetic operation, logical operation, or data manipulation produces a negative
result.
nibble — A set of four bits (half of a byte).
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object code — The output from an assembler or compiler that is itself executable machine code,
or is suitable for processing to produce executable machine code.
opcode — A binary code that instructs the CPU to perform an operation.
open-drain — An output that has no pullup transistor. An external pullup device can be
connected to the power supply to provide the logic 1 output voltage.
operand — Data on which an operation is performed. Usually a statement consists of an
operator and an operand. For example, the operator may be an add instruction, and the
operand may be the quantity to be added.
oscillator — A circuit that produces a constant frequency square wave that is used by the
computer as a timing and sequencing reference.
OTPROM — One-time programmable read-only memory. A nonvolatile type of memory that
cannot be reprogrammed.
overflow — A quantity that is too large to be contained in one byte or one word.
page zero — The first 256 bytes of memory (addresses $0000–$00FF).
parity — An error-checking scheme that counts the number of logic 1s in each byte transmitted.
In a system that uses odd parity, every byte is expected to have an odd number of logic
1s. In an even parity system, every byte should have an even number of logic 1s. In the
transmitter, a parity generator appends an extra bit to each byte to make the number of
logic 1s odd for odd parity or even for even parity. A parity checker in the receiver counts
the number of logic 1s in each byte. The parity checker generates an error signal if it finds
a byte with an incorrect number of logic 1s.
PC — See “program counter (PC).”
peripheral — A circuit not under direct CPU control.
phase-locked loop (PLL) — A oscillator circuit in which the frequency of the oscillator is
synchronized to a reference signal.
PLL — See "phase-locked loop (PLL)."
pointer — Pointer register. An index register is sometimes called a pointer register because its
contents are used in the calculation of the address of an operand, and therefore points to
the operand.
polarity — The two opposite logic levels, logic 1 and logic 0, which correspond to two different
voltage levels, VDD and VSS.
polling — Periodically reading a status bit to monitor the condition of a peripheral device.
port — A set of wires for communicating with off-chip devices.
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prescaler — A circuit that generates an output signal related to the input signal by a fractional
scale factor such as 1/2, 1/8, 1/10 etc.
program — A set of computer instructions that cause a computer to perform a desired operation
or operations.
program counter (PC) — A 16-bit register in the CPU08. The PC register holds the address of
the next instruction or operand that the CPU will use.
pull — An instruction that copies into the accumulator the contents of a stack RAM location. The
stack RAM address is in the stack pointer.
pullup — A transistor in the output of a logic gate that connects the output to the logic 1 voltage
of the power supply.
pulse-width — The amount of time a signal is on as opposed to being in its off state.
pulse-width modulation (PWM) — Controlled variation (modulation) of the pulse width of a
signal with a constant frequency.
push — An instruction that copies the contents of the accumulator to the stack RAM. The stack
RAM address is in the stack pointer.
PWM period — The time required for one complete cycle of a PWM waveform.
RAM — Random access memory. All RAM locations can be read or written by the CPU. The
contents of a RAM memory location remain valid until the CPU writes a different value or
until power is turned off.
RC circuit — A circuit consisting of capacitors and resistors having a defined time constant.
read — To copy the contents of a memory location to the accumulator.
register — A circuit that stores a group of bits.
reserved memory location — A memory location that is used only in special factory test modes.
Writing to a reserved location has no effect. Reading a reserved location returns an
unpredictable value.
reset — To force a device to a known condition.
ROM — Read-only memory. A type of memory that can be read but cannot be changed (written).
The contents of ROM must be specified before manufacturing the MCU.
SCI — See "serial communication interface module (SCI)."
serial — Pertaining to sequential transmission over a single line.
Technical Data
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serial communications interface module (SCI) — A module in the M68HC08 Family that
supports asynchronous communication.
serial peripheral interface module (SPI) — A module in the M68HC08 Family that supports
synchronous communication.
set — To change a bit from logic 0 to logic 1; opposite of clear.
shift register — A chain of circuits that can retain the logic levels (logic 1 or logic 0) written to
them and that can shift the logic levels to the right or left through adjacent circuits in the
chain.
signed — A binary number notation that accommodates both positive and negative numbers.
The most significant bit is used to indicate whether the number is positive or negative,
normally logic 0 for positive and logic 1 for negative. The other seven bits indicate the
magnitude of the number.
software — Instructions and data that control the operation of a microcontroller.
software interrupt (SWI) — An instruction that causes an interrupt and its associated vector
fetch.
SPI — See "serial peripheral interface module (SPI)."
stack — A portion of RAM reserved for storage of CPU register contents and subroutine return
addresses.
stack pointer (SP) — A 16-bit register in the CPU08 containing the address of the next available
storage location on the stack.
start bit — A bit that signals the beginning of an asynchronous serial transmission.
status bit — A register bit that indicates the condition of a device.
stop bit — A bit that signals the end of an asynchronous serial transmission.
subroutine — A sequence of instructions to be used more than once in the course of a program.
The last instruction in a subroutine is a return from subroutine (RTS) instruction. At each
place in the main program where the subroutine instructions are needed, a jump or branch
to subroutine (JSR or BSR) instruction is used to call the subroutine. The CPU leaves the
flow of the main program to execute the instructions in the subroutine. When the RTS
instruction is executed, the CPU returns to the main program where it left off.
synchronous — Refers to logic circuits and operations that are synchronized by a common
reference signal.
TIM — See "timer interface module (TIM)."
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timer interface module (TIM) — A module used to relate events in a system to a point in time.
timer — A module used to relate events in a system to a point in time.
toggle — To change the state of an output from a logic 0 to a logic 1 or from a logic 1 to a logic 0.
tracking mode — Mode of low-jitter PLL operation during which the PLL is locked on a
frequency. Also see "acquisition mode."
two’s complement — A means of performing binary subtraction using addition techniques. The
most significant bit of a two’s complement number indicates the sign of the number (1
indicates negative). The two’s complement negative of a number is obtained by inverting
each bit in the number and then adding 1 to the result.
unbuffered — Utilizes only one register for data; new data overwrites current data.
unimplemented memory location — A memory location that is not used. Writing to an
unimplemented location has no effect. Reading an unimplemented location returns an
unpredictable value. Executing an opcode at an unimplemented location causes an illegal
address reset.
V —The overflow bit in the condition code register of the CPU08. The CPU08 sets the V bit when
a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE,
and BLT use the overflow bit.
variable — A value that changes during the course of program execution.
VCO — See "voltage-controlled oscillator."
vector — A memory location that contains the address of the beginning of a subroutine written
to service an interrupt or reset.
voltage-controlled oscillator (VCO) — A circuit that produces an oscillating output signal of a
frequency that is controlled by a dc voltage applied to a control input.
waveform — A graphical representation in which the amplitude of a wave is plotted against time.
wired-OR — Connection of circuit outputs so that if any output is high, the connection point is
high.
word — A set of two bytes (16 bits).
write — The transfer of a byte of data from the CPU to a memory location.
X — The lower byte of the index register (H:X) in the CPU08.
Z — The zero bit in the condition code register of the CPU08. The CPU08 sets the zero bit when
an arithmetic operation, logical operation, or data manipulation produces a result of $00.
Technical Data
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Revision History
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
Changes from Rev 3.0 published in February 2002 to Rev 4.0
published in June 2002. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
Changes from Rev 2.0 published in January 2002 to Rev 3.0 published in February 2002 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Changes from Rev 1.0 published in April 2001 to Rev 2.0 published in December 2001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Introduction
This section contains the revision history for the MC68HC908GR8
technical data book.
Changes from Rev 3.0 published in February 2002 to Rev 4.0 published in
June 2002
Section
Page (in Rev 3.0)
Description of change
All references to the ROM MC68HC08GR8 removed. Appendix A removed.
Electrical
Specifications
363
Maximum junction temperature increased to 140°C
364
Input High Voltage for OSC1 changed
Stop IDD for temperatures >85°C added
366
Input High Voltage for OSC1 changed
Input Low Voltage for OSC1 changed
Stop IDD for temperatures >85°C added
MC68HC908GR8 — Rev 4.0
MOTOROLA
Technical Data
Revision History
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Revision History
Changes from Rev 2.0 published in January 2002 to Rev 3.0 published in
February 2002
Section
Page (in Rev 3.0)
Description of change
All references to the ROM MC68HC08GR8 removed. Appendix A removed.
363
Electrical
Specifications
Ordering
Information
376-377
Maximum operating temperature increased to 125°C
Maximum temperature increased to 125°C in titles of figures 2313, 23-14 and 23-15
383
Maximum operating temperature increaed to 125°C
391
New section added
Changes from Rev 1.0 published in April 2001 to Rev 2.0 published in
December 2001
Section
Page (in Rev 2.0)
Description of change
The blank state of the reset vectors, $FFFE and $FFFF, was incorrectly defined as $00
and is now $FF. This affects several places in the Monitor ROM (MON) section. The
information was previously described in an addendum. See details below:
Monitor ROM
(MON)
190
Penultimate bullet of features list
192
Final sentence of first paragraph
Each list item in Entering Monitor Mode section
193
Third column of Table 15-1
Timebase Module
(TBM)
329
Several changes for clarification
Timer Interface
Module (TIM)
335
Several changes for clarification
Electrical
Specifications
385
Typical column added to table. Typical values added for FLASH
row program endurance and FLASH data retention time
Technical Data
406
MC68HC908GR8 — Rev 4.0
Revision History
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For More Information On This Product,
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MC68HC908GR8/D
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