Intersil EL9200IL Programmable vcom Datasheet

EL9200, EL9201, EL9202
®
Data Sheet
October 30, 2008
FN7438.1
Programmable VCOM
Features
The EL9200, EL9201, and EL9202 represent programmable
VCOM amplifiers for use in TFT-LCD displays. Featuring 1,
2, and 4 channels of VCOM amplification, respectively, each
device features just a single programmable current source
for adding offset to one VCOM output. This current source is
programmable using a single wire interface to one of 128
levels. The value is stored on an internal EEPROM memory.
• 128 Step Adjustable Sink Current
• EEPROM Memory
• 2-pin Adjustment and Disable
• Single, Dual or Quad Amplifiers
- 44MHz Bandwidth
- 80V/µs Slew Rate
- 60mA Continuous Output
- 180mA Peak Output
The EL9200 is available in the 12 LD DFN package and the
EL9201 and EL9202 are available in 24 LD QFN packages.
All are specified for operation over the -40°C to +85°C
temperature range.
• Up to 18V Operation
• 2.6V to 3.6VLogic Control
Typical Block Diagram
• Pb-free Available (RoHS compliant)
RF
AVDD
VS+
RG
+
VSD
CTL
• TFT-LCD VCOM Supplies For
- LCD-TVs
- LCD Monitors
AVDD
VOUT
R1
INP
R2
GND
CE
Applications
INN
EEPROM
CONTROL
UP/DOWN
COUNTER
ANALOG
POT
GND
IOUT
SET
RSET
Pinouts
20 VINB-
21 VINB+
22 VS+
NC 1
19 NC
VOUTA 1
19 VOUTB
NC 2
18 VOUTA
VOUTD 2
18 VOUTC
12 VS+
GND 2
11 VOUTA
VINB+ 3
VINA+ 3
17 VS+
VIND- 3
17 VINC-
10 SET
IOUT 4
9 CE
16 VOUTB
AVDD 6
14 SET
AVDD 6
14 GND
GND 7
13 CE
1
NC 12
13 AVDD
IOUT 11
CTL 7
SET 10
CTL 12
15 VINC+
VSD 11
7 VSD
16 NC
VIND+ 5
NC 10
GND 6
NC 4
15 VINB-
NC 8
8 CTL
NC 9
NC 5
AVDD 5
THERMAL
PAD
NC 9
THERMAL
PAD
THERMAL
PAD
CE 8
IOUT 4
24 VINA-
20 VINA-
21 VINA+
22 NC
23 GND
24 NC
VINA- 1
23 VINA+
EL9202
(24 LD QFN)
TOP VIEW
EL9201
(24 LD QFN)
TOP VIEW
EL9200
(12 LD DFN)
TOP VIEW
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL9200, EL9201, EL9202
Ordering Information
PART
NUMBER
PART
MARKING
TEMP
RANGE
(°C)
PKG.
DWG. #
PACKAGE
EL9200IL
9200IL
-40 to +85
12 LD DFN
L12.4x4B
EL9200IL-T7*
9200IL
-40 to +85
12 LD DFN
L12.4x4B
EL9200IL-T13*
9200IL
-40 to +85
12 LD DFN
L12.4x4B
EL9200ILZ (Note)
9200ILZ
-40 to +85
12 LD DFN
(Pb-Free)
L12.4x4B
EL9200ILZ-T7* (Note)
9200ILZ
-40 to +85
12 LD DFN
(Pb-Free)
L12.4x4B
EL9200ILZ-T13* (Note)
9200ILZ
-40 to +85
12 LD DFN
(Pb-Free)
L12.4x4B
EL9201IL
9201IL
-40 to +85
24 LD QFN
MDP0046
EL9201IL-T7*
9201IL
-40 to +85
24 LD QFN
MDP0046
EL9201IL-T13*
9201IL
-40 to +85
24 LD QFN
MDP0046
EL9201ILZ ( Note)
9202ILZ
-40 to +85
24 LD QFN
(Pb-Free)
MDP0046
EL9201ILZ-T7* ( Note)
9202ILZ
-40 to +85
24 LD QFN
(Pb-Free)
MDP0046
EL9201ILZ-T13* (Note)
9202ILZ
-40 to +85
24 LD QFN
(Pb-Free)
MDP0046
EL9202IL
9202IL
-40 to +85
24 LD QFN
MDP0046
EL9202IL-T7*
9202IL
-40 to +85
24 LD QFN
MDP0046
EL9202IL-T13*
9202IL
-40 to +85
24 LD QFN
MDP0046
EL9202ILZ (Note)
9202ILZ
-40 to +85
24 LD QFN
(Pb-Free)
MDP0046
EL9202ILZ-T7* (Note)
9202ILZ
-40 to +85
24 LD QFN
MDP0046
EL9202ILZ-T13* (Note)
9202ILZ
-40 to +85
24 LD QFN
(Pb-Free)
MDP0046
*Add “-T” suffix for tape and reel *Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
2
FN7438.1
October 30, 2008
EL9200, EL9201, EL9202
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
VS+ Supply Voltage between VS+ and GND . . . . . . . . . . . . . .18V
Supply Voltage between VSD and GND . . . . . . . . . . . . . . . . . . . .4V
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 65mA
Input Voltages to GND
SET, CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +4V
CTL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +16V
Output Voltages to GND
OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +20V
AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +20V
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VSD = 3V, VS+ = 15V, AVDD = 15V, RSET = 24.9kΩ, and TA = +25°C unless otherwise specified.
DESCRIPTION
VS+
Supply Voltage
IS+
Quiescent Current
CONDITION
MIN
TYP
4.5
MAX
UNIT
16.5
V
EL9200
3.8
4.8
mA
EL9201
7.6
9.6
mA
EL9202
10.5
16
mA
3
3.6
V
2.6
VSD
Logic Supply Voltage
For programming
3.6
V
ISD
Quiescent Logic Current
CE = 3.6V
50
µA
CE = GND
25
µA
Program (charge pump current) (Note 1)
23
mA
Read (Note 1)
3
mA
25
µA
For operation
IADD
Supply Current
(Note 2)
CTLIH
CTL High Voltage
2.6V < VSD < 3.6V
0.7*VSD
0.8*VSD
V
CTLIL
CTL Low Voltage
2.6V < VSD < 3.6V
0.2*VSD
0.3*VSD
V
CTLIHRPW
CTL High Rejected Pulse Width
20
µs
CTLILRPW
CTL Low Rejected Pulse Width
20
µs
CTLIHMPW
CTL High Minimum Pulse Width
200
µs
CTLILMPW
CTL Low Minimum Pulse Width
CTLMTC
CTL Minimum Time Between Counts
ICTL
CTL Input Current
CTLCAP
CTL Input Capacitance
200
10
µs
CTL = GND
10
µA
CTL = VSD
10
µA
10
CEIL
CE Input Low Voltage
2.6V < VSD < 3.6V
CEIH
CE Input High Voltage
2.6V < VSD < 3.6V
CEST
CE Minimum Start-Up Time
(Note 1)
CTLPROM
CTL EEPROM Program Voltage
2.6V < VSD < 3.6V (Note 2)
4.9
CTLPT
CTL EEPROM Programming Signal
Time
> 4.9V
200
PT
Programming Time
EEWC
EE Write Cycles
pF
0.4
V
1.6
V
1
ms
15.75
1000
V
µs
100
(Note 5)
3
µs
ms
cycles
FN7438.1
October 30, 2008
EL9200, EL9201, EL9202
Electrical Specifications
PARAMETER
VSD = 3V, VS+ = 15V, AVDD = 15V, RSET = 24.9kΩ, and TA = +25°C unless otherwise specified. (Continued)
DESCRIPTION
CONDITION
SETDN
SET Differential Nonlinearity
Monotonic over-temperature
MIN
TYP
MAX
±1
UNIT
LSB
SETZSE
SET Zero-Scale Error
(Note 3)
±2
LSB
SETFSE
SET Full-Scale Error
(Note 3)
±8
LSB
ISET
SET Current
Through RSET (Note 1)
120
µA
SETER
SET External Resistance
To GND, AVDD = 20V (Note 1)
10
200
kΩ
To GND, AVDD = 4.5V (Note 1)
2.25
45
kΩ
AVDD to SET
AVDD to SET Voltage Attenuation
OUTST
OUT Settling Time
To ±0.5 LSB error band (Note 1)
VOUT
OUT Voltage Range
(Note 1)
OUTVD
OUT Voltage Drift
(Note 1)
1:20
V/V
20
µs
VSET + 0.5V
13
V
10
mV
15
mV
AMPLIFIER CHARACTERISTICS
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
TCVOS
Average Offset Voltage Drift (Note 1)
IB
Input Bias Current
RIN
Input Impedance
1
GΩ
CIN
Input Capacitance
2
pF
CMRR
Common-Mode Rejection Ratio
For VIN from -5.5V to +5.5V
50
70
dB
AVOL
Open-Loop Gain
-4.5V ≤ VOUT ≤ +4.5V
60
70
dB
VCM = 0V
3
7
VCM = 0V
2
µV/°C
60
nA
OUTPUT CHARACTERISTICS
VOL
Output Swing Low
RL = 1.5kΩ to 0
0.09
0.15
V
VOH
Output Swing High
14.85
14.9
V
ISC
Short-Circuit Current
±150
±180
mA
IOUT
Output Current
±65
mA
POWER SUPPLY PERFORMANCE
PSRR
Power Supply Rejection Ratio
VS+ is moved from 4.5V to 15.5V
55
80
dB
60
80
V/µs
80
ns
DYNAMIC PERFORMANCE
SR
Slew Rate (Note 4)
-4.0V ≤ VOUT ≤ 4.0V, 20% to 80%
tS
Settling to +0.1% (AV = +1)
(AV = +1), VOUT = 2V step
BW
-3dB Bandwidth
44
MHz
GBWP
Gain-Bandwidth Product
32
MHz
PM
Phase Margin
50
°
CS
Channel Separation
f = 5MHz (EL9201 and EL9202 only)
110
dB
dG
Differential Gain (Note 5)
RF = RG = 1kΩ and VOUT = 1.4V
0.17
%
dP
Differential Phase (Note 5)
RF = RG = 1kΩ and VOUT = 1.4V
0.24
°
NOTES:
1. Simulated and determined via design and not directly tested
2. Tested at AVDD = 20V
3. Wafer sort only
4. NTSC signal generator used
5. Limits established by characterization and are not production tested.
4
FN7438.1
October 30, 2008
EL9200, EL9201, EL9202
Pin Descriptions
PIN
IN/OUT
VINx-
Input
DESCRIPTION
EQUIVALENT CIRCUIT
Amplifier x inverting input, where:
x = A for EL9200
x = A, B for EL9201
x = A, B, C, D for EL9202
VS+
GND
CIRCUIT 1
VINx+
Input
Amplifier x non-inverting input, where:
x = A for EL9200
x = A, B for EL9201
x = A, B, C, D for EL9202
VS+
Supply
Op amp supply; bypass to GND with 0.1µF capacitor
VOUTX
Output
Amplifier X output, where:
x = A for EL9200
x = A, B for EL9201
x = A, B, C, D for EL9202
Reference Circuit 1
VS+
GND
GND
CIRCUIT 2
NC
-
No connect; not internally connected
GND
Supply
Ground connection
IOUT
Output
Adjustable sink current output pin; the current sinks into the
OUT pin is equal to the DAC setting times the maximum
adjustable sink current divided by 128; see SET pin function
description for the maxim adjustable sink current setting
SET
Output
Maximum sink current adjustment point; connect a resistor
from SET to GND to set the maximum adjustable sink
current of the OUT pin; the maximum adjustable sink
current is equal to (AVDD/20) divided by RSET
CE
Input
Counter enable pin; connect CE to VDD to enable counting
of the internal counter; connect CE to GND to inhibit
counting
CTL
Input
Internal counter up/down control and internal EEPROM
programming control input; if CE is high, a mid-to-low
transition increments the 7-bit counter, raising the DAC
setting, increasing the OUT sink current, and lowering the
divider voltage at OUT; a mid-to-high transition decrements
the 7-bit counter, lowering the DAC setting, decreasing the
OUT sink current, and increasing the divider voltage at
OUT; applying 4.9V and above with appropriately arranged
timing will overwrite EEPROM with the contents in the 7-bit
counter; see EEPROM Programming section for details
AVDD
Supply
Analog voltage supply; bypass to GND with 0.1µF
capacitor
VSD
Supply
System power supply input; bypass to GND with 0.1µF
capacitor
5
FN7438.1
October 30, 2008
EL9200, EL9201, EL9202
Amplifier Typical Performance Curves
0.008
TYPICAL
PRODUCTION
DISTRIBUTION
VS = 5V
TA = +25°C
400
300
200
100
VS = 5V
INPUT BIAS CURRENT (µA)
QUANTITY (AMPLIFIERS)
500
0
-0.004
-0.008
-0.012
-50
12
8
10
6
4
2
0
-2
-4
-6
-8
-10
-12
0
0.004
-10
FIGURE 1. INPUT OFFSET VOLTAGE DISTRIBUTION
110
150
FIGURE 2. INPUT BIAS CURRENT vs TEMPERATURE
4.96
VS = 5V
TYPICAL
PRODUCTION
DISTRIBUTION
20
15
10
5.0
OUTPUT HIGH VOLTAGE (V)
25
QUANTITY (AMPLIFIERS)
70
TEMPERATURE (°C)
INPUT OFFSET VOLTAGE (mV)
VS = 5V
IOUT = 5mA
4.94
4.92
4.90
4.88
4.86
-50
21
19
17
15
13
11
9
7
5
3
1
0
-10
FIGURE 3. INPUT OFFSET VOLTAGE DRIFT
70
110
150
FIGURE 4. OUTPUT HIGH VOLTAGE vs TEMPERATURE
-4.85
OUTPUT LOW VOLTAGE (V)
2.0
1.5
1.0
0.5
0
-0.5
-50
30
TEMPERATURE (°C)
INPUT OFFSET VOLTAGE DRIFT, TCVOS (µV/°C)
INPUT OFFSET VOLTAGE (mV)
30
-10
30
70
110
150
TEMPERATURE (°C)
FIGURE 5. INPUT OFFSET VOLTAGE vs TEMPERATURE
6
VS = 5V
IOUT = 5mA
-4.87
-4.89
-4.91
-4.93
-4.95
-50
-10
30
70
110
150
TEMPERATURE (°C)
FIGURE 6. OUTPUT LOW VOLTAGE vs TEMPERATURE
FN7438.1
October 30, 2008
EL9200, EL9201, EL9202
Amplifier Typical Performance Curves (Continued)
75
78
VS = ±V
77
SLEW RATE (V/µs)
OPEN-LOOP GAIN (dB)
VS = ±5V
RL = 1kΩ
70
65
76
75
74
73
60
-50
-10
30
70
110
72
-50
150
-10
70
110
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 7. OPEN-LOOP GAIN vs TEMPERATURE
FIGURE 8. SLEW RATE vs TEMPERATURE
0
0.30
-0.04
DIFFERENTIAL PHASE (°)
VS = 5V
AV = 2
RL = 1kΩ
-0.02
DIFFERENTIAL GAIN (%)
30
-0.06
-0.08
-0.10
-0.12
-0.14
0.25
0.20
0.15
0.10
0.05
-0.16
-0.18
0
0
100
200
0
100
IRE
FIGURE 9. DIFFERENTIAL GAIN
FIGURE 10. DIFFERENTIAL PHASE
-30
VS = 5V
AV = 2
RL = 1kΩ
FREQ = 1MHz
80
250
60
190
2nd HD
-60
3rd HD
40
130
20
70
PHASE
PHASE (°)
GAIN
-50
GAIN (dB)
DISTORTION (dB)
-40
200
IRE
-70
0
-80
-90
0
2
4
6
8
VOP-P (V)
FIGURE 11. HARMONIC DISTORTION vs VOP-P
7
10
-20
1k
10
10k
100k
1M
10M
-50
100M
FREQUENCY (Hz)
FIGURE 12. OPEN LOOP GAIN AND PHASE
FN7438.1
October 30, 2008
EL9200, EL9201, EL9202
Amplifier Typical Performance Curves (Continued)
3
25
VS = 5V
AV = 1
CLOAD = 0pF
MAGNITUDE (NORMALIZED) (dB)
MAGNITUDE (NORMALIZED) (dB)
5
1kΩ
1
-1
150Ω
560Ω
-3
-5
100k
1M
10M
100pF
15
1000pF
47pF
10pF
5
-5
-15
VS = 5V
AV = 1
RL = 1kΩ
-25
100k
100M
1M
FREQUENCY (Hz)
FIGURE 14. FREQUENCY RESPONSE FOR VARIOUS CL
12
MAXIMUM OUTPUT SWING (VP-P)
400
OUTPUT IMPEDANCE (Ω)
350
300
250
200
150
100
50
100k
10M
1M
100M
10
8
6
4
VS = 5V
2 AV = 1
RL = 1kΩ
DISTORTION <1%
0
10k
100k
FREQUENCY (Hz)
1M
10M
FIGURE 16. MAXIMUM OUTPUT SWING vs FREQUENCY
-15
-80
PSRR+
-25
-60
PSRR (dB)
CMRR (dB)
100M
FREQUENCY (Hz)
FIGURE 15. CLOSED LOOP OUTPUT IMPEDANCE
-35
-45
VS = 5V
TA = +25°C
PSRR-
-40
-20
-55
-65
1k
100M
FREQUENCY (Hz)
FIGURE 13. FREQUENCY RESPONSE FOR VARIOUS RL
0
10k
10M
10k
100k
1M
FREQUENCY (Hz)
FIGURE 17. CMRR
8
10M
100M
0
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 18. PSRR
FN7438.1
October 30, 2008
EL9200, EL9201, EL9202
Amplifier Typical Performance Curves (Continued)
-60
DUAL MEASURED CH A TO B
QUAD MEASURED CH A TO D OR B TO C
-80 OTHER COMBINATIONS YIELD
IMPROVED REJECTION
100
XTALK (dB)
VOLTAGE NOISE (nV/√Hz)
1k
10
-100
-120
-140
1
100
1k
10k
100k
1M
10M
-160
1k
100M
VS = 5V
RL=1kΩ
AV = 1
VIN = 110mVRMS
10k
FREQUENCY (Hz)
10M 30M
FIGURE 20. CHANNEL SEPARATION
100
5
VS = 5V
AV = 1
RL = 1kΩ
VIN = 50mV
TA = +25°C
3
STEP SIZE (V)
OVERSHOOT (%)
1M
FREQUENCY (Hz)
FIGURE 19. INPUT VOLTAGE NOISE SPECTRAL DENSITY
80
100k
60
40
VS = 5V
AV = 1
RL = 1kΩ
0.1%
1
-1
0.1%
20
-3
0
10
100
1k
-5
55
65
LOAD CAPACITANCE (pF)
FIGURE 21. SMALL-SIGNAL OVERSHOOT vs LOAD
CAPACITANCE
75
85
95
105
SETTLING TIME (ns)
FIGURE 22. SETTLING TIME vs STEP SIZE
VS = ±5V
TA = +25°C
AV = 1
RL = 1kΩ
VS = ±5V
TA = +25°C
AV = 1
RL = 1kΩ
100mV STEP
1V STEP
50ns/DIV
FIGURE 23. LARGE SIGNAL TRANSIENT RESPONSE
9
50ns/DIV
FIGURE 24. SMALL SIGNAL TRANSIENT RESPONSE
FN7438.1
October 30, 2008
EL9200, EL9201, EL9202
Amplifier Typical Performance Curves (Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - QFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
4.5
1.2
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
POWER DISSIPATION (W)
POWER DISSIPATION (W)
4.0
3.5 3.378W
3.0
θJ
A=
2.5
QF
37
2.0
N2
4
°C
/W
1.5
1.0
0.5
0
0
25
75 85 100
50
125
893mW
0.8
QF
N2
θ
JA
0.6
=1
40
°C
4
/W
0.4
0.2
0
150
0
AMBIENT TEMPERATURE (°C)
FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
1.0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Application Information
Adjustable Sink Current Output
This device provides the ability to reduce the flicker of an
LCD panel by adjustment of the VCOM voltage during
production test and alignment. A 128-step resolution is
provided under digital control which adjusts the sink current
of the output. The output is connected to an external voltage
divider, so that the device will have the capability to reduce
the voltage on the output by increasing the output sink
current.
The device provides an output sink current which lowers the
voltage on the external voltage divider. The equations that
control the output are given in Equation 1:
The adjustment of the output and the programming of the
non-volatile memory are provided on one pin while the
counter enable (CE) is provided on a separate pin. The
output is adjusted via the CTL pin either by counting up with
a mid to low transition or by counting down with a mid to high
transition. Once the minimum or maximum value is reached
on the 128 steps, the device will not overflow or underflow
beyond that minimum or maximum value. An increment of
the counter will increase the output sink current which will
lower the voltage on the external voltage divider. A
decrement of the counter will decrease the output sink
current, which will raise the voltage on the external voltage
divider.
Once the desired output level is obtained, the part can store
it's setting using the non-volatile memory in the device. See
the “Non-Volatile Memory (EEPROM) Programming” on
page 12 for detailed information.
Note: Once the desired output level is stored in the
EEPROM, the CE pin must go low to preserve the stored
value.
10
A VDD
Setting
I OUT = --------------------- × --------------------------20 ( R SET )
128
(EQ. 1)
R1
⎛ R2 ⎞
⎛
⎞
Setting
V OUT = ⎜ ---------------------⎟ V AVDD ⎜ 1 – --------------------- × ---------------------------⎟
20 ( R SET )⎠
128
⎝ R 1 + R 2⎠
⎝
NOTE: Where setting is an integer between 1 and 128.
7-Bit Up/Down Counter
The counter sets the level to the digital potentiometer and is
connected to the non-volatile memory. When the part is
programmed, the counter setting is loaded into the
non-volatile memory. This value will be loaded from the
non-volatile memory into the counter during power-on. The
counter will not exceed its maximum level and will hold that
value during subsequent increment requests on the CTL pin.
The counter will not exceed its minimum level and will hold
that value during subsequent decrement requests on the
CTL pin.
CTL Pin
CTL should have a noise filter to reduce bouncing or noise
on the input that could cause unwanted counting when the
CE pin is high. The board should have an additional ESD
protection circuit, with a series 1kΩ resistor and a shunt
0.01µF capacitor connected on the CTL pin.
In order to increment the setting, pulse CTL low for more
than 200µs. The output sink current increases and lowers
the VCOM lever by one least-significant bit (LSB). On the
other hand, to decrement the setting, pulse CTL high for
FN7438.1
October 30, 2008
EL9200, EL9201, EL9202
Since the internal comparators come up in an unknown
state, the very first CTL pulse is ignored to avoid the
possibility of a false pulse.
more than 200µs. The output sink current will decrease and
the VCOM level will increase by one LSB.
To avoid unintentional adjustment, the EL9200, EL9201, and
EL9202 guarantees to reject CTL pulses shorter than 20µs.
See Figure 27 for the timing information.
TABLE 1. TRUTH TABLE
INPUT
OUTPUT
CTL
CE
VDD
SET
ICC
MEMORY
Mid to Hi
Hi
VDD
Decrement
Normal
X
Mid to Lo
Hi
VDD
Increment
Normal
X
X
Lo
VDD
No Change
Lower
X
> 4.9V
X
VDD
No Change
Increased
Program
X
X
0 to VDD
Read
Increased
Read
NOTE: CE should be disabled (pulled low) before powering down the device to assure that the glitches and transients will not cause unwanted
EEPROM overwriting.
CTLMTC
CTLIHRPW
CTL HIGH
CTL
VDD/2
CTL LOW
CTLILMPW
CTLIHMPW
CTLILRPW
CE
COUNTER
OUTPUT
UNDEF
78
79
7A
7B
7A
VCOM
FIGURE 27. VCOM ADJUSTMENT
11
FN7438.1
October 30, 2008
EL9200, EL9201, EL9202
Non-Volatile Memory (EEPROM)
Programming
Short-Circuit Current Limit
When the CTL pin exceeds 4.9V, the non-volatile
programming cycle will be activated. The CTL signal needs
to remain above 4.9V for more than 200µs. The level and
timing needed to program the non-volatile memory is given
below. It then takes a maximum of 100ms for the
programming to be completed inside the device (see PT
specification in Table Electrical Specifications on page 3.
CTL VOLTAGE
4.9V
TIME
The amplifiers will limit the short circuit current to ±180mA if
the output is directly shorted to the positive or the negative
supply. If an output is shorted indefinitely, the power
dissipation could easily increase such that the device may
be damaged. Maximum reliability is maintained if the output
continuous current never exceeds ±65mA. This limit is set by
the design of the internal metal interconnects.
Output Phase Reversal
The amplifiers are immune to phase reversal as long as the
input voltage is limited from VS- -0.5V to VS+ +0.5V.
Figure 28 shows a photo of the output of the device with the
input voltage driven beyond the supply rails. Although the
device's output will not change phase, the input's
overvoltage should be avoided. If an input voltage exceeds
supply voltage by more than 0.6V, electrostatic protection
diodes placed in the input stage of the device begin to
conduct and over-voltage damage could occur.
CTLPT
1V
10µs
FIGURE 28. EEPROM PROGRAMMING
Amplifiers’ Operating Voltage, Input, and Output
The amplifiers are specified with a single nominal supply
voltage from 5V to 15V or a split supply with its total range
from 5V to 15V. Correct operation is guaranteed for a supply
range of 4.5V to 16.5V. Most amplifier specifications are
stable over both the full supply range and operating
temperatures of -40°C to +85°C. Parameter variations with
operating voltage and/or temperature are shown in the See
“Amplifier Typical Performance Curves” on page 6.
The input common-mode voltage range of the amplifiers
extends 500mV beyond the supply rails. The output swings
of the those typically extend to within 100mV of positive and
negative supply rails with load currents of 5mA. Decreasing
load currents will extend the output voltage range even
closer to the supply rails. Figure 27 shows the input and
output waveforms for the device in the unity-gain
configuration. Operation is from 5V supply with a 1kΩ load
connected to GND. The input is a 10VP-P sinusoid. The
output voltage is approximately 9.8VP-P.
5V
AV = 1
VS = 5V
TA = +25°C
VIN = 10VP-P
5V
FIGURE 30. OPERATION WITH BEYOND-THE-RAILS INPUT
Unused Amplifiers
It is recommended that any unused amplifiers in a dual and
a quad package be configured as a unity gain follower. The
inverting input should be directly connected to the output
and the non-inverting input tied to the ground plane.
Power Supply Bypassing and Printed Circuit
Board Layout
The amplifiers can provide gain at high frequency. As with
any high-frequency device, good printed circuit board layout
is necessary for optimum performance. Ground plane
construction is highly recommended, lead lengths should be
as short as possible and the power supply pins must be well
bypassed to reduce the risk of oscillation. For normal
operation, a 0.1µF ceramic capacitor should be placed from
VS to pin to GND. A 4.7µF tantalum capacitor should then be
connected in parallel, placed in the region of the amplifier.
OUTPUT
INPUT
10µs
1V
VS = 2.5V
AV = 1
TA = +25°C
VIN = 6VP-P
FIGURE 29. OPERATION WITH RAIL-TO-RAIL INPUT AND
OUTPUT
12
FN7438.1
October 30, 2008
EL9200, EL9201, EL9202
Replacing Existing Mechanical
Potentiometer Circuits
Figures 29 and 30 show the common adjustment mechanical circuits and equivalent replacement with the EL920x.
AVDD
AVDD
RF
RA
AVDD
IN+
RB
RG
VOUT
VCOM
EL9200
R1
IN+
R2
RC
VCOM
OUT
SET
RSET
R1 = RA
R2 = RB + RC
RA ( RB + RC )
R SET = -----------------------------------20R B
FIGURE 31. EXAMPLE OF THE REPLACEMENT FOR THE MECHANICAL POTENTIOMETER CIRCUIT USING EL9200
AVDD
RF
AVDD
RX
RY
AVDD
IN+
RG
VOUT
VCOM
EL9200
R1
IN+
R2
RZ
VCOM
OUT
SET
RSET
R1 = RX
R2 = RZ
RX ( RX + RY + RZ )
R SET = -------------------------------------------------20R Y
FIGURE 32. EXAMPLE OF THE REPLACEMENT FOR THE MECHANICAL POTENTIOMETER CIRCUIT USING THE EL9200
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
13
FN7438.1
October 30, 2008
EL9200, EL9201, EL9202
QFN (Quad Flat No-Lead) Package Family
MDP0046
QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY
(COMPLIANT TO JEDEC MO-220)
A
MILLIMETERS
D
N
(N-1)
(N-2)
B
1
2
3
PIN #1
I.D. MARK
E
(N/2)
2X
0.075 C
2X
0.075 C
N LEADS
TOP VIEW
0.10 M C A B
(N-2)
(N-1)
N
b
L
SYMBOL QFN44 QFN38
TOLERANCE
NOTES
A
0.90
0.90
0.90
0.90
±0.10
-
A1
0.02
0.02
0.02
0.02
+0.03/-0.02
-
b
0.25
0.25
0.23
0.22
±0.02
-
c
0.20
0.20
0.20
0.20
Reference
-
D
7.00
5.00
8.00
5.00
Basic
-
Reference
8
Basic
-
Reference
8
Basic
-
D2
5.10
3.80
5.80 3.60/2.48
E
7.00
7.00
8.00
1
2
3
6.00
E2
5.10
5.80
5.80 4.60/3.40
e
0.50
0.50
0.80
0.50
L
0.55
0.40
0.53
0.50
±0.05
-
N
44
38
32
32
Reference
4
ND
11
7
8
7
Reference
6
NE
11
12
8
9
Reference
5
MILLIMETERS
PIN #1 I.D.
3
QFN32
SYMBOL QFN28 QFN24
QFN20
QFN16
A
0.90
0.90
0.90
0.90
0.90
±0.10
-
A1
0.02
0.02
0.02
0.02
0.02
+0.03/
-0.02
-
b
0.25
0.25
0.30
0.25
0.33
±0.02
-
c
0.20
0.20
0.20
0.20
0.20
Reference
-
D
4.00
4.00
5.00
4.00
4.00
Basic
-
D2
2.65
2.80
3.70
2.70
2.40
Reference
-
(E2)
(N/2)
NE 5
7
(D2)
BOTTOM VIEW
0.10 C
e
C
SEATING
PLANE
TOLERANCE NOTES
E
5.00
5.00
5.00
4.00
4.00
Basic
-
E2
3.65
3.80
3.70
2.70
2.40
Reference
-
e
0.50
0.50
0.65
0.50
0.65
Basic
-
L
0.40
0.40
0.40
0.40
0.60
±0.05
-
N
28
24
20
20
16
Reference
4
ND
6
5
5
5
4
Reference
6
NE
8
7
5
5
4
Reference
5
Rev 11 2/07
0.08 C
N LEADS
& EXPOSED PAD
SEE DETAIL "X"
NOTES:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Tiebar view shown is a non-functional feature.
SIDE VIEW
3. Bottom-side pin #1 I.D. is a diepad chamfer as shown.
4. N is the total number of terminals on the device.
(c)
C
5. NE is the number of terminals on the “E” side of the package
(or Y-direction).
2
A
(L)
A1
N LEADS
DETAIL X
6. ND is the number of terminals on the “D” side of the package
(or X-direction). ND = (N/2)-NE.
7. Inward end of terminal may be square or circular in shape with radius
(b/2) as shown.
8. If two values are listed, multiple exposed pad options are available.
Refer to device-specific datasheet.
14
FN7438.1
October 30, 2008
EL9200, EL9201, EL9202
Package Outline Drawing
L12.4x4B
12 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 06/08
3.20
4.00
2X 2.50
A
6
PIN 1
INDEX AREA
10X 0.50
PIN #1 INDEX AREA
B
6
1
12 X 0.55
6
4.00
(4X)
2.40
0.15
7
12
0.10 M C A B
TOP VIEW
4 12 x 0.25
BOTTOM VIEW
SEE DETAIL "X"
( 3.20)
0.10 C
C
0.90 MAX
SEATING PLANE
0.08 C
SIDE VIEW
3.65
( 2.40 )
C
0.2 REF
5
12 X 0.75
0 . 00 MIN.
0 . 05 MAX.
( 12X 0.25 )
( 10X 0 . 5 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6.
15
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN7438.1
October 30, 2008