Rev. 1.0 JAN. 2000 4-BIT SINGLE CHIP MICROCOMPUTERS GMS36/37XXX(T) SERIES USER`S MANUAL • GMS36/37004(T) • GMS36/37112(T) • GMS36/37140(T) Revision 1.0 Published by MCU Application Team in HYUNDAI ELECTRONICS INDUSTRIES Co., Ltd. " HYUNDAI ELECTRONICS INDUSTRIES Co., Ltd. 2000 All Right Reserved. Editor's E-Mail : [email protected] [email protected] [email protected] Additional information of this manual may be served by Hyundai Electronics Industries Offices in Korea or Distributors and Representative listed at address directory. Hyundai Electronics Industries reserves the right to make changes to any Information here at any time without notice. The information, diagrams, and other data in this manual are correct and reliable; however, Hyundai Electronics Industries Co., Ltd. is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual. Table of Contents Table of Contents Chapter 1 GMS36XXX Description Features Block diagram Pin assignment Pin description Pin circuit Port operation Optional features Electrical characteristics Chapter 2 ………...………………..……………………1-1 ……………………………………………….1-1 ……………………………………………….1-2 ……………………………………………….1-3 ……………………………………………….1-4 ……………………………………………….1-5 ……………………………………………….1-7 ……………………………………………….1-7 ……………………………………………….1-8 GMS37XXX Description Features Block diagram Pin assignment Pin description Pin circuit Port operation Optional features Electrical characteristics ………...………………..……………………2-1 ……………………………………………….2-1 ……………………………………………….2-2 ……………………………………………….2-3 ……………………………………………….2-4 ……………………………………………….2-5 ……………………………………………….2-7 ……………………………………………….2-7 ……………………………………………….2-8 Chapter 3 PACKAGE DIMENSIONS Chapter 4 FUNCTIONAL DESCRIPTION Program memory (ROM) ROM address register Data memory (RAM) X-register (X) Y-register (Y) Accumulator (Acc) Arithmetic and Logic Unit (ALU) State Counter (SC) Clock generator Pulse generator Reset operation Watch Dog Timer (WDT) Stop operation ……………………………………………….4-1 ……………………………………………….4-2 ……………………………………………….4-3 ……………………………………………….4-3 ……………………………………………….4-4 ……………………………………………….4-4 ……………………………………………….4-4 ……………………………………………….4-5 ……………………………………………….4-6 ……………………………………………….4-7 ……………………………………………….4-8 ………………………………………………4-10 ………………………………………………4-11 Table of Contents Chapter 5 INSTRUCTION Instruction format Instruction table Details of instruction system Chapter 6 APPLICATION Guideline for S/W GMS36112 Circuit diagram GMS37112 Circuit diagram Truth Table for example program Output waveform of uPD6121G Example program-uPD6121G Reference to GMS36XXXT B/D Reference to GMS37XXXT B/D Chapter 7 ………...………………..……………………7-1 ……………………………………………….7-1 ……………………………………………….7-2 ……………………………………………….7-3 ……………………………………………….7-4 GMS37XXXT Description Features Pin description Stop operation Electrical characteristics Chapter 9 ………………………...……………………6-1 …………………………...…………………6-2 ………………………………...……………6-3 …………………………………...…………6-4 ……………………………………...………6-5 ………………………………………...……6-6 …………………………...………………..6-12 ……………………………...……………..6-13 GMS36XXXT Description Features Pin description Stop operation Electrical characteristics Chapter 8 ………………...……………………………5-1 …………………...…………………………5-2 ……………………...………………………5-4 ………...………………..……………………8-1 ……………………………………………….8-1 ……………………………………………….8-2 ……………………………………………….8-3 ……………………………………………….8-4 EPROM Mode define ……………………………………………….9-1 Port define for GMS36XXXT ……………………………………………….9-1 Port define for GMS37XXXT ……………………………………………….9-2 AC/DC timing requirements for program / read mode ...…………….9-3 Program / verify timing diagrams in kHz version ……………....9-4 Program / verify timing diagrams in MHz version ……………….9-8 Caution when programming …..………….9-14 GMS36XXX 1 GMS37XXX 2 PACKAGE DIMENSIONS 3 FUNCTIONAL DESCRIPTION 4 INSTRUCTION 5 APPLICATION 6 GMS36XXXT 7 GMS37XXXT 8 EPROM 9 Chapter 1. GMS36XXX 1. GMS36XXX Description The GMS36XXX series are remote control transmitter which uses CMOS technology. This enables transmission code outputs of different configurations, multiple custom code output, and double push key output for easy fabrication. The GMS36XXX series are suitable for remote control of TV, VCR, FANS, Airconditioners, Audio Equipment, Toys, Games etc. Features • • • • • • • • • • • • • • • Program memory : 1,024 bytes for GMS36004/112/140 Data memory : 32 4 bits 43 types of instruction set 3 levels of subroutine nesting Operating frequency : 300kHz ~ 1MHz at kHz version 2.4MHz ~ 4MHz at MHz version Instruction cycle : fOSC/6 at kHz version fOSC/48 at MHz version CMOS process (Single 3.0V power supply) Stop mode (Through internal instruction) Released stop mode by key input (Masked option) Built in Power-on Reset circuit Built in Low Voltage Detection circuit Built in capacitor for ceramic oscillation circuit at kHZ version Built in a watch dog timer (WDT) Built in transistor for I.R LED Drive : IOL =210mA at VDD =3V and VO =0.3V Low operating voltage : 2.0 ~ 3.6V (at 300kHz ~ 4MHz) Ø Table 1-1 GMS36XXX series members Series GMS36004 GMS36112 Program memory 1,024 1,024 Data memory I/O ports 32 Ø4 32 - Ø4 4 GMS36140 1,024 32 Ø4 4 Input ports 4 4 4 Output ports 6 (D0~D5) 6 (D0~D5) 10 (D0~D9) Package 16DIP/SOP 20DIP/SOP/SSOP 24Skinny DIP/SOP 1-1 Chapter 1. GMS36XXX Block Diagram VDD GND 24 ROM 10 Ø16page Ø8bit 8 Power-on Reset Watchdog timer 3-level Stack Program counter 64word 1 Low-Voltage Detection 10 4 4 8 08; 4 Instruction Decoder 4 MUX ALU 4 4 Control Signal 2 X-Reg RAM 16word x 2page x 4bit 16 4 3 Y-Reg ST ACC 4 D-Latch Pulse Generator 4 2 10 R-Latch OSC OSC1 OSC2 RAM Word Selector 4 6 7 8 K0 ~ K3 4 9 10 4 10 11 12 13 14 R0 ~ R3 15 16 17 18 I.R. LED Drive Tr. 19 20 D0 ~ D9 Fig 1-1 Block Diagram (In case of GMS36140) 1-2 21 5 4 22 23 PGND REMOUT Chapter 1. GMS36XXX Pin Assignment GND 1 GND 1 16 VDD 20 VDD OSC1 2 15 REMOUT OSC1 2 19 REMOUT OSC2 3 14 PGND OSC2 3 K0 4 13 D5 K0 4 18 PGND 17 D5 16 D4 K1 5 12 D4 K1 5 K2 6 11 D3 K2 6 15 D3 K3 7 10 D2 K3 7 14 D2 9 D1 R0 8 13 D1 R1 9 12 D0 R2 10 11 R3 D0 8 Fig 1-2 GMS36004 Pin Assignment (16DIP/SOP) GND 1 24 VDD OSC1 2 23 REMOUT OSC2 3 22 PGND D9 4 21 D7 D8 5 20 D6 K0 6 19 D5 K1 7 18 D4 K2 8 17 D3 K3 9 16 D2 R0 10 15 D1 R1 11 14 D0 R2 12 13 R3 Fig 1-4 GMS36140 Pin Assignment (24Skinny-DIP/SOP) 1-3 Fig 1-3 GMS36112 Pin Assignment (20DIP/SOP/SSOP) Chapter 1. GMS36XXX Pin Description Pin I/O Function VDD - Connected to 2.0~ 3.6V power supply GND - Connected to 0V power supply. K0 ~ K3 Input D0 ~ D9 Output R0 ~ R3 I/O 4-bit input port with built in pull-up resistor. STOP mode is released by "L" input of each pin.(masked option) Each can be set and reset independently. The output is the structure of N-channel-open-drain. 4-bit I/O port. (Input mode is set only when each of them output "H".) In outputting, each can be set and reset independently(or at once.) The output is in the form of C-MOS. Pull-up resistor and STOP release mode can be respectively selected as masked option for each pin. (It is released by ‘’L’’ input at STOP.) Oscillator input. Input to the oscillator circuit and connection point for ceramic resonator. Internal capacitors available at kHz version. A feedback resistor is internally connected between this pin and OSC2. OSC1 Input OSC2 Output Connect a resonator between this pin and OSC1. REMOUT Output High current output port driving I.R. LED. The output is in the form of N-channel-open-drain. PGND - High current Tr. ground pin. (connected to GND) High current output Tr. is connected between this pin and REMOUT. 1-4 Chapter 1. GMS36XXX Pin Circuit Pin I/O Note I/O circuit pull-up - CMOS output. - "H" output at reset. R0 ~ R3 I/O (Option) - Built in MOS Tr for pull-up, about 140 . Ï pull-up - Built in MOS Tr for pull-up, about 140 . K0 ~ K3 I D0 ~ D9 O REMOUT O Ï - Open drain output. - "L" output at reset. REMOUT RESET - Open drain output. - Output Tr. disable at reset. DATA PGND PGND 1-5 Chapter 1. GMS36XXX Pin I/O circuit I/O Note STOP OSC2 - Built in feedbackresistor about 1 Ð Rd O OSC1 OSC2 - Built in damping-resistor [No resistor in MHz operation] (Option) - Built in resonance capacitor at kHz version OSC1 I ² Rf C2 C1 1-6 - C1=C2 = 100pF 15% [C1,C2 are not available for MHz version] Chapter 1. GMS36XXX Port Operation Value of X-reg 0 or 1 Value of Y-reg Operation SO : D(Y) RO : D(Y) 0~ 7 0 or 1 8 0 or 1 9 0 or 1 A~D 0 or 1 E 0 or 1 F 2 or 3 0 2 or 3 1 à 1 (High-Z) à0 REMOUT port repeats ‘’L’’ and ‘’H’’ in pulse frequency. (when PMR = 5, it is fixed at ‘’L’’ ) SO : REMOUT (PMR) 0 RO : REMOUT (PMR) 1 (High-Z) à à à 1 (High-Z) à0 SO : R(Y-Ah) à 1 RO : R(Y-Ah) à 0 SO : R0 ~ R3 à 1 RO : R0 ~ R3 à 0 SO : D0 ~ D9 à 1 (High-Z), R0 ~ R3 à 1 RO : D0 ~ D9 à 0, R0 ~ R3 à 0 SO : D(8) à 1 (High-Z) RO : D(8) à 0 SO : D(9) à 1 (High-Z) RO : D(9) à 0 SO : D0 ~ D9 RO : D0 ~ D9 Optional Features The GMS36XXX series offer the following optional features. Theses options are masked. • • • I/O terminals having pull-up resistor : R0 ~ R3 Input terminals having STOP release mode : K0 ~ K3, R0 ~ R3. Output form at STOP mode D0 ~ D9 : ‘’L’’ or keep before stop mode. Theses options are offered default. • • Ceramic oscillation circuit contained (or not contained) [ This option is not available for MHz Ceramic oscillator. ] Instruction cycle selection : T = 48 / fOSC or 6 / fOSC 1-7 Chapter 1. GMS36XXX Electrical Characteristics Î Absolute maximum ratings (Ta = 25 ) Parameter Symbol Max. rating Unit Supply Voltage VDD -0.3 ~ 5.0 V Power dissipation PD 700 * mW Tstg -55 ~ 125 Î VIN -0.3 ~ VDD+0.3 V VOUT -0.3 ~ VDD+0.3 V 6mW per degree Î rise in temperature. Storage temperature range Input voltage Output voltage Î: * Thermal derating above 25 Recommended operating condition Parameter Symbol Condition Rating Unit Supply Voltage VDD 300KHz ~ 4MHz 2.0 ~ 3.6 V Operating temperature Topr - -20 ~ +70 1-8 Î Chapter 1. GMS36XXX Î Electrical characteristics (Ta=25 , VDD= 3V) Parameter Limits Symbol Unit Min. Typ. Max. Condition Input H current IIH - - 1 uA VI = VDD , R having no Pull-up Input L current IIL -1 - - uA VI = GND, R having no Pull-up K Pull-up Resistance RPU1 70 140 300 R Pull-up Resistance RPU2 70 140 300 Feedback Resistance RFD 0.3 1.0 3.0 K, R Input H voltage VIH1 2.1 - - V - K, R Input L voltage VIL1 - - 0.9 V - VOL2*1 - 0.15 0.4 V IOL2 = 3mA OSC2 Output L voltage VOL3 - 0.4 0.9 V IOL3 = 40uA (kHz) , 150uA(MHz) OSC2 Output H voltage VOH3 2.1 2.5 - V IOH3= -40uA (kHz), -150uA(MHz) REMOUT Output L current IOL1*2 170 210 250 mA VOL1= 0.3V REMOUT leakage current IOLK1 - - 1 uA VOUT= VDD, Output off D, R Output leakage current IOLK2 - - 1 uA VOUT= VDD, Output off Current on STOP mode ISTP - - 1 uA At STOP mode Operating Supply current 1 IDD1*3 - 0.2 1.0 mA fOSC= 455kHz Operating Supply current 2 IDD2*3 - 0.5 1.5 mA fOSC= 4MHz fOSC/6 fOSC 300 - 1000 kHz kHz Version fOSC /48 fOSC 2.4 - 4 MHz MHz Version. D, R Output L voltage System colck frequency *1 Refer to *2 Refer to ¹ Fig.1-5 ¹ Fig.1-6 IOL2 vs. VOL2 Graph IOL1 vs. VOL1 Graph º º *3 IDD1, IDD2, is measured at RESET mode. 1-9 Ï Ï Ð VI = GND VI = GND, Output off VOSC1= GND, VOSC2= GND Chapter 1. GMS36XXX ´ ¨µ Î ª ª £ ¯Á± ª£ ¯ª± Fig 1-5. IOL2 vs. VOL2 Graph. ( D, R Port ) h ]` \[[[ nnh^Ya d[[ c[[ tzw\ l b[[ nnh^Y[ a[[ `[[ _[[ nnh]Y[ ^[[ ][[ \[[ [ [Y[ [Y_ [Yc \Y] \Ya ]Y[ ]Y_ ]Yc zw\ Fig 1-6. IOL1 vs. VOL1 Graph. ( REMOUT port) 1-10 ^Y] ^Ya _Y[ GMS36XXX 1 GMS37XXX 2 PACKAGE DIMENSIONS 3 FUNCTIONAL DESCRIPTION 4 INSTRUCTION 5 APPLICATION 6 GMS36XXXT 7 GMS37XXXT 8 EPROM 9 Chapter 2. GMS37XXX 2. GMS37XXX Description The GMS37XXX series are remote control transmitter which uses CMOS technology. This enables transmission code outputs of different configurations, multiple custom code output, and double push key output for easy fabrication. The GMS37XXX series are suitable for remote control of TV, VCR, FANS, Airconditioners, Audio Equipment, Toys, Games etc. It is possible to structure the 8 x 7 key matrix for GMS37112, and the 4 x 7 key matrix for GMS37004. Features • • • • • • • • • • • • • • Program memory : 1,024 bytes for GMS37004/112/140 Data memory : 32 4 bits 43 types of instruction set 3 levels of subroutine nesting Operating frequency : 300kHz ~ 1MHz at kHz version 2.4MHz ~ 4MHz at MHz version Instruction cycle : fOSC/6 at kHz version fOSC/48 at MHz version CMOS process (Single 3.0V power supply) Stop mode (Through internal instruction) Released stop mode by key input (Masked option) Built in Power-on Reset circuit Built in Low Voltage Detection circuit Built in capacitor for ceramic oscillation circuit at kHZ version Built in a watch dog timer (WDT) Low operating voltage : 2.0 ~ 3.6V (at 300kHz ~ 4MHz) Ø Table 2-1 GMS37XXX series members Series GMS37004 GMS37112 GMS37140 Program memory 1,024 1,024 1,024 32 32 Data memory I/O ports Ø4 - Ø4 4 32 Ø4 4 Input ports 4 4 4 Output ports 7 (D0~D6) 7 (D0~D6) 10 (D0~D9) Package 16DIP/SOP 20DIP/SOP/SSOP 24Skinny DIP/SOP 2-1 Chapter 2. GMS37XXX Block Diagram VDD GND 24 ROM 10 Ø16page Ø8bit 8 Power-on Reset Watchdog timer 3-level Stack Program counter 64word 1 Low-Voltage Detection 10 4 4 8 08; 4 Instruction Decoder 4 MUX ALU 4 4 Control Signal 2 X-Reg RAM 16word x 2page x 4bit 16 4 RAM Word Selector 4 10 ST ACC 4 D-Latch R-Latch OSC Y-Reg Pulse Generator 10 4 2 3 OSC1 OSC2 6 7 8 K0 ~ K3 4 9 4 10 11 12 13 R0 ~ R3 14 D0 15 16 D1 D2 17 D3 18 19 20 D4 D5 D6 21 5 D7 D8 4 D9 22 23 NC REMOUT * NC : No connection Fig 2-1 Block Diagram (In case of GMS37140) 2-2 Chapter 2. GMS37XXX Pin Assignment GND 1 GND 1 16 VDD 20 VDD OSC1 2 15 REMOUT OSC1 2 OSC2 3 14 D6 OSC2 3 18 D6 K0 4 13 D5 K0 4 17 D5 K1 5 12 D4 K1 5 16 D4 K2 6 11 D3 K2 6 15 D3 K3/Vpp 7 10 D2 K3/Vpp 7 14 D2 9 D1 R0 8 13 D1 R1 9 12 D0 R2 10 11 R3 D0 8 Fig 2-2 GMS37004 Pin Assignment (16DIP/SOP) GND 1 24 VDD OSC1 2 23 REMOUT OSC2 3 22 NC D9 4 21 D7 D8 5 20 D6 K0 6 19 D5 K1 7 18 D4 K2 8 17 D3 K3/Vpp 9 16 D2 R0 10 15 D1 R1 11 14 D0 R2 12 13 R3 Fig 2-4 GMS37140 Pin Assignment (24Skinny-DIP/SOP) 2-3 19 REMOUT Fig 2-3 GMS37112 Pin Assignment (20DIP/SOP/SSOP) Chapter 2. GMS37XXX Pin Description Pin I/O Function VDD - Connected to 2.0~ 3.6V power supply GND - Connected to 0V power supply. K0 ~ K3 Input D0 ~ D9 Output 4-bit input port with built in pull-up resistor. STOP mode is released by "L" input of each pin. ( masked option) Each can be set and reset independently. The output is the structure of N-channel-open-drain. 4-bit I/O port. (Input mode is set only when each of them output "H".) In outputting, each can be set and reset independently(or at once.) The output is in the form of C-MOS. Pull-up resistor and STOP release mode can be respectively selected as masked option for each pin. (It is released by "L" input at STOP) R0 ~ R3 I/O OSC1 Input OSC2 Output Connect a resonator between this pin and OSC1. REMOUT Output High current output port. The output is in the form of CMOS. The state of large current on is "H". Oscillator input. Input to the oscillator circuit and connection point for ceramic resonator. Internal capacitors available at kHz version. A feedback resistor is internally connected between this pin and OSC2. 2-4 Chapter 2. GMS37XXX Pin Circuit Pin I/O I/O circuit pull-up R0 ~ R3 I/O Note - CMOS output. - "H" output at reset. (Option) - Built in MOS Tr for pull-up, about 140 . Ï pull-up K0 ~ K3 I D0 ~ D9 O REMOUT - Built in MOS Tr for pull-up, about 140 . Ï - Open drain output. - "L" output at reset. - CMOS output. - "L" output at reset. - High current output source. O 2-5 Chapter 2. GMS37XXX Pin I/O circuit I/O Note STOP OSC2 - Built in feedbackresistor about 1 Ð Rd O OSC1 OSC2 - Built in damping-resistor [No resistor in MHz operation] (Option) - Built in resonance capacitor at kHz version OSC1 I ² Rf C2 C1 2-6 - C1=C2 = 100pF 15% [C1,C2 are not available for MHz version] Chapter 2. GMS37XXX Port operation Value of X-reg 0 or 1 Value of Y-reg Operation SO : D(Y) RO : D(Y) 0~ 7 à 1 (High-Z) à0 0 or 1 8 REMOUT port repeats ‘’H’’ and ‘’L’’ in pulse frequency. (when PMR = 5, it is fixed at ‘’H’’ ) SO : REMOUT (PMR) 1 RO : REMOUT (PMR) 0 0 or 1 9 SO : D0 ~ D9 RO : D0 ~ D9 0 or 1 A~ D 0 or 1 E 0 or 1 F 2 or 3 0 2 or 3 1 à à à 1 (High-Z) à0 SO : R(Y-Ah) à 1 RO : R(Y-Ah) à 0 SO : R0 ~ R3 à 1 RO : R0 ~ R3 à 0 SO : D0 ~ D9 à 1 (High-Z), R0 ~ R3 à 1 RO : D0 ~ D9 à 0, R0 ~ R3 à 0 SO : D(8) à 1 (High-Z) RO : D(8) à 0 SO : D(9) à 1 (High-Z) RO : D(9) à 0 Optional Features The GMS37XXX series offer the following optional features. Theses options are masked. • • • I/O terminals having pull-up resistor : R0 ~ R3 Input terminals having STOP release mode : K0 ~ K3, R0 ~ R3. Output form at STOP mode D0 ~ D9 : ‘’L’’ or keep before stop mode. Theses options are offered default. • • Ceramic oscillation circuit contained (or not contained) [ This option is not available for MHz Ceramic oscillator. ] Instruction cycle selection : T = 48 / fOSC or 6 / fOSC 2-7 Chapter 2. GMS37XXX Electrical Characteristics Î Absolute maximum ratings (Ta = 25 ) Parameter Symbol Max. rating Unit Supply Voltage VDD -0.3 ~ 5.0 V Power dissipation PD 700 * mW Tstg -55 ~ 125 Î VIN -0.3 ~ VDD+0.3 V VOUT -0.3 ~ VDD+0.3 V 6mW per degree Î rise in temperature. Storage temperature range Input voltage Output voltage Î: * Thermal derating above 25 Recommended operating condition Parameter Symbol Condition Rating Unit Supply Voltage VDD 300KHz ~ 4MHz 2.0 ~ 3.6 V Topr - -20 ~ +70 Operating temperature 2-8 Î Chapter 2. GMS37XXX Î Electrical characteristics (Ta=25 , VDD= 3V) Parameter Limits Symbol Unit Min. Typ. Max. Condition Input H current IIH - - 1 uA VI = VDD , R having no Pull-up Input L current IIL -1 - - uA VI = GND, R having no Pull-up K Pull-up Resistance RPU1 70 140 300 R Pull-up Resistance RPU2 70 140 300 Feedback Resistance RFD 0.3 1.0 3.0 K, R Input H voltage VIH1 2.1 - - V - K, R Input L voltage VIL1 - - 0.9 V - VOL2*1 - 0.15 0.4 V IOL2 = 3mA OSC2 Output L voltage VOL3 - 0.4 0.9 V IOL3 = 40uA (kHz), 150uA (MHz) OSC2 Output H voltage VOH3 2.1 2.5 - V IOH3= -40uA (kHz), -150uA (MHz) REMOUT Output L current IOL1*2 1 2.2 4 mA VOL1= 0.4V REMOUT Output H current IOH1*3 -5 -15 -30 mA VOH1= 2V D, R Output leakage current IOLK2 - - 1 uA VOUT= VDD, Output off Current on STOP mode ISTP - - 1 uA At STOP mode Operating Supply current 1 IDD1*3 - 0.2 1.0 mA fOSC= 455kHz Operating Supply current 2 IDD2*3 - 0.5 1.5 mA fOSC= 4MHz fOSC/6 fOSC 300 - 1000 kHz kHz Version fOSC /48 fOSC 2.4 - 4 MHz MHz Version. D, R Output L voltage System colck frequency ¹ Fig.2-5 ¹ Fig.2-6 *3 Refer to ¹ Fig.2-7 º º Graph º *1 Refer to IOL2 vs. VOL2 Graph *2 Refer to IOL1 vs. VOL1 Graph IOH1 vs. VOH1 *4 IDD1, IDD2, is measured at RESET mode. 2-9 Ï Ï Ð VI = GND VI = GND, Output off VOSC1= GND, VOSC2= GND Chapter 2. GMS37XXX ´ ¨µ Î ª ª £ |Á} ª£ |ª} Fig 2-5. IOL2 vs. VOL2 Graph. ( D, R Port ) h ]` c nnh^Ya b a ` nnh^Y[ _ ^ ] nnh]Y[ \ [ [Y[ [Y_ [Yc \Y] \Ya ]Y[ ]Y_ zw\ Fig 2-6. IOL1 vs VOL1 Graph 2-10 ]Yc (REMOUT Port) ^Y] ^Ya _Y[ Chapter 2. GMS37XXX h ]` [ X` nnh]Y[ tzs\ l X\[ X\` X][ nnh^Y[ X]` nnh^Ya X^[ X^` [Y[ [Y_ [Yc \Y] \Ya ]Y[ ]Y_ zs\ Fig 2-7. IOH1 vs VOH1 Graph 2-11 ]Yc (REMOUT Port) ^Y] ^Ya _Y[ GMS36XXX 1 GMS37XXX 2 PACKAGE DIMENSIONS 3 FUNCTIONAL DESCRIPTION 4 INSTRUCTION 5 APPLICATION 6 GMS36XXXT 7 GMS37XXXT 8 EPROM 9 Chapter 3. PACKAGE DIMENSIONS 3. PACKAGE DIMENSIONS The GMS36/37XXX series can be used the following package dimesions. UNIT : INCH Fig 3-1. 16PDIP (300MIL) UNIT : INCH Fig 3-2. 16SOP (150MIL) (* This type is not supported at OTP) 3-1 Chapter 3. PACKAGE DIMENSIONS UNIT : INCH Fig 3-3. 16SOP (300MIL) UNIT : INCH Fig 3-4. 20SSOP (150MIL) 3-2 Chapter 3. PACKAGE DIMENSIONS UNIT : INCH Fig 3-5. 20PDIP (300MIL) UNIT : INCH Fig 3-6. 20SOP (300MIL) 3-3 Chapter 3. PACKAGE DIMENSIONS UNIT : INCH Fig 3-7. 24Skinny-DIP (300MIL) UNIT : INCH Fig 3-8. 24SOP (300MIL) 3-4 GMS36XXX 1 GMS37XXX 2 PACKAGE DIMENSIONS 3 FUNCTIONAL DESCRIPTION 4 INSTRUCTION 5 APPLICATION 6 GMS36XXXT 7 GMS37XXXT 8 EPROM 9 Chapter 4. FUNCTIONAL DESCRIPTION 4. FUNCTIONAL DESCRIPTION Program Memory (ROM) Ø The GMS36/37XXX series can incorporate maximum 1,024 words (64 words 16 pages 8bits) for program memory. Program counter PC (A0~A5) and page address register (A6~A9) are used to address the whole area of program memory having an instruction (8bits) to be next executed. The program memory consists of 64 words on each page, and thus each page can hold up to 64 steps of instructions. The program memory is composed as shown below. Ø Program capacity (pages) 01 2 3 4 5 8 6 7 Page 0 Page 1 Page 2 Page 15 6 63 0 1 2 15 A0~A5 A6~A9 Program counter (PC) Page address register (PA) 6 4 4 Stack register (Level "1") (Level "2") (SR) (PSR) (Level "3") Fig 4-1 Configuration of Program Memory 4-1 Page buffer (PB) Chapter 4. FUNCTIONAL DESCRIPTION ROM Address Register The following registers are used to address the ROM. • Page address register (PA) : Holds ROM's page number (0 ~ Fh) to be addressed. • Page buffer register (PB) : Value of PB is loaded by an LPBI command when newly addressing a page. Then it is shifted into the PA when rightly executing a branch instruction (BR) and a subroutine call (CAL). • Program counter (PC) : Available for addressing word on each page. • Stack register (SR) : Stores returned-word address in the subroutine call mode. (1) Page address register and page buffer register : Address one of pages #0 to #15 in the ROM by the 4-bit binary counter. Unlike the program counter, the page address register is usually unchanged so that the program will repeat on the same page unless a page changing command is issued. To change the page address, take two steps such as (1) writing in the page buffer what page to jump (execution of LPBI) and (2) execution of BR or CAL, because instruction code is of eight bits so that page and word can not be specified at the same time. In case a return instruction (RTN) is executed within the subroutine that has been called in the other page, the page address will be changed at the same time. (2) Program counter : This 6-bit binary counter increments for each fetch to address a word in the currently addressed page having an instruction to be next executed. For easier programming, at turning on the power, the program counter is reset to the zero location. The PA is also set to "0". Then the program counter specifies the next ROM address in random sequence. When BR, CAL or RTN instructions are decoded, the switches on each step are turned off not to update the address. Then, for BR or CAL, address data are taken in from the instruction operands (a0 to a5), or for RTN, and address is fetched from stack register No. 1. (3) Stack register : This stack register provides two stages each for the program counter (6bits) and the page address register (4bits) so that subroutine nesting can be made on two levels. 4-2 Chapter 4. FUNCTIONAL DESCRIPTION Data Memory (RAM) Ø Ø Up to 32 nibbles (16 words 2pages 4bits) is incorporated for storing data. The whole data memory area is indirectly specified by a data pointer (X,Y). Page number is specified by zero bit of X register, and words in the page by 4 bits in Y-register. Data memory is composed in 16 nibbles/page. Figure 2-2 shows the configuration. D0 D9 R0 R3 REMOUT Data memory page (0~1) Output port 0 1 2 3 Page 0 Page 1 15 4 a0~a3 0 Y-register (Y) 1 X-register (X) Fig 4-2 Composition of Data Memory X-register (X) X-register is consist of 2bit, X0 is a data pointer of page in the RAM, X1 is only used for selecting of D8 ~ D9 with value of Y-register X1=0 X1=1 Y=0 D0 D8 Y=1 D1 D9 Table 4-1 Mapping table between X and Y register 4-3 Chapter 4. FUNCTIONAL DESCRIPTION Y-register (Y) Y-register has 4 bits. It operates as a data pointer or a general-purpose register. Y-register specifies an address (a0~a3) in a page of data memory, as well as it is used to specify an output port. Further it is used to specify a mode of carrier signal outputted from the REMOUT port. It can also be treated as a generalpurpose register on a program. Accumulator (ACC) The 4-bit register for holding data and calculation results. Arithmetic and Logic Unit (ALU) In this unit, 4bits of adder/comparator are connected in parallel as it's main components and they are combined with status latch and status logic (flag.) (1) Operation circuit (ALU) : The adder/comparator serves fundamentally for full addition and data comparison. It executes subtraction by making a complement by processing an inversed output of ACC (ACC+1) (2) Status logic : This is to bring an ST, or flag to control the flow of a program. It occurs when a specified instruction is executed in three cases such as overflow or underflow in operation and two inputs unequal. 4-4 Chapter 4. FUNCTIONAL DESCRIPTION State Counter (SC) A fundamental machine cycle timing chart is shown below. Every instruction is one byte length. Its execution time is the same. Execution of one instruction takes 6 clocks for fetch cycle and 6 clocks for execute cycle (12 clocks in total). Virtually these two cycles proceed simultaneously, and thus it is apparently completed in 6 clocks (one machine cycle). Exceptionally BR, CAL and RTN instructions is normal execution time since they change an addressing sequentially. Therefore, the next instruction is prefetched so that its execution is completed within the fetch cycle. T1 T2 T3 T4 T5 T6 T1 T2 T3 T4 T5 T6 Phase é Phase ê Phase ë Fetch cycle N Execute cycle N Execute cycle N-1 Fetch cycle N-1 Machine Cycle Machine Cycle Fig. 4-3 Fundamental timing chart 4-5 Chapter 4. FUNCTIONAL DESCRIPTION Clock Generator The GMS36/37XXX series has an internal clock oscillator. The oscillator circuit is designed to operate with an external ceramic resonator. Internal capacitors are available at kHz version. Oscillator circuit is able to organize by connecting ceramic resonator to outside. * It is necessary to connect capacitor to outside in order to change ceramic resonator, you must refer to a manufacturer`s resonator matching guide. OSC1 OSC2 2 3 C1 rx~^aZ^b\\]v _]dv _^]v _``v _c[v `[[v a_[v C2 x}ll n~m_]d{ X n~m_``p n~m_c[p n~m`[[p n~ma_[{ n| X m_^] m_`` m_c[ m`[[ ma_[ w Y n\hn]hz n\hn]hz n\hn]hz n\hn]hz n\hn]hz n\hn]hz r x~ ^aZ^b\\]x ov v z np} l w Y ^Ya_x qn} ^Ya_x~ n`S\`qT vm} X^Ya_xvp S^^qT X vm} X^Ya_x~ p S^^qT n\hn]h^^q ^Yc_x qn} ^Ya_x~ n`S\`qT vm} X^Yc_xvp S^^qT X vm} X^Yc_x~ p S^^qT n\hn]h^^q _Y[[x qn} _Y[x~ n`S\`qT vm} X_Y[[xvp S^^qT X vm} X_Y[[x~ p S^^qT n\hn]h^^q * MURATA & CQ MHz type is under matching. 4-6 Chapter 4. FUNCTIONAL DESCRIPTION Pulse Generator The following frequency and duty ratio are selected for carrier signal outputted from the REMOUT port depending on a PMR (Pulse Mode Register) value set in a program. T T1 PMR REMOUT signal 0 T=1/fPUL = 12/fOSC [96/fOSC], T1/T = 1/2 1 T=1/fPUL = 12/fOSC [96/fOSC], T1/T = 1/3 2 T=1/fPUL = 8/fOSC [64/fOSC], T1/T = 1/2 3 T=1/fPUL = 8/fOSC [64/fOSC], T1/T = 1/4 4 T=1/fPUL = 11/fOSC [88/fOSC], T1/T = 4/11 5 No Pulse (same to D0 ~ D9) 6 T=1/fPUL = 12/fOSC [96/fOSC], 7 No pulse (same to D0 ~ D9) T1/T = 1/4 * Default value is "0" * [ ] means the value of "T", when Instruction cycle is fOSC/48 in MHz version Table 4-2 PMR selection table 4-7 Chapter 4. FUNCTIONAL DESCRIPTION Reset Operation GMS36/37XXX has three reset sources. One is a built-in Power-on reset circuit, another is a built-in Low VDD Detection circuit, the other is the overflow of Watch Dog Timer. (WDT) All reset operations are internal in the GMS36/37XXX. Built-in Power On Reset Circuit Ð GMS36/37XXX has a built-in Power-on reset circuit consisting of an about 1 Resistor and a 3pF Capacitor. When the Power-on reset pulse occurs, system reset signal is latched and WDT is cleared. After the overflow time of WDT (213 x System clock time) system reset signal is released. 9'' Ð &RXQWHU :'7 6\VWHP 5(6(7% S) *1' <GMS36/37XXX> VCC System RESETB treset About 108msec at fosc = 455kHz Fig. 4-4 Power-On Reset Circuit and Timing Chart 4-8 Chapter 4. FUNCTIONAL DESCRIPTION Built-in Low VDD Detection Circuit GMS36/37XXX has a Low VDD detection circuit. If VDD become Reset Voltage of Low VDD Detection circuit at active status, system reset occur and WDT is cleared. After VDD is increased upper Reset Voltage again, WDT is re-counted and if WDT is overflowed, system reset is released. VDD Reset Voltage Internal RESETB About 108msec at fosc =455kHz Fig. 4-5 Low Voltage Detection diagram ^Y[ ]Yc ]Ya ]Y_ ]Y] ST ]Y[ w¢ o \Yc \Ya \Y_ \Y] \Y[ [Yc xY z n{ W }zx [Ya [Y_ [Y] [Y[ X][ X\[ [ \[ ][ ^[ S _[ T Fig. 4-6 Low Voltage vs Temperature 4-9 `[ a[ b[ Chapter 4. FUNCTIONAL DESCRIPTION Watch Dog Timer (WDT) Watch dog timer is organized binary of 14 steps. The signal of fOSC/6 cycle comes in the first step of WDT after WDT reset. If this counter was overflowed, reset signal automatically come out so that internal circuit is initialized. The overflow time is 6 2 13/fOSC (108.026ms at fOSC=455KHz.) 8 6 213/fOSC (108.026ms at fOSC = 3.64MHz) Normally, the binary counter must be reset before the overflow by using reset instruction (WDTR), Power-on reset pulse or Low VDD detection pulse. Ø ØØ * It is constantly reset in STOP mode. When STOP is released, counting is restarted. Binary counter(14 steps) fOSC/6 or fOSC/48 RESET (edge-trigger) Reset by instruction Power-On Reset Low VDD Detection Fig. 4-7 Block Diagram of Watch-dog Timer 4-10 CPU reset Chapter 4. FUNCTIONAL DESCRIPTION STOP Operation Stop mode can be achieved by STOP instructions. In stop mode : 1. Oscillator is stopped, the operating current is low. 2. Watch dog timer is reset, REMOUT output is disable (High-Z at GMS36XXX(T) , “L” at GMS37XXX(T)) 3. Part other than WDT and REMOUT output have a value before come into stop mode. * But the state of D0 ~ D9 output in stop mode is able to choose as masked option. "L" output or same level before come into stop mode. The Function to release stop mode is able to choose each bit of K or R input as masked option. Stop mode is released when one of K or R input is going to "L". 1. State of D0 ~ D9 output and REMOUT output is return to state of before stop mode is achieved. Ø 2. After 210 {System clock time} for stable oscillating, first instruction start to operate. 3. In return to normal operation, WDT is counted from zero again. But, at executing stop instruction, if one of K or R input is chosen to "L", stop instruction is same to NOP instruction. 4-11 GMS36XXX 1 GMS37XXX 2 PACKAGE DIMENSIONS 3 FUNCTIONAL DESCRIPTION 4 INSTRUCTION 5 APPLICATION 6 GMS36XXXT 7 GMS37XXXT 8 EPROM 9 Chapter 5. INSTRUCTION CHAPTER 5. INSTRUCTION INSTRUCTION FORMAT All of the 43 instruction in GMS36/37XXX(T) series is format in two fields of OP code and operand which consist of eight bits. The following formats are available with different types of operands. *Format é All eight bits are for OP code without operand. *Format ê Two bits are for operand and six bits for OP code. Two bits of operand are used for specifying bits of RAM and X-register (bit 1 and bit 7 are fixed at Ì0Ì) *Format ë Four bits are for operand and the others are OP code. Four bits of operand are used for specifying a constant loaded in RAM or Yregister, a comparison value of compare command, or page addressing in ROM. *Format ì Six bits are for operand and the others are OP code. Six bits of operand are used for word addressing in the ROM. 5-1 Chapter 5. INSTRUCTION INSTRUCTION TABLE The GMS36/37XXX(T) series provides the following 43 basic instructions. Category 1 2 Mnemonic LAY Register to Register LYA 3 LAZ 4 LMA 5 LMAIY 6 RAM to Register LYM 7 LAM 8 XMA 9 LYI i 10 Immediate 11 LXI n SEM n 12 13 LMIIY i RAM Bit Manipulation REM n Function àY Y à A A à 0 A àA M(X,Y) à A, Y à Y+1 Y à M(X,Y) A à M(X,Y) A ä M(X,Y) Y à i M(X,Y) à i, Y à Y+1 X à n M(n) à 1 M(n) à 0 M(X,Y) ST*1 S S S S S S S S S S S S S 14 TM n TEST M(n) = 1 E 15 BR a if ST = 1 then Branch S if ST = 1 then Subroutine call S Return from Subroutine S 16 17 ROM Address CAL a RTN 18 LPBI i 19 AM 20 SM 21 IM 22 Arithmetic DM 23 IA 24 IY 25 DA ài A à A + M(X,Y) A à M(X,Y) - A A à M(X,Y) + 1 A à M(X,Y) - 1 A à A+1 Y à Y+1 A à A-1 PB 5-2 S C B C B S C B Chapter 5. INSTRUCTION Category DY 26 27 Mnemonic Arithmetic EORM 28 NEGA 29 ALEM 30 ALEI i 31 MNEZ 32 Comparison YNEA 33 YNEI i 34 KNEZ 35 RNEZ 36 LAK 37 38 Input / Output LAR SO Function à Y-1 A à A + M (X,Y) A à A+1 TEST A õ M(X,Y) TEST A õ i TEST M(X,Y) ó 0 TEST Y ó A TEST Y ó i TEST K ó 0 TEST R ó 0 A à K A à R Outputà 0 at GMS36XXX, 1 at GMS37XXX Outputà 1 at GMS36XXX, 0 at GMS37XXX Y ST*1 B S Z E E N N N N N S S S 39 RO 40 WDTR Watch Dog Timer Reset S STOP Stop operation S 41 Control àY 42 LPY PMR 43 NOP No operation S S S Note) i = 0~f, n = 0~3, a = 6bit PC Address *1 Column ST indicates conditions for changing status. Symbols have the following meanings S : On executing an instruction, status is unconditionally set. C : Status is only set when carry or borrow has occurred in operation. B : Status is only set when borrow has not occurred in operation. E : Status is only set when equality is found in comparison. N : Status is only set when equality is not found in comparison. Z : Status is only set when the result is zero. 5-3 Chapter 5. INSTRUCTION DETAILS OF INSTRUCTION SYSTEM All 43 basic instructions of the GMS36/37XXX(T) Series are one by one described in detail below. Description Form Each instruction is headlined with its mnemonic symbol according to the instructions table given earlier. Then, for quick reference, it is described with basic items as shown below. After that, detailed comment follows. • Items : - Naming : - Status : - Format : - Operand : - Function Full spelling of mnemonic symbol Check of status function Categorized into to Omitted for Format é ì é 5-4 Chapter 5. INSTRUCTION (1) LAY Naming : Status : Format : Function : <Comment> Load Accumulator from Y-Register Set I A à Y Data of four bits in the Y-register is unconditionally transferred to the accumulator. Data in the Y-register is left unchanged. (2) LYA Naming : Status : Format : Function : <Comment> Load Y-register from Accumulator Set I Y à A Load Y-register from Accumulator (3) LAZ Naming : Status : Format : Function : <Comment> Clear Accumulator Set I A à 0 Data in the accumulator is unconditionally reset to zero. (4) LMA Naming : Status : Format : Function : <Comment> (5) LMAIY Naming : Status : Format : Function : <Comment> Load Memory from Accumulator Set I M(X,Y) à A Data of four bits from the accumulator is stored in the RAM location addressed by the X-register and Y-register. Such data is left unchanged. Load Memory from Accumulator and Increment Y-Register Set I M(X,Y) à A, Y à Y+1 Data of four bits from the accumulator is stored in the RAM location addressed by the X-register and Y-register. Such data is left unchanged. 5-5 Chapter 5. INSTRUCTION (6) LYM Naming : Status : Format : Function : <Comment> (7) LAM Naming : Status : Format : Function : <Comment> (8) XMA Naming : Status : Format : Function : <Comment> (9) LYI i Naming : Status : Format : Operand : Function : <Purpose> <Comment> Load Y-Register form Memory Set I Y à M(X,Y) Data from the RAM location addressed by the X-register and Y-register is loaded into the Y-register. Data in the memory is left unchanged. Load Accumulator from Memory Set I A à M(X,Y) Data from the RAM location addressed by the X-register and Y-register is loaded into the Y-register. Data in the memory is left unchanged. Exchanged Memory and Accumulator Set I M(X,Y) ä A Data from the memory addressed by X-register and Y-register is exchanged with data from the accumulator. For example, this instruction is useful to fetch a memory word into the accumulator for operation and store current data from the accumulator into the RAM. The accumulator can be restored by another XMA instruction. Load Y-Register from Immediate Set ë Constant 0 õ i õ 15 Y à i To load a constant in Y-register. It is typically used to specify Y-register in a particular RAM word address, to specify the address of a selected output line, to set Y-register for specifying a carrier signal outputted from OUT port, and to initialize Y-register for loop control. The accumulator can be restored by another XMA instruction. Data of four bits from operand of instruction is transferred to the Y-register. 5-6 Chapter 5. INSTRUCTION (10) LMIIY i Naming : Status : Format : Operand : Function : <Comment> (11) LXI n Naming : Status : Format : Operand : Function : <Comment> (12) SEM n Naming : Status : Format : Operand : Function : <Comment> (13) REM n Naming : Status : Format : Operand : Function : <Comment> Load Memory from Immediate and Increment Y-Register Set ë Constant 0 õ i õ 15 M(X,Y) à i, Y à Y + 1 Data of four bits from operand of instruction is stored into the RAM location addressed by the X-register and Y-register. Then data in the Y-register is incremented by one. Load X-Register from Immediate Set ê X file address 0 õ n õ 3 X à n A constant is loaded in X-register. It is used to set X-register in an index of desired RAM page. Operand of 1 bit of command is loaded in X-register. Set Memory Bit Set ê Bit address 0 õ n õ 3 M(X,Y,n) à 1 Depending on the selection in operand of operand, one of four bits is set as logic 1 in the RAM memory addressed in accordance with the data of the X-register and Y-register. Reset Memory Bit Set ê Bit address 0 õ n õ 3 M(X,Y,n) à 0 Depending on the selection in operand of operand, one of four bits is set as logic 0 in the RAM memory addressed in accordance with the data of the X-register and Y-register. 5-7 Chapter 5. INSTRUCTION (14) TM n Naming : Status : Format : Operand : Function : <Purpose> (15) BR a Naming : Status : Format : Operand : Function : <Purpose> <Comment> Test Memory Bit Comparison results to status ê Bit address 0 õ n õ 3 M(X,Y,n) à 1? ST à 1 when M(X,Y,n)=1, ST à 0 when M(X,Y,n)=0 A test is made to find if the selected memory bit is logic. 1 Status is set depending on the result. Branch on status 1 Conditional depending on the status ì Branch address a (Addr) When ST =1 , PA à PB, PC à a(Addr) When ST = 0, PC à PC + 1, ST à 1 Note : PC indicates the next address in a fixed sequence that is actually pseudo-random count. For some programs, normal sequential program execution can be change. A branch is conditionally implemented depending on the status of results obtained by executing the previous instruction. • Branch instruction is always conditional depending on the status. a. If the status is reset (logic 0), a branch instruction is not rightly executed but the next instruction of the sequence is executed. b. If the status is set (logic 1), a branch instruction is executed as follows. • Branch is available in two types - short and long. The former is for addressing in the current page and the latter for addressing in the other page. Which type of branch to exeute is decided according to the PB register. To execute a long branch, data of the PB register should in advance be modified to a desired page address through the LPBI instruction. 5-8 Chapter 5. INSTRUCTION (16) CAL a Naming : Status : Format : Operand : Function : <Comment> Subroutine Call on status 1 Conditional depending on the status ì Subroutine code address a(Addr) When ST =1 , PC à a(Addr) PA à PB SR1 à PC + 1, PSR1 à PA SR2 à SR1 PSR2 à PSR1 SR3 à SR2 PSR3 à PSR2 When ST = 0 PC à PC + 1 PB à PS ST à 1 Note : PC actually has pseudo-random count against the next instruction. • In a program, control is allowed to be transferred to a mutual subroutine. Since a call instruction preserves the return address, it is possible to call the subroutine from different locations in a program, and the subroutine can return control accurately to the address that is preserved by the use of the call return instruction (RTN). Such calling is always conditional depending on the status. a. If the status is reset, call is not executed. b. If the status is set, call is rightly executed. The subroutine stack (SR) of three levels enables a subroutine to be manipulated on three levels. Besides, a long call (to call another page) can be executed on any level. • For a long call, an LPBI instruction should be executed before the CAL. When LPBI is omitted (and when PA=PB), a short call (calling in the same page) is executed. 5-9 Chapter 5. INSTRUCTION (17) RTN Naming : Status : Format : Function : <Purpose> <Comment> (18) LPBI i Naming : Status : Format : Operand : Function : <Purpose> <Comment> (19) AM Naming : Status : Format : Function : <Comment> Return from Subroutine Set é PC à SR1 SR1 à SR2 SR2 à SR3 SR3 à SR3 PA, PB à PSR1 PSR1 à PSR2 PSR2 à PSR3 PSR3 à PSR2 à1 ST Control is returned from the called subroutine to the calling program. Control is returned to its home routine by transferring to the PC the data of the return address that has been saved in the stack register (SR1). At the same time, data of the page stack register (PSR1) is transferred to the PA and PB. Load Page Buffer Register from Immediate Set ë ROM page address 0 õ i õ 15 PB à i A new ROM page address is loaded into the page buffer register (PB). This loading is necessary for a long branch or call instruction. The PB register is loaded together with three bits from 4 bit operand. Add Accumulator to Memory and Status 1 on Carry Carry to status é A à M(X,Y)+A, ST à 1(when total>15), ST à 0 (when total õ15) Data in the memory location addressed by the X and Y-register is added to data of the accumulator. Results are stored in the accumulator. Carry data as results is transferred to status. When the total is more than 15, a carry is caused to put Ì1Ì in the status. Data in the memory is not changed. 5-10 Chapter 5. INSTRUCTION (20) SM Naming : Status : Format : Function : Subtract Accumulator to Memory and Status 1 Not Borrow Carry to status é ST à 1(when A õ M(X,Y)) ST à 0(when A > M(X,Y)) <Comment> Data of the accumulator is, through a 2`s complemental addition, subtracted from the memory word addressed by the Y-register. Results are stored in the accumulator. If data of the accumulator is less than or equal to the memory word, the status is set to indicate that a borrow is not caused. If more than the memory word, a borrow occurs to reset the status to Ì0Ì. (21) IM Naming : Status : Format : Function : A à M(X,Y) - A Increment Memory and Status 1 on Carry Carry to status é ST à 1(when M(X,Y) ö 15) ST à 0(when M(X,Y) < 15) <Comment> Data of the memory addressed by the X and Y-register is fetched. Adding 1 to this word, results are stored in the accumulator. Carry data as results is transferred to the status. When the total is more than 15, the status is set. The memory is left unchanged. (22) DM Naming : Status : Format : Function : <Comment> A à M(X,Y) + 1 Decrement Memory and Status 1 on Not Borrow Carry to status é A à M(X,Y) - 1 ST à 1(when M(X,Y) ö1) ST à 0 (when M(X,Y) = 0) Data of the memory addressed by the X and Y-register is fetched, and one is subtracted from this word (addition of Fh)> Results are stored in the accumulator. Carry data as results is transferred to the status. If the data is more than or equal to one, the status is set to indicate that no borrow is caused. The memory is left unchanged. 5-11 Chapter 5. INSTRUCTION (23) IA Naming : Status : Format : Function : <Comment> (24) IY Naming : Status : Format : Function : <Comment> (25) DA Naming : Status : Format : Function : <Comment> Increment Accumulator Set é A à A+1 Data of the accumulator is incremented by one. Results are returned to the accumulator. A carry is not allowed to have effect upon the status. Increment Y-Register and Status 1 on Carry Carry to status é Y à Y+1 ST à 1 (when Y = 15) ST à 0 (when Y < 15) Data of the Y-register is incremented by one and results are returned to the Y-register. Carry data as results is transferred to the status. When the total is more than 15, the status is set. Decrement Accumulator and Status 1 on Borrow Carry to status é A à A -1 ST à 1(when A ö1) ST à 0 (when A = 0) Data of the accumulator is decremented by one. As a result (by addition of Fh), if a borrow is caused, the status is reset to Ì0Ì by logic. If the data is more than one, no borrow occurs and thus the status is set to Ì1Ì. 5-12 Chapter 5. INSTRUCTION (26) DY Naming : Status : Format : Function : <Purpose> <Comment> (27) EORM Naming : Status : Format : Function : <Comment> (28) NEGA Naming : Status : Format : Function : <Purpose> <Comment> Decrement Y-Register and Status 1 on Not Borrow Carry to status é Y à Y -1 ST à 1 (when Y ö 1) ST à 0 (when Y = 0) Data of the Y-register is decremented by one. Data of the Y-register is decremented by one by addition of minus 1 (Fh). Carry data as results is transferred to the status. When the results is equal to 15, the status is set to indicate that no borrow has not occurred. Exclusive or Memory and Accumulator Set é A à M(X,Y) + A Data of the accumulator is, through a Exclusive OR, subtracted from the memory word addressed by X and Yregister. Results are stored into the accumulator. Negate Accumulator and Status 1 on Zero Carry to status é A à A+1 ST à 1(when A = 0) ST à 0 (when A != 0) The 2`s complement of a word in the accumulator is obtained. The 2`s complement in the accumulator is calculated by adding one to the 1`s complement in the accumulator. Results are stored into the accumulator. Carry data is transferred to the status. When data of the accumulator is zero, a carry is caused to set the status to Ì1Ì. 5-13 Chapter 5. INSTRUCTION (29) ALEM Naming : Status : Format : Function : <Comment> (30) ALEI Naming : Status : Format : Function : Accumulator Less Equal Memory Carry to status é A õ M(X,Y) ST à 1 (when A õ M(X,Y)) ST à 0 (when A > M(X,Y)) Data of the accumulator is, through a complemental addition, subtracted from data in the memory location addressed by the X and Y-register. Carry data obtained is transferred to the status. When the status is Ì1Ì, it indicates that the data of the accumulator is less than or equal to the data of the memory word. Neither of those data is not changed. Accumulator Less Equal Immediate Carry to status ë ST à 1 (when A õ i) ST à 0 (when A > i) <Purpose> Data of the accumulator and the constant are arithmetically compared. <Comment> Data of the accumulator is, through a complemental addition, subtracted from the constant that exists in 4bit operand. Carry data obtained is transferred to the status. The status is set when the accumulator value is less than or equal to the constant. Data of the accumulator is left unchanged. (31) MNEZ Naming : Status : Format : Function : <Purpose> <Comment> A õi Memory Not Equal Zero Comparison results to status é M(X,Y) ó 0 ST à 1(when M(X,Y) ó 0) ST à 0 (when M(X,Y) = 0) A memory word is compared with zero. Data in the memory addressed by the X and Y-register is logically compared with zero. Comparison data is thransferred to the status. Unless it is zero, the status is set. 5-14 Chapter 5. INSTRUCTION (32) YNEA Naming : Status : Format : Function : <Purpose> <Comment> (33) YNEI Naming : Status : Format : Operand : Function : <Comment> (34) KNEZ Naming : Status : Format : Function : <Purpose> <Comment> (35) RNEZ Naming : Status : Format : Function : <Purpose> <Comment> Y-Register Not Equal Accumulator Comparison results to status é YóA ST à 1 (when Y ó A) ST à 0 (when Y = A) Data of Y-register and accumulator are compared to check if they are not equal. Data of the Y-register and accumulator are logically compared. Results are transferred to the status. Unless they are equal, the status is set. Y-Register Not Equal Immediate Comparison results to status ë Constant 0 õ i õ 15 Yói ST à 1 (when Y ó i) ST à 0 (when Y = i) The constant of the Y-register is logically compared with 4bit operand. Results are transferred to the status. Unless the operand is equal to the constant, the status is set. K Not Equal Zero The status is set only when not equal é When K ó 0, ST à 1 A test is made to check if K is not zero. Data on K are compared with zero. Results are transferred to the status. For input data not equal to zero, the status is set. R Not Equal Zero The status is set only when not equal é When R ó 0, ST à 1 A test is made to check if R is not zero. Data on R are compared with zero. Results are transferred to the status. For input data not equal to zero, the status is set. 5-15 Chapter 5. INSTRUCTION (36) LAK Naming : Status : Format : Function : <Comment> (37) LAR Naming : Status : Format : Function : <Comment> (38) SO Naming : Status : Format : Function : <Purpose> <Comment> Load Accumulator from K Set é AàK Data on K are transferred to the accumulator Load Accumulator from R Set é AàR Data on R are transferred to the accumulator Set Output Register Latch Set é D(Y) à 1 0õYõ7 REMOUT à 0(PMR=5) Y = 8 at GMS36XXX(T) REMOUT à 1(PMR=5) Y = 8 at GMS37XXX(T) D0~D9 à 1 (High-Z) Y=9 R(Y) à 1 Ah õ Y õ Dh Rà1 Y = Eh D0~D9, R à 1 Y = Fh A single D output line is set to logic 1, if data of Y-register is between 0 to 7. Carrier frequency come out from REMOUT port, if data of Y-register is 8. All D output line is set to logic 1, if data of Y-register is 9. It is no operation, if data of Y-register between 10 to 15. When Y is between Ah and Dh, one of R output lines is set at logic 1. When Y is Eh, the output of R is set at logic 1. When Y is Fh, the output D0~D9 and R are set at logic 1. Data of Y-register is between 0 to 7, selects appropriate D output. Data of Y-register is 8, selects REMOUT port. Data of Y-register is 9, selects all D port. Data in Y-register, when between Ah and Dh, selects an appropriate R output (R0~R3). Data in Y-register, when it is Eh, selects all of R0~R3. Data in Y-register, when it is Fh, selects all of D0~D9 and R0~R3. 5-16 Chapter 5. INSTRUCTION (39) RO Naming : Status : Format : Function : <Purpose> <Comment> (40) WDTR Naming : Status : Format : Function : <Purpose> Reset Output Register Latch Set é D(Y) à 0 0õYõ7 REMOUT à 1 Y = 8 at GMS36XXX(T) REMOUT à 0 Y = 8 at GMS37XXX(T) D0~D9 à 0 Y=9 R(Y) à 0 Ah õ Y õ Dh Rà0 Y = Eh D0~D9, R à 0 Y = Fh A single D output line is set to logic 0, if data of Y-register is between 0 to 9. REMOUT port is set to logic 0, if data of Y-register is 9. All D output line is set to logic 0, if data of Y-register is 9. When Y is between Ah and Dh, one of R output lines is set at logic 0. When Y is Eh, the output of R is set at logic 0 When Y is Fh, the output D0~D9 and R are set at logic 1. Data of Y-register is between 0 to 7, selects appropriate D output. Data of Y-register is 8, selects REMOUT port. Data of Y-register is 9, selects D port. Data in Y-register, when between Ah and Dh, selects an appropriate R output (R0~R3). Data in Y-register, when it is Eh, selects all of R0~R3. Data in Y-register, when it is Fh, selects all of D0~D9 and R0~R3. Watch Dog Timer Reset Set é Reset Watch Dog Timer (WDT) Normally, you should reset this counter before overflowed counter for dc watch dog timer. this instruction controls this reset signal. 5-17 Chapter 5. INSTRUCTION (41) STOP Naming : Status : Format : Function : <Purpose> (42) LPY Naming : Status : Format : Function : <Comment> (43) NOP Naming : Status : Format : Function : STOP Set é Operate the stop function Stopped oscillator, and little current. (See 1-12 page, STOP function.) Pulse Mode Set Set é PMR à Y Selects a pulse signal outputted from REMOUT port. No Operation Set é No operation 5-18 GMS36XXX 1 GMS37XXX 2 PACKAGE DIMENSIONS 3 FUNCTIONAL DESCRIPTION 4 INSTRUCTION 5 APPLICATION 6 GMS36XXXT 7 GMS37XXXT 8 EPROM 9 Chapter 6. Application Guideline for S/W 1. All rams need to be initialized to zero in reset address for proper design. 2. Make the output ports `H` after reset. 3. Do not use WDTR instruction in subroutine. 4. Before reading the input port the waiting time should be more than 200uS. 5. To decrease current consumption, make the output port as high in normal routine except for key scan strobe and STOP mode. 6. We recommend you do not use all 64 bytes in a page. You had better write ` BR $` in unused area. This will help you prevent unusual operation of MCU. 7. Be careful not to use long call or branch (CALL,BL) with arithmetic manipulation. If you want to use branch right after arithmetic manipulation, the long call or branch will be against your intention. ex) LAR ; The value of R ports -> Accumulator A 14 : S = 0 ALEI 14 ; Aõ14 : S = 1, BL TRUE ; S is always 1 because BL is composed of LPBI and BR. -------------- Fail ! LAR ; The value of R ports -> Accumulator ALEI 14 ; Aõ14 : S = 1, A 14 : S = 0 BR TRUE ; When S is 1 Branch will occur. Otherwise Branch will not occur and LAK ; next instruction will be operated. -------------- Right ! 6-1 Chapter 6. Application *06 &LUFXLW 'LDJUDP 6-2 . 26& . 26& . *1' . 5 5 5 5 ' ' ' ' ' ' *065%;;; 9GG 5(0 287 3*1' We recommend alkaline battery Chapter 6. Application *06 &LUFXLW 'LDJUDP 6-3 . 26& . 26& . . 5 5 5 5 ' ' ' ' ' ' ' *065&;;; *1' We recommend alkaline battery 9GG 5(0 287 Chapter 6. Application 7UXWK 7DEOH IRU H[DPSOH SURJUDP CUSTOM:04H vp yzY ollSsT vp yzY ollSsT v[\ [[ v]d \n v[] [\ v^[ \o v[^ [] v^\ \p v[_ [^ v^] \q v[` [_ v^^ ][ v[a [` v^_ ]\ v[b [a v^` ]] v[c [b v^a ]^ v[d [c v^b ]_ v\[ [d v^c ]` v\\ [l v^d ]a v\] [m v_[ ]b v\^ [n v_\ ]c v\_ [o v_] ]d v\` [p v_^ ]l v\a [q v__ ]m v\b \[ v_` ]n v\c \\ v_a ]o v\d \] v_b ]p v][ \^ v_c ]q v]\ \_ v_d ^[ v]] \` v`[ ^\ v]^ \a v`\ ^] v]_ \b v`] ^^ v]` \c v`^ ^_ v]a \d v`_ ^` v]b \l v`` ^a v]c \m v`a ^b 6-4 Chapter 6. Application 2XWSXW ZDYHIRUP RI X3'* $ VLQJOH SXOVH PRGXODWHG ZLWK .+] VLJQDO DW .+] 7F &DUULHU IUHTXHQF\ I&$5 7F 'XW\ UDWLR 7 I26& 77F - Configuration of Flame 1st flame Lead code 9ms Custom code Custom code Data code Data code 4.5ms C0 C1 C2 C3 C4 C5 C6 C7 C0 C1 C2 C3 C4 C5 C6 C7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D5 D7 - Repeat code 0.56ms 9ms 2.25ms - Bit Description Bit Ì0Ì Bit Ì1Ì 0.56ms 0.56ms 1.125ms 2.25ms - Flame Interval : Tf The transmitted waveform as long as a key is depressed Tf=108mS Tf=108mS 6-5 Chapter 6. Application Example program - uPD6121G ¢ © ¡§ ¨¼½Ç ÄÆûƵÁ ½Ç ¹ÌµÁÄÀ¹ ÄÆûƵÁ ºÃÆ ¨¼¹ ºÃÆÁµÈ ½Ç ¢ ºÃÆÁµÈ ¦¡ ¢ ¬ £©¢¨ ¥© £¢ ¥© ¨ ¢ ¦§¨ ¥© ¤¨ ¥© ¢¨ ¥© £¨ ¥© £¢¨ ¥© ¨¦£ ¥© ¥© ¥© ¥© ¥© «¨ ¥© «¨ ¥© ¨ ¥© ¨ ¥© ¥© ¥© ¤ ¦§¨ ¬ ¦¡ ¦ ¡ ¢ ¦ ¢ ¦ ¨ ¤ § ¢ ¢ £ £ t ¨ t t t t t ¡ t t t t t t t t § t t t t t t t t t t t t t t t t £ t t t t t t t t t t t t t t t t t t t t t t t t t t t t t ¦ t t t t t t t t t t t t t t ¦ t t t t t t t t t t t t t t t £ t t t t t ¢ t t t t t t t t t ¢ t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t ttt ttt t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t tt§£ tt ttttttt tt¦£ tt tt¦tttttttt¨£ tt tttttt¨ tt§¨£¤ ttt tt ¬ttttttt tt ttttttt tt§£ tt ttttttt£ tt ¡ tttt tt tttttttt tt ¤ tt ttttttt£ tt¦¡ttttttt tt¦¡ttttttt¢£ tt ttttttt¢ tt ¡ttttt tt ¡ttttt tt¢tttttt tt¦tttttttt tt tttttt§ tt«¨¦ tt ttttttt¨£ tt¡¢® tt¦tttttttt tt ttttttt£ tt¨¡tttttttt¢£ tt¦tttttttt¦§ tt§¡ttttttt¢£ tt¦tttttttt§ tt ¡ tt¢tttttt tt¦tttttttt¡ % / . ¡§ tt£¦t§¨ ¹¹ ½Â £«t£¦t§¨£¤t¡£ ®¨£¢t¤£¦¨ t¤£¦¨tt£¦t¦§¢t©¦¦¢¨t£¢§©¡¤¨£¢ ©¢¨ t © ¦ ¢ ¢¨ §¨ ¨ ¨ ¦ ¢ ¨ © ¢ ¨ ¢ ¦© tt¡t§¨¦£t¤£¦¨t ¦£ ¡ t t£¢{¨t©§t«¨¦t¢t§©¦£©¨¢ ¢¨ ¢ ¢ ( < 6-6 Chapter 6. Application t t t t t t t t t t t ¦ t t t ¨ t t t ¨ t t t t t £ t t t ¦ t t t t t t t t t t ¨ t ¡ t t t ¨ t t t £ t t t £ t t t t t ¤ t t t ¢ t t t ¡ t t t ¡ t t t t t t t t t t t t t t § t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t ¢ t t t t t t t t t t t t t t t t t t t t t t t t §ª ¦§ª §ª t t t t t t t t t t ¦ t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t ¦ ¦ ttt tt ¦tttt tttt ttt tt ¦tttt ¦tttt ttt ¨¢ ¡ £¦¡ ¨¢ t t t t t t t t t t t t t t t t £¡¤¦ ¨£¡ ¨¡ t t t t t t t t t t t t t t t t t t t t £¡¤¦ ¨ ¦¦¨¢ tttttt ttttt¢£¤ tt¦ttttttttx ttttt¤tttttttt ttttt¦ttttttttx ttttt ttttttt¤£ ttttt ¡ ttttt¦£ ttttt tttttt¨ ttttt ttttt tttttt ttttt ttttttt§ ttttt ¦ ttttt tttttt ttttt ttttttt¦§ ttttt ttttttt ttttt§£ ¡ ¡ ¦ ¦¨ ¢£ ¦ § ¡ ¡ ¡ ¡ ¦¨ ¤ ¢ ¡ ¡ ¢ t¢t¦§§ §¨¦¨t¦§§ ¢¨ ¡t ª ª ¤£¢¨ §¢ §ª ¢«¨ ¢¨ §¨¦£ £©¢ ¨¡ ¦ §¡ £ © ¦ ¦ ¢ § § ¨ ¨ ¨ ¢«¨ ¨¡£ª ¡ §¢ ¢ ¦ ¢«¨ ¨£¡ 6-7 t£¦tt§¢ Chapter 6. Application t t t t t t t t t t t t t t t t t t t t t t t t t t t t tt tt tt tt t tttt t ttt t¢ttt t¦ttttt t t t t t t t t t¨ t¨£¡ t t ttttt ttttttt¨ tttttttttt tttttt¨¡£ª tttttttttt tttttttt©§¦ t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t tt tt tt tt tt tt tt tt t t t t t t t t t t t t t t t t t t £ t £ t t t t t t t t t t t t t t £ t £ t t t t t t t t t t t t t t ¤ t ¤ t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t ttt ttttttt§¨¦£ ttt¨¡tttttttt ttt¦tttttttt ££¤ ttt¢£¤ ttt¦tttttttt ££¤ ttt ttttttt¢«¨ ttt§¡ttttttt ttt ttttttt§¨¦£ ttt ¡ ttt ttttttt¢«¨ tttt ttt tttttt ttt¦tttttttt¢¨ ttt tttttt ttt¦tttttttt¢¨ ttt tttttt ttt¦tttttttt¢¨ ttt ¡ttttt tt¦tttttttt¢ª ¢ t t ¢ t t t ¢ t t t t t t t t t t t t t t t t t t t t ¨ t t ¨ t t t ¨ t t ¢ t t t t t t t t t t t t t t t t « £ t £ t ttt tttt tttt ttt tttt tttt tttt ttt tttt tttt ªtt tttt tttt tttt tttt tttt tttt tttt tttt tttt tttt tttt tttt tttt tttt tttt tttt t ¢tt tttt ¢tt tttt t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t ¦ t ¢ ¤ ttttttt£©¢¨ ¡ttttttt¦¤¨ ¦tttttttt £ ¦ ¦ ¤ t t ¡ ¦t ¡ ¢£¤ ¢£¤ ¦t ¡ ¢£¤ ttt ¡ ¦t ¦t ¦t ¦t ¦t ¦t ¦t t tt tt t tt t t t t t t t t t t t t ttttx ttt tttx t t t t t t t t t t¨¡ t¢ª t ttttttt¢ª ttttt ttttttttt ttttttt¢¨ tt t tt t tt t tt t tt t tt t tt t tt tt t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t¡ « £¢tttttt « £ « £ £ ¢tttttt ¢tttttt ¢ªtttttt ¢ tttttt¨¡ tttttt¨¡ 6-8 Chapter 6. Application t t t t t t t t t t t t t t t t t t t t t t t t t t t t t £ t £ t t t t t t t t t © t t t t © t t t t t t t t t t t t t t © t ¢ t ¢ t t t t t t t t t § t t t t § t t t t t t t t t t t t t t t ª t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t ¦ t t t t t t t t t t t t t t t t t t tt t t t t t t t £ t t t t t t t t t t t t t t £ t t t t t t t t ¡ t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t tt¢£¤ tt¦tt tt¤tt tt¦tt tt t tt ¡ tt ¡ tt ¡ tt ¡ tt t tt tt t tt§£tt tt t tt tt tt t tt¦£tt tt t tt tt tt t tt¨¡tt tt¦tt tt t tt t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t x x t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t ¨ ¤ ¨ t t t t t t t t t t t ¢£¤ ttttttt¢«¨ ¡ ¡ tttttttt£©¢ t t t t ¡ t tt ttttttt tttttttttt tttttttttt tt tttttttttt tttttttttt«¨ tttttttttt tttttttttt tttttttttt tttttttttt t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t ¡ ¡ t t t tt t tt tt tt t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t ¢ t ¨ t «¨ ¦tttttttt¢«¨ tttttttttt ¡ ¡ ttttttttttt¦£ ¨ ¦ ¡ ¡ £©¢¨ ¤¨ ¡ tttttt¤ ttttttt ttttttt tttt ttttttt ¦ ttttttt ttttttt tttttt¨ ttttttt tt tt tt¦tt tt¦¨¢ ttt tt tt tt tt tt ® tt¬¡ tt¢® tt¦¢® tt ¡ tt¢£¤ t t tt¦tt tt¤tt ¡ £¢¨ ¬ © § ¡ ¡ ¡ ¡ ¡ ¡ tttttt¨¡ tttttt ¡ ©¢©§t¢§¨¦©¨£¢t§t«¦¨¨¢t¢t t t t t t t t t t t t t ¢t¦ x 6-9 Chapter 6. Application t ¤ ¤ t t t t © © t t t tt § § tt tt tt t t t t t t t t t t t t t t t ttt ttt ttt ttt§ ttt ttt¦ tt tttttttttt tttttttttt ¦ttttttttx tttttt¨¡ ttttttt £ tttttt¨¡ £ ttttttt¤£¢¨ ¡ tttttttt¨¡ £©¨tttt tttttt¨¡ tttttttttt tttttttt¨¡ ¨ t t t t t t t t t t t t t t t t ¬ t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt t t t t t t t t t t t t t t t t t ¨ ¨ ¨ ¨ t t t t t t t t t t t ¶ ¶ t t t t t ¢ t t t t t t t t t t t µ µ t £ t t t t t t t t t t ¨ t t t t t t t t t t t t ¬ t t t t t t t t t t t t t t t t t t t t t t ¦ t t t t t t t t t t t t t t t t t t t t ¨ t t t t tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt t t t t t t t t t t t t t t t t t t t t t «¨ §¡ t t ·µÀ ½Á ¹» ¡ ¦¨¢ t t t t t t ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ t t t t t t ¡ ¡ t t t t t t ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ttt tt ttt ttt ttt ttt ttt ttt ttt ttt ttt ttt ttt ttt ttt ttt t t t t t t t t t t t t t t t t ¦ tt ¢£ ¦ ¤ ¦ ¢£ ¢£ ¢£ ¢£ ¢£ ¢£ ¢£ ¢£ t t t t t Æ Æ t ¡ t t t t t ¤ t t t t £ £ t t t t t t t t t t t t t t t t t t ª ª t t t t t t t t t t t t t t t t t t t t ¡ ¡ ¡ ¡ ¡ ¡ ¦ tt ttt tt tt ttt tt tt ttt tt tt ttt tt tt t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t¤ t t t¤ t t t¤ t t t¤ t t t¤ © § £©¨ © § £©¨ © § £©¨ © § £©¨ £¢¨ tttttt tttttttt¨¬ tt ¦ tt tt tt t t tt t t t tt ttttt¤© t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t¦ t t t¨ t t t t¨ t § £©¢¨ ¤¨ ¡ ¡ ¡ ¡ ¡ ttttttt¶µÆ µ ttttttt¨¡£ª ¡ tttttttt£¡¤¦¨ ¤ t t t ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ tt tt tt t t t t t t t t t t t t tx t tx 6-10 Chapter 6. Application ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¨ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¨¡ ¨¡ ¨¡ ¨¡ ¨¡ ¨¡ ¨¡ ¨¡ ¨¡ ¨¡ ¨¡ ¨¡ ¨¡ ¨¡ ¨¡ ¨¡ ¨¡ ¨¡ ¨¡ t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt tt t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ £ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¢£¤ ¢£¤ ¢£¤ ¢£¤ ¢£¤ ¢£¤ ¢£¤ ¢£¤ ¢£¤ ¢£¤ ¢£¤ ¢£¤ ¢£¤ ¢£¤ ¢£¤ ¢£¤ ¢£¤ ¢£¤ ¦¨¢ 6-11 Chapter 6. Application 5HIHUHQFH WR *06;;;7 %' $WWDFK UHVRQDWRU WR ; &RQQHFW EDVH DQG FROOHFWRU DW 4 &RQQHFW 3*1' DQG 75*1' ZLWK MXPSHU DW ( & % ( 4 '6 % $ ....5555 ....5555 . . & 5 5 5 '6 '''' '''' ; ( ' 3*1' 75*1' 5(0287 75287 26& ' *1' 6:a 6:a '''' '''' . . 5 5 5 5 ' ' ' ' ' ' '6 LV FRQQHFWHG WR $ ,I ' VZLWFK LV RQ DPRQJ '6 $ EHFRPHV ' SRUW '6 LV FRQQHFWHG WR % ,I ' VZLWFK LV RQ DPRQJ '6 % EHFRPHV ' SRUW ,I ' VZLWFK DPRQJ 6:a6: LV RQ DW ' WKH NH\ a FDQ EH XVHG DV ' SRUW ,I ' VZLWFK DPRQJ 6:a6: LV RQ DW ' WKH NH\ a FDQ EH XVHG DV ' SRUW QRWH WKH SRVLWLRQ RI 6:a DQG 6:a LQ %' LV FKDQJHG 7KH UHIHUHQFH SRVLWLRQ LV ULJKW ,I \RX ZDQW WR LQFUHDVH WKH UHPRWH FRQWUROOHU YDOLG GLVWDQFH \RX WU\ WR GLVFRQQHFW 5 UHVLVWRU DQG OHVVHQ 5 UHVLVWRU 6-12 Chapter 6. Application 5HIHUHQFH WR *06;;;7 %' $WWDFK UHVRQDWRU WR ; $WWDFK $ WUDQVLVWRU WR 4 &RQQHFW 3*1' DQG ' ZLWK MXPSHU DW ( UHPDLQ ' RSHQ VWDWH LQ FDVH RI *067 $WWDFK DERXW . WR 5 & % ( 4 '6 % $ ....5555 ....5555 . . & 5 5 5 '6 '''' '''' ; ( ' 3*1' 75*1' 5(0287 75287 26& ' *1' 6:a 6:a '''' '''' . . 5 5 5 5 ' ' ' ' ' ' '6 LV FRQQHFWHG WR $ ,I ' VZLWFK LV RQ DPRQJ '6 $ EHFRPHV ' SRUW '6 LV FRQQHFWHG WR % ,I ' VZLWFK LV RQ DPRQJ '6 % EHFRPHV ' SRUW ,I ' VZLWFK DPRQJ 6:a6: LV RQ DW ' WKH NH\ a FDQ EH XVHG DV ' SRUW ,I ' VZLWFK DPRQJ 6:a6: LV RQ DW ' WKH NH\ a FDQ EH XVHG DV ' SRUW QRWH WKH SRVLWLRQ RI 6:a DQG 6:a LQ %' LV FKDQJHG 7KH UHIHUHQFH SRVLWLRQ LV ULJKW ,I \RX ZDQW WR LQFUHDVH WKH UHPRWH FRQWUROOHU YDOLG GLVWDQFH \RX WU\ WR GLVFRQQHFW 5 UHVLVWRU DQG OHVVHQ 5 UHVLVWRU 6-13 GMS36XXX 1 GMS37XXX 2 PACKAGE DIMENSIONS 3 FUNCTIONAL DESCRIPTION 4 INSTRUCTION 5 APPLICATION 6 GMS36XXXT 7 GMS37XXXT 8 EPROM 9 Chapter 7.GMS36XXXT CHAPTER 7. GMS36XXXT Description The GMS36XXXT series are remote control transmitter which uses CMOS technology and the EPROM version. This enables transmission code outputs of different configurations, multiple custom code output and double push key output for easy fabrication. The GMS36XXXT series are suitable for remote control of TV, VCR, FANS, Air-conditioners, Audio Equipment, Toys, Games etc. Features • • • • • • • • • • • • • • • Program memory : 1,024 bytes for GMS36/004T/112T/140T Data memory : 32 4 bits 43 types of instruction set 3 levels of subroutine nesting Operating frequency : 300kHz ~ 1MHz at kHz version 2.4MHz ~ 4MHz at MHz version Instruction cycle : fOSC/6 at kHz version fOSC/48 at MHz version CMOS process (Single 3.0V power supply) Stop mode (Through internal instruction) Released stop mode by key input Built in Power-on Reset circuit Built in Low Voltage Detection circuit Built in capacitor for ceramic oscillation circuit at kHz version Built in a watch dog timer (WDT) Built in transistor for I.R LED Drive : IOL =190mA at VDD =3V and VO =0.3V Low operating voltage : 2.2 ~ 3.6V (at 300kHz ~ 4MHz) Ø Table 7-1 GMS36XXXT series members Series GMS36004T GMS36112T Program memory 1,024 1,024 1,024 32 32 32 Data memory I/O ports Ø4 - Ø4 4 GMS36140T Ø4 4 Input ports 4 4 4 Output ports 6 (D0~D5) 6 (D0~D5) 10 (D0~D9) Package 16DIP/SOP 20DIP/SOP/SSOP 24Skinny DIP/SOP 7-1 Chapter 7. GMS36XXXT Pin Description Pin I/O Function VDD - Connected to 2.2~ 3.6V power supply GND - Connected to 0V power supply. K0 ~ K3 Input D0 ~ D9 Output R0 ~ R3 I/O 4-bit input port with built in pull-up resistor. STOP mode is released by "L" input of each pin. Especially, K3 is the input pin for VPP. For programming K3 pin receives 12.5V(programming voltage). Each can be set and reset independently. The output is the structure of N-channel-open-drain. 4-bit I/O port. (Input mode is set only when each of them output "H".) In outputting, each can be set and reset independently(or at once.) The output is in the form of C-MOS. STOP mode is released by "L" input of each pin. Oscillator input. Input to the oscillator circuit and connection point for ceramic resonator. Internal capacitors available at kHz version. A feedback resistor is internally connected between this pin and OSC2. OSC1 Input OSC2 Output Connect a resonator between this pin and OSC1. REMOUT Output High current output port driving I.R. LED. The output is in the form of N-channel-open-drain. PGND - High current Tr. ground pin. (connected to GND) High current output Tr. is connected between this pin and REMOUT. 7-2 Chapter 7. GMS36XXXT STOP Operation Stop mode can be achieved by STOP instructions. In stop mode : 1. Oscillator is stopped, the operating current is low. 2. Watch dog timer is reset, D0~D3 output is "L"and REMOUT output is "H" (Output Tr. is off.) 3. Part other than WDT, D0~D3 output and REMOUT output have a value before come into stop mode. Stop mode is released when one of K or R input is going to "L". 1. State of D0~D3 output and REMOUT output is return to state of before stop mode is achieved. Ø 2. After 210 System clock time for stable oscillating, first instruction start to operate. 3. In return to normal operation, WDT is counted from zero again. But, at executing stop instruction, if one of K or R input is chosen to "L", stop instruction is same to NOP instruction. 7-3 Chapter 7. GMS36XXXT Electrical Characteristics Î Absolute maximum ratings (Ta = 25 ) Parameter Symbol Max. rating Unit Supply Voltage VDD -0.3 ~ 5.0 V Programming Voltage VPP -0.3 ~ 13.5 V Power dissipation PD 700 * mW Tstg -55 ~ 125 Î VIN -0.3 ~ V DD+0.3 V VOUT -0.3 ~ V DD+0.3 V Storage temperature range Input voltage Output voltage * Thermal derating above 25 Î: 6mW per degree Î rise in temperature. Recommended operating condition Parameter Symbol Condition Rating Unit Supply Voltage VDD 300kHz ~ 4MHz 2.2 ~ 3.6 V Operating temperature Topr - 7-4 -20 ~ +70 Î Chapter 7. GMS36XXXT Î Electrical characteristics (Ta=25 , VDD= 3V) Limits Parameter Symbol Unit Min. Typ. Max. IIH - - 1 K Pull-up Resistance RPU1 70 140 300 R Pull-up Resistance RPU2 70 140 300 Feedback Resistance RFD 0.3 1.0 3.0 K, R input H voltage VIH1 2.1 - K, R input L voltage VIL1 - D. R output L voltage VOL2 *1 - Input H current uA Condition VI=VDD Ï Ï Ð VI=GND, Output off - V - - 0.9 V - 0.15 0.4 V IOL2=3mA V IOL3=40uA (455kHz) = 150uA (4MHz) IOH3= -40uA (455kHz) = -150uA (4MHz) VI=GND VOSC1=GND, VOSC2=VDD OSC2 output L voltage VOL3 - 0.4 OSC2 output H voltage VOH3 2.1 2.5 150 190 230 mA VOL1=0.3V 200 250 300 mA VOL1=0.4V REMOUT output L current 0.9 - V IOL1*2 REMOUT leakage current IOLK1 - - 1 uA VOUT=VDD, Output off D, R output leakage current IOLK2 - - 1 uA VOUT=VDD, Output off ISTP - - 1 uA At STOP mode Operating supply current 1 IDD1 *3 - 0.8 1.5 mA fOSC=455KHz Operating supply current 2 IDD2 *3 - 1.0 3.0 mA fOSC=4MHz fOSC/6 fOSC 300 - 1000 kHz kHz version fOSC/48 fOSC 2.4 - 4 MHz MHz version Current on STOP mode System clock frequency ¹ Fig.7-1 *2 Refer to ¹ Fig.7-2 *1 Refer to º Graph º IOL2 vs. VOL2 Graph IOL1 vs. VOL1 *3 IDD1, IDD2, is measured at RESET mode. 7-5 Chapter 7. GMS36XXXT ´ ¨µ Î ª ª £ ¯Á± ª£ ¯ª± Fig 7-1. IOL2 vs. VOL2 Graph. ( D, R Port ) Î ¨µ ª ª ª ª ¯Á± £ ª ª ª£ ¯ª± Fig 7-2. IOL1 vs. VOL1 Graph. ( REMOUT port) 7-6 Chapter 7. GMS36XXXT /RZ 9ROWDJH 9 7HPSHUDWXUH Fig 7-3. Low Voltage vs Temperature 7-7 GMS36XXX 1 GMS37XXX 2 PACKAGE DIMENSIONS 3 FUNCTIONAL DESCRIPTION 4 INSTRUCTION 5 APPLICATION 6 GMS36XXXT 7 GMS37XXXT 8 EPROM 9 Chapter 8. GMS37XXXT CHAPTER 8. GMS37XXXT Description The GMS37XXXT series are remote control transmitter which uses CMOS technology and the EPROM version. This enables transmission code outputs of different configurations, multiple custom code output, and double push key output for easy fabrication. The GMS37XXXT series are suitable for remote control of TV, VCR, FANS, Airconditioners, Audio Equipment, Toys, Games etc. It is possible to structure the 8 x 7 key matrix for GMS37112T, and the 4 x 7 key matrix for GMS37004T. Features • • • • • • • • • • • • • • Program memory : 1,024 bytes for GMS37004T/112T/140T Data memory : 32 4 bits 43 types of instruction set 3 levels of subroutine nesting Operating frequency : 300kHz ~ 1MHz at kHz version 2.4MHz ~ 4MHz at MHz version Instruction cycle : fOSC/6 at kHz version fOSC/48 at MHz version CMOS process (Single 3.0V power supply) Stop mode (Through internal instruction) Released stop mode by key input Built in Power-on Reset circuit Built in Low Voltage Detection circuit Built in capacitor for ceramic oscillation circuit at kHz version Built in a watch dog timer (WDT) Low operating voltage : 2.2 ~ 3.6V (at 300kHz ~ 4MHz) Ø Table 8-1 GMS37XXXT series members Series GMS37004T GMS37112T Program memory 1,024 1,024 1,024 32 32 32 Data memory I/O ports Ø4 - Ø4 4 GMS37140T Ø4 4 Input ports 4 4 4 Output ports 7 (D0~D6) 7 (D0~D6) 10 (D0~D9) Package 16DIP/SOP 20DIP/SOP/SSOP 24Skinny DIP/SOP 8-1 Chapter 8. GMS37XXXT Pin Description Pin I/O Function VDD - Connected to 2.2~ 3.6V power supply GND - Connected to 0V power supply. K0 ~ K3 Input D0 ~ D9 Output R0 ~ R3 I/O 4-bit input port with built in pull-up resistor. STOP mode is released by "L" input of each pin. Especially, K3 is the input pin for VPP. For programming K3 pin receives 12.5V(programming voltage). Each can be set and reset independently. The output is the structure of N-channel-open-drain. 4-bit I/O port. (Input mode is set only when each of them output "H".) In outputting, each can be set and reset independently(or at once.) The output is in the form of C-MOS. STOP mode is released by "L" input of each pin. Oscillator input. Input to the oscillator circuit and connection point for ceramic resonator. Internal capacitors available at kHz version. A feedback resistor is internally connected between this pin and OSC2. OSC1 Input OSC2 Output Connect a resonator between this pin and OSC1. REMOUT Output High current output port The output is in the form of C-MOS. The state of large current on is “ H “ 8-2 Chapter 8. GMS37XXXT STOP Operation Stop mode can be achieved by STOP instructions. In stop mode : 1. Oscillator is stopped, the operating current is low. 2. Watch dog timer is reset, D0~D3 output is "L"and REMOUT output is ”L" 3. Part other than WDT, D0~D3 output and REMOUT output have a value before come into stop mode. Stop mode is released when one of K or R input is going to "L". 1. State of D0~D3 output and REMOUT output is return to state of before stop mode is achieved. Ø 2. After 210 System clock time for stable oscillating, first instruction start to operate. 3. In return to normal operation, WDT is counted from zero again. But, at executing stop instruction, if one of K or R input is chosen to "L", stop instruction is same to NOP instruction. 8-3 Chapter 8. GMS37XXXT Electrical Characteristics Î Absolute maximum ratings (Ta = 25 ) Parameter Symbol Max. rating Unit Supply Voltage VDD -0.3 ~ 5.0 V Programming Voltage VPP -0.3 ~ 13.5 V Power dissipation PD 700 * mW Tstg -55 ~ 125 Î VIN -0.3 ~ V DD+0.3 V VOUT -0.3 ~ V DD+0.3 V Storage temperature range Input voltage Output voltage * Thermal derating above 25 Î: 6mW per degree Î rise in temperature. Recommended operating condition Parameter Symbol Condition Rating Unit Supply Voltage VDD 300kHz ~ 4MHz 2.2 ~ 3.6 V Operating temperature Topr - 8-4 -20 ~ +70 Î Chapter 8. GMS37XXXT Î Electrical characteristics (Ta=25 , VDD= 3V) Limits Parameter Symbol Unit Min. Typ. Max. IIH - - 1 K Pull-up Resistance RPU1 70 140 300 R Pull-up Resistance RPU2 70 140 300 Feedback Resistance RFD 0.3 1.0 3.0 K, R input H voltage VIH1 2.1 - K, R input L voltage VIL1 - Input H current D. R output L voltage VOL2 *1 uA Condition VI=VDD Ï Ï Ð VI=GND, Output off - V - - 0.9 V - - 0.15 0.4 V IOL2=3mA IOL3=40uA (455kHz) =150uA (4MHz) IOH3= -40uA (455kHz) = -150uA (4Mhz) VI=GND VOSC1=GND, VOSC2=VDD OSC2 output L voltage VOL3 - 0.4 0.9 V OSC2 output H voltage VOH3 2.1 2.5 - V IOL1 *2 1 2.2 4 mA VOL1=0.4V *3 -5 -15 -30 mA VOH1=2V REMOUT output L current REMOUT output H current IOH1 D, R output leakage current IOLK2 - - 1 uA VOUT=VDD, Output off Current on STOP mode ISTP - - 1 uA At STOP mode Operating supply current 1 IDD1 *4 - 0.8 1.5 mA fOSC=455KHz Operating supply current 2 IDD2 *4 - 1.0 3.0 mA fOSC=4MHz fOSC/6 fOSC 300 - 1000 kHz kHz version fOSC/48 fOSC 2.4 - 4 MHz MHz version System clock frequency *1 Refer to Fig.8-1 < IOL2 vs. VOL2 Graph> *2 Refer to Fig.8-2 < IOL1 vs. VOL1 Graph> *3 Refer to Fig.8-3 < IOH1 vs. VOH1 Graph> *4 IDD1, IDD2, is measured at RESET mode. 8-5 Chapter 8. GMS37XXXT ´ ¨µ Î ª ª £ |Á} ª£ |ª} Fig 8-1. IOL2 vs. VOL2 Graph. ( D, R, OD6 Port ) ¨µ Î ª ª £ |Á} ª ª ª ª ª£ Fig 8-2. IOL1 vs VOL1 Graph 8-6 |ª} (REMOUT Port) Chapter 8. GMS37XXXT ¨µ Î |Á} £ ª ª ª ª ª ª ª£ Fig 8-3. IOH1 vs VOH1 Graph |ª} (REMOUT Port) /RZ 9ROWDJH 9 7HPSHUDWXUH Fig 8-4. Low Voltage vs Temperature 8-7 GMS36XXX 1 GMS37XXX 2 PACKAGE DIMENSIONS 3 FUNCTIONAL DESCRIPTION 4 INSTRUCTION 5 APPLICATION 6 GMS36XXXT 7 GMS37XXXT 8 EPROM 9 Chapter 9. EPROM CHAPTER 9. EPROM MODE Define Item Device operation User mode Exact User pgm EPROM read mode Address in, Data out 1Byte PGM Write & Verify Address in, Data in Data out Mode setting K3~ K0 = 0 ~ 3V Vcc=3V K1~0=01/10 Vcc=5.5V K1~0=01/10 Vcc=5.5V K3 =12.5V K2 = Vcc Lock bit Write mode Lock bit write K1~0=01/00 Lock bit Read mode Lock bit out (to D5 port) K1~0=01/01 Reset mode System reset before all test K2 = 0V Vcc=5.5V, (Default : unlock) - - * Mode setting (K1~0=01/10) means the serial input by 2bits. Port Define for GMS36XXXT 8VHU 0RGH (SURP 0RGH *1' &ORFN 00 00 5HVHW 933 &ORFN 00 5HVHW 933 *1' &ORFN 9'' 5(0287 26& 3*1' ' ' ' ' . 3,1 ' . *067 ' . ' . ' 5 ' 5 ' 5 5 00 5HVHW 933 'D'D $G$G *1' 9'' 26& 5(0287 26& 3*1' . ' . 3,1 ' . *067 ' . ' 5 ' 5 ' 5 5 00 *1' 00 26& *1' 8VHU 0RGH *1' 9'' 26& 5(0287 26& 3*1' . . 3,1 ' *067 ' . . ' ' ' ' (SURP 0RGH 3RUW 1DPH 9'' 9''*1' /RFN GDWD RXW $G$G $G$G 'D'D $G$G 'D'D $G$G 'D'D $G$G 'D'D 9'' 3*1' 26& 8VHU 0RGH (3520 0RGH 3RZHU 3RZHU 3JQG 9 &ORFN &ORFN 5HPRXW 5HPRXW . . ,QSXW 0RGH VHWWLQJ . . ,QSXW $GGUHVV 'DWD &RQWURO . . ,QSXW 5HVHW 5HDG :ULWH &RQWURO 933 9 . . ,QSXW ' ' 2XWSXW $G $G 'D 'D ' ' 2XWSXW $G $G 'D 'D ' ' 2XWSXW $G $G 'D 'D ' ' 2XWSXW $G $G 'D 'D ' ' 2XWSXW $G $G ' ' 2XWSXW /RFN GDWD RXWSXW ' ' 2XWSXW ' ' 2XWSXW ' ' 2XWSXW ' ' 2XWSXW 5 5 ,2 5 5 ,2 5 5 ,2 5 5 ,2 /RFN GDWD RXW $G$G $G$G 'D'D $G$G 'D'D $G$G 'D'D $G$G 'D'D 9'' /RFN GDWD RXW $G$G $G$G 'D'D $G$G 'D'D $G$G 'D'D 9-1 Chapter 9. EPROM Port Define for GMS37XXXT 8VHU 0RGH (SURP 0RGH *1' &ORFN 00 00 5HVHW 933 &ORFN 9'' 5(0287 26& 1& ' ' ' ' . 3,1 ' . *067 ' . ' . ' 5 ' 5 ' 5 5 00 5HVHW 933 *1' &ORFN 00 00 5HVHW 933 'D'D $G$G *1' 9'' 26& 5(0287 26& ' . ' . 3,1 ' . *067 ' . ' 5 ' 5 ' 5 5 *1' 9'' 5(0287 ' . 3,1 ' . *067 ' ' ' ' ' $G$G 'D'D $G$G 'D'D $G$G 'D'D $G$G 'D'D 9'' /RFN GDWD RXW $G$G 8VHU 0RGH (3520 0RGH 9''*1' 3RZHU 3RZHU 26& &ORFN . . ,QSXW 0RGH VHWWLQJ . . ,QSXW $GGUHVV 'DWD &RQWURO . . ,QSXW 5HVHW . . ,QSXW 933 9 ' ' 2XWSXW $G $G 'D 'D ' ' 2XWSXW $G $G 'D 'D ' ' 2XWSXW $G $G 'D 'D ' ' 2XWSXW $G $G 'D 'D ' ' 2XWSXW $G $G ' ' 2XWSXW /RFN GDWD RXWSXW ' ' 2XWSXW ' ' 2XWSXW ' ' 2XWSXW &ORFN 5HDG :ULWH &RQWURO $G$G 'D'D $G$G 'D'D $G$G 'D'D $G$G 'D'D $G$G . /RFN GDWD RXW 3RUW 1DPH 26& . 9'' 26& (SURP 0RGH *1' 00 26& *1' 8VHU 0RGH 9'' /RFN GDWD RXW ' ' 2XWSXW 1& 5HPRXW 5HPRXW 5 5 ,2 5 5 ,2 5 5 ,2 5 5 ,2 $G$G $G$G 'D'D $G$G 'D'D $G$G 'D'D 9-2 Chapter 9. EPROM Î) AC / DC Timing Requirements for Program / Read Mode (Ta = 25 1D PH 6\ PER O 26& &OR FN 3HULRG 7S 1Í 8QLWV 0LQ 7\ S 0D[ XV D W .+= 9H UVLRQ QV D W 0+= 9H UVLR Q 3UR JUD PPLQJ 6XSSO\ &XUUH QW ,933 P$ 6XSSO\ &XUUHQW LQ (3520 0RGH ,9''3 P$ 933 /H Y HO GXULQJ 3UR JUD PPLQJ 9,+3 9 9'' /H Y H O LQ 3UR JUD P 0R GH 9''+ 9 9'' /H Y H O LQ 5HD G 0R GH 9''+ 9 . a . +LJK /HY H O LQ (3520 0R GH 9,+. 9 9'' [ . a . /R Z /H Y HO LQ (3520 0R GH 9,/. 9 9'' [ 'a' +LJK /H YH O LQ (3520 0RGH 9,+' 9 9'' [ 'a' +LJK /H YH O LQ (3520 0RGH 9,/' 9 9'' [ 9'' 6WXUD WLRQ 7LPH 79''6 PV 933 6H WXS 7LPH 79335 PV 933 6D WXUD WLR Q 7LPH 79336 PV . ,QSXW 'H OD \ WLPH 7.' QV 7S 7S 7S . ,QSXW 6H WXS WLPH 7.6 QV 7S 7S 7S .a. 0RGH LQSXW 6H WXS WLPH 702'( XV 7S [ 7S [ 7S [ 'a' 'D WD LQSXW +ROG 7LPH 7+/' XV 7S .a. 'D WD LQSXW 6H WXS 7LPH 7'/< QV 7S [ 7S [ 7S [ 'a' 'D WD LQSXW 6H WXS 7LPH 7'/< QV 7S [ 7S [ 7S [ 'a' 2XWSXW 6WUR ELQJ 7LPH 767% QV 7S [ 7S [ 7S [ ' 2XWSXW 6WUR ELQJ 7LPH 767% XV 7S [ 7S [ 7S [ 9-3 6\ VWH P UH VH W v $W /R FN 5H D G 2QO\ Chapter 9. EPROM Program / Verify Timing Diagrams In kHz Version. 1) EPROM Write & Verify Mode (1Byte) 73 26& 9''+ 9'' 79336 .933 79335 9,+3 7.6 9''+ . 702'( 7.' 0+ .a. 7'/< 0/ 7'/< 'a' 5HVHW $+ $/ '+ '/ (SURP :ULWH 0RGH VHWWLQJ 2+ WLPHV UHSHDW 7+/' XV [ XV 767% 2/ $+ $/ '+ '/ 7+/' $GGU $GGU $+ +LJK ELW $GGUHVV ,QSXW /DWFK '+ +LJK ELW 'DWD ,QSXW /DWFK 2+ +LJK ELW 'DWD 2XWSXW $/ /RZ ELW $GGUHVV ,QSXW /DWFK '/ /RZ ELW 'DWD ,QSXW /DWFK 2/ /RZ ELW 'DWD 2XWSXW 0+ +LJK ELW 0 RGH , QSXW /DWFK 0/ /RZ ELW 0RGH ,QSXW /DWFK #. Note : 1. Internal system is reset at VPP = 12.5V and K2=`Low` 2. The reset release (K2=`High`) must be set within OSC1 = `Low` state. (From this time, OSC1 clock is counted.) 3. The Data will be inputted from the 19th rising edge of OSC1. 4. If not written during 10 times repeats (120us), repeat the 5 times until all is written. 5. For device verify. If you set Lock bit, output data is always `0F`h. 9-4 Chapter 9. EPROM 2) EPROM Read Mode (1Byte) 73 26& 9''+ 9'' 79336 .933 79335 9,+3 7.6 9''+ . 702'( 7.' 0+ .a. 7'/< 0/ 7'/< 'a' 5HVHW $+ $/ (SURP 5HDG 0RGH VHWWLQJ 7+/' $GGU 2+ 2/ 767% $+ $/ 7+/' 2+ 2/ 767% $GGU $+ $/ 7+/' $GGU 2+ 2/ 767% $+ $/ 7+/' $GGU $+ +LJK ELW $GGUHVV ,QSXW /DWFK '+ +LJK ELW 'DWD ,QSXW /DWFK 2+ +LJK ELW 'DWD 2XWSXW $/ /RZ ELW $GGUHVV ,QSXW /DWFK '/ /RZ ELW 'DWD ,QSXW /DWFK 2/ /RZ ELW 'DWD 2XWSXW 0+ +LJK ELW 0 RGH , QSXW /DWFK 0/ /RZ ELW 0RGH ,QSXW /DWFK #. Note : 1. Internal system is reset at VPP = 12.5V and K2=`Low` 2. The reset release (K2=`High`) must be set within OSC1 = `Low` state. (From this time, OSC1 clock is counted.) 3. The Data will be inputted from the 19th rising edge of OSC1. 4. For device verify. If you set Lock bit, output data is always `0F`h. 9-5 2+ 767% Chapter 9. EPROM 3) Lock Bit Write Mode 73 26& 9''+ 9'' 79336 .933 79335 9,+3 7.6 . 7.' 9''+ 702'( 0+ .a. 7'/< 7'/< 7'/< 0/ 'a' :DLW F\FOH 5HVHW WLPHV UHSHDW /RFN :ULWH 0RGH VHWWLQJ XV [ 0+ +LJK ELW 0 RGH , QSXW /DWFK XV 0/ /RZ ELW 0RGH ,QSXW /DWFK #. Note : 1. Internal system is reset at VPP = 12.5V and K2=`Low` 2. The reset release (K2=`High`) must be set within OSC1 = `Low` state. (From this time, OSC1 clock is counted.) 3. If not written during 10 times repeats (120us), repeat the 5 times until all is written. 9-6 Chapter 9. EPROM 4) Lock Bit Read Mode 73 26& 9''+ 9'' 79336 .933 79335 9,+3 7.6 9''+ . 7.' 702'( 0+ .a. 0/ 'a' /RFN ELW RXWSXW ' 5HVHW /RFN 5HDG 0RGH VHWWLQJ 767% 0+ +LJK ELW 0 RGH , QSXW /DWFK 0/ /RZ ELW 0RGH ,QSXW /DWFK #. Note : 1. Internal system is reset at VPP = 12.5V and K2=`Low` 2. The reset release (K2=`High`) must be set within OSC1 = `Low` state. (From this time, OSC1 clock is counted.) 3. Lock data is outputted from D5 port. If you set Lock bit, the output data of D5 is always `H`. 9-7 Chapter 9. EPROM Program / Verify Timing Diagrams In MHz Version. 1) EPROM Write & Verify Mode (1Byte) %ORFN %ORFN 73 [ 73 %ORFN %ORFN %ORFN 26& 9''+ 9'' .933 79336 79335 . 9,+3 7.6 9''+ 7.' .a. 0+ 'a' 702'( 7'/< 0/ 7'/< $+ 7+/' 5HVHW (SURP :ULWH 0RGH VHWWLQJ $GGU $+ +LJK ELW $GGUHVV ,QSXW /DWFK '+ +LJK ELW 'DWD ,QSXW /DWFK 2+ +LJK ELW 'DWD 2XWSXW $/ /RZ ELW $GGUHVV ,QSXW /DWFK '/ /RZ ELW 'DWD ,QSXW /DWFK 2/ /RZ ELW 'DWD 2XWSXW 0+ +LJK ELW 0RGH ,QSXW /DWFK 0/ /RZ ELW 0RGH ,QSXW /DWFK #. Note : 1. Internal system is reset at VPP = 12.5V and K2=`Low` 2. OSC1 is made of a block of 8 x Tp clock. 3. From this time when the reset is released (K2=`High`) , OSC1 clock is counted by 1-bolck. 4. If not written during 10 times repeats (120us), repeat the 5 times until all is written. 5. For device verify. If you set Lock bit, output data is always `0F`h. &RQWLQXH WR 1H[W 3DJH 9-8 Chapter 9. EPROM - Continue - %ORFN %ORFN %ORFN %ORFN 7'/< 7'/< %ORFN 26& 9''+ 9'' .933 9,+3 9''+ . 7'/< .a. 7'/< 'a' $+ $/ 7+/' 7+/' '+ '/ 7+/' 7+/' $GGU %ORFN %ORFN %ORFN %ORFN 26& 9''+ 9'' .933 9,+3 9''+ . .a. 7'/< 7'/< 7'/< 7'/< 'a' 2/ 2+ $+ WLPHV UHSHDW XV [ 767% XV $GGU 9-9 767% $GGU Chapter 9. EPROM 2) EPROM Read Mode %ORFN %ORFN 73 [ 73 %ORFN %ORFN %ORFN 26& 9''+ 9'' 79336 .933 79335 . 9,+3 7.6 9''+ 7.' .a. 0+ 'a' 702'( 7'/< 0/ 7'/< $+ 7+/' 5HVHW $GGU (SURP 9HULI\ 0RGH VHWWLQJ $+ +LJK ELW $GGUH VV ,QSXW /D WFK '+ +LJK ELW 'D WD ,QSXW /D WFK 2+ +LJK ELW 'D WD 2XWSXW $/ '/ 2/ /R Z ELW $GGUH VV ,QSXW /D WFK 0+ +LJK ELW 0R GH ,QSXW /D WFK /R Z ELW 'D WD ,QSXW /D WFK /R Z ELW 'D WD 2XWSXW 0/ /R Z ELW 0RGH ,QSXW /D WFK #. Note : 1. Internal system is reset at VPP = 12.5V and K2=`Low` 2. OSC1 is made of a block of 8 x Tp clock. 3. From this time when the reset is released (K2=`High`) , OSC1 clock is counted by 1-bolck. 4. For device verify. If you set Lock bit, output data is always `0F`h. &RQWLQXH WR 1H[W 3DJH 9-10 Chapter 9. EPROM - Continue %ORFN %ORFN %ORFN %ORFN %ORFN 26& 9''+ 9'' .933 9,+3 9''+ . 7'/< .a. 7'/< 'a' $+ $/ 7+/' 7+/' 2+ 767% 2/ 767% $GGU %ORFN %ORFN %ORFN %ORFN 26& 9''+ 9'' 9,+3 .933 9''+ . 7 '/< .a. 7'/< 7'/< 'a' 2/ 7'/< $+ 7+/' 2+ $/ 767% 7+/' $GGU 9-11 Chapter 9. EPROM 3) Lock Bit Write Mode %ORFN %ORFN 73 [ 73 %ORFN %ORFN %ORFN 26& 9''+ 9'' 79336 .933 79335 9,+3 7.6 . 9''+ 7.' .a. 702'( 0+ 0/ 'a' 5HVHW %ORFN %ORFN /RFN :ULWH 0RGH VHWWLQJ %ORFN :DLW F\ FOH %ORFN 26& 9''+ 9'' .933 9,+3 9''+ . .a. 7'/< 7'/< 'a' WLPHV UHSHDW :DLW F\ FOH XV [ XV 0+ +LJK ELW 0RGH ,QSXW /DWFK 0/ /RZ ELW 0RGH ,QSXW /DWFK #. Note : 1. Internal system is reset at VPP = 12.5V and K2=`Low` 2. OSC1 is made of a block of 8 x Tp clock. 3. From this time when the reset is released (K2=`High`) , OSC1 clock is counted by 1-bolck. 4. If not written during 10 times repeats(120us), repeat the 5 times until all is written. 9-12 Chapter 9. EPROM 4) Lock Bit Read Mode %ORFN %ORFN 73 [ 73 %ORFN %ORFN %ORFN 26& 9''+ 9'' .933 79336 79335 . 9,+3 7.6 9''+ 7.' .a. 702'( 0+ 0/ 'a' /RFN ELW 2XWSXW ' 5HVHW 0+ +LJK ELW 0RGH ,QSXW /DWFK /RFN 5HDG 0RGH VHWWLQJ 767% 0/ /RZ ELW 0RGH ,QSXW /DWFK #. Note : 1. Internal system is reset at VPP = 12.5V and K2=`Low` 2. OSC1 is made of a block of 8 x Tp clock. 3. From this time when the reset is released (K2=`High`) , OSC1 clock is counted by 1-bolck. 4. Lock data is outputted from D5 port. If you set Lock bit, the output data of D5 is always `H`. 9-13 Chapter 9. EPROM Caution when programming Writing should be done at the defined voltage and timing. In case of EPROM mode, programming voltage is 12.5V. More than defined voltage can give device so great damage to destroy it. Before writing you had better ascertain the characteristics of socket and socket adapter of EPROM writer. It can happen to write error when you touch socket adapter or device. We recommend below flow to improve reliability after writing. :ULWH XVLQJ WKH 6FUHHQLQJ Î (3520 :ULWHU KRXUV 9HULI\ 7HVW XVLQJ )XQFWLRQ 7HVW (3520 :ULWHU XVLQJ 0DQXDO 7HVW Ý Timing Flowchart for Eprom Program / Verify. 67$57 &KDQJH WKH P RGH 5HVHW 9 '' 9 6HW (SURP 5HDG PRGH 9 33 9 UHDG DOO DGGUHVV IDLO 933 5HSRUW 5HVHW 9 '' 9 6HW (SURP 5HDG PRGH 9 33 9 )DLOXUH SDVV IDLO &KDQJH WKH P RGH 9 9'' SDVV UHDG DOO DGGUHVV 9 5HVHW 9 '' 9 6HW (3520 ZULWH PRGH 9 33 9 5HSRUW 5HSRUW 9HULI\ 3URJUDPPLQJ )DLOXUH 2. )LUVW $GGUHVV Q Q â Q \HV (SURP :ULWH QR 5HSRUW Q " 3URJUDPPLQJ 5HSHDW XQWLO QHDU XV XV )DLOXUH XV #N+] IDLO 9HULI\ SDVV 6HW 933 9 6HW 9'' 9 (SURP :ULWH :ULWH RQH PRUH WLPH (1' DGGUHVV QR â 9 %ODQN 9HULI\ %ODQN 9HULI\ 933 9 9'' DGGUHVV ODVW DGGUHVV " \HV 9-14 Chapter 9. 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