NM27LV010 1,048,576-Bit (128k x 8) Low Voltage EPROM General Description Features The NM27LV010 is a high performance Low Voltage Electrically Programmable Read Only Memory. It is manufactured using Fairchild’s AMG™ EPROM technology. This technology allows the part to operate at speeds as fast as 200 ns. ■ 3.0V to 3.6V operation ■ 200 ns access time ■ Low current operation — 8 mA ICC active current @ 5 MHz (typ.) — 20µA ICC standby current @ 5 MHz (typ.) This Low Voltage and Low Power EPROM is designed with power sensitive hand held and portable battery products in mind. This allows for code storage of firmware for applications like notebook computers, palm top computers, cellular phones, and HDD. ■ Ultra low power operation — 66 µW standby power @ 3.3V — 50 mW active power @ 3.3V ■ Surface mount package options| — 32-pin TSOP — 32-pin PLCC Small outline packages are just as critical to portable applications as Low Voltage and Low Power. The NM27LV010 is one member of Fairchild’s growing Low Voltage product Family. Block Diagram Vcc Data Outputs O0 - O7 GND Vpp OE PGM CE Output Enable, Chip Enable & Program Logic Output Buffers Y Decoder A0 - A16 Address Inputs 1,048,576-Bit Cell Matrix X Decoder DS011377-1 AMG™ is a trademark of WSI, Incorporated. © 1998 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com NM27LV010 1,048,576-Bit (128k x 8) Low Voltage EPROM July 1998 PLCC Pin Configuration A12 A15 A16 XX/VPP VCC XX/PGM XX TSOP Pin Configuration 4 2 1 32 31 30 29 28 27 26 25 24 23 22 21 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A14 A13 A8 A9 A11 OE A10 CE O7 O1 O2 GND O3 O4 O5 O6 A7 A6 A5 A4 A3 A2 A1 A0 O0 3 A11 A9 A8 A13 A14 NC PGM VCC VPP A16 A15 A12 A7 A6 A5 A4 DS011377-6 1 2 3 4 5 6 7 8 8 x 20 MM 9 TSOP 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE O7 O6 O5 O4 O3 VSS O2 O1 O0 A0 A1 A2 A3 DS011377-2 Top View Top View Commercial Temperature Range (0°C to +70°C) VCC = 3.3 ± 0.3 Industrial Temperature Range (-40°C to +85°C) VCC = 3.3 ± 0.3 Parameter/Order Number Access Time (ns) Parameter/Order Number Access Time (ns) NM27LV010 V, T 200 200 NM27LV010 VE, TE 200 NM27LV010 V, T 250 250 NM27LV010 VE, TE 250 Package Types: NM27LV010 V, T Pin Names A0–A16 V = PLCC Addresses CE Chip Enable OE Output Enable O0–O7 Outputs PGM Program XX Don’t Care (During Read) VPP Programming Voltage T = TSOP • All packages conform to the JEDEC standard. • All versions are guaranteed to function for slower speeds. • Consult the Fairchild Sales office on new released products and packages. • Consult the Fairchild representative for custom products for your specific application. 2 www.fairchildsemi.com NM27LV010 1,048,576-Bit (128k x 8) Low Voltage EPROM Connection Diagrams Storage Temperature All Output Voltages with Respect to Ground (Note 10) VCC + 1.0V to GND - 0.6V -65°C to +150°C All Input Voltages except A9 with Respect to Ground (Note 10) VPP and A9 with Respect to Ground VCC Supply Voltage with Respect to Ground Operating Range -0.6V to +7V Range -0.6V to +14V -0.6V to +7V ESD Protection Temperature VCC Tolerance Commercial 0°C to +70°C 3.3V ±0.3V Industrial -40°C to +85°C 3.3V ±0.3V >2000V DC Electrical Characteristics Over Operating Range with VPP = VCC Symbol Min Max Units VIL Input Low Level Parameter Test Conditions -0.3 0.7 V VIH Input High Level 2.0 VCC + 0.3 V 0.4 V VOL1 Output Low Voltage (TTL) IOL = 2.0 mA VOH1 Output High Voltage (TTL) IOH = -2.0 mA VOL2 Output Low Voltage IOL = 100 µA VOH2 Output High Voltage (CMOS) IOH = -100 µA ISB1 VCC Standby Current (CMOS) ISB2 2.4 V 0.2 V CE = VCC ± 0.3V 50 µA VCC Standby Current (TTL) CE = VIH 100 µA ICC VCC Active Current CE = OE = VIL, I/O = 0 µA 15 mA IPP VPP Supply Current VPP = VCC 10 µA VPP VPP Read Voltage ILI Input Load Current VIN = 3.0V or GND ILO Output Leakage Current VOUT = 3.0V or GND VCC - 0.3 f = 5 MHz VCC - 0.7 -1 VCC V 1 µA 10 µA AC Electrical Characteristics Over Operating Range with VPP = VCC Symbol Parameter 200 Min 250 Max Min Units Max tACC Address to Output Delay 200 250 tCE CE to Output Delay 200 250 tOE OE to Output Delay 70 75 tDF (Note 2) Output Disable to Output Float 50 50 tOH (Note 2) Output Hold from Addresses, CE or OE , Whichever Occurred First 0 ns 0 3 www.fairchildsemi.com NM27LV010 1,048,576-Bit (128k x 8) Low Voltage EPROM Absolute Maximum Ratings (Note 1) Symbol Parameter CIN COUT Conditions Input Capacitance VIN = 0V Output Capacitance VOUT = 0V Typ Max Units 9 15 pF 12 15 pF AC Test Conditions Output Load 1 TTL Gate and CL = 100 pF (Note 8) ≤5 ns Input Rise and Fall Times Input Pulse Levels 0.45V to 2.4V Timing Measurement Reference Level Inputs Outputs 0.8V and 2V 0.8V and 2V AC Waveforms (Note 6) , (Note 7) , and (Note 9) ADDRESS 2.0V 0.8V CE 2.0V 0.8V Address Valid ,, , t CF (Note 2, 4, 5) t CE OE 2.0V 0.8V t OE (Note 3) OUTPUT 2.0V 0.8V t DF (Note 2, 4, 5) Hi-Z Valid Output t ACC t OH (Note 3) DS011377-3 Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operations sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: This parameter is only sampled and is not 100% tested. Note 3: OE may be delayed up to tACC - tCE after the falling edge of CE without impacting tACC. Note 4: The tDF and tCF compare level is determined as follows: High to TRI-STATE®, the measured VOH1 (DC) - 0.10V; Low to TRI-STATE, the measured VOL1 (DC) + 0.10V. Note 5: TRI-STATE may be attained using OE or CE . Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.2 µF ceramic capacitor be used on every device between VCC and GND. Note 7: The outputs must be restricted to VCC + 1.0V to avoid latch-up and device damage. Note 8: 1 TTL Gate: IOL = 1.6 mA, IOH = -400 µA. CL: 100pF includes fixture capacitance. Note 9: VPP may be connected to VCC except during programming. Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max. 4 www.fairchildsemi.com NM27LV010 1,048,576-Bit (128k x 8) Low Voltage EPROM Capacitance (Note 2) TA = +25°C, 1 = 1 MHz Symbol Parameter Conditions Min Typ Max Units tAS Address Setup Time 1 µs tOES OE Setup Time 1 µs tCES CE Setup Time 1 µs tDS Data Setup Time 1 µs tVPS VPP Setup Time 1 µs tVCS VCC Setup Time 1 µs tAH Address Hold Time 0 µs tDH Data Hold Time 1 µs tDF Output Enable to Output Float Delay tPW Program Pulse Width 105 µs tOE Data Valid from OE CE/PGM = VIL 100 ns IPP VPP Supply Current during Programming Pulse CE/PGM = VIL 20 mA ICC VCC Supply Current 20 mA TA Temperature Ambient 20 25 30 °C VCC Power Supply Voltage 6.25 6.5 6.75 V VPP Programming Supply Voltage 12.5 12.75 13.0 V tFR Input Rise, Fall Time CE/PGM = VIL 0 60 45 50 ns 5 ns VIL Input Low Voltage VIH Input High Voltage 2.4 tIN Input Timing Reference Voltage 0.8 2.0 V Output Timing Reference Voltage 0.8 2.0 V tOUT 0.0 0.45 4.0 V V Programming Waveform (Note 13) Program Addresses 2.0V 0.8V Program Verify Address N t AH t AS 2.0V Data Hi-Z Data In Stable ADD N 0.8V t DS Data Out Valid ADD N t DH t DF VCC VPP 6.25V t VCS 12.75V t VPS t CES CE PGM 2.0V 0.8V tOES tOE t PW OE 2.0V 0.8V DS011377-4 Note 11: Fairchild’s standard product warranty applies to devices programmed to specifications described herein. Note 12: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removedfrom a board with voltage applied to VPP or VCC. Note 13: The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 µF capacitor is required across VPP, VCC to GND to suppress spurious voltage transients which may damage the device. Note 14: During power up the PGM pin must be brought high (≥ VIH) either coincident with or before power is applied to VPP. 5 www.fairchildsemi.com NM27LV010 1,048,576-Bit (128k x 8) Low Voltage EPROM Programming Characteristics (Note 11), (Note 12), (Note 13) and (Note 14) NM27LV010 1,048,576-Bit (128k x 8) Low Voltage EPROM LV Turbo Programming Algorithm Flow Chart VCC = 6.5V VPP = 12.75V n=0 ADDRESS = FIRST LOCATION PROGRAM ONE 50µs PULSE INCREMENT n NO DEVICE FAILED YES n = 10? FAIL VERIFY BYTE PASS LAST ADDRESS ? NO INCREMENT ADDRESS n=0 YES ADDRESS = FIRST LOCATION VERIFY BYTE FAIL PASS INCREMENT ADDRESS NO PROGRAM ONE 50 µs PULSE LAST ADDRESS ? YES CHECK ALL BYTES 1ST: VCC = VPP = 5.0V 2ND: VCC = VPP = 3.0V DS011377-5 Note: The standard National Semiconductor algorithm may also be used but it will have longer programming time. FIGURE 1. 6 www.fairchildsemi.com DEVICE OPERATION The six modes of operation of the EPROM are listed in Table 1. It should be noted that all inputs for the six modes are at TTL levels. The power supplies required are VCC and VPP. The VPP power supply must be at 12.75V during the three programming modes, and must be at 3.3V in the other three modes. The VCC power supply must be at 6.5V during the three programming modes, and at 3.3V in the other three modes. When the address and data are stable, an active low, TTL program pulse is applied to the PGM input. A program pulse must be applied at each address location to be programmed. The EPROM is programmed with the LV Turbo Programming Algorithm shown in Figure 1. Each Address is programmed with a series of 50 µs pulses until it verifies good, up to a maximum of 10 pulses. Most memory cells will program with a single 50 µs pulse. (The standard National Semiconductor Algorithm may also be used, but it will have longer programming time.) Read Mode The EPROM has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE, assuming that CE has been low and addresses have been stable for at least tACC –tOE. The EPROM must not be programmed with a DC signal applied to the PGM input. Programming multiple EPROM in parallel with the same data can be easily accomplished due to the simplicity of the programming requirements. Like inputs of the parallel EPROM may be connected together when they are programmed with the same data. A low level TTL pulse applied to the PGM input programs the paralleled EPROM. Standby Mode The EPROM has a standby mode which reduces the active power dissipation by over 99%, from 50 mW to 0.17 mW. The EPROM is placed in the standby mode by applying a CMOS high signal to the CE input. When in standby mode, the outputs are in a high impedance state, independent of the OE input. Program Inhibit Programming multiple EPROM’s in parallel with different data is also easily accomplished. Except for CE, all like inputs (including OE and PGM) of the parallel EPROM may be common. A TTL low level program pulse applied to an EPROM’s PGM input with CE at VIL and VPP at 12.75V will program that EPROM. A TTL high level CE input inhibits the other EPROM’s from being programmed. Output Disable The EPROM is placed in output disable by applying a TTL high signal to the OE input. When in output disable all circuitry is enabled, except the outputs are in a high impedance state (TRISTATE). Program Verify A verify should be performed on the programmed bits to determine whether they were correctly programmed. The verify may be performed with V PP at 6.25V. VPP must be at VCC, except during programming and program verify. Output OR-Tying Because the EPROM is usually used in larger memory arrays, Fairchild has provided a 2-line control function that accommodates this use of multiple memory connections. The 2-line control function allows for: AFTER PROGRAMMING Opaque labels should be placed over the EPROM window to prevent unintentional erasure. Covering the window will also prevent temporary functional failure due to the generation of photo currents. 1. the lowest possible memory power dissipation, and 2. complete assurance that output bus contention will not occur. MANUFACTURER’S IDENTIFICATION CODE To most efficiently use these two control lines, it is recommended that CE be decoded and used as the primary device selecting function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device. The EPROM has a manufacturer’s identification code to aid in programming. When the device is inserted in an EPROM programmer socket, the programmer reads the code and then automatically calls up the specific programming algorithm for the part. This automatic programming control is only possible with programmers which have the capability of reading the code. Programming The Manufacturer’s Identification code, shown in Table 2, specifically identifies the manufacturer and device type. The code for the NM27LV010 is “8F86”, where “8F” designates that it is made by Fairchild Semiconductor, and “86” designates a 1 Megabit (128k x 8) part. CAUTION: Exceeding 14V on pin 1 (VPP) will damage the EPROM. Initially, and after each erasure, all bits of the EPROM are in the “1’s” state. Data is introduced by selectively programming “0’s” into the desired bit locations. Although only “0’s” will be programmed, both “1’s” and “0’s” can be presented in the data word. The only way to change a “0” to a “1” is by ultraviolet light erasure. The code is accessed by applying 12V ±0.5V to address pin A9. Addresses A1–A8, A10–A16, and all control pins are held at VIL. Address pin A0 is held at VIL for the manufacturer’s code, and held at VIH for the device code. The code is read on the lower eight data pins, O0–07. Proper code access is only guaranteed at 25°C ± 5°C. The EPROM is in the programming mode when the VPP power supply is at 12.75V and OE is at VIH. It is required that at least a 7 www.fairchildsemi.com NM27LV010 1,048,576-Bit (128k x 8) Low Voltage EPROM 0.1 µF capacitor be placed across VPP and VCC to ground to suppress spurious voltage transients which may damage the device. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. Functional Description ring. Incomplete erasure will cause symptoms that can be misleading. Programmers, components, and even system designs have been erroneously suspected when incomplete erasure was the problem. ERASURE CHARACTERISTICS The erasure characteristics of the device are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (Å). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000Å – 4000Å range. SYSTEM CONSIDERATION The power switching characteristics of EPROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. The associated VCC transient voltage peaks can be suppressed by properly selected decoupling capacitors. It is recommended that at least a 0.1 µF ceramic capacitor be used on every device between VCC and GND. This should be a high frequency capacitor of low inherent inductance. In addition, at least a 4.7 µF bulk electrolytic capacitor should be used between VCC and GND for each eight devices. The bulk capacitor should be located near where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the PC board traces. The recommended erasure procedure for the EPROM is exposure to short wave ultraviolet light which has a wavelength of 2537Å. The integrated dose (i.e., UV intensity x exposure time) for erasure should be a minimum of 30W-sec/cm2 . The EPROM should be placed within 1 inch of the lamp tubes during erasure. Some lamps have a filter on their tubes which should be removed before erasure. An erasure system should be calibrated periodically. The distance from lamp to device should be maintained at one inch. The erasure time increases as the square of the distance from the lamp (if distance is doubled the erasure time increases by factor of 4). Lamps lose intensity as they age. When a lamp has aged, the system should be checked to make certain full erasure is occur- Mode Selection The modes of operation of the NM27LV010 are listed in Table 1. A single 3.3V power supply is required in the read mode. All inputs are TTL levels except for VPP and A9 for device signature. TABLE 1. Modes Selection Pins CE OE PGM VPP VCC Outputs VIL VIL X VCC 3.3V DOUT X (Note 15) VIH X VCC 3.3V High Z Mode Read Output Disable Standby VIH X X VCC 3.3V High Z Programming VIL VIH VIL 12.75V 6.25V DIN Program Verify VIL VIL VIH 12.75V 12.75V DOUT Program Inhibit VIH VIH X 12.75V 6.25V High Z Note 15: X can be VIL or VIH . TABLE 2. Manufacturer’s Identification Code Pins A0 (12) A9 (26) O7 (21) O6 (20) O5 (19) O4 (18) O3 (17) O2 (15) O1 (14) O0 (13) Hex Data Manufacturer Code VIL 12V 1 0 0 0 1 1 1 1 8F Device Code VIH 12V 1 0 0 0 0 1 1 0 86 8 www.fairchildsemi.com NM27LV010 1,048,576-Bit (128k x 8) Low Voltage EPROM Functional Description (Continued) 20.0 ± 0.2 0.96 - 1.06 8.0 ± 0.2 32 1 0.5 16 17 0.15-0.25 TYP 0.150±0.08 (Leadframe Thickness) 18.4 ± 0.1 0.10 See Detail A 1.27 MAX 0°-5° 0-0.25 0.4-0.6 DETAIL A Typical 32-Lead TSOP Package (T) Order Number NM27LV010TXXX Package Number MBH32A 9 www.fairchildsemi.com NM27LV010 1,048,576-Bit (128k x 8) Low Voltage EPROM Physical Dimensions inches (millimeters) unless otherwise noted NM27LV010 1,048,576-Bit (128k x 8) Low Voltage EPROM Physical Dimensions inches (millimeters) unless otherwise noted 0.485-0.495 [12.32-12.57] 0.007[0.18] S B D-E S 0.449-0.453 [11.40-11.51] -A0.045 [1.143] 0.002[0.05] S B 0.000-0.010 [0.00-0.25] Polished Optional -H- 0.106-0.112 [2.69-2.84] 0.007[0.18] S B D-E S Base Plane 0.023-0.029 [0.58-0.74] 0.015 [0.38] Min Typ -D1 30 60 ° 4 29 5 0.490-0530 [12.45-13.46] 0.400 ( [10.16] ) 0.549-0.553 [13.94-14.05] -G0.541-0.545 [13.74-13-84] -B0.585-0.595 [14.86-15.11] 0.015[0.38] S C D-E, F-G S -F- 13 21 14 -J- 0.007[0.18] M A F-G S 0.007[0.18] S 0.007[0.18] S See detail A -E- 0.002[0.05] S A 0.013-0.021 TYP [0.33-0.53] 0.050 20 0.123-0.140 [3.12-3.56] A F-G S -C0.004[0.10] 0.118-0.129 [3.00-3.28] 0.010[0.25] L B A D-E, F-G S B ,, 0.042-0.048 45°X [1.07-1.22] B 0.020 [0.51] 0.025 [0.64] Min D-E, F-G S 0.005 Max [0.13] 0.0100 [0.254] 0.045 [1.14] Detail A Typical Rotated 90° 0.021-0.027 [0.53-0.69] 0.025 [0.64] Min C 0.078-0.095 [1.98-2.41] R 0.030-0.040 [0.76-1.02] 0.065-0.071 [1.65-1.80] 0.053-0.059 [1.65-1.80] 0.007[0.18] S 0.031-0.037 [0.79-0.94] 0.006-0.012 [0.15-0.30] 0.026-0.032 Typ [0.66-0.81] H D-E, F-G S 0.027-0.033 [0.69-0.84] 0.019-0.025 [0.48-0.64] Section B-B Typical 32-Lead PLCC Package Order Number NM27LV010VXXX Package Number VA32A Life Support Policy Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. Fairchild Semiconductor Americas Customer Response Center Tel. 1-888-522-5372 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Fairchild Semiconductor Europe Fax: +44 (0) 1793-856858 Deutsch Tel: +49 (0) 8141-6102-0 English Tel: +44 (0) 1793-856856 Français Tel: +33 (0) 1-6930-3696 Italiano Tel: +39 (0) 2-249111-1 Fairchild Semiconductor Hong Kong 8/F, Room 808, Empire Centre 68 Mody Road, Tsimshatsui East Kowloon. Hong Kong Tel; +852-2722-8338 Fax: +852-2722-8383 Fairchild Semiconductor Japan Ltd. 4F, Natsume Bldg. 2-18-6, Yushima, Bunkyo-ku Tokyo, 113-0034 Japan Tel: 81-3-3818-8840 Fax: 81-3-3818-8841 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 10 www.fairchildsemi.com