AD AD9106 Quad, low power, 12-bit, 180 msps, digital-to-analog converter and waveform generator Datasheet

Quad, Low Power, 12-Bit, 180 MSPS, Digital-toAnalog Converter and Waveform Generator
AD9106
Data Sheet
FEATURES
GENERAL DESCRIPTION
Highly integrated quad DAC
On-chip 4096 × 12-bit pattern memory
On-chip DDS
Power dissipation at 3.3 V, 4 mA output
315 mW at 180 MSPS
Sleep mode: < 5 mW at 3.3 V
Supply voltage: 1.8 V to 3.3 V
SFDR to Nyquist
86 dBc at 1 MHz output
85 dBc at 10 MHz output
Phase noise at 1 kHz offset, 180 MSPS, 8 mA: −140 dBc/Hz
Differential current outputs: 8 mA maximum at 3.3 V
Small footprint 32-lead, 5 mm × 5 mm with 3.5 mm ×
3.6 mm exposed paddle LFCSP
Pb-free package
The AD9106 TxDAC® and waveform generator is a high performance quad DAC integrating on-chip pattern memory for complex
waveform generation with a direct digital synthesizer (DDS). The
DDS is a 12-bit output, up to 180 MHz master clock sinewave
generator with a 24-bit tuning word allowing 10.8 Hz/LSB
frequency resolution. The DDS has a single frequency output
for all four DACs and independent programmable phase shift
outputs for each of the four DACs.
APPLICATIONS
Medical instrumentation
Ultrasound transducer excitation
Portable instrumentation
Signal generators, arbitrary waveform generators
SRAM data can include directly generated stored waveforms,
amplitude modulation patterns applied to DDS outputs, or
DDS frequency tuning words.
An internal pattern control state machine allows the user to
program the pattern period for all four DACs as well as the start
delay within the pattern period for the signal output on each
DAC channel.
An SPI interface is used to configure the digital waveform
generator and load patterns into the SRAM.
There are gain adjustment factors and offset adjustments
applied to the digital signals on their way into the four DACs.
The AD9106 offers exceptional ac and dc performance and
supports DAC sampling rates up to 180 MSPS. The flexible
power supply operating range of 1.8 V to 3.3 V and low power
dissipation of the AD9106 make it well suited for portable and low
power applications.
Rev. A
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 ©2012–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD9106
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Analog Current Outputs ........................................................... 22
Applications ....................................................................................... 1
Setting IOUTFSx, DAC Gain .......................................................... 22
General Description ......................................................................... 1
Automatic IOUTFSx Calibration ................................................... 23
Revision History ............................................................................... 2
Clock Input.................................................................................. 23
Functional Block Diagram .............................................................. 3
DAC Output Clock Edge ........................................................... 24
Specifications..................................................................................... 4
Generating Signal Patterns ........................................................ 24
DC Specifications (3.3 V) ............................................................ 4
Pattern Generator Programming ............................................. 25
DC Specifications (1.8 V) ............................................................ 5
DACx Input Data Paths ............................................................. 25
Digital Timing Specifications (3.3 V) ........................................ 6
DOUT Function ......................................................................... 26
Digital Timing Specifications (1.8 V) ........................................ 6
Direct Digital Synthesizer (DDS) ............................................. 26
Input/Output Signal Specifications ............................................ 7
SRAM ........................................................................................... 27
AC Specifications (3.3 V) ............................................................ 8
Sawtooth Generator ................................................................... 27
AC Specifications (1.8 V) ............................................................ 8
Pseudo-Random Signal Generator .......................................... 27
Power Supply Voltage Inputs and Power Dissipation .............. 9
DC Constant ............................................................................... 27
Absolute Maximum Ratings.......................................................... 10
Power Supply Notes ................................................................... 27
Thermal Resistance .................................................................... 10
Power-Down Capabilities.......................................................... 27
ESD Caution ................................................................................ 10
Applications Information .............................................................. 28
Pin Configuration and Function Descriptions ........................... 11
Signal Generation Examples ..................................................... 28
Typical Performance Characteristics ........................................... 13
Register Map ................................................................................... 30
Terminology .................................................................................... 19
Register Descriptions ................................................................. 33
Theory of Operation ...................................................................... 20
Outline Dimensions ....................................................................... 48
SPI Port ........................................................................................ 21
Ordering Guide .......................................................................... 48
DAC Transfer Function ............................................................. 22
REVISION HISTORY
2/13—Rev. 0 to Rev. A
Updated Format .................................................................. Universal
Changes to Features Section............................................................ 1
Changes to Figure 1 .......................................................................... 3
Deleted Figure 20; Renumbered Sequentially ............................ 16
Changes to Figure 31 ...................................................................... 20
Changes to Table 13 ........................................................................ 22
Deleted Recommendations When Using an External
Reference Section............................................................................ 23
11/12—Revision 0: Initial Version
Rev. A | Page 2 of 48
Data Sheet
AD9106
START DLY
GAIN1
FSADJ1
FSADJ2/CAL_SENSE
RESET
SCLK
REFIO
RSET1
16kΩ
IREF
100µA
OFFSET1
DAC1
DAC CLOCK
AGND
RSET2
16kΩ
DAC1 TO DAC2
TIMERS + STATE MACHINES
TRIGGER
SDO/SDI2/DOUT
1V
10kΩ
SPI
INTERFACE
DDS1
STOP ADDR
START ADDR
CONSTANT1
RANDOM1
AD9106
SAWTOOTH1
CS
SDIO
FUNCTIONAL BLOCK DIAGRAM
IOUTP1
DAC1
IOUTN1
ADDRESS 1, 2
AVDD1
GAIN2
IOUTP2
OFFSET2
DAC2
DAC2
DPRAM
GAIN3
IOUTN2
BAND
GAP
IOUTP3
OFFSET3
DAC3
DAC3
IOUTN3
DAC CLOCK
AVDD2
IOUTP4
GAIN4
ADDRESS 3, 4
DAC4
OFFSET4
IOUTN4
DAC4
DAC3 TO DAC4
TIMERS + STATE MACHINES
PHASE1
DDS1
START DLY
TUNING WORD
DDS2
STOP ADDR
DDS
DAC CLOCK
CLOCK
DIST
RSET3
16kΩ
Rev. A | Page 3 of 48
11121-001
FSADJ4
FSADJ3
CLKP
CLKN
CLKVDD
Figure 1.
CLDO
PHASE4
DGND
PHASE3
DLDO2
1.8V
LDO
DDS4
1.8V
LDOs
DLDO1
DDS3
CLKGND
START ADDR
DVDD
RSET4
16kΩ
PHASE2
AD9106
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS (3.3 V)
TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V; internal CLDO, DLDO1, and DLDO2; IOUTFS = 4 mA, maximum sample rate,
unless otherwise noted.
Table 1.
Parameter
RESOLUTION
Min
Typ
12
Max
Unit
Bits
ACCURACY at 3.3 V
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
±0.4
±0.5
DAC OUTPUTS
Offset Error
LSB
LSB
±.00025
Gain Error Internal Reference—No Automatic IOUTFS Calibration
Full-Scale Output Current 1 at 3.3 V
Output Resistance
Output Compliance Voltage
Crosstalk, DAC to DAC (fOUT = 10 MHz)
Crosstalk, DAC to DAC (fOUT = 60 MHz)
−1.0
2
% of FSR
96
82
% of FSR
mA
MΩ
V
dBC
dBc
±251
±119
ppm/°C
ppm/°C
4
200
−0.5
+1.0
8
+1.0
DAC TEMPERATURE DRIFT
Gain with Internal Reference
Internal Reference Voltage
REFERENCE OUTPUT
Internal Reference Voltage with AVDD = 3.3 V
Output Resistance
0.8
1.0
10
1.2
V
kΩ
1.25
1
V
MΩ
±0.75
% of FSR
REFERENCE INPUT
Voltage Compliance
Input Resistance External, Reference Mode
DAC MATCHING
Gain Matching—No Automatic IOUTFS Calibration
1
0.1
Based on use of 8 kΩ external xRSET resistors.
Rev. A | Page 4 of 48
Data Sheet
AD9106
DC SPECIFICATIONS (1.8 V)
TMIN to TMAX, AVDD = 1.8 V, DVDD = DLDO1 = DLDO2 = 1.8 V, CLKVDD = CLDO = 1.8 V, IOUTFS = 4 mA, maximum sample rate, unless
otherwise noted.
Table 2.
Parameter
RESOLUTION
ACCURACY at 1.8 V
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
DAC OUTPUTS
Offset Error
Gain Error Internal Reference—No Automatic IOUTFS Calibration
Full-Scale Output Current1 at 1.8 V
Output Resistance
Output Compliance Voltage
Crosstalk, DAC to DAC (fOUT = 30 MHz)
Crosstalk, DAC to DAC (fOUT = 60 MHz)
DAC TEMPERATURE DRIFT
Gain
Reference Voltage
REFERENCE OUTPUT
Internal Reference Voltage with AVDD = 1.8 V
Output Resistance
REFERENCE INPUT
Voltage Compliance
Input Resistance External, Reference Mode
DAC MATCHING
Gain Matching—No Automatic IOUTFS Calibration
1
Min
Typ
12
Max
±0.4
±0.4
LSB
LSB
±.00025
−1.0
2
94
78
% of FSR
% of FSR
mA
MΩ
V
dB
dB
±228
±131
ppm/°C
ppm/°C
4
200
−0.5
0.8
Rev. A | Page 5 of 48
+1.0
4
+1.0
1.0
10
1.2
V
kΩ
1.25
1
V
MΩ
±0.75
% of FSR
0.1
Based on use of 8 kΩ external xRSET resistors.
Unit
Bits
AD9106
Data Sheet
DIGITAL TIMING SPECIFICATIONS (3.3 V)
TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V; internal CLDO, DLDO1, and DLDO2; IOUTFS = 4 mA, maximum sample rate,
unless otherwise noted.
Table 3.
Parameter
DAC CLOCK INPUT (CLKIN)
Maximum Clock Rate
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK)
Minimum Pulse Width High
Minimum Pulse Width Low
Setup Time SDIO to SCLK
Hold Time SDIO to SCLK
Output Data Valid SCLK to SDO or SDIO
Setup Time CS to SCLK
Min
Typ
Max
180
MSPS
80
MHz
ns
ns
ns
ns
ns
ns
6.25
6.25
4.0
5.0
6.2
4.0
E
A
Unit
DIGITAL TIMING SPECIFICATIONS (1.8 V)
TMIN to TMAX, AVDD = 1.8 V, DVDD = DLDO1 = DLDO2 = 1.8 V, CLKVDD = CLDO = 1.8 V, IOUTFS = 4 mA, maximum sample rate, unless
otherwise noted.
Table 4.
Parameter
DAC CLOCK INPUT (CLKIN)
Maximum Clock Rate
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK)
Minimum Pulse Width High
Minimum Pulse Width Low
Setup Time SDIO to SCLK
Hold Time SDIO to SCLK
Output Data Valid SCLK to SDO or SDIO
Setup Time CS to SCLK
Min
180
6.25
6.25
4.0
5.0
8.8
4.0
A
Rev. A | Page 6 of 48
Max
Unit
MSPS
80
E
A
Typ
MHz
ns
ns
ns
ns
ns
ns
Data Sheet
AD9106
INPUT/OUTPUT SIGNAL SPECIFICATIONS
Table 5.
Parameter
CMOS INPUT LOGIC LEVEL (SCLK, CS, SDIO, SDO/SDI2/DOUT, RESET,
TRIGGER)
Input VIN Logic High
E
A
Test Conditions/ Comments
Min
DVDD = 1.8 V
DVDD = 3.3 V
DVDD = 1.8 V
DVDD = 3.3 V
1.53
2.475
DVDD = 1.8 V
DVDD = 3.3 V
DVDD = 1.8 V
DVDD = 3.3 V
1.79
3.28
Typ
Max
Unit
0.27
0.825
V
V
V
V
0.25
0.625
V
V
V
V
E
A
A
A
E
A
A
Input VIN Logic Low
CMOS OUTPUT LOGIC LEVEL (SDIO, SDO/SDI2/DOUT)
Output VOUT Logic High
Output VOUT Logic Low
DAC CLOCK INPUT (CLKP, CLKN)
Minimum Peak-to-Peak Differential Input Voltage, VCLKP/VCLKN
Maximum Voltage at VCLKP or VCLKN
Minimum Voltage at VCLKP or VCLKN
Common-Mode Voltage Generated on Chip
Rev. A | Page 7 of 48
150
VDVDD
VDGND
0.9
mV
V
V
V
AD9106
Data Sheet
AC SPECIFICATIONS (3.3 V)
TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V; internal CLDO, DLDO1, and DLDO2; IOUTFS = 4 mA, maximum sample rate,
unless otherwise noted.
Table 6.
Parameter
SPURIOUS FREE DYNAMIC RANGE (SFDR)
fDAC = 180 MSPS, fOUT = 10 MHz
fDAC = 180 MSPS, fOUT = 50 MHz
TWO-TONE INTERMODULATION DISTORTION (IMD)
fDAC = 180 MSPS, fOUT = 10 MHz
fDAC = 180 MSPS, fOUT = 50 MHz
NSD
fDAC = 180 MSPS, fOUT = 50 MHz
PHASE NOISE at 1 kHz FROM CARRIER
fDAC = 180 MSPS, fOUT = 10 MHz
DYNAMIC PERFORMANCE
Output Settling Time, Full Scale Output Step (to 0.1%)1
Trigger to Output Delay, fDAC = 180 MSPS2
Rise Time, Full-Scale Swing1
Fall Time, Full-Scale Swing1
1
2
Min
Typ
Max
Unit
86
73
dBc
dBc
92
77
dBc
dBc
−167
dBm/Hz
−135
dBc/Hz
31.2
96
3.25
3.26
ns
ns
ns
ns
Based on the 85 Ω resistors from DAC output terminals to ground.
Start delay = 0 fDAC clock cycles.
AC SPECIFICATIONS (1.8 V)
TMIN to TMAX, AVDD = 1.8 V, DVDD = DLDO1 = DLDO2 = 1.8 V, CLKVDD = CLDO = 1.8 V, IOUTFS = 4 mA, maximum sample rate, unless
otherwise noted.
Table 7.
Parameter
SPURIOUS FREE DYNAMIC RANGE (SFDR)
fDAC = 180 MSPS, fOUT = 10 MHz
fDAC = 180 MSPS, fOUT = 50 MHz
TWO-TONE INTERMODULATION DISTORTION (IMD)
fDAC = 180 MSPS, fOUT = 10 MHz
fDAC = 180 MSPS, fOUT = 50 MHz
NSD
fDAC = 180 MSPS, fOUT = 50 MHz
PHASE NOISE at 1 kHz FROM CARRIER
fDAC = 180 MSPS, fOUT = 10 MHz
DYNAMIC PERFORMANCE
Output Settling Time (to 0.1%)1
Trigger to Output Delay, fDAC = 180 MSPS2
Rise Time1
Fall Time1
1
2
Min
Based on the 85 Ω resistors from DAC output terminals to ground.
Start delay = 0 fDAC clock cycles.
Rev. A | Page 8 of 48
Typ
Max
Unit
83
74
dBc
dBc
91
83
dBc
dBc
−163
dBm/Hz
−135
dBc/Hz
31.2
96
3.25
3.26
ns
ns
ns
ns
Data Sheet
AD9106
POWER SUPPLY VOLTAGE INPUTS AND POWER DISSIPATION
Table 8.
Parameter
ANALOG SUPPLY VOLTAGES
AVDD1, AVDD2
CLKVDD
CLDO
DIGITAL SUPPLY VOLTAGES
DVDD
DLDO1, DLDO2
POWER CONSUMPTION
fDAC = 180 MSPS, Pure CW Sine Wave
IAVDD
IDVDD
DDS Only
RAM Only
DDS and RAM Only
ICLKVDD
Power-Down Mode
POWER CONSUMPTION
fDAC = 180 MSPS, Pure CW Sine Wave
IAVDD
IDVDD
IDLDO2
DDS Only
RAM Only
DDS and RAM Only—50% Duty Cycle Sine
Wave Output
IDLDO1
ICLKVDD
ICLDO
Power-Down Mode
Test Conditions/Comments
Min
On-chip LDO not in use
On-chip LDO not in use
AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, internal CLDO, DLDO1,
and DLDO2
12.5 MHz (DDS only), all four DACs
CW sine wave output
50% duty cycle FS pulse output
50% duty cycle sine wave output
REF_PDN = 0, DACs sleep, CLK power down, external CLK, and
supplies on
AVDD = 1.8 V, DVDD = DLDO1 = DLDO2 = 1.8 V, CLKVDD = CLDO =
1.8 V
12.5 MHz (DDS only)
CW sine wave output
50% duty cycle FS pulse output
REF_PDN = 0, DACs sleep, CLK power down, external CLK, and
supplies on
Rev. A | Page 9 of 48
Typ
Max
Unit
1.7
1.7
1.7
3.6
3.6
1.9
V
V
V
1.7
1.7
3.6
1.9
V
V
315.25
28.51
mW
mA
60.3
27.1
39.75
6.72
4.73
mA
mA
mA
mA
mW
167
28.14
0.151
mW
mA
mA
53.75
17.78
35.4
mA
mA
mA
4.0
0.0096
6.6
1.49
mA
mA
mA
mW
AD9106
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 9.
Parameter
AVDD1, AVDD2, DVDD to AGND,
DGND, CLKGND
CLKVDD to AGND, DGND, CLKGND
CLDO, DLDO1, DLDO2 to AGND,
DGND, CLKGND
AGND to DGND, CLKGND
DGND to AGND, CLKGND
CLKGND to AGND, DGND
CS, SDIO, SCLK, SDO/SDI2/DOUT,
RESET, TRIGGER to DGND
CLKP, CLKN to CLKGND
REFIO to AGND
IOUTP1, IOUTN1, IOUTP2, IOUTN2,
IOUTP3, IOUTN3, IOUTP4, IOUTN4 to
AGND
FSADJ1, FSADJ2/CAL_SENSE, F4DJ3,
FSADJ4 to AGND
Junction Temperature
Storage Temperature
E
A
A
E
A
θJA is specified for the worst-case conditions, that is, a device
soldered in a standard circuit board for surface-mount
packages. θJC is measured from the solder side (bottom) of the
package.
Rating
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to +2.2 V
Table 10. Thermal Resistance
−0.3 V to +0.3V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to DVDD + 0.3 V
E
A
A
A
−0.3 V to CLKVDD + 0.3 V
−1.0 V to AVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
Package Type
32-Lead LFCSP with
Exposed Paddle
ESD CAUTION
−0.3 V to AVDD + 0.3 V
125 οC
−65 οC to +150 οC
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. A | Page 10 of 48
θJA
30.18
θJB
6.59
θJC
3.84
Unit
C/W
ο
Data Sheet
AD9106
32
31
30
29
28
27
26
25
TRIGGER
IOUTP2
IOUTN2
AVDD1
IOUTN1
IOUTP1
AGND
FSADJ1
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
AD9106
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
FSADJ2/CAL_SENSE
CLKVDD
CLDO
CLKP
CLKN
CLKGND
REFIO
FSADJ4
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO DGND.
11121-002
RESET
IOUTP4
IOUTN4
AVDD2
IOUTN3
IOUTP3
AGND
FSADJ3
9
10
11
12
13
14
15
16
SCLK
SDIO
DGND
DLDO2
DVDD
DLDO1
SDO/SDI2/DOUT
CS
Figure 2. Pin Configuration
Table 11. Pin Function Descriptions
Pin No.
1
2
3
4
Mnemonic
SCLK
SDIO
DGND
DLDO2
5
DVDD
6
DLDO1
7
SDO/SDI2/DOUT
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
CS
RESET
IOUTP4
IOUTN4
AVDD2
IOUTN3
IOUTP3
AGND
FSADJ3
FSADJ4
REFIO
CLKGND
CLKN
CLKP
CLDO
E
A
E
A
23
24
25
CLKVDD
FSADJ2/CAL_SENSE
FSADJ1
26
27
AGND
IOUTP1
Description
SPI Clock Input.
SPI Data Input/Output. Primary bidirectional data line for the SPI port.
Digital Ground.
1.8 V Internal Digital LDO1 Output. When the internal digital LDO1 is enabled, this pin should be bypassed
with a 0.1 µF capacitor.
3.3 V External Digital Power Supply. DVDD defines the level of the digital interface of the AD9106 (SPI
interface).
1.8 V Internal Digital LDO2 Outputs. When the internal digital LDO2 is enabled, this pin should be bypassed
with a 0.1 µFcapacitor.
Digital I/O Pin.
In 4-wire SPI mode, this pin outputs the data from the SPI.
In double SPI mode, this pin is a second data input line, SDI2, for the SPI port used to write to the SRAM.
In data output mode, this terminal is a programmable pulse output.
SPI Port Chip Select, Active Low.
Active Low Reset Pin. Resets registers to their default values.
DAC4 Current Output, Positive Side.
DAC4 Current Output, Negative Side.
1.8 V to 3.3 V Power Supply Input for DAC3 and DAC4.
DAC3 Current Output, Negative Side.
DAC3 Current Output, Positive Side.
Analog Ground.
External Full-Scale Current Output Adjust for DAC3.
External Full-Scale Current Output Adjust for DAC4.
DAC Voltage Reference Input/Output.
Clock Ground.
Clock Input, Negative Side.
Clock Input, Positive Side.
Clock Power Supply Output (Internal Regulator in Use), Clock Power Supply Input (Internal Regulator
Bypassed).
Clock Power Supply Input.
External Full-Scale Current Output Adjust for DAC2 or Sense Input for Automatic IOUTFS Calibration.
External Full-Scale Current Output Adjust for DAC1 or Full-Scale Current Output Adjust Reference for
Automatic IOUTFS Calibration.
Analog Ground.
DAC1 Current Output, Positive Side.
Rev. A | Page 11 of 48
AD9106
Pin No.
28
29
30
31
32
Data Sheet
Mnemonic
IOUTN1
AVDD1
IOUTN2
IOUTP2
TRIGGER
EPAD
E
A
Description
DAC1 Current Output, Negative Side.
1.8 V to 3.3 V Power Supply Input for DAC1 and DAC2.
DAC2 Current Output, Negative Side.
DAC2 Current Output, Positive Side.
Pattern Trigger Input.
Exposed Pad. The exposed pad must be connected to DGND.
Rev. A | Page 12 of 48
Data Sheet
AD9106
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, internal CLDO, DLDO1, and DLDO2.
–50
–50
–55
–55
–60
–60
SFDR
8mA
–65
–70
THIRD (dBc)
–75
–70
SFDR (dBc)
LEVEL (dBc)
–65
–80
–75
2mA
–80
4mA
–85
–85
SECOND (dBc)
–90
–95
–100
0
10
20
30
40
50
60
70
FOUT (MHz)
11121-003
–95
–100
0
30
40
50
60
70
60
70
Figure 6. SFDR at Three IOUTFS vs. FOUT
–50
–50
–55
–55
–60
–60
–65
–65
–70
–70
SFDR (dBc)
LEVEL (dBc)
20
FOUT (MHz)
Figure 3. SFDR, 2nd and 3rd Harmonics at IOUTFS = 8 mA vs. FOUT
SFDR
–75
10
11121-006
–90
–80
–75
–40°C
–80
–85
–85
–90
–90
+85°C
SECOND (dBc)
THIRD (dBc)
–100
0
10
20
30
40
50
60
70
FOUT (MHz)
–100
0
20
30
40
50
FOUT (MHz)
Figure 4. SFDR, 2nd and 3rd Harmonics at IOUTFS = 4 mA vs. FOUT
Figure 7. SFDR at Three Temperatures vs. FOUT
–50
–50
–55
–55
–60
–60
–65
100MHz
–65
180MHz
50MHz
SFDR
–75
–80
–70
SFDR (dBc)
–70
SECOND (dBc)
–75
–80
–85
–85
–90
–90
THIRD (dBc)
–95
–100
0
10
20
30
40
50
60
70
FOUT (MHz)
–100
0
10
20
30
40
50
FOUT (MHz)
Figure 5. SFDR, 2nd and 3rd Harmonics at IOUTFS = 2 mA vs. FOUT
Figure 8. SFDR at Three FDAC vs. FOUT
Rev. A | Page 13 of 48
60
70
11121-008
–95
11121-005
LEVEL (dBc)
10
11121-007
–95
11121-004
–95
+25°C
AD9106
Data Sheet
REF –5dBm
MKR3 41.73MHz
–90.031dBm
ATTEN 18dB
–60
–65
1
–70
DAC4
IMD (dBc)
–75
–80
DAC2
DAC3
–85
DAC1
–90
–95
3
–100
0
10
20
30
40
50
60
70
80
FOUT (MHz)
MARKER
1
2
3
VBW 5.6kHz
TRACE
(1)
(1)
(1)
TYPE
FREQ
FREQ
FREQ
X-AXIS
13.87MHz
27.87MHz
41.73MHz
STOP 80MHz
SWEEP 3.076s (601PTS)
AMPLITUDE
–11.13dBm
–88.70dBm
–90.03dBm
11121-009
START 0Hz
Figure 12. IMD vs. FOUT, All Four DACs
Figure 9. Output Spectrum FOUT = 13.87 MHz
–130
–60
–135
–65
100MHz
180MHz
–140
–80
–85
–145
–150
8mA
–155
–90
–160
–95
–165
4mA
0
10
20
30
40
50
60
70
80
FOUT (MHz)
–170
11121-010
–100
2mA
0
10
20
30
40
50
60
70
80
90
80
90
FOUT (MHz)
Figure 10. IMD vs. FOUT, Three FDAC Values
Figure 13. NSD vs. FOUT, Three IOUTFS Values
–60
–130
–65
–135
8mA
–140
–75
–145
–80
NSD (dBm/Hz)
–70
2mA
4mA
–85
–150
–155
–40°C
–90
–160
–95
–165
–100
–170
+25°C
0
10
20
30
40
50
60
FOUT (MHz)
70
80
11121-011
+85°C
0
10
20
30
40
50
60
70
FOUT (MHz)
Figure 11. IMD vs. FOUT, Three IOUTFS Values
Figure 14. NSD vs. FOUT at Three Temperatures
Rev. A | Page 14 of 48
11121-014
IMD (dBc)
–75
NSD (dBm/Hz)
50MHz
11121-013
–70
IMD (dBc)
11121-012
2
Data Sheet
AD9106
0.4
–80
FS = 175MHz, 10MHz
FS = 175MHz, 10.9375MHz
FS = 175MHz, 20MHz
0.3
–100
PHASE NOISE (dBc/Hz)
DNL (LSB)
0.2
0.1
0
–0.1
–120
–140
–0.3
0
500
1000
1500
2000
2500
3000
3500
4000
4500
CODE
11121-015
2mA
4mA
8mA
–180
100
0.4
0.3
0.1
0
–0.1
2mA
4mA
8mA
500
1000
1500
2000
2500
3000
3500
CODE
4000
4500
11121-016
INL (LSB)
0.2
0
100k
Figure 17. Phase Noise
0.5
–0.3
10k
OFFSET (Hz)
Figure 15. DNL, Three IOUTFS Values
–0.2
1k
Figure 16. INL, Three IOUTFS Values
Rev. A | Page 15 of 48
1M
10M
11121-017
–160
–0.2
AD9106
Data Sheet
AVDD = 1.8 V, DVDD = DLDO1 = DLDO2 = 1.8 V, CLKVDD = CLDO = 1.8 V.
–50
–50
–55
–55
–60
–60
–65
–65
–70
SFDR (dBc)
SFDR
–75
–80
–75
–80
–40°C
+25°C
THIRD (dBc)
–85
–85
SECOND (dBc)
–90
–90
–95
–100
0
10
20
30
40
50
60
70
FOUT (MHz)
11121-018
–95
–100
0
10
20
30
40
50
60
70
FOUT (MHz)
Figure 18. SFDR, 2nd and 3rd Harmonics at IOUTFS = 4 mA vs. FOUT
11121-022
LEVEL (dBc)
+85°C
–70
Figure 21. SFDR at Three Temperatures vs. FOUT
–50
–50
–55
–55
–60
–60
–65
–65
SFDR
–70
–75
–80
180MHz
–70
SFDR (dBc)
LEVEL (dBc)
180MHz
50MHz
–75
–80
SECOND (dBc)
–85
–85
–90
–95
–95
–100
0
10
20
30
40
50
60
70
FOUT (MHz)
11121-019
–90
–100
0
10
20
30
40
50
60
70
FOUT (MHz)
Figure 22. SFDR at Three FDAC vs. FOUT
Figure 19. SFDR, 2nd and 3rd Harmonics at IOUTFS = 2 mA vs. FOUT
–50
REF –5dBm
MKR3 41.73MHz
–88.255dBm
ATTEN 18dB
–55
1
–60
–65
–75
–80
4mA
–85
–90
–95
0
10
20
30
40
50
FOUT (MHz)
60
70
3
TYPE
FREQ
FREQ
FREQ
X-AXIS
13.87MHz
27.87MHz
41.73MHz
START 0Hz
MARKER
1
2
3
Figure 20. SFDR at Two IOUTFS vs. FOUT
VBW 5.6kHz
TRACE
(1)
(1)
(1)
STOP 80MHz
SWEEP 3.076s (601PTS)
AMPLITUDE
–11.13dBm
–89.05dBm
–88.25dBm
Figure 23. Output Spectrum FOUT = 13.87 MHz
Rev. A | Page 16 of 48
11121-024
–100
2
11121-021
SFDR (dBc)
2mA
–70
11121-023
THIRD (dBc)
Data Sheet
AD9106
–60
–130
–65
–135
100MHz
–140
IMD (dBc)
NSD (dBm/Hz)
180MHz
–75
50MHz
–80
–85
–145
–150
4mA
–155
–90
–160
–95
–165
0
10
20
30
40
50
60
70
80
FOUT (MHz)
–170
11121-025
–100
2mA
0
30
40
50
60
70
80
90
80
90
4000
4500
Figure 27. NSD vs. FOUT, Two IOUTFS Values
–60
–130
–65
–135
–140
4mA
NSD (dBm/Hz)
–75
IMD (dBc)
20
FOUT (MHz)
Figure 24. IMD vs. FOUT, Three FOUT Values
–70
10
11121-028
–70
–80
–85
–145
–150
+85°C
+25°C
–155
2mA
–90
–160
–95
–165
10
20
30
40
50
60
70
80
FOUT (MHz)
–170
11121-026
0
0
20
30
40
50
60
70
FOUT (MHz)
Figure 25. IMD vs. FOUT, Two IOUTFS Values
Figure 28. NSD vs. FOUT at Three Temperatures
–60
0.5
2mA
4mA
DAC4
–65
0.4
DAC3
–70
0.3
–75
DNL (LSB)
DAC2
–80
0.2
0.1
–85
DAC1
0
–90
–100
0
10
20
30
40
50
60
FOUT (MHz)
70
80
–0.2
0
500
1000
1500
2000
2500
3000
3500
CODE
Figure 26. IMD vs. FOUT, All Four DACs
Figure 29. DNL, Three IOUTFS Values
Rev. A | Page 17 of 48
11121-030
–0.1
–95
11121-027
IMD (dBc)
10
11121-029
–40°C
–100
AD9106
Data Sheet
0.5
0.4
0.3
0.1
0
–0.1
–0.2
2mA
4mA
–0.3
0
500
1000
1500
2000
2500
3000
3500
CODE
4000
4500
11121-031
INL (LSB)
0.2
Figure 30. INL, Two IOUTFS Values
Rev. A | Page 18 of 48
Data Sheet
AD9106
TERMINOLOGY
Linearity Error (Integral Nonlinearity or INL)
INL is defined as the maximum deviation of the actual analog
output from the ideal output, determined by a straight line
drawn from zero to full scale.
Power Supply Rejection
Power supply rejection is the maximum change in the full-scale
output as the supplies are varied from nominal to minimum
and maximum specified voltages.
Differential Nonlinearity (DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Settling Time
Settling time is the time required for the output to reach and
remain within a specified error band about its final value,
measured from the start of the output transition.
Monotonicity
A digital-to-analog converter is monotonic if the output either
increases or remains constant as the digital input increases.
Offset Error
Offset error is the deviation of the output current from the ideal of
zero. For IOUTPx, 0 mA output is expected when the inputs are all
0s. For IOUTNz, 0 mA output is expected when all inputs are set to 1.
Gain Error
Gain error is the difference between the actual and ideal output
span. The actual span is determined by the output when all inputs
are set to 1, minus the output when all inputs are set to 0. The
ideal gain is calculated using the measured VREF. Therefore,
the gain error does not include effects of the reference.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in picovolt-seconds (pV-s).
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the output signal and the peak spurious signal
over the specified bandwidth.
Noise Spectral Density (NSD)
Noise spectral density is the average noise power normalized to
a 1 Hz bandwidth, with the DAC converting and producing an
output tone.
Output Compliance Voltage
Output compliance voltage is the range of allowable voltage
at the output of a current output DAC. Operation beyond the
maximum compliance limits can cause either output stage
saturation or breakdown, resulting in nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from
the ambient (25°C) value to the value at either TMIN or TMAX.
For offset and gain drift, the drift is reported in ppm of fullscale range (FSR) per °C. For reference drift, the drift is
reported in ppm per °C.
Rev. A | Page 19 of 48
AD9106
Data Sheet
DAC1 TO DAC2
TIMERS + STATE MACHINES
FSADJ1
FSADJ2/CAL_SENSE
RESET
SCLK
SDO/SDI2/DOUT
SDIO
REFIO
AGND
RSET2
16kΩ
GAIN1
RSET1
16kΩ
IREF
100µA
OFFSET1
DAC1
DAC CLOCK
TRIGGER
10kΩ
SPI
INTERFACE
DDS1
START DLY
1V
RANDOM1
STOP ADDR
START ADDR
CONSTANT1
AD9106
SAWTOOTH1
CS
THEORY OF OPERATION
IOUTP1
DAC1
IOUTN1
ADDRESS 1, 2
AVDD1
GAIN2
IOUTP2
OFFSET2
DAC2
DAC2
DPRAM
GAIN3
IOUTN2
BAND
GAP
IOUTP3
OFFSET3
DAC3
DAC3
IOUTN3
DAC CLOCK
AVDD2
IOUTP4
GAIN4
ADDRESS 3, 4
DAC4
OFFSET4
IOUTN4
DAC4
DAC3 TO DAC4
TIMERS + STATE MACHINES
PHASE1
DDS1
START DLY
TUNING WORD
STOP ADDR
DAC CLOCK
1.8V
LDO
CLOCK
DIST
RSET3
16kΩ
11121-032
FSADJ4
FSADJ3
CLKP
CLKN
CLKVDD
CLDO
PHASE4
DGND
PHASE3
DLDO2
DDS3
DDS4
1.8V
LDOs
DLDO1
DDS2
DDS
CLKGND
START ADDR
DVDD
RSET4
16kΩ
PHASE2
Figure 31. AD9106 Block Diagram
Figure 31 is a block diagram of the AD9106. The AD9106 has
four 12-bit current output DACs.
The DACs use a single common voltage reference. An on-chip
band gap reference is provided. Optionally, an off-chip voltage
reference may be used. Full-scale DAC output current, also
known as gain, is governed by the current, IREF. IREF is the
current that flows through each IREF resistor. Each DAC has its
own IREF set resistor. These resistors may be on or off chip at
the discretion of the user. When on-chip RSET resistors are in
use DAC gain accuracy can be improved by employing the
product’s built in automatic gain calibration capability. Automatic calibration may be used with the on-chip reference or
an external REFIO voltage. A procedure for automatic gain
calibration is presented in this section.
The power supply rails for the AD9106 are AVDD for analog
circuits, CLKVDD/CLDO for clock input receiver and
DVDD/DLDO1/DLDO2 for digital I/O and for the on-chip
digital data path. AVDD, DVDD, and CLKVDD can range from
1.8 V to 3.3 V nominal. DLDO1, DLDO2, and CLDO run at
1.8 V. If DVDD = 1.8 V, then DLDO1 and DLDO2 should both
be connected to DVDD, with the on-chip LDOs disabled. All
three supplies are provided externally in this case. This also
applies to CLKVDD and CLDO if CLKVDD = 1.8 V.
Digital signals input to the four DACs are generated by on-chip
digital waveform generation resources. Twelve-bit samples are
input to each DAC at the CLKP/CLKN sample rate from a
dedicated digital data path. Each DAC’s data path includes gain
and offset corrections and a digital waveform source selection
multiplexer. Waveform sources are SRAM, direct digital
synthesizer (DDS), DDS output amplitude modulated by SRAM
data, a sawtooth generator, dc constant, and a pseudo-random
sequence generator. The waveforms output by the source
selection multiplexer have programmable pattern characteristics. The waveforms can be set up to be continuous,
continuous pulsed (fixed pattern period and start delay within
each pattern period), or finite pulsed (a set number of pattern
periods are output, then the pattern stops).
Pulsed waveforms (finite or continuous) have a programmed
pattern period and start delay. The waveform is present in each
Rev. A | Page 20 of 48
Data Sheet
AD9106
pulse period following the global (applies to all four DACs)
programmed pattern period start and each DAC’s start delay.
When the first bit of this command byte is a logic low (RW
bit = 0), the SPI command is a write operation. In this case,
SDIO remains an input (see Figure 32).
E
An SPI port enables loading of data into SRAM and programming of all the control registers inside the device.
COMMAND CYCLE
SPI PORT
E
A
DB14
A14
11121-033
E
A
A
A
E
A
COMMAND CYCLE
A
DATA TRANSFER CYCLE
CS
SCLK
DB13
A13
DB12
A12
…
…
DB2
A2
DB1
A1
READ
Rev. A | Page 21 of 48
11121-035
D00
D10
D15N – 2
D0N – 1
D0N
Figure 34. Serial Register Interface Timing, MSB First Read, 4-Wire SPI
D15N – 1
A0
A1
D15N
SDO/
SDI2/
DOUT
A2
A13
A14
R/W
D0
D1
A0
D15
A1
A2
A13
SCLK
A14
11121-034
Figure 33. Serial Register Interface Timing, MSB First Read, 3-Wire SPI
LSB
DB0
A0
WRITE
R/W
D00
D10
D20
D30
D13N
D14N
D15N
A0
A1
A2
A13
A14
SDIO
R/W
A
CS
SDIO
D0N
D1N
D2N
D3N
D13N
D14N
A0
D15N
A1
A2
When the first bit of this command byte is a logic high (RW
bit = 1), the SPI command is a read operation. In this case, data
is driven out of the SPI port as shown in Figure 33 and Figure 34.
The SPI communication finishes after the CS pin goes high.
Table 12. Command Word
E
A13
Figure 32. Serial Register Interface Timing, MSB First Write, 3-Wire SPI
E
A
A14
SDIO
E
A
R/W
SCLK
The SPI interface operates as a standard synchronous serial
communication port. CS is a low true chip select. When CS
goes true, SPI address and data transfer begins. The first bit
coming from the SPI master on SDIO is a read/write indicator
(high for read, low for write). The next 15-bits are the initial
register address. The SPI port automatically increments the
register address if CS stays low beyond the first data word
allowing writes to or reads from a set of contiguous addresses.
A
DATA TRANSFER CYCLE
CS
The AD9106 provides a flexible, synchronous serial communications (SPI) port that allows easy interfacing to ASICs, FPGAs,
and industry standard microcontrollers. The interface allows
read/write access to all registers that configure the AD9106 and
to the on-chip SRAM. Its data rate can be up to the SCLK clock
speed shown in Table 3 and Table 4.
MSB
DB15
RW
A
A
AD9106
Data Sheet
Writing to On-Chip SRAM
IOUTFSx = 32 × IIREFx
(3)
The AD9106 includes an internal 4096 × 12 SRAM. The SRAM
address space is 0x6000 to 0x6FFF of the AD9106 SPI address map.
where:
IREFx = VREFIO/xRSET
(4)
Double SPI for Write for SRAM
IREFx is the current that flows through each IREFx resistor. Each
DAC has its own IREF set resistor. IREF resistors may be on or off
chip at the users’ discretion. When on-chip xRSET resistors are
in use, DAC gain accuracy can be improved by employing the
product’s built in automatic gain calibration capability.
The time to write data to the entire SRAM can be halved using
the SPI access mode shown in Figure 35. The SDO/SDI2/
DOUT line becomes a second serial data input line, doubling
the achievable update rate of the on-chip SRAM. SDO/SDI2/
DOUT is write-only in this mode. The entire SRAM can be
written in (2 + 2 × 4096) × 8/(2 × FSCLK) seconds.
Optimum linearity and noise performance of DAC outputs
can be achieved when they are connected differentially to an
amplifier or a transformer. In these configurations, commonmode signals at the DAC outputs are rejected.
WAVEFORM DATA TO BE WRITTEN
D00
D10
D0N – 1
D15 N – 2
D0N
D15 N – 1
The output compliance voltage specifications shown in
Table 1 and Table 2 must be adhered to for the performance
specifications in these tables to be met.
D0N + 1
D1N + 1
D0M – 1
D15 M – 2
SETTING IOUTFSx, DAC GAIN
11121-036
WAVEFORM PATTERN
ADDRESS2 = M
D0M
WAVEFORM
PATTERN DATA
D15 M
A0
A1
A2
A13
A14
SDO/
SDI2/
DOUT
R/W = 0
ALWAYS
WAVEFORM PATTERN
ADDRESS1 = N
D15 M – 1
A0
D15 N
A1
A2
A13
A14
SDIO
R/W
SCLK
WAVEFORM
PATTERN DATA
Figure 35. Double SPI Write of SRAM Data
Configuration Register Update Procedure
Most SPI accessible registers are double buffered. An active
register set controls operation of the AD9106 during pattern
generation. A set of shadow registers stores updated register
values. Register updates can be written at any time and when
the configuration update is complete, a 1 is written to the
UPDATE bit in the RAMUPDATE register. The UPDATE bit
arms the register set for transfer from shadow registers to active
registers. The AD9106 will perform this transfer automatically
the next time the pattern generator is off. This procedure does
not apply to the 4K × 12 SRAM. Refer to the SRAM section for
the SRAM update procedure.
As expressed in Equation 3 and Equation 4, DAC gain (IOUTFSx)
is a function of the reference voltage at the REFIO terminal and
xRSET for each DAC.
Voltage Reference
The AD9106 contains an internal 1.0 V nominal band gap
reference. The internal reference may be used. Alternatively,
it can be replaced by a more accurate off-chip reference. An
external reference can provide tighter reference voltage
tolerances and/or lower temperature drift than the on-chip
band gap.
By default, the on-chip reference is powered up and ready to be
used. When using the on-chip reference, the REFIO terminal
needs to be decoupled to AGND using a 0.1 μF capacitor as
shown in Figure 36.
AD9106
VBG
1.0V
DAC TRANSFER FUNCTION
REFIO
The AD9106 DACs provide four differential current outputs:
IOUTP1/IOUTN1, IOUTP2/IOUTN2, IOUTP3/IOUTN3, and
IOUTP4/IOUTN4.
CURRENT
SCALING
x32
–
0.1µF
xRSET
IOUTFSx
IREFx
AVSS
(1)
12
IOUTNx = IOUTFSx × ((2 − 1) − xDAC INPUT CODE)/2
12
+
FSADJx
The DAC output current equations are as follows:
IOUTPx= IOUTFSx × xDAC INPUT CODE/2
DACx
11121-037
CS
SET WAVEFORM ADDRESS
TO BE READ/WRITTEN
ANALOG CURRENT OUTPUTS
12
(2)
where:
xDAC INPUT CODE = 0 to 212 − 1.
IOUTFSx = full-scale current or DAC gain set independently for
each DAC.
Figure 36. On-Chip Reference with External xRSET Resistor
Table 13 summarizes reference connections and programming.
Table 13. Reference Operation
Reference Mode
Internal
External
Rev. A | Page 22 of 48
REFIO Pin
Connect 0.1 µF capacitor
Connect off-chip reference
Data Sheet
AD9106
Programming Internal VREFIO
The internal REFIO voltage level is programmable.
When the internal voltage reference is in use, the BGDR field in
the lower six bits in Register 0x03 adjusts the VREFIO level. This
adds or subtracts up to 20% from the nominal band gap voltage
on REFIO. The voltage across the FSADJx resistors tracks this
change. As a result, IREFx varies by the same amount. Figure 37
shows VREFIO vs. BGDR code for an on-chip reference with a
default voltage (BGDR = 0x00) of 1.04 V.
1.30
1.25
1.20
VREFIO (V)
1.15
1.10
1.05
1.00
0.95
0.90
0.80
0
8
16
24
32
CODE
40
48
56
11121-038
0.85
Figure 37. Typical VREF Voltage vs. BGDR
xRSET Resistors
xRSET in Equation 4 for each DAC can be an internal resistor or
a board level resistor of the users choosing connected to the
appropriate FSADJx terminal.
To make use of on-chip xRSET resistors, Bit15 of Register 0x0C,
Register 0x0B, Register 0x0A, and Register 0x09 for DAC1,
DAC2, DAC3, and DAC4, respectively, are set to Logic 1.
Bits[4:0] of Register 0x0C, Register 0x0B, Register 0x0A, and
Register 0x09 are used to manually program values for the on-chip
xRSET associated with DAC1, DAC2, DAC3, and DAC4,
respectively.
AUTOMATIC IOUTFSX CALIBRATION
Many applications require tight DAC gain control. The AD9106
provides an automatic IOUTFSx calibration procedure used with
on-chip xRSET resistors only. The voltage reference VREFIO can be
the on-chip reference or an off-chip reference. The automatic
calibration procedure does a fine adjustment of each internal
xRSET value and each current IREFx .
When using automatic calibration the following board-level
connections are required:
1.
2.
Connect FSADJ1 and FSADJ2/CAL_SENSE together.
A resistor should be installed between FSADJ2/
CAL_SENSE and ground. The value of this resistor should
be RCAL_SENSE = 32 × VREFIO/IOUTFS where IOUTFS is the target
full-scale current for all four DACs.
Automatic calibration uses an internal clock. This calibration
clock is equal to the DAC clock divided by the division factor
chosen by the CAL_CLK_DIV bits of Register 0x0D. Each
calibration cycle is between 4 and 512 DAC clock cycles,
depending on the value of CAL_CLK_DIV[2:0]. The frequency
of the calibration clock should be less than 500 kHz.
To perform an automatic calibration, follow these steps:
1.
Set the calibration ranges in Registers 0x08[7:0] and
0x0D[5:4] to their minimum values to allow best
calibration.
2. Enable the calibration clock bit, CAL_CLK_EN, in
Register 0x0D.
3. Set the divider ratio for the calibration clock by setting
CAL_CLK_DIV[2:0] bits in Register 0x0D. The default is
512.
4. Set the CAL_MODE_EN bit in Register 0x0D to Logic 1.
5. Set the START_CAL bit in Register 0x000E to Logic 1. This
begins the calibration of the comparator, xRSET and gain.
6. The CAL_MODE flag in Register 0x000D will go to
Logic 1 while the part is calibrating. The CAL_FIN flag in
Register 0x0E will go to Logic 1 when the calibration is
complete.
7. Set the START_CAL bit in Register 0x0E to Logic 0.
8. After calibration, verify that the overflow and underflow
flags in Register 0x0D are not set (Bits[14:8]). If they are,
change the corresponding calibration range to the next
larger range and begin again at Step 5.
9. If no flag is set, read the DACx_RSET_CAL and
DACx_AGAIN_CAL values in the DACxRSET[12:8] and
DACxGAIN[14:8] registers, respectively, and write them
into their corresponding DACxRSET and DACxAGAIN
registers.
10. Reset the CAL_MODE_EN bit and the calibration clock bit
CAL_CLK_EN in Register 0x0D to Logic 0 to disable the
calibration clock.
11. Set the CAL_MODE_EN bit in Register 0x0D to Logic 0.
This sets the RSET and gain control muxes towards the
regular registers.
12. Disable the calibration clock bit, CAL_CLK_EN, in
Register 0x0D.
To reset the calibration, pulse the CAL_RESET bit in Register 0x0D
to Logic 1 and Logic 0, pulse the RESET pin, or pulse the RESET bit
in the SPICONFIG register.
E
A
CLOCK INPUT
For optimum DAC performance, the AD9106 clock input signal
pair (CLKP/CLKN) should be a very low jitter, fast rise time
differential signal. The clock receiver generates its own commonmode voltage requiring these two inputs to be ac-coupled.
Figure 38 shows the recommended interface to a number of
Analog Devices, Inc., LVDS clock drivers that work well with the
AD9106. A 100 Ω termination resistor and two 0.1 µF coupling
capacitors are used. Figure 40 shows an interface to an Analog
Devices differential PECL driver. Figure 41 shows a single-endedto-differential converter using a balun driving CLKP/CLKN, the
preferred methods for clocking the AD9106.
Rev. A | Page 23 of 48
AD9106
Data Sheet
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515/
AD9516/AD9518
0.1µF
CLK+
GENERATING SIGNAL PATTERNS
0.1µF
CLK–
CLKP
100Ω
LVDS DRIVER
•
•
•
AD9106
0.1µF
CLKN
CLK
50Ω*
11121-039
50Ω*
The AD9106 can generate three types of signal patterns under
control of its programmable pattern generator.
0.1µF
CLK
*50Ω RESISTORS ARE OPTIONAL.
Run Bit
Figure 38. Differential LVDS Clock Input
Setting the RUN bit in the PAT_STATUS register to 1 arms the
AD9106 for pattern generation. Clearing this bit shuts down the
pattern generator as shown in Figure 45.
In applications where the analog output signals are at low
frequencies, it is acceptable to drive the AD9106 clock input
with a single-ended CMOS signal. Figure 39 shows such an
interface. CLKP is driven directly from a CMOS gate, and the
CLKN pin is bypassed to ground with a 0.1 μF capacitor in
parallel with a 39 kΩ resistor. The optional resistor is a series
termination.
Trigger Terminal
A falling edge on the trigger terminal starts the generation of a
pattern. If RUN is set, the falling edge of trigger starts pattern
generation. As shown in Figure 43, the pattern generator state
goes to “pattern on” a number of CLKP/CLKN clock cycles
following the falling edge of trigger. This delay is programmed
in the PATTERN_DELAY bit field.
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515/
AD9516/AD9518
0.1µF
CLK+
CLK
50Ω
CMOS DRIVER
The rising edge on the trigger terminal is a request for the
termination of pattern generation (see Figure 44).
CLKP
OPTIONAL
100Ω
CLK
AD9106
Pattern Bit (Read Only)
0.1µF
CLKN
39kΩ
The read-only PATTERN bit in the PAT_STATUS register
indicates, when set to 1, that the pattern generator is in the
“pattern on” state. A 0 indicates that the pattern generator is in
the “pattern off ” state.
11121-040
0.1µF
Figure 39. Single-Ended 1.8 V CMOS Sample Clock
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515/
AD9516/AD9518
0.1µF
CLK+
0.1µF
CLKP
CLK
100Ω
PECL DRIVER
0.1µF
CLK–
CLKN
240Ω
240Ω
11121-041
50Ω*
AD9106
0.1µF
CLK
50Ω*
*50Ω RESISTORS ARE OPTIONAL.
Figure 40. Differential PECL Sample Clock
Mini-Circuits®
ADT1-1WT, 1:1Z
0.1µF
0.1µF
XFMR
CLK+
CLKP
50Ω
AD9106
0.1µF
Continuous waveforms
Periodic pulse train waveforms that repeat indefinitely
Periodic pulse train waveforms that repeat a finite number
of times
11121-042
CLKN
SCHOTTKY
DIODES:
HSM2812
Figure 41. Transformer Coupled Clock
DAC OUTPUT CLOCK EDGE
Each of the four DACs can be configured independently to
output samples on the rising or falling edge of the CLKP/CLKN
clock input by configuring the DACx_INV_CLK bits in the
CLOCKCONFIG register. This functionality sets the DAC
output timing resolution at 1/(2 × FCLKP/CLKN).
Rev. A | Page 24 of 48
Data Sheet
AD9106
Pattern Types
Setting Waveform Start Delay Base
•
The waveform start delay base is programmed in the
START_DELAY_BASE field of the PAT_TIMEBASE register.
Each DACx has a START_DLYx register described in
the DACX Input Data Paths section. The start delay base
determines how many CLKP/CLKN clock cycles there are
per START_DELAYx LSB.
•
•
Continuous waveforms are output by some or all DACx for
the duration of the pattern on state of the pattern
generator. Continuous waveforms ignore pattern periods.
Periodic pulse trains that repeat indefinitely are waveforms
that are output once during each pattern period. Pattern
periods occur one after the other as long as the pattern
generator is in the pattern on state.
Periodic pulse trains that repeat a finite number of times
are just like those that repeat indefinitely except that the
waveforms are output during a finite number of
consecutive pattern periods.
RUN BIT
tDLY = PATTERN_DELAY VALUE + 1
tSU
PATTERN
STARTS
TRIGGER
TRIGGER
PATTERN
EXECUTED
CLKP/
CLKN
PATTERN
EXECUTED
PATTERN_PERIOD
PATTERN
GENERATOR
STATE
START_DLY1
PATTERN
GENERTAOR OFF
PATTERN
GENERTAOR ON
11121-044
PATTERN
EXECUTED
Figure 43. Trigger Initiated Pattern Start with Pattern Delay
DAC1
tSU
DATA @
START_ADDR.1
DATA @
STOP_ADDR.1
TRIGGER
START_DLY2
DAC2
DATA @
START_ADDR.2
DATA @
STOP_ADDR.2
CLKP/
CLKN
START_DLY3
PATTERN
GENERATOR
STATE
DAC3
PATTERN OFF
PATTERN
STOPS
DATA @
STOP_ADDR.3
11121-045
DATA @
START_ADDR.3
PATTERN ON
START_DLY4
DATA @
START_ADDR.4
11121-043
DAC4
DATA @
STOP_ADDR.4
Figure 44. Trigger Rising Edge Initiated Pattern Stop
Figure 42. Periodic Pulse Trains output on all DACx
RUN
BIT
PATTERN GENERATOR PROGRAMMING
Setting Pattern Period
Two register bit fields are used to set the pattern period. The
PAT_PERIOD_BASE field in the PAT_TIMEBASE register sets
the number of CLKP/N clock per PATTERN_PERIOD LSB.
The PATTERN_PERIOD is programmed in the PAT_PERIOD
register. The longest pattern period available is 65535 ×
16/FCLKP/CLKN.
CLKP/
CLKN
PATTERN
GENERATOR
STATE
PATTERN ON
PATTERN OFF
PATTERN
STOPS
11121-046
Figure 44 shows periodic pulse train waveforms as seen at
the output to each of the four DACx. The four waveforms are
generated in each pattern period. Each has its own start delay
(START_DLYx), a delay between the start of each pattern
period and the start of the waveform. The four DACx
waveforms are the same digital signal stored in SRAM and
multiplied by the DACx digital gain factor. The SRAM data
is read using each DACx address counter simultaneously.
Figure 45. RUN Bit Driven Pattern Stop
DACx INPUT DATA PATHS
Each of the four DACx has its own digital data path. Timing
in the DACx data paths is governed by the pattern generator.
Each DACx data path includes a waveform selector, a waveform
repeat controller, RAM output and DDS output multiplier
(RAM output can amplitude modulate DDS output), DDSx
cycle counter, DACx digital gain multiplier, and a DACx digital
offset summer.
Rev. A | Page 25 of 48
AD9106
Data Sheet
DACx Digital Gain Multiplier
Manually Controlled DOUT
On its way into each DACx, the samples are multiplied by a
12-bit gain factor that has a range of ±2.0. These gain values are
programmed in the DACx_DGAIN registers.
If DOUT_MODE = 0 in the DOUT_CONFIG register, DOUT can
be turned on or off using the DOUT_VAL bit of that same register.
DACx Digital Offset Summer
Figure 46 depicts the rising edge of a pattern generator
controlled DOUT pulse. Figure 47 shows the falling edge.
Pattern generator controlled DOUT is set by setting
DOUT_MODE = 1. Then, the start delay is programmed in the
DOUT_START_DLY register and the stop delay is programmed
into the DOUT_STOP field of the DOUT_CONFIG register.
DACx input samples are summed with a 12-bit dc offset
value as well. The dc offset values are programmed in the
DACxDOF registers.
DACx Waveform Selectors
Waveform selector inputs are
DOUT goes high DOUT_START[15:0] CLKP/CLKN cycles
after the falling edge of the signal input to the trigger terminal.
DOUT stays high as long as a pattern is being generated. DOUT
goes low DOUT_STOP[3:0] CLKP/CLKN cycles after the clock
edge that causes pattern generation to stop.
DACx sawtooth generator output
DACx pseudo random sequence generator output
DACx dc constant generator output
DACx pulsed, phase shifted DDS sine wave output
RAM output
DACx pulsed, phase shifted DDS sine wave output
amplitude modulated by ram output
DOUT DELAY=
DOUT_START[15:0] CLKP/CLKN CYCLES
tSU
Waveform selection for each DACx is made by programming
the WAVEx_yCONFIG registers.
TRIGGER
DACx Pattern Period Repeat Controller
CLKP/
CLKN
The PATTERN_RPT bit in the PAT_TYPE register controls
whether the pattern output auto repeats (periodic pulse train
repeats indefinitely) or repeats a number of consecutive times
defined by the DACx_REPEAT_CYCLE fields. The latter are
periodic pulse trains that repeat a finite number of times.
11121-047
•
•
•
•
•
•
Pattern Generator Controlled DOUT
DOUT
Figure 46. DOUT Start Sequence
PATTERN
STOPS
DACx, Number of DDS Cycles
PATTERN
GENERATOR
STATE
PATTERN ON
PATTERN OFF
CLKP/CLKN
DACx DDS Phase Shift
DOUT DELAY = DOUT_STOP[3:0]
CLKP/CLKN CYCLES
Each DACx input data path shifts the phase of the output of the
single common DDS. The phase shift is programmed using the
DDSx_PHASE fields.
11121-048
Each DACx input data path establishes the pulse width of the
sine wave output from the single common DDS in number
of sine wave cycles. The cycle counts are programmed in
DDS_CYCx registers.
DOUT
Figure 47. DOUT Stop Sequence
DOUT FUNCTION
DIRECT DIGITAL SYNTHESIZER (DDS)
In applications where AD9106 DACs drive high voltage
amplifiers, such as in ultrasound transducer array element
driver signal chains, it can be useful to turn on and off each
amplifier at precise times relative to the waveform generated by
each AD9106 DAC. The SDO/SDI2/DOUT terminal, can be
configured to provide this function. One amplifier on/off strobe
can be provided for all four DACs.
The direct digital synthesizer generates a sine wave that can be
output on any of the four DACx. The DDS is a global shared
signal resource. It can generate one sinusoid at a frequency
determined by its tuning word input. The tuning word is 24 bits
wide. The resolution of DDS tuning is FCLKP/CLKN/224. The DDS
output frequency is DDS_TW × FCLKP/CLKN/224.
The SPI interface needs to be configured in 3-wire mode (see
Figure 32 and Figure 33). This is accomplished by setting the
SPI3WIRE or SPI3WIREM bits in the SPICONFIG register.
When SPID_RV or SPI_DRVM of the SPICONFIG register is
set to Logic 1, the SDO/SDI2/DOUT terminal provides the
DOUT function.
The DDS tuning word is programmed using one of two
methods. For a fixed frequency, DDSTW_MSB and
DDSTW_LSB are programmed with a constant. When the
frequency of the DDS needs to change within each pattern
period, a sequence of values stored in SRAM is combined with
a selection of DDSTW_MSB bits to form the tuning word.
Rev. A | Page 26 of 48
Data Sheet
AD9106
The AD9106 4K × 12 SRAM can contain signal samples,
amplitude modulation patterns, lists of DDS tuning words, or
lists of DDS output phase offset words. Data is written to and
read from the memory via the SPI port as long as the SRAM is
not actively engaged in pattern generation (RUN = 0). To write
to SRAM, set up the PAT_STATUS register as follows:
•
•
•
NEGATIVE
SAWTOOTH
TRIANGLE
WAVE
BUF_READ = 0
MEM_ACCESS = 1
RUN = 0
Figure 48. Sawtooth Patterns
To read data from SRAM, set up the PAT_STATUS as follows:
•
•
•
POSITIVE
SAWTOOTH
11121-049
SRAM
BUF_READ = 1
MEM_ACCESS = 1
RUN = 0
The SPI port address space for SRAM is location 0x6000
through 0x6FFF.
PSEUDO-RANDOM SIGNAL GENERATOR
The pseudo-random noise generator generates a noise signal on
each DACx output if “Pseudo-Random Sequence” is selected in
any of the PRESTORE_SELx fields in the WAV4_3CONFIG or
WAV2_1 CONFIG registers. The pseudo-random noise signals
are generated as continuous waveforms only.
DC CONSTANT
SRAM can be accessed using any of the SPI operating modes
shown in Figure 32 through Figure 35. Using the SPI modes of
operation shown in Figure 33 and Figure 34, the entire SRAM
can be written in (2 + 2 × 4096) × 8/FSCLK seconds. The SRAM is
a shared signal generation resource. Data from this one 4K × 12
memory can be used to generate signals for all four DAC.
When the PAT_STATUS register RUN bit = 1 (pattern
generation enabled), each DACx data path has its own
SRAM address counter. Each address counter has its own
START_ADDRx and STOP_ADDRx. During each pattern
period, data is read from RAM after the START_DELAYx
period and while the each address counter is incrementing.
SRAM is read simultaneously by all four DACx data paths.
A programmable dc current between 0.0 and IOUTFSx can be
generated on each DACx if the “Constant Value” in selected in
any of the PRESTORE_SELx fields of the WAV4_3CONFIG
or WAV2_1 CONFIG registers. DC constant currents are
generated as continuous waveforms only. The dc current level is
programmed by writing to the DACx_CONST field in the
appropriate DACx_CST register.
POWER SUPPLY NOTES
The AD9106 supply rails are specified in Table 9. The AD9106
includes three on-chip linear regulators. The supply rails driven
by these regulators are run at 1.8 V. Two usage rules for these
regulators follow.
Incrementing Pattern Generation Mode SRAM Address
Counters
Each of the SRAM address counters can be programmed to be
incremented by CLKP/CLKN (default) or by the rising edge of
the DDSx MSB. DDSx[11:0] are the DDS output samples for a
given DACx. The DDS_MSB_ENx bits in the DDSx_CONFIG
register make this selection.
As an example, DDSx MSB could be used to clock the address
counter when generating a chirp waveform from the DDS using
a list of tuning words in SRAM. Each frequency setting dwells
for one DDS output sinewave cycle.
SAWTOOTH GENERATOR
There is a separate sawtooth signal generator for each DACx.
When the sawtooth is selected in any of the PRESTORE_SELx
fields in the WAV4_3CONFIG or WAV2_1 CONFIG registers,
the appropriate sawtooth generator is connected to the desired
DACx digital data path.
Sawtooth types, shown in Figure 48, are selected using the
SAW_TYPEx fields in the SAWx_yCONFIG registers. The
number of samples per sawtooth waveform step is programmed
in each SAW_STEPx field.
•
•
When CLKVDD is 2.5 V or higher, the 1.8 V on-chip
CLDO regulator may be used. If CLKVDD = 1.8 V, then
the CLDO regulator must be disabled by setting the
PDN_LDO_CLK bit in the POWERCONFIG register.
CLKVDD and CLDO are connected together.
When DVDD is 2.5 V or higher, the 1.8 V on-chip DLDO1
and DLDO2 regulators may be used. If DVVD is 1.8 V, the
DLDO1 and DLDO2 regulators must be disabled by setting
the PDN_LDO_DIG1 and PDN_LDO_DIG2 bits in the
POWERCONFIG register. DVDD, DLDO1, and DLDO2
are connected together.
POWER-DOWN CAPABILITIES
The POWERCONFIG register allows the user to place the
AD9106 in a reduced power dissipation configuration while the
CLKP/CLKN input is running and the power supplies are on.
DAC1, DAC2, DAC3, and DAC4 can all be put to sleep by setting
the DACx_SLEEP bits in the POWERCONFIG register.
Clocking of the waveform generator and the DACs can be turned
off by setting the CLK_PDN bit in the CLOCKCONFIG register.
Taking these actions places the AD9106 in the power-down mode
specified in Table 8.
Rev. A | Page 27 of 48
AD9106
Data Sheet
APPLICATIONS INFORMATION
PATTERN_PERIOD
SIGNAL GENERATION EXAMPLES
START_DLY1 #CYCLES1
AD9106 waveform and pattern generation examples are
provided in this section.
Figure 49 shows a different waveform being generated by each
DACx. The waveforms are all stored in the 4K × 12 SRAM in
different segments. DACx path address counters access the
SRAM simultaneously. Each waveform is repeated once during
each pattern period. In each pattern period a start delay is
executed, then the pattern is read from SRAM.
DAC1
START_DLY2 #CYCLES2
DAC2
#CYCLES3
START_DLY3
TRIGGER
PATTERN
EXECUTED
PATTERN
EXECUTED
PATTERN
EXECUTED
DAC3
#CYCLES4
PATTERN_PERIOD
START_DLY4
START_DLY1
DATA @
START_ADDR1
DATA @
STOP_ADDR1
11121-051
DAC4
DAC1
Figure 50. Pulsed Sine Waves in Pattern Periods
START_DLY2
Figure 51 shows a pulsed sinewave generated by DAC1 and each
of the three available sawtooth wave shapes generated by DAC2,
DAC3, and DAC4 in successive pattern periods with start delay.
DAC2
DATA @
START_ADDR2
DATA @
STOP_ADDR2
START_DLY3
PATTERN_PERIOD
DAC3
START_DLY1 #CYCLES1
DATA @
START_ADDR3
DATA @
STOP_ADDR3
DAC1
DATA @
START_ADDR4
DATA @
STOP_ADDR4
Figure 49. Pattern Using Different Waveforms Stored in SRAM
Figure 50 shows pulsed sine waves generated by each DACx.
The DDS generates a sine wave at a programmed frequency.
Each DACx channel is programmed with a start delay and a
number of sine wave cycles to output.
START_DLY2
DAC2
START_DLY3
DAC3
START_DLY4
DAC4
Figure 51. Pulsed SineWaves and Sawtooth Waveforms in Pattern Periods
Rev. A | Page 28 of 48
11121-052
DAC4
11121-050
START_DLY4
Data Sheet
AD9106
Figure 52 shows all DACx outputting sine waves modulated by
an amplitude envelope. The sine wave is generated by the DDS
and the amplitude envelope is stored in SRAM. Different start
delays and digital gain multipliers are applied by each DACx
input data path.
START_DLY1
DAC1
START_DLY2
PATTERN_PERIOD
START_DLY1
DAC2
START_DLY3
DAC1
DATA @
START_ADDR1
DATA @
STOP_ADDR1
DAC3
START_DLY2
DAC2
START_DLY4
DATA @
STOP_ADDR2
11121-054
DATA @
START_ADDR2
START_DLY3
DAC4
Figure 53. Waveforms with Start Delays
DAC3
DATA @
START_ADDR3
DATA @
STOP_ADDR3
DAC1
START_DLY4
DATA @
STOP_ADDR4
Figure 52. DDS Output Amplitude Modulated by RAM Envelope
11121-053
DAC4
DATA @
START_ADDR4
DAC2
Figure 53 and Figure 54 show the four DACs generating
continuous waveforms. One with start delays, one without.
11121-055
DAC3
DAC4
Figure 54. Waveforms Without Start Delays
Rev. A | Page 29 of 48
AD9106
Data Sheet
REGISTER MAP
Table 14. Register Summary
Addr Register
(Hex) Name
0x00 SPICONFIG
Bits Bit 7
[15:8] LSBFIRST
POWERCONFIG [15:8]
0x02
CLOCKCONFIG
0x03
REFADJ
0x04
DAC4AGAIN
0x05
DAC3AGAIN
0x06
DAC2AGAIN
0x07
DAC1AGAIN
0x08
DACxRANGE
0x09
DAC4RSET
0x0A
DAC3RSET
0x0B
DAC2RSET
0x0C
DAC1RSET
[7:0]
Bit 2
SPI3WIRE
RESET
DOUBLESPI
SPI_DRV
DOUT_EN
DOUT_ENM
SPI_DRVM
DOUBLESPIM
RESETM
SPI3WIREM
CLK_LDO_STAT
DIG1_LDO_STAT
DIG2_LDO_STAT PDN_LDO_CLK
DAC1_SLEEP
DAC2_SLEEP
DAC3_SLEEP
DAC4_SLEEP
DIS_CLK1
DIS_CLK2
DIS_CLK3
DIS_CLK4
DAC1_INV_CLK
DAC2_INV_CLK
DAC3_INV_CLK
DAC4_INV_CLK
PDN_LDO_DIG1 PDN_LDO_DIG2
REF_PDN
REF_EXT
RESERVED[15:12]
DIS_DCLK
CLK_SLEEP
CLK_PDN
EPS
RESERVED[1:0]
RESERVED
RESERVED
RESERVED
DAC4_GAIN_RNG
DAC3_GAIN_RNG
[15:8] DAC3_RSET_EN
DAC4_RSET
RESERVED
[15:8] DAC2_RSET_EN
DAC3_RSET_CAL
DAC3_RSET
RESERVED
DAC2_RSET_CAL
RESERVED
[7:0]
[15:8] DAC1_RSET_EN
DAC2_RSET
RESERVED
DAC1_RSET_CAL
RESERVED
COMP_OFFSET
_OF
DAC1_RSET
COMP_OFFSET
_UF
CAL_MODE_EN
COMP_CAL_RNG
PAT_TYPE
0x22
PATTERN_DLY
DAC4DOF
DAC3DOF
DAC2DOF
DAC1DOF
0x27
PATTERN_DELAY[7:0]
PATTERN
RW
0x00
RW
0x00
RW
0x00
RW
0x00
RW
0x
000A
RW
0x
000A
RW
0x
000A
RW
0x
000A
RW
0x00
RW
0x00
RW
0x00
RW
0x00
RW
0x00
RW
0x
000E
RW
0x00
RW
0x00
RW
0x00
RW
0x00
RW
0000
RW
0x00
RW
E
A
E
A
E
A
E
A
E
A
E
A
E
A
E
A
E
A
E
A
E
A
E
A
E
A
RUN
DAC4_DIG_OFFSET[11:4]
[15:8]
DAC4_DIG_OFFSET[3:0]
E
A
E
A
E
A
RESERVED
DAC3_DIG_OFFSET[11:4]
[15:8]
DAC3_DIG_OFFSET[3:0]
E
A
RESERVED
DAC2_DIG_OFFSET[11:4]
[15:8]
DAC2_DIG_OFFSET[3:0]
E
A
RESERVED
DAC1_DIG_OFFSET[11:4]
[15:8]
[7:0]
0x00
E
A
PATTERN_RPT
PATTERN_DELAY[15:8]
WAV2_1CONFIG [15:8]
RW
START_CAL
RESERVED[14:7]
[7:0]
[7:0]
MEM_ACCESS
RESERVED[6:0]
[15:8]
WAV4_3CONFIG [15:8]
0x00
E
A
RAMUPDATE
BUF_READ
[15:8]
DAC1_DIG_OFFSET[3:0]
[7:0]
0x26
CAL_FIN
RESERVED[3:0]
[7:0]
0x25
CAL_RESET
RESERVED[12:5]
[15:8]
[7:0]
0x24
RW
CAL_CLK_DIV
RESERVED[6:0]
[7:0]
0x23
CAL_CLK_EN
GAIN_CAL_UF
RESERVED[14:7]
[15:8]
[7:0]
0x20
GAIN_CAL_OF
RESERVED
[7:0]
0x1F
RSET_CAL_UF
COMP_OFFSET_CAL
[7:0]
PAT_STATUS
RSET_CAL_OF
[15:8] RESERVED
[7:0]
0x1E
0x00
E
A
DAC1_GAIN_RNG
DAC4_RSET_CAL
RESERVED
[7:0]
0x1D RAMUPDATE
DAC2_GAIN_RNG
RESERVED
RESERVED
[7:0]
CAL_MODE
RW
DAC1_GAIN
RESERVED
[15:8] DAC4_RSET_EN
[7:0]
0x00
DAC2_GAIN
DAC1_GAIN_CAL
[15:8]
[15:8] RESERVED
A
DAC3_GAIN
DAC2_GAIN_CAL
RESERVED
[7:0]
E
DAC4_GAIN
[15:8] RESERVED
[7:0]
Reset RW
0x00 RW
LSBFIRSTM
DAC3_GAIN_CAL
[15:8] RESERVED
[7:0]
RESERVED[3:2]
DAC4_GAIN_CAL
[15:8] RESERVED
[7:0]
Bit 0
BGDR
[15:8] RESERVED
[7:0]
Bit 1
RESERVED[9:2]
[15:8]
[7:0]
COMPOFFSET
Bit 3
RESERVED
[7:0]
0x0E
Bit 4
[15:8]
[7:0]
0x0D CALCONFIG
Bit 5
RESERVED[1:0]
[7:0]
0x01
Bit 6
E
A
RESERVED
RESERVED
PRESTORE_SEL4
RESERVED
WAVE_SEL4
RESERVED
PRESTORE_SEL3
RESERVED
WAVE_SEL3
RESERVED
PRESTORE_SEL2
MASK_DAC4
CH2_ADD
WAVE_SEL2
RESERVED
PRESTORE_SEL1
MASK_DAC3
CH1_ADD
WAVE_SEL1
Rev. A | Page 30 of 48
E
A
A
E
E
Data Sheet
Addr Register
(Hex) Name
0x28 PAT_TIMEBASE
AD9106
Bits Bit 7
[15:8]
Bit 6
[7:0]
0x29
0x2A
0x2B
0x2C
PAT_PERIOD
DAC4_3PATx
DAC2_1PATx
DOUT_START
_DLY
0x2D DOUT_CONFIG
Bit 5
HOLD
START_DELAY_BASE
[7:0]
[15:8]
DAC4_REPEAT_CYCLE
[7:0]
DAC3_REPEAT_CYCLE
[15:8]
DAC2_REPEAT_CYCLE
[7:0]
DAC1_REPEAT_CYCLE
[15:8]
DOUT_START[15:8]
[7:0]
DOUT_START[7:0]
DAC3_CST
0x30
DAC2_CST
0x31
DAC1_CST
0x32
DAC4_DGAIN
0x33
DAC3_DGAIN
0x34
DAC2_DGAIN
0x35
DAC1_DGAIN
0x36
SAW4_3CONFIG [15:8]
0x37
SAW2_1CONFIG [15:8]
RESERVED[1:0]
DOUT_VAL
DOUT_MODE
DAC3_CONST[3:0]
DAC2_CONST[3:0]
DAC1_CONST[3:0]
DAC4_DIG_GAIN[3:0]
0x43
DDS2_PW
DDS1_PW
0x44
TRIG_TW_SEL
0x45
DDSx_CONFIG
0x47
TW_RAM
_CONFIG
E
A
0x00
RW
0x00
RW
0x00
RW
0x00
RW
0x00
RW
0x00
RW
0x00
RW
0x00
RW
0x00
RW
0x00
RW
0x00
RW
0x00
RW
0x00
RW
0x00
RW
0x00
RW
0x00
RW
0x00
RW
0x00
RW
0x00
RW
0x00
RW
E
A
E
A
E
A
E
A
E
A
E
A
RESERVED
DAC3_DIG_GAIN[11:4]
DAC3_DIG_GAIN[3:0]
E
A
RESERVED
DAC2_DIG_GAIN[11:4]
[15:8]
DAC2_DIG_GAIN[3:0]
E
A
RESERVED
DAC1_DIG_GAIN[11:4]
[15:8]
DAC1_DIG_GAIN[3:0]
E
A
RESERVED
SAW_STEP4
SAW_TYPE4
SAW_STEP3
SAW_TYPE3
SAW_STEP2
SAW_TYPE2
SAW_STEP1
E
A
E
A
SAW_TYPE1
RESERVED
[15:8]
DDSTW_MSB[15:8]
[7:0]
DDSTW_MSB[7:0]
DDSTW_LSB
[15:8]
[15:8]
DDS4_PHASE[15:8]
[7:0]
DDS4_PHASE[7:0]
[15:8]
DDS3_PHASE[15:8]
[7:0]
DDS3_PHASE[7:0]
[15:8]
DDS2_PHASE[15:8]
[7:0]
DDS2_PHASE[7:0]
[15:8]
DDS1_PHASE[15:8]
[7:0]
DDS1_PHASE[7:0]
RESERVED[13:6]
[15:8]
RESERVED[5:0]
[7:0]
TRIG_DELAY_EN
[15:8] DDS_COS_EN4
DDS_MSB_EN4
RESERVED
DDS_COS_EN3
DDS_MSB_EN3
RESERVED
DDS_COS_EN2
DDS_MSB_EN2
RESERVED
DDS_COS_EN1
DDS_MSB_EN1
RESERVED
[7:0]
E
A
E
A
RESERVED
[7:0]
0x42
0x0003 RW
RESERVED
[15:8]
[7:0]
E
A
DAC4_DIG_GAIN[11:4]
[7:0]
DDS3_PW
0x0101 RW
RESERVED
[15:8]
[7:0]
E
A
DAC1_CONST[11:4]
[7:0]
0x41
0x0101 RW
RESERVED
[15:8]
[7:0]
E
A
DAC2_CONST[11:4]
[7:0]
DDS4_PW
0x8000 RW
RESERVED
[15:8]
[7:0]
0x40
A
DAC3_CONST[11:4]
[7:0]
A
DOUT_STOP
DAC4_CONST[3:0]
[15:8]
[7:0]
Reset RW
0x0111 RW
E
DAC4_CONST[11:4]
[15:8]
[7:0]
DDS_TW1
Bit 0
RESERVED[9:2]
[15:8]
0x2F
Bit 1
RESERVED
PATTERN_PERIOD[7:0]
[7:0]
Bit 2
PAT_PERIOD_BASE
PATTERN_PERIOD[15:8]
DAC4_CST
0x3F
Bit 3
[15:8]
0x2E
0x38 RESERVED
to
0x3D
0x3E DDS_TW32
Bit 4
[15:8]
RESERVED
RESERVED
[7:0]
RESERVED
TW_MEM_SHIFT
Rev. A | Page 31 of 48
E
A
E
A
E
A
E
A
E
A
RESERVED
E
A
TW_MEM_EN
A
E
E
AD9106
Addr Register
(Hex) Name
0x50 START_DLY4
Data Sheet
Bits Bit 7
[15:8]
Bit 6
Bit 5
START_ADDR4
STOP_ADDR4
DDS_CYC4
0x54
START_DLY3
0x55
START_ADDR3
0x56
STOP_ADDR3
0x57
DDS_CYC3
0058
START_DLY2
0x59
START_ADDR2
0x5A
STOP_ADDR2
0x5B
DDS_CYC2
0x5C
START_DLY1
START_ADDR4[3:0]
DDS_CYC4[15:8]
[7:0]
DDS_CYC4[7:0]
[7:0]
START_DELAY3[7:0]
[15:8]
START_ADDR3[11:4]
START_ADDR3[3:0]
START_DELAY2[7:0]
[15:8]
START_ADDR2[11:4]
START_ADDR2[3:0]
E
0x00
RW
0x00
RW
0x00
RW
E
A
E
A
E
A
0x0001 RW
E
A
STOP_ADDR2[3:0]
RW
0x00
RW
0x00
RW
E
A
E
A
E
A
RESERVED
DDS_CYC2[15:8]
[15:8]
0x00
RESERVED
STOP_ADDR2[11:4]
[15:8]
0x0001 RW
E
A
DDS_CYC2[7:0]
START_DELAY1[15:8]
[15:8]
[7:0]
START_DELAY1[7:0]
[15:8]
START_ADDR1[11:4]
START_ADDR1[3:0]
STOP_ADDR1[3:0]
RW
0x00
RW
0x00
RW
E
A
E
A
E
A
RESERVED
DDS_CYC1[15:8]
[15:8]
0x00
RESERVED
STOP_ADDR1[11:4]
[15:8]
0x0001 RW
E
A
DDS_CYC1[7:0]
[7:0]
[7:0]
E
A
RESERVED
[7:0]
[15:8]
RW
DDS_CYC3[7:0]
[7:0]
0x6000 SRAM_DATA
to
0x6FFF
0x00
E
A
A
START_DELAY2[15:8]
[15:8]
[15:8]
[7:0]
RW
0x0001 RW
DDS_CYC3[15:8]
[7:0]
CFG_ERROR
0x00
RESERVED
STOP_ADDR3[3:0]
[15:8]
[7:0]
0060
A
STOP_ADDR3[11:4]
[15:8]
[7:0]
DDS_CYC1
E
START_DELAY3[15:8]
[15:8]
[7:0]
005F
A
RESERVED
[15:8]
[7:0]
STOP_ADDR1
Reset RW
0x00 RW
RESERVED
STOP_ADDR4[3:0]
[7:0]
0x5E
Bit 0
STOP_ADDR4[11:4]
[15:8]
[7:0]
0x5D START_ADDR1
Bit 1
START_ADDR4[11:4]
[15:8]
[7:0]
0x53
Bit 2
START_DELAY4[7:0]
[7:0]
0x52
Bit 3
START_DELAY4[15:8]
[7:0]
0x51
Bit 4
ERROR_CLEAR
CFG_ERROR[1:0]
CFG_ERROR[8:2]
DOUT_START_LG PAT_DLY_SHORT DOUT_START
_ERR
_ERR
_SHORT_ERR
RESERVED
PERIOD
_SHORT_ERR
ODD_ADDR
_ERR
SRAM_DATA[11:8]
SRAM_DATA[7:0]
Rev. A | Page 32 of 48
0x00
R
N/A
RW
MEM_READ
_ERR
A
E
E
Data Sheet
AD9106
REGISTER DESCRIPTIONS
SPI Control Register (SPICONFIG, Address 0x00)
Table 15. Bit Descriptions for SPICONFIG
Bits
15
Bit Field Name
LSBFIRST
Settings
0
1
14
SPI3WIRE
0
1
13
RESET
0
1
12
DOUBLESPI
0
1
Description
LSB first selection.
MSB first per SPI standard (default).
LSB first per SPI standard.
Selects if SPI is using 3-wire or 4-wire interface.
4-wire SPI.
3-wire SPI.
Executes software reset of SPI and controllers, reloads default register
values, except for Register 0x00.
Normal status.
Resets whole register map, except for Register 0x00.
Double SPI data line.
The SPI port has only 1 data line and can be used as a 3-wire or 4-wire
interface.
The SPI port has 2 data lines: both bidirectional defining a pseudo dual
3-wire interface where CS and SCLK are shared between the two ports.
This mode is only available for RAM data read or write.
Double-drive ability for SPI output.
Single SPI output drive ability.
Two-time drive ability on SPI output.
Enables DOUT signal on SDO/SDI2/DOUT pin.
SDO/SDI2 function input/output.
DOUT function output.
Reset
0
Access
RW
0
RW
0
RW
0
RW
0
RW
0
RW
E
A
E
A
E
A
E
A
E
A
11
SPI_DRV
0
1
10
DOUT_EN
0
1
A
E
A
E
A
[9:6]
RESERVED
5
DOUT_ENM 1
Enable DOUT signal on SDO/SDI2/DOUT pin.
4
SPI_DRVM1
Double-drive ability for SPI output.
0
RW
3
DOUBLESPIM1
Double SPI data line.
0
RW
2
RESETM1
0
RW
1
0
SPI3WIREM1
LSBFIRSTM1
Executes software reset of SPI and controllers, reloads default register
values, except for Register 0x00.
Selects if SPI is using 3-wire or 4-wire interface.
LSB first selection.
0
0
RW
RW
1
RW
E
A
0F
RW
E
A
E
A
E
A
E
A
E
A
SPICONFIG[10:15] should always be set to the mirror of SPICONFIG[5:0] to allow easy recovery of the SPI operation when the LSBFIRST bit is set incorrectly. Bit[15] =
Bit[0], Bit[14] = Bit[1], Bit[13] = Bit[2], Bit[12] = Bit[3], Bit[11] = Bit[4] and Bit[10] = Bit[5].
Rev. A | Page 33 of 48
AD9106
Data Sheet
Power Status Register (POWERCONFIG, Address 0x01)
Table 16. Bit Descriptions for POWERCONFIG
Bits
[15:12]
Bit Field Name
RESERVED
11
10
9
8
CLK_LDO_STAT
DIG1_LDO_STAT
DIG2_LDO_STAT
PDN_LDO_CLK
7
Settings
Description
Reset
0x00
Access
RW
Read-only flag indicating CLKVDD_1P8 LDO is on.
Read-only flag indicating DVDD1 LDO is on.
Read-only flag indicating DVDD2 LDO is on.
Disables the CLKVDD_1P8 LDO. An external supply is required.
0
0
0
0
R
R
R
RW
PDN_LDO_DIG1
Disables the DVDD1 LDO. An external supply is required.
0
RW
6
PDN_LDO_DIG2
Disables the DVDD2 LDO. An external supply is required.
0
RW
5
REF_PDN
0
RW
4
REF_EXT
Disables 10 kΩ resistor that creates REFIO voltage. User can drive with
external voltage or provide external BG resistor.
Power down main BG reference including DAC bias.
0
RW
3
DAC1_SLEEP
Disables DAC1 output current.
0
RW
2
DAC2_SLEEP
Disables DAC2 output current.
0
RW
1
DAC3_SLEEP
Disables DAC3 output current.
0
RW
0
DAC4_SLEEP
Disables DAC4 output current.
0
RW
Reset
0x000
Access
RW
E
A
E
A
E
A
E
A
E
A
E
A
E
A
E
A
E
A
E
A
Clock Control Register (CLOCKCONFIG, Address 0x02)
Table 17. Bit Descriptions for CLOCKCONFIG
Bits
[15:12]
Bit Field Name
RESERVED
Settings
Description
11
DIS_CLK1
Disables the analog clock to DAC1 out of the clock distribution block.
0
RW
10
DIS_CLK2
Disables the analog clock to DAC2 out of the clock distribution block.
0
RW
9
DIS_CLK3
Disables the analog clock to DAC3 out of the clock distribution block.
0
RW
8
DIS_CLK4
Disables the analog clock to DAC4 out of the clock distribution block.
0
RW
7
DIS_DCLK
Disables the clock to core digital block.
0
RW
6
CLK_SLEEP
Enables a very low power clock mode.
0
RW
5
CLK_PDN
0
RW
4
EPS
0
RW
3
DAC1_INV_CLK
0
RW
2
DAC2_INV_CLK
0
RW
1
DAC3_INV_CLK
0
RW
0
DAC4_INV_CLK
Disables and powers down main clock receiver. No clocks will be active in
the part.
Enables Power Save (EPS) enables a low power option for the clock
receiver, but maintains low jitter performance on DAC clock rising edge.
The DAC clock falling edge is substantially degraded.
Cannot use EPS while using this bit. Inverts the clock inside DAC Core 1
allowing 180° phase shift in DAC1 update timing.
Cannot use EPS while using this bit. Inverts the clock inside DAC Core 2
allowing 180° phase shift in DAC2 update timing.
Cannot use EPS while using this bit. Inverts the clock inside DAC Core 3
allowing 180° phase shift in DAC3 update timing.
Cannot use EPS while using this bit. Inverts the clock inside DAC Core 4
allowing 180° phase shift in DAC4 update timing.
0
RW
E
A
E
A
E
A
E
A
E
A
E
A
E
A
E
A
E
A
E
A
E
A
E
A
E
A
Reference Resistor Register (REFADJ, Address 0x03)
Table 18. Bit Descriptions for REFADJ
Bits
[15:6]
Bit Field Name
RESERVED
[5:0]
BGDR
Settings
Description
Adjusts the BG 10 kΩ resistor (nominal) to 8 kΩ to 12 kΩ, changes BG
voltage from 800 mV to 1.2 V, respectively.
Rev. A | Page 34 of 48
Reset
0x000
Access
RW
0x00
RW
E
A
A
E
Data Sheet
AD9106
DAC4 Analog Gain Register (DAC4AGAIN, Address 0x04)
Table 19. Bit Descriptions for DAC4AGAIN
Bits
15
Bit Field Name
RESERVED
Settings
Description
[14:8]
7
DAC4_GAIN_CAL
RESERVED
DAC4 analog gain calibration output—read only.
[6:0]
DAC4_GAIN
DAC4 analog gain control while not in calibration mode—twos
complement.
Reset
0
Access
RW
0x00
0
R
RW
0x00
RW
Reset
0
Access
RW
0x00
0
R
RW
0x00
RW
Reset
0
Access
RW
0x00
0
R
RW
0x00
RW
Reset
0
Access
RW
0x00
0
R
RW
0x00
RW
E
A
E
A
E
A
DAC3 Analog Gain Register (DAC3AGAIN, Address 0x05)
Table 20. Bit Descriptions for DAC3AGAIN
Bits
15
Bit Field Name
RESERVED
Settings
Description
[14:8]
7
DAC3_GAIN_CAL
RESERVED
DAC3 analog gain calibration output—read only.
[6:0]
DAC3_GAIN
DAC3 analog gain control while not in calibration mode—twos
complement.
E
A
E
A
E
A
DAC2 Analog Gain Register (DAC2AGAIN, Address 0x06)
Table 21. Bit Descriptions for DAC2AGAIN
Bits
15
Bit Field Name
RESERVED
Settings
Description
[14:8]
7
DAC2_GAIN_CAL
RESERVED
DAC2 analog gain calibration output—read only.
[6:0]
DAC2_GAIN
DAC2 analog gain control while not in calibration mode—twos
complement.
E
A
E
A
E
A
DAC1 Analog Gain Register (DAC1AGAIN, Address 0x07)
Table 22. Bit Descriptions for DAC1AGAIN
Bits
15
Bit Field Name
RESERVED
Settings
Description
[14:8]
7
DAC1_GAIN_CAL
RESERVED
DAC1 analog gain calibration output—read only.
[6:0]
DAC1_GAIN
DAC1 analog gain control while not in calibration mode—twos
complement.
E
A
E
A
E
A
DAC Analog Gain Range Register (DACxRANGE, Address 0x08)
Table 23. Bit Descriptions for DACxRANGE
Bits
[15:8]
Bit Field Name
RESERVED
[7:6]
DAC4_GAIN_RNG
[5:4]
Settings
Description
Reset
0x00
Access
RW
DAC4 gain range control.
0x0
RW
DAC3_GAIN_RNG
DAC3 gain range control.
0x0
RW
[3:2]
DAC2_GAIN_RNG
DAC2 gain range control.
0x0
RW
[1:0]
DAC1_GAIN_RNG
DAC1 gain range control.
0x0
RW
Rev. A | Page 35 of 48
E
A
E
A
E
A
E
A
AD9106
Data Sheet
FSADJ4 Register (DAC4RSET, Address 0x09)
Table 24. Bit Descriptions for DAC4RSET
Bits
15
Bit Field Name
DAC4_RSET_EN
Settings
Description
For write, enable the internal RSET resistor for DAC4; for read, RSET for
DAC4 is enabled during calibration mode.
[14:13]
RESERVED
[12:8]
[7:5]
DAC4_RSET_CAL
RESERVED
Digital control value of RSET resistor for DAC4 after calibration—read only.
[4:0]
DAC4_RSET
Digital control to set the value of RSET resistor in DAC4.
Reset
0x00
Access
RW
0x00
RW
0x00
0x00
R
RW
0x0A
RW
Reset
0
Access
RW
0x0
RW
0x00
0x0
R
RW
0x0A
RW
Reset
0
Access
RW
0x0
RW
0x00
0x0
R
RW
0xA
RW
Reset
0x00
Access
RW
0x00
RW
0x00
0x0
R
RW
0x0A
RW
E
A
E
A
E
A
E
A
FSADJ3 Register (DAC3RSET, Address 0x0A)
Table 25. Bit Descriptions for DAC3RSET
Bits
15
Bit Field Name
DAC3_RSET_EN
Settings
Description
For write, enable the internal RSET resistor for DAC3; for read, RSET for
DAC3 is enabled during calibration mode.
[14:13]
RESERVED
[12:8]
[7:5]
DAC3_RSET_CAL
RESERVED
Digital control value of RSET resistor for DAC3 after calibration—read only.
[4:0]
DAC3_RSET
Digital control to set the value of RSET resistor in DAC3.
E
A
E
A
E
A
E
A
FSADJ2 Register (DAC2RSET, Address 0x0B)
Table 26. Bit Descriptions for DAC2RSET
Bits
15
Bit Field Name
DAC2_RSET_EN
Settings
Description
For write, enable the internal RSET resistor for DAC2; for read, RSET for
DAC2 is enabled during calibration mode.
[14:13]
RESERVED
[12:8]
[7:5]
DAC2_RSET_CAL
RESERVED
Digital control value of RSET resistor for DAC2 after calibration—read only.
[4:0]
DAC2_RSET
Digital control to set the value of RSET resistor in DAC2.
E
A
E
A
E
A
E
A
FSADJ1 Register (DAC1RSET, Address 0x0C)
Table 27. Bit Descriptions for DAC1RSET
Bits
15
Bit Field Name
DAC1_RSET_EN
Settings
Description
For write, enable the internal RSET resistor for DAC1; for read, RSET for DAC1
is enabled during calibration mode.
[14:13]
RESERVED
[12:8]
[7:5]
DAC1_RSET_CAL
RESERVED
Digital control value of RSET resistor for DAC1 after calibration—read only.
[4:0]
DAC1_RSET
Digital control to set the value of RSET resistor in DAC1.
Rev. A | Page 36 of 48
E
A
E
A
E
A
A
E
Data Sheet
AD9106
Calibration Register (CALCONFIG, Address 0x0D)
Table 28. Bit Descriptions for CALCONFIG
Bits
15
Bit Field Name
RESERVED
14
13
12
11
10
9
8
COMP_OFFSET_OF
COMP_OFFSET_UF
RSET_CAL_OF
RSET_CAL_UF
GAIN_CAL_OF
GAIN_CAL_UF
CAL_RESET
71
61
Reset
0
Access
RW
Compensation offset calibration value overflow.
Compensation offset calibration value underflow.
RSET calibration value overflow.
RSET calibration value underflow.
Gain calibration value overflow.
Gain calibration value underflow.
Pulse this bit high and low to reset the calibration results.
0
0
0
0
0
0
0
R
R
R
R
R
R
RW
CAL_MODE
CAL_MODE_EN
Read-only flag indicating calibration is being used.
Enables the gain calibration circuitry.
0
0
R
RW
[5:4]
COMP_CAL_RNG
Offset calibration range.
0x0
RW
3
CAL_CLK_EN
Enables the calibration clock to calibration circuitry.
0
RW
[2:0]
CAL_CLK_DIV
Sets divider from DAC clock to calibration clock.
0x0
RW
Reset
0x00
Access
RW
0x00
0x00
R
RW
0x00
0x00
R
RW
1
Settings
Description
E
A
E
A
E
A
E
A
E
A
E
A
Change of location
Comp Offset Register (COMPOFFSET, Address 0x0E)
Table 29. Bit Descriptions for COMPOFFSET
Bits
15
Bit Field Name
RESERVED
Settings
Description
[14:8]
[7:2]
COMP_OFFSET_CAL
RESERVED
The result of the offset calibration for the comparator.
1
0
CAL_FIN
START_CAL
Read-only flag indicating calibration is completed.
Start a calibration cycle.
E
A
E
A
E
A
Update Pattern Register (RAMUPDATE, Address 0x1D)
Table 30. Bit Descriptions for RAMUPDATE
Bits
[15:1]
Bit Name
RESERVED
0
RAMPUPDATE
Settings
Description
Update all SPI setting with new configuration (self clearing).
Reset
0x00
Access
RW
0
RW
E
A
E
A
Command/Status Register (PAT_STATUS, Address 0x1E)
Table 31. Bit Descriptions for PAT_STATUS
Bits
[15:4]
Bit Field Name
RESERVED
3
BUF_READ
2
1
0
Settings
Description
Reset
0x000
Access
RW
Read back from updated buffer.
0
RW
MEM_ACCESS
Memory SPI access enable.
0
RW
PATTERN
RUN
Status of pattern being played, read only.
Allows the pattern generation and stop pattern after trigger.
0
0
R
RW
Rev. A | Page 37 of 48
E
A
E
A
E
A
A
E
AD9106
Data Sheet
Command/Status Register (PAT_TYPE, Address 0x1F)
Table 32. Bit Descriptions for PAT_TYPE
Bits
[15:1]
Bit Field Name
RESERVED
0
PATTERN_RPT
Settings
Description
Setting this bit allows the pattern to repeat the number of times
defined in DAC4_3PATx and DAC2_1PATx.
Pattern continuously runs.
Pattern repeats the number of times defined in DAC4_3PATx and
DAC2_1PATx.
0
1
Reset
0x0000
Access
RW
0
RW
E
A
E
A
Trigger Start to Real Pattern Delay Register (PATTERN_DLY, Address 0x20)
Table 33. Bit Descriptions for PATTERN_DLY
Bits
[15:0]
Bit Field Name
PATTERN_DELAY
Settings
Description
Time between trigger low and pattern start in number of DAC clock
cycles + 1.
Reset
0x000E
Access
RW
E
A
DAC4 Digital Offset Register (DAC4DOF, Address 0x22)
Table 34. Bit Descriptions for DAC4DOF
Bits
[15:4]
Bit Field Name
DAC4_DIG_OFFSET
[3:0]
RESERVED
Settings
Description
DAC4 digital offset.
Reset
0x000
Access
RW
0x00
RW
Reset
0x000
Access
RW
0x0
RW
Reset
0x000
Access
RW
0x00
RW
Reset
0x000
Access
RW
0x00
RW
E
A
E
A
DAC3 Digital Offset Register (DAC3DOF, Address 0x23)
Table 35. Bit Descriptions for DAC3DOF
Bits
[15:4]
Bit Field Name
DAC3_DIG_OFFSET
[3:0]
RESERVED
Settings
Description
DAC3 digital offset.
E
A
E
A
DAC2 Digital Offset Register (DAC2DOF, Address 0x24)
Table 36. Bit Descriptions for DAC2DOF
Bits
[15:4]
Bit Field Name
DAC2_DIG_OFFSET
[3:0]
RESERVED
Settings
Description
DAC2 digital offset.
E
A
E
A
DAC1 Digital Offset Register (DAC1DOF, Address 0x25)
Table 37. Bit Descriptions for DAC1DOF
Bits
[15:4]
Bit Field Name
DAC1_DIG_OFFSET
[3:0]
RESERVED
Settings
Description
DAC1 digital offset.
Rev. A | Page 38 of 48
E
A
A
E
Data Sheet
AD9106
Wave3/Wave4 Select Register (WAV4_3CONFIG, Address 0x26)
Table 38. Bit Descriptions for WAV4_3CONFIG
Bits
[15:14]
Bit Field Name
RESERVED
[13:12]
PRESTORE_SEL4
Settings
0
1
2
3
Description
Reset
0x00
Access
RW
0x00
RW
E
A
Constant value held into DAC4 constant value MSB/LSB register.
Sawtooth defined in DAC4 sawtooth configuration register
(SAW4_3CONFIG).
Pseudo-random sequence.
DDS4 output.
[11:10]
RESERVED
0x00
RW
[9:8]
WAVE_SEL4
0x1
RW
0
1
2
3
E
A
E
A
E
A
Waveform read from RAM between START_ADDR4 and STOP_ADDR4.
Prestored waveform.
Prestored waveform using START_DELAY4 and PATTERN_PERIOD.
Prestored waveform modulated by waveform from RAM.
[7:6]
RESERVED
0x00
RW
[5:4]
PRESTORE_SEL3
0x00
RW
0x00
RW
0x1
RW
Reset
0x0
Access
RW
0x0
RW
0
RW
0
RW
0x1
RW
0x0
RW
0
1
2
3
[3:2]
RESERVED
[1:0]
WAVE_SEL3
0
1
2
3
E
A
E
A
Constant value held into DAC3 constant value MSB/LSB register.
Sawtooth defined in DAC3 sawtooth configuration register
(SAW4_3CONFIG).
Pseudo-random sequence.
DDS3 output.
E
A
Waveform read from RAM between START_ADDR3 and STOP_ADDR3.
Prestored waveform.
Prestored waveform using START_DELAY3 and PATTERN_PERIOD.
Prestored waveform modulated by waveform from RAM.
Wave1/Wave2 Select Register (WAV2_1CONFIG, Address 0x27)
Table 39. Bit Descriptions for WAV2_1CONFIG
Bits
[15:14]
Bit Field Name
RESERVED
[13:12]
PRESTORE_SEL2
Settings
0
1
2
3
11
MASK_DAC4
10
CH2_ADD
0
1
[9:8]
Constant value held into DAC2 constant value MSB/LSB register.
Sawtooth defined in DAC2 sawtooth configuration register
(SAW2_1CONFIG).
Pseudo-random sequence.
DDS2 output.
Mask DAC4 to DAC4_CONST value.
Add DAC2 and DAC4, output at DAC2.
Normal operation for DAC2/DAC4.
Add DAC2 and DAC4, output from DAC2.
WAVE_SEL2
0
1
2
3
[7:6]
Description
E
A
E
A
E
A
E
A
E
A
Waveform read from RAM between START_ADDR2 and STOP_ADDR2.
Prestored waveform.
Prestored waveform using START_DELAY2 and PATTERN_PERIOD.
Prestored waveform modulated by waveform from RAM.
RESERVED
Rev. A | Page 39 of 48
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E
AD9106
Bits
[5:4]
Bit Field Name
PRESTORE_SEL1
Data Sheet
Settings
0
1
Constant value held into DAC1 constant value MSB/LSB register.
Sawtooth defined in DAC1 sawtooth configuration register
(SAW2_1CONFIG).
Pseudo-random sequence.
DDS1 output.
Mask DAC3 to DAC3_CONST value.
2
3
3
MASK_DAC3
2
CH1_ADD
Add DAC1 and DAC3, output at DAC1.
Normal operation for DAC1/DAC3.
Add DAC1 and DAC3, and output at DAC1. In this start_delay case, DAC3
output remains unchanged.
0
1
[1:0]
Description
WAVE_SEL1
0
1
2
3
Reset
0x0
Access
RW
0
RW
0
RW
0x1
RW
Reset
0x00
Access
RW
0x1
RW
0x1
RW
0x1
RW
Reset
0x8000
Access
RW
E
A
E
A
E
A
E
A
Waveform read from RAM between START_ADDR1 and STOP_ADDR1.
Prestored waveform.
Prestored waveform using START_DELAY1 and PATTERN_PERIOD.
Prestored waveform modulated by waveform from RAM.
DAC Time Control Register (PAT_TIMEBASE, Address 0x28)
Table 40. Bit Descriptions for PAT_TIMEBASE
Bits
[15:12]
Bit Field Name
RESERVED
[11:8]
HOLD
[7:4]
PAT_PERIOD_BASE
[3:0]
START_DELAY_BASE
Settings
Description
Number of times the DAC value holds the sample (0 = DAC holds for 1
sample).
Number of DAC clock period per PATTERN_PERIOD LSB
(0 = PATTERN_PERIOD LSB = 1 DAC clock period).
Number of DAC clock period per START_DELAYx LSB
(0 = START_DELAYx LSB = 1 DAC clock period).
E
A
E
A
E
A
E
A
Pattern Period Register (PAT_PERIOD, Address 0x029)
Table 41. Bit Descriptions for PAT_PERIOD
Bits
[15:0]
Bit Field Name
PATTERN_PERIOD
Settings
Description
Pattern period register.
E
A
DAC3/DAC4 Pattern Repeat Cycles Register (DAC4_3PATx, Address 0x2A)
Table 42. Bit Descriptions for DAC4_3PATx
Bits
[15:8]
Bit Field Name
DAC4_REPEAT_CYCLE
[7:0]
DAC3_REPEAT_CYCLE
Settings
Description
Number of DAC4 pattern repeat cycles + 1, (0  repeat 1 pattern).
Reset
0x01
Access
RW
Number of DAC3 pattern repeat cycles + 1, (0  repeat 1 pattern).
0x01
RW
Reset
0x01
0x01
Access
RW
RW
E
A
E
A
DAC1/DAC2 Pattern Repeat Cycles Register (DAC2_1PATx, Address 0x2B)
Table 43. Bit Descriptions for DAC2_1PATx
Bits
[15:8]
[7:0]
Bit Field Name
DAC2_REPEAT_CYCLE
DAC1_REPEAT_CYCLE
Settings
Description
Number of DAC2 pattern repeat cycles + 1, (0  repeat 1 pattern).
Number of DAC1 pattern repeat cycles + 1, (0  repeat 1 pattern).
Rev. A | Page 40 of 48
E
A
E
A
Data Sheet
AD9106
Trigger Start to DOUT Signal Register (DOUT_START_DLY, Address 0x2C)
Table 44. Bit Descriptions for DOUT_START_DLY
Bits
[15:0]
Bit Field Name
DOUT_START
Settings
Description
Time between trigger low and DOUT signal high in number of DAC
clock cycles.
Reset
0x0003
Access
RW
Reset
0x0000
Access
RW
0
RW
0
RW
0x0
RW
E
A
DOUT CONFIG Register (DOUT_CONFIG, Address 0x2D)
Table 45. Bit Descriptions for DOUT_CONFIG
Bits
[15:6]
Bit Field Name
RESERVED
5
DOUT_VAL
4
DOUT_MODE
Settings
Description
Manually sets DOUT signal value, only valid when DOUT_MODE = 0
(manual mode).
Sets different enable signal mode.
DOUT pin is output from SDO/SDI2/DOUT pin and is manually controlled
by Bit 5, DOUT_EN in Register 0x00 which must be set to use this feature.
DOUT pin is output from SDO/SDI2/DOUT. The pin is controlled by
DOUT_START and DOUT_STOP. DOUT_EN in Register 0x00 must be set to
use this feature.
Time between pattern end and DOUT signal low in number of DAC clock
cycles.
0x0
0x1
[3:0]
DOUT_STOP
E
A
E
A
E
A
E
A
DAC4 Constant Value Register (DAC4_CST, Address 0x2E)
Table 46. Bit Descriptions for DAC4_CST
Bits
[15:4]
Bit Field Name
DAC4_CONST
[3:0]
RESERVED
Settings
Description
Most significant byte of DAC4 constant value.
Reset
0x000
Access
RW
0x0
RW
Reset
0x000
Access
RW
0x0
RW
Reset
0x000
Access
RW
0x0
RW
Reset
0x000
Access
RW
0x0
RW
E
A
E
A
DAC3 Constant Value Register (DAC3_CST, Address 0x2F)
Table 47. Bit Descriptions for DAC3_CST
Bits
[15:4]
Bit Field Name
DAC3_CONST
[3:0]
RESERVED
Settings
Description
Most significant byte of DAC3 constant value.
E
A
E
A
DAC2 Constant Value Register (DAC2_CST, Address 0x30)
Table 48. Bit Descriptions for DAC2_CST
Bits
[15:4]
Bit Field Name
DAC2_CONST
[3:0]
RESERVED
Settings
Description
Most significant byte of DAC2 constant value.
E
A
E
A
DAC1 Constant Value Register (DAC1_CST, Address 0x31)
Table 49. Bit Descriptions for DAC1_CST
Bits
[15:4]
Bit Field Name
DAC1_CONST
[3:0]
RESERVED
Settings
Description
Most significant byte of DAC1 constant value.
Rev. A | Page 41 of 48
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A
A
E
AD9106
Data Sheet
DAC4 Digital Gain Register (DAC4_DGAIN, Address 0x32)
Table 50. Bit Descriptions for DAC4_DGAIN
Bits
[15:4]
Bit Field Name
DAC4_DIG_GAIN
[3:0]
RESERVED
Settings
Description
DAC4 digital gain range of +2 to −2.
Reset
0x000
Access
RW
0x0
RW
Reset
0x000
Access
RW
0x0
RW
Reset
0x000
Access
RW
0x0
RW
Reset
0x000
Access
RW
0x0
RW
Description
Number of samples per step for DAC4.
Reset
0x01
Access
RW
The type of sawtooth (positive, negative, or triangle) for DAC4.
Ramp up saw wave.
Ramp down saw wave.
Triangle saw wave.
No wave, zero.
Number of samples per step for DAC3.
0x0
RW
0x01
RW
The type of sawtooth (positive, negative, or triangle) for DAC3.
Ramp up saw wave.
Ramp down saw wave.
Triangle saw wave.
No wave, zero.
0x0
RW
Description
Number of samples per step for DAC2.
Reset
0x01
Access
RW
The type of sawtooth (positive, negative, or triangle) for DAC2.
Ramp up saw wave.
Ramp down saw wave.
Triangle saw wave.
No wave, zero.
0x0
RW
E
A
E
A
DAC3 Digital Gain Register (DAC3_DGAIN, Address 0x33)
Table 51. Bit Descriptions for DAC3_DGAIN
Bits
[15:4]
Bit Field Name
DAC3_DIG_GAIN
[3:0]
RESERVED
Settings
Description
DAC3 digital gain. Range of +2 to −2.
E
A
E
A
DAC2 Digital Gain Register (DAC2_DGAIN, Address 0x34)
Table 52. Bit Descriptions for DAC2_DGAIN
Bits
[15:4]
Bit Field Name
DAC2_DIG_GAIN
[3:0]
RESERVED
Settings
Description
DAC2 digital gain. Range of +2 to −2.
E
A
E
A
DAC1 Digital Gain Register (DAC1_DGAIN, Address 0x35)
Table 53. Bit Descriptions for DAC1_DGAIN
Bits
[15:4]
Bit Field Name
DAC1_DIG_GAIN
[3:0]
RESERVED
Settings
Description
DAC1 digital gain. Range of +2 to −2.
E
A
E
A
DAC3/4 Sawtooth Configuration Register (SAW4_3CONFIG, Address 0x36)
Table 54. Bit Descriptions for SAW4_3CONFIG
Bits
[15:10]
Bit Field Name
SAW_STEP4
[9:8]
SAW_TYPE4
Settings
0
1
2
3
[7:2]
SAW_STEP3
[1:0]
SAW_TYPE3
0
1
2
3
E
A
E
A
E
A
E
A
DAC1/2 Sawtooth Configuration Register (SAW2_1CONFIG, Address 0x37)
Table 55. Bit Descriptions for SAW2_1CONFIG
Bits
[15:10]
Bit Field Name
SAW_STEP2
[9:8]
SAW_TYPE2
Settings
0
1
2
3
Rev. A | Page 42 of 48
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Data Sheet
Bits
[7:2]
Bit Field Name
SAW_STEP1
[1:0]
SAW_TYPE1
AD9106
Settings
0
1
2
3
Description
Number of samples per step for DAC1.
Reset
0x01
Access
RW
The type of sawtooth (positive, negative, or triangle) for DAC1.
Ramp up saw wave.
Ramp down saw wave.
Triangle saw wave.
No wave, zero.
0x0
RW
Reset
0x0000
Access
RW
E
A
E
A
DDS Tuning Word MSB Register (DDS_TW32, Address 0x3E)
Table 56. Bit Descriptions for DDS_TW32
Bits
[15:0]
Bit Field Name
DDSTW_MSB
Settings
Description
DDS tuning word MSB.
E
A
DDS Tuning word LSB Register (DDS_TW1, Address 0x3F)
Table 57. Bit Descriptions for DDS_TW1
Bits
[15:8]
Bit Field Name
DDSTW_LSB
[7:0]
RESERVED
Settings
Description
DDS tuning word LSB.
Reset
0x00
Access
RW
0x00
RW
E
A
E
A
DDS4 Phase Offset Register (DDS4_PW, Address 0x40)
Table 58. Bit Descriptions for DDS4_PW
Bits
[15:0]
Bit Field Name
DDS4_PHASE
Settings
Description
DDS4 phase offset.
Reset
0x0000
Access
RW
Reset
0x0000
Access
RW
Reset
0x0000
Access
RW
Reset
0x0000
Access
RW
E
A
DDS3 Phase Offset Register (DDS3_PW, Address 0x41)
Table 59. Bit Descriptions for DDS3_PW
Bits
[15:0]
Bit Field Name
DDS3_PHASE
Settings
Description
DDS3 phase offset.
E
A
DDS2 Phase Offset Register (DDS2_PW, Address 0x42)
Table 60. Bit Descriptions for DDS2_PW
Bits
[15:0]
Bit Field Name
DDS2_PHASE
Settings
Description
DDS2 phase offset.
E
A
DDS1 Phase Offset Register (DDS1_PW, Address 0x43)
Table 61. Bit Descriptions for DDS1_PW
Bits
[15:0]
Bit Field Name
DDS1_PHASE
Settings
Description
DDS1 phase offset.
Rev. A | Page 43 of 48
E
A
AD9106
Data Sheet
Pattern Control 1 Register (TRIG_TW_SEL, Address 0x44)
Table 62. Bit Descriptions for TRIG_TW_SEL
Bits
[15:2]
Bit Field Name
RESERVED
1
TRIG_DELAY_EN
Settings
0
1
0
Description
Enable start delay as trigger delay for all four channels.
Delay repeats for all patterns.
Delay is only at the start of first pattern.
RESERVED
Reset
0x0000
Access
RW
0
RW
0
RW
E
A
E
A
E
A
Pattern Control 2 Register (DDSx_CONFIG, Address 0x45)
Table 63. Bit Descriptions for DDSx_CONFIG
Bits
15
Bit Field Name
DDS_COS_EN4
14
DDS_MSB_EN4
13
Settings
Description
Enable DDS4 cosine output of DDS instead of sine wave.
Reset
0
Access
RW
Enable the clock for the RAM address. Increment is coming from the
DDS4 MSB. Default is coming from DAC clock.
0
RW
RESERVED
0
RW
12
RESERVED
0
RW
11
DDS_COS_EN3
Enable DDS3 cosine output of DDS instead of sine wave.
0
RW
10
DDS_MSB_EN3
0
RW
9
PHASE_MEM_EN3
Enable the clock for the RAM address. Increment is coming from the
DDS3 MSB. Default is coming from DAC clock.
Enable DDS3 phase offset input coming from RAM reading
START_ADDR3. Since phase word is 8 bits and RAM data is 14 bits, only
8 MSB of RAM are taken into account. Default is coming from SPI map,
DDS3_PHASE.
0
RW
8
RESERVED
0
RW
7
DDS_COS_EN2
Enable DDS2 cosine output of DDS instead of sine wave.
0
RW
6
DDS_MSB_EN2
Enable the clock for the RAM address. Increment is coming from the
DDS2 MSB. Default is coming from DAC clock.
0
RW
5
RESERVED
0
RW
4
RESERVED
0
RW
3
DDS_COS_EN1
Enable DDS1 cosine output of DDS instead of sine wave.
0
RW
2
DDS_MSB_EN1
Enable the clock for the RAM address. Increment is coming from the
DDS1 MSB. Default is coming from DAC clock.
0
RW
1
RESERVED
0
RW
0
TW_MEM_EN
0
RW
Reset
0x000
Access
RW
0x00
RW
Enable DDS tuning word input coming from RAM reading using
START_ADDR1. Since tuning word is 24 bits and RAM data is 14 bits,
10 bits are set to 0s depending on the value of the TW_MEM_SHIFT bits in
the TW_RAM_CONFIG register. Default is coming from SPI map, DDSTW.
E
A
E
A
E
A
E
A
E
A
E
A
E
A
E
A
E
A
E
A
E
A
E
A
E
A
E
A
E
A
E
A
TW_RAM_CONFIG Register (TW_RAM_CONFIG, Address 0x47)
Table 64. Bit Descriptions for TW_RAM_CONFIG
Bits
[15:5]
Bit Field Name
RESERVED
[4:0]
TW_MEM_SHIFT
Settings
0x00
0x01
0x02
0x03
0x04
0x05
0x06
Description
TW_MEM_EN1 must be set = 1 to use this bit field.
DDS1TW = {RAM[11:0],12'b0}
DDS1TW = {DDS1TW[23],RAM[11:0],11'b0}
DDS1TW = {DDS1TW[23:22],RAM[11:0],10'b0}
DDS1TW = {DDS1TW[23:21],RAM[11:0],9'b0}
DDS1TW = {DDS1TW[23:20],RAM[11:0],8'b0}
DDS1TW = {DDS1TW[23:19],RAM[11:0],7'b0}
DDS1TW = {DDS1TW[23:18],RAM[11:0],6'b0}
Rev. A | Page 44 of 48
E
A
A
E
Data Sheet
Bits
Bit Field Name
AD9106
Settings
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
x
Description
DDS1TW = {DDS1TW[23:17],RAM[11:0],5'b0}
DDS1TW = {DDS1TW[23:16],RAM[11:0],3'b0}
DDS1TW = {DDS1TW[23:15],RAM[11:0],4'b0}
DDS1TW = {DDS1TW[23:14],RAM[11:0],2’b0}
DDS1TW = {DDS1TW[23:13],RAM[11:0],1’b0}
DDS1TW = {DDS1TW[23:12],RAM[11:0]}
DDS1TW = {DDS1TW[23:11],RAM[11:1]}
DDS1TW = {DDS1TW[23:10],RAM[11:2]}
DDS1TW = {DDS1TW[23:9],RAM[11:3]}
DDS1TW = {DDS1TW[23:8],RAM[11:4]}
Reserved
Reset
Access
Start Delay4 Register (START_DLY4, Address 0x50)
Table 65. Bit Descriptions for START_DLY4
Bits
[15:0]
Bit Field Name
START_DELAY4
Settings
Description
Start delay of DAC4.
Reset
0x0000
Access
RW
Reset
0x000
Access
RW
0x00
RW
Reset
0x000
Access
RW
0x00
RW
Reset
0x0001
Access
RW
Reset
0x0000
Access
RW
Reset
0x000
Access
RW
0x0
RW
E
A
Start Address4 Register (START_ADDR4, Address 0x51)
Table 66. Bit Descriptions for START_ADDR4
Bits
[15:4]
Bit Field Name
START_ADDR4
[3:0]
RESERVED
Settings
Description
RAM address where DAC4 starts to read waveform.
E
A
E
A
Stop Address4 Register (STOP_ADDR4, Address 0x52)
Table 67. Bit Descriptions for STOP_ADDR4
Bits
[15:4]
Bit Field Name
STOP_ADDR4
[3:0]
RESERVED
Settings
Description
RAM address where DAC4 stops to read waveform.
E
A
E
A
DDS Cycle4 Register (DDS_CYC4, Address 0x53)
Table 68. Bit Descriptions for DDS_CYC4
Bits
[15:0]
Bit Field Name
DDS_CYC4
Settings
Description
Number of sine wave cycles when DDS prestored waveform with
start and stop delays is selected for DAC4 output.
E
A
Start Delay3 Register (START_DLY3, Address 0x54)
Table 69. Bit Descriptions for START_DLY3
Bits
[15:0]
Bit Field Name
START_DELAY3
Settings
Description
Start delay of DAC3.
E
A
Start Address3 Register (START_ADDR3, Address 0x55)
Table 70. Bit Descriptions for START_ADDR3
Bits
[15:4]
Bit Field Name
START_ADDR3
[3:0]
RESERVED
Settings
Description
RAM address where DAC3 starts to read waveform.
Rev. A | Page 45 of 48
E
A
A
E
AD9106
Data Sheet
Stop Address3 Register (STOP_ADDR3, Address 0x56)
Table 71. Bit Descriptions for STOP_ADDR3
Bits
[15:4]
Bit Field Name
STOP_ADDR3
[3:0]
RESERVED
Settings
Description
RAM address where DAC3 stops to read waveform.
Reset
0x0000
Access
RW
0x0
RW
E
A
E
A
DDS Cycles3 Register (DDS_CYC3, Address 0x57)
Table 72. Bit Descriptions for DDS_CYC3
Bits
[15:0]
Bit Field Name
DDS_CYC3
Settings
Description
Number of sine wave cycles when DDS prestored waveform with start and
stop delays is selected for DAC3 output.
Reset
0x0001
Access
RW
Reset
0x0000
Access
RW
E
A
Start Delay2 Register (START_DLY2, Address 0x58)
Table 73. Bit Descriptions for START_DLY2
Bits
[15:0]
Bit Field Name
START_DELAY2
Settings
Description
Start delay of DAC2.
E
A
Start Address2 Register (START_ADDR2, Address 0x59)
Table 74. Bit Descriptions for START_ADDR2
Bits
[15:4]
Bit Field Name
START_ADDR2
[3:0]
RESERVED
Settings
Description
RAM address where DAC2 starts to read waveform.
Reset
0x000
Access
RW
0x0
RW
Reset
0x000
Access
RW
0x0
RW
Reset
0x0001
Access
RW
Reset
0x0000
Access
RW
E
A
E
A
Stop Address2 Register (STOP_ADDR2, Address 0x5A)
Table 75. Bit Descriptions for STOP_ADDR2
Bits
[15:4]
Bit Field Name
STOP_ADDR2
[3:0]
RESERVED
Settings
Description
RAM address where DAC2 stops to read waveform.
E
A
E
A
DDS Cycle2 Register (DDS_CYC2, Address 0x5B)
Table 76. Bit Descriptions for DDS_CYC2
Bits
[15:0]
Bit Field Name
DDS_CYC2
Settings
Description
Number of sine wave cycles when DDS prestored waveform with
start and stop delays is selected for DAC2 output.
E
A
Start Delay1 Register (START_DLY1, Address 0x5C)
Table 77. Bit Descriptions for START_DLY1
Bits
[15:0]
Bit Field Name
START_DELAY1
Settings
Description
Start delay of DAC1.
Rev. A | Page 46 of 48
E
A
Data Sheet
AD9106
Start Address1 Register (START_ADDR1, Address 0x5D)
Table 78. Bit Descriptions for START_ADDR1
Bits
[15:4]
Bit Field Name
START_ADDR1
[3:0]
RESERVED
Settings
Description
RAM address where DAC1 starts to read waveform.
Reset
0x000
Access
RW
0x0
RW
Reset
0x000
Access
RW
0x0
RW
Reset
0x0001
Access
RW
Reset
0
0x00
0
Access
R
R
R
0
R
0
R
0
R
0
R
0
R
E
A
E
A
Stop Address1 Register (STOP_ADDR1, Address 0x5E)
Table 79. Bit Descriptions for STOP_ADDR1
Bits
[15:4]
Bit Field Name
STOP_ADDR1
[3:0]
RESERVED
Settings
Description
RAM address where DAC1 stops to read waveform.
E
A
E
A
DDS Cycle1 Register (DDS_CYC1, Address 0x5F)
Table 80. Bit Descriptions for DDS_CYC1
Bits
[15:0]
Bit Field Name
DDS_CYC1
Settings
Description
Number of sine wave cycles when DDS prestored waveform with
start and stop delays is selected for DAC1 output.
E
A
CFG Error Register (CFG_ERROR, Address 0x60)
Table 81. Bit Descriptions for CFG_ERROR
Bits
15
[14:6]
5
Bit Field Name
ERROR_CLEAR
CFG_ERROR
DOUT_START_LG_ERR
4
PAT_DLY_SHORT_ERR
3
DOUT_START_SHORT_ERR
2
PERIOD_SHORT_ERR
1
ODD_ADDR_ERR
0
MEM_READ_ERR
Settings
Description
Writing this bit clears all errors.
When DOUT_START is larger than pattern delay, this error
is toggled.
When pattern delay value is smaller than default value,
this error is toggled.
When DOUT_START value is smaller than default value,
this error is toggled.
When period register setting value is smaller than pattern
play cycle, this error is toggled.
When memory pattern play is not even in length in trigger
delay mode, this error flag is toggled.
When there is a memory read conflict, this error flag is
toggled.
Rev. A | Page 47 of 48
AD9106
Data Sheet
OUTLINE DIMENSIONS
0.30
0.25
0.18
32
25
1
24
0.50
BSC
*3.75
3.60 SQ
3.55
EXPOSED
PAD
17
TOP VIEW
0.80
0.75
0.70
0.50
0.40
0.30
8
16
9
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
PIN 1
INDICATOR
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
*COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5
WITH EXCEPTION TO EXPOSED PAD DIMENSION.
08-16-2010-B
PIN 1
INDICATOR
5.10
5.00 SQ
4.90
Figure 55. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
5 mm × 5 mm Body, Very Very Thin Quad
(CP-32-12)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD9106BCPZ
AD9106BCPZRL7
AD9106-EBZ
2F
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
32-Lead LFCSP_WQ
32-Lead LFCSP_WQ
Evaluation Board
Z = RoHS Compliant Part.
©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11121-0-2/13(A)
Rev. A | Page 48 of 48
Package Option
CP-32-12
CP-32-12