Cypress CY7C1345B-117BGC 128k x 36 synchronous flow-through 3.3v cache ram Datasheet

CY7C1345B
128K x 36 Synchronous Flow-Through 3.3V Cache RAM
Features
Functional Description
• Supports 117-MHz microprocessor cache systems with
zero wait states
• 128K by 36 common I/O
• Fast clock-to-output times
— 7.5 ns (117-MHz version)
• Two-bit wrap-around counter supporting either
interleaved or linear burst sequence
• Separate processor and controller address strobes provide direct interface with the processor and external
cache controller
• Synchronous self-timed write
• Asynchronous output enable
• Supports 3.3V & 2.5V I/O levels
• ZZ “sleep” mode
Logic Block Diagram
GW
The CY7C1345B allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the Processor
Address Strobe (ADSP) or the cache Controller Address
Strobe (ADSC) inputs. Address advancement is controlled by
the Address Advancement (ADV) input.
A synchronous self-timed write mechanism is provided to simplify the write interface. A synchronous chip enable input and
an asynchronous output enable input provide easy control for
bank selection and output three-state control.
MODE
(A0,A1) 2
BURST Q0
CE COUNTER
Q1
CLR
CLK
ADV
ADSC
ADSP
A[16:0]
The CY7C1345B is a 3.3V, 128K by 36 synchronous cache
RAM designed to interface with high-speed microprocessors
with minimum glue logic. Maximum access delay from clock
rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address
automatically for the rest of the burst access.
Q
17
15
ADDRESS
CE REGISTER
D
15
17
128K X 36
MEMORY
ARRAY
DDQ[31:24],DP3Q
BYTEWRITE
REGISTERS
BWE
BWS3
BWS 2
DDQ[23:16],DP2Q
BYTEWRITE
REGISTERS
BWS 1
D DQ[15:8],DP1 Q
BYTEWRITE
REGISTERS
D DQ[7:0],DP0 Q
BYTEWRITE
REGISTERS
BWS 0
CE1
CE2
CE3
36
36
D
ENABLE Q
CE REGISTER
CLK
INPUT
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQ[31:0]
DP[3:0]
Selection Guide
7C1345B-117
7C1345B-100
Maximum Access Time (ns)
7.5
8.0
Maximum Operating Current (mA)
350
325
Maximum Standby Current (mA)
2.0
2.0
Intel and Pentium are registered trademarks of Intel Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
September 11, 2000
CY7C1345B
Pin Configurations
2
3
VDDQ
VSSQ
DQ18
A8
A9
81
82
ADSP
ADV
83
84
BWE
GW
CLK
VSS
OE
ADSC
85
86
87
88
89
CE3
BWS0
VDD
90
91
92
93
BWS2
BWS3
CE2
BWS1
94
95
96
97
A7
CE1
98
80
79
DP1
78
DQ15
DQ14
4
77
VDDQ
5
6
76
75
VSSQ
DQ13
DQ19
7
74
DQ12
DQ20
DQ21
8
9
73
72
DQ11
VSSQ
10
71
VDDQ
DQ22
11
12
70
69
DQ23
13
68
DQ10
VSSQ
DQ9
DQ8
NC
14
15
16
VSS
17
64
VDD
ZZ
DQ24
DQ25
18
19
63
62
DQ7
DQ6
VDDQ
20
61
VDDQ
VSSQ
DQ26
21
22
60
59
VSSQ
DQ27
23
58
DQ28
DQ29
24
57
56
VSSQ
67
CY7C1345B
66
65
25
26
VSS
NC
DQ5
DQ4
DQ3
DQ2
39
40
41
42
45
46
47
48
49
50
VSS
VDD
DNU
DNU
A10
A11
A12
A13
A14
A15
A16
44
38
DNU
DNU
43
37
A0
DP0
36
51
A1
30
35
DP3
34
VDDQ
DQ1
DQ0
A2
53
52
A3
28
29
33
54
A4
VSSQ
27
32
55
VDDQ
DQ30
DQ31
2
BYTE1
VDDQ
VDD
NC
31
BYTE3
1
MODE
A5
BYTE2
DP2
DQ16
DQ17
99
100
A6
100-Pin TQFP
BYTE0
CY7C1345B
Pin Configurations (continued)
119-Ball BGA
1
2
3
4
5
6
7
A
VDDQ
A
A
ADSP
A
A
VDDQ
B
NC
CE2
A
ADSC
A
CE3
NC
C
NC
A
A
VDD
A
A
NC
D
DQc
DQPc
VSS
NC
VSS
DQPb
DQb
E
F
DQc
VDDQ
DQc
DQc
VSS
VSS
CE1
OE
VSS
VSS
DQb
DQb
DQb
VDDQ
G
H
J
DQc
DQc
DQc
DQc
BWc
VSS
ADV
GW
BWb
VSS
DQb
DQb
DQb
DQb
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K
DQd
DQd
VSS
CLK
VSS
DQa
DQa
L
DQd
DQd
BWd
NC
BWa
DQa
DQa
M
N
VDDQ
DQd
DQd
DQd
VSS
VSS
BWE
A1
VSS
VSS
DQa
DQa
VDDQ
DQa
P
DQd
DQPd
VSS
A0
VSS
DQPa
DQa
R
NC
A
MODE
VDD
VSS
A
NC
T
NC
NC
A
A
A
NC
ZZ
U
VDDQ
NC
NC
NC
NC
NC
VDDQ
Pin Descriptions
Name
I/O
Description
ADSC
InputSynchronous
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A[15:0]
is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
ADSP
InputSynchronous
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A[15:0]
is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
A[1:0]
InputSynchronous
A1, A 0 Address Inputs. These inputs feed the on-chip burst counter as the LSBs as well as being
used to access a particular memory location in the memory array.
A[16:2]
InputSynchronous
Address Inputs used in conjunction with A[1:0] to select one of the 64K address locations. Sampled
at the rising edge of the CLK, if CE1, CE2, and CE3 are sampled active, and ADSP or ADSC is active
LOW.
BW[3:0]
InputSynchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes. Sampled on the
rising edge. BW0 controls DQ[7:0] and DP0, BW1 controls DQ [15:8] and DP1, BW2 controls DQ[23:16]
and DP2, and BW3 controls DQ[31:24] and DP3. See Write Cycle Description table for further details.
ADV
InputSynchronous
Advance Input, used to advance the on-chip address counter. When LOW the internal burst counter
is advanced in a burst sequence. The burst sequence is selected using the MODE input.
BWE
InputSynchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
GW
InputSynchronous
Global Write Input, active LOW. Sampled on the rising edge of CLK. This signal is used to conduct
a global write, independent of the state of BWE and BW[3:0]. Global writes override byte writes.
CLK
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device.
CE1
InputSynchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
and CE3 to select/deselect the device. CE1 gates ADSP.
CE2
InputSynchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE3 to select/deselect the device.
3
CY7C1345B
Pin Descriptions (continued)
Name
I/O
Description
CE3
InputSynchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
and CE2 to select/deselect the device.
OE
InputAsynchronous
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,
the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input
data pins.
ZZ
InputAsynchronous
Snooze Input. Active HIGH asynchronous. When HIGH, the device enters a low-power standby
mode in which all other inputs are ignored, but the data in the memory array is maintained.Leaving
ZZ floating or NC will default the device into an active state. ZZ pin has an internal pull-down.
MODE
-
Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
Pulled LOW selects the linear burst order. When left floating or NC, defaults to interleaved burst
order. Mode pin has an internal pull-up.
DQ[31:0],
DP[3:0]
I/OSynchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by
the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by A[16:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by
OE in conjunction with the internal control logic. When OE is asserted LOW, the pins behave as
outputs. When HIGH, DQ[31:0] and DP[3:0] are placed in a three-state condition. The outputs are
automatically three-stated when a Write cycle is detected.
VDD
Power Supply
Power supply inputs to the core of the device. Should be connected to 3.3V power supply.
VSS
Ground
Ground for the I/O circuitry of the device. Should be connected to ground of the system.
VSSQ
Ground
Ground for the device. Should be connected to ground of the system.
VDDQ
I/O Power
Supply
Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.
NC
-
No connects.
DNU
-
Do not use pins. Should be left unconnected or tied LOW.
Functional Overview
serted active, and (2) ADSP or ADSC is asserted LOW (if the
access is initiated by ADSC, the write inputs must be deasserted during this first cycle). The address presented to the address inputs is latched into the address register and the burst
counter/control logic and presented to the memory core. If the
OE input is asserted LOW, the requested data will be available
at the data outputs a maximum to tCDV after clock rise. ADSP
is ignored if CE1 is HIGH.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (t CDV) is 7.5 ns (117-MHz device).
The CY7C1345B supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486 processors. The
linear burst sequence is suited for processors that utilize a
linear burst sequence. The burst order is user selectable, and
is determined by sampling the MODE input. Accesses can be
initiated with either the Processor Address Strobe (ADSP) or
the Controller Address Strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the
address for the rest of the burst access.
Functional Description
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, and (2) ADSP is asserted LOW. The addresses presented are loaded into the address register and the burst
counter/control logic and delivered to the RAM core. The write
inputs (GW, BWE, and BW[3:0]) are ignored during this first
clock cycle. If the write inputs are asserted active (see Write
Cycle Descriptions table for appropriate states that indicate a
write) on the next clock rise, the appropriate data will be
latched and written into the device. Byte writes are allowed.
During byte writes, BW0 controls DQ[7:0], BW1 controls
DQ [15:8], BW2 controls DQ[23:16], and BW3 controls DQ[31:24].
All I/Os are three-stated during a byte write. Since this is a
common I/O device, the asynchronous OE input signal must
be deasserted and the I/Os must be three-stated prior to the
presentation of data to DQ[31:0]. As a safety precaution, the
data lines are three-stated once a write cycle is detected, regardless of the state of OE.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[3:0]) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. ADSP is ignored if CE1
is HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all as-
4
CY7C1345B
Single Write Accesses Initiated by ADSC
Table 1. Counter Implementation for the Intel®
Pentium®/80486 Processor’s Sequence
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BW[3:0])
indicate a write access. ADSC is ignored if ADSP is active LOW.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the RAM
core. The information presented to DQ[31:0] will be written into
the specified address location. Byte writes are allowed. During
byte writes, BW0 controls DQ [7:0], BW1 controls DQ [15:8], BW2
controls DQ[23:16], and BWS3 controls DQ [31:24]. All I/Os are
three-stated when a write is detected, even a byte write. Since
this is a common I/O device, the asynchronous OE input signal
must be deasserted and the I/Os must be three-stated prior to
the presentation of data to DQ[31:0]. As a safety precaution, the
data lines are three-stated once a write cycle is detected, regardless of the state of OE.
First
Address
Second
Address
Third
Address
Fourth
Address
AX + 1, Ax
AX + 1, Ax
AX + 1, Ax
AX + 1, Ax
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Table 2. Counter Implementation for a Linear Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
AX + 1, Ax
AX + 1, Ax
AX + 1, Ax
AX + 1, Ax
Burst Sequences
00
01
10
11
The CY7C1345B provides an on-chip 2-bit wraparound burst
counter inside the SRAM. The burst counter is fed by A[1:0],
and can follow either a linear or interleaved burst order. The
burst order is determined by the state of the MODE input. A
LOW on MODE will select a linear burst sequence. A HIGH on
MODE will select an interleaved burst order. Leaving MODE
unconnected will cause the device to default to a interleaved
burst sequence.
01
10
11
00
10
11
00
01
11
00
01
10
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ HIGH
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the
“sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LOW. Leaving ZZ unconnected defaults the device into an active state.
5
CY7C1345B
Cycle Description Table[1, 2, 3]
Cycle Description
ADD
Used
CE1
CE3
CE2
ZZ
ADSP
ADSC
ADV
WE
OE
CLK
DQ
Deselected Cycle, Power-down
None
H
X
X
L
X
L
X
X
X
L-H
High-Z
Deselected Cycle, Power-down
None
L
X
L
L
L
X
X
X
X
L-H
High-Z
Deselected Cycle, Power-down
None
L
H
X
L
L
X
X
X
X
L-H
High-Z
Deselected Cycle, Power-down
None
L
X
L
L
H
L
X
X
X
L-H
High-Z
Deselected Cycle, Power-down
None
X
X
X
L
H
L
X
X
X
L-H
High-Z
Snooze Mode, Power-down
None
X
X
X
H
X
X
X
X
X
X
High-Z
Read Cycle, Begin Burst
External
L
L
H
L
L
X
X
X
L
L-H
Q
Read Cycle, Begin Burst
External
L
L
H
L
L
X
X
X
H
L-H
High-Z
Write Cycle, Begin Burst
External
L
L
H
L
H
L
X
L
X
L-H
D
Read Cycle, Begin Burst
External
L
L
H
L
H
L
X
H
L
L-H
Q
Read Cycle, Begin Burst
External
L
L
H
L
H
L
X
H
H
L-H
High-Z
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L-H
High-Z
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L-H
High-Z
Write Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L-H
D
Write Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L-H
D
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L-H
High-Z
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L-H
High-Z
Write Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L-H
D
Write Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L-H
D
Notes:
1. X = “Don't Care,” 1 = Logic HIGH, 0 = Logic LOW.
2. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BWS[3:0]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE
is a “Don't Care” for the remainder of the write cycle.
3. OE is asynchronous and is not sampled with the clock rise. During a read cycle DQ=High-Z when OE is inactive, and DQ=data when OE is active.
6
CY7C1345B
Write Cycle Descriptions[1, 2, 3, 4]
Function
GW
BWE
BW3
BW2
BW1
BW0
Read
1
1
X
X
X
X
Read
1
0
1
1
1
1
Write Byte 0, DP0
1
0
1
1
1
0
Write Byte 1, DP1
1
0
1
1
0
1
Write Bytes 1, 0, DP0, DP1
1
0
1
1
0
0
Write Byte 2, DP2
1
0
1
0
1
1
Write Bytes 2, 0, DP2, DP0
1
0
1
0
1
0
Write Bytes 2, 1, DP2, DP1
1
0
1
0
0
1
Write Bytes 2, 1, 0, DP2, DP1, DP0
1
0
1
0
0
0
Write Byte 3, DP3
1
0
0
1
1
1
Write Bytes 3, 0, DP3, DP0
1
0
0
1
1
0
Write Bytes 3, 1, DP3, DP0
1
0
0
1
0
1
Write Bytes 3, 1, 0, DP3, DP1, DP0
1
0
0
1
0
0
Write Bytes 3, 2, DP3, DP2
1
0
0
0
1
1
Write Bytes 3, 2, 0, DP3, DP2, DP0
1
0
0
0
1
0
Write Bytes 3, 2, 1, DP3, DP2, DP1
1
0
0
0
0
1
Write All Bytes
1
0
0
0
0
0
Write All Bytes
0
X
X
X
X
X
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Snooze mode
standby current
ZZ > VDD − 0.2V
10
mA
Device operation to
ZZ
ZZ > VDD − 0.2V
2tCYC
ns
ZZ recovery time
ZZ < 0.2V
ICCZZ
tZZS
tZZREC
Min.
Max.
Unit
2tCYC
Maximum Ratings
ns
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guidelines, not tested.)
Latch-Up Current .................................................... >200 mA
Storage Temperature ................................. –65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied ............................................. –55°C to +125°C
Ambient
Range Temperature[6]
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
Com’l
DC Voltage Applied to Outputs
in High Z State[5] ....................................–0.5V to VDD + 0.5V
Ind’l
DC Input Voltage[5].................................–0.5V to VDD + 0.5V
Notes:
4. When a write cycle is detected, all I/Os are three-stated, even during byte writes.
5. Minimum voltage equals –2.0V for pulse durations of less than 20 ns.
6. TA is the case temperature.
7
0°C to +70°C
–40°C to +85°C
VDD
VDDQ
3.135V to 3.6V
2.375V to VDD
CY7C1345B
Electrical Characteristics Over the Operating Range
Parameter
Description
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
Test Conditions
Min.
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
2.4
VDDQ = 2.5V, VDD = Min., IOH = –2.0 mA
2.0
Max.
Unit
V
V
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
0.4
V
VDDQ = 2.5V, VDD = Min., IOL = 2.0 mA
0.7
V
VIH
Input HIGH Voltage
VDDQ = 3.3V
2.0
VDD +
0.3V
V
VIH
Input HIGH Voltage
VDDQ = 2.5V
1.7
VDD +
0.3V
V
VIL
Input LOW Voltage[5]
VDDQ = 3.3V
–0.3
0.8
V
VIL
Input LOW Voltage
[5]
VDDQ = 2.5V
–0.3
0.7
V
IX
Input Load Current
(except ZZ and MODE)
GND ≤ VI ≤ VDDQ
−1
1
µA
Input Current of MODE
Input = VSS
–30
Input = VDDQ
Input Current of ZZ
Input = VSS
Output Leakage Current
[7]
IOS
Output Short Circuit Current
IDD
VDD Operating Supply Current
5
µA
30
µA
5
µA
–300
mA
µA
–5
Input = VDDQ
IOZ
µA
GND ≤ VI ≤ VDD, Output Disabled
VDD = Max., VOUT = GND
–5
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
8.5-ns cycle, 117 MHz
350
mA
10-ns cycle, 100 MHz
325
mA
Automatic CE Power-Down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC,
inputs switching
8.5-ns cycle, 117 MHz
125
mA
10-ns cycle, 100 MHz
110
mA
ISB2
Automatic CE Power-Down
Current—CMOS Inputs
Max. VDD, Device Deselected,
All speeds
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
f = 0, inputs static
10
mA
ISB3
Automatic CE Power-Down
Current—CMOS Inputs
8.5-ns cycle, 117 MHz
Max. VDD, Device Deselected,
VIN ≥ VDDQ– 0.3V or VIN ≤ 0.3V,
10-ns cycle, 100 MHz
f = fMAX, inputs switching
95
mA
85
mA
Automatic CE Power-Down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN ≥ VDD –0.3V or VIN ≤ 0.3V, f = 0,
inputs static
30
mA
ISB1
ISB4
Note:
7. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
8
CY7C1345B
Capacitance[8]
Parameter
Description
CIN
Input Capacitance
CI/O
I/O Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VDD = 5.0V
Max.
Unit
4.0
pF
4.0
pF
AC Test Loads and Waveforms
R1=317Ω
OUTPUT
3.3V
Z0 =50Ω
RL =50Ω
ALL INPUT PULSES
OUTPUT
3.0V
R2=351Ω GND
5 pF
VL =1.5V
INCLUDING
JIG AND
SCOPE
(a)
10%
90%
10%
90%
Rise Time: 1 V/ns
Fall Time: 1 V/ns
(b)
Switching Characteristics Over the Operating Range[9]
-117
Parameter
Description
Min.
-100
Max.
Min.
Max.
Unit
tCYC
Clock Cycle Time
tCH
Clock HIGH
3.0
4.0
ns
tCL
Clock LOW
3.0
4.0
ns
tAS
Address Set-Up Before CLK Rise
2.0
2.0
ns
tAH
Address Hold After CLK Rise
0.5
0.5
ns
tCDV
Data Output Valid After CLK Rise
tDOH
Data Output Hold After CLK Rise
2.0
2.0
ns
tADS
ADSP, ADSC Set-Up Before CLK Rise
2.0
2.0
ns
tADH
ADSP, ADSC Hold After CLK Rise
0.5
0.5
ns
tWES
BWS[1:0], GW,BWE Set-Up Before CLK Rise
2.0
2.0
ns
tWEH
BWS[1:0], GW,BWE Hold After CLK Rise
0.5
0.5
ns
tADVS
ADV Set-Up Before CLK Rise
2.0
2.0
ns
tADVH
ADV Hold After CLK Rise
0.5
0.5
ns
8.5
10
7.5
ns
8.0
ns
tDS
Data Input Set-Up Before CLK Rise
2.0
2.0
ns
tDH
Data Input Hold After CLK Rise
0.5
0.5
ns
tCES
Chip Enable Set-Up
2.0
2.0
ns
tCEH
Chip Enable Hold After CLK Rise
0.5
0.5
ns
[10, 11]
tCHZ
Clock to High-Z
tCLZ
Clock to Low-Z[10, 11]
tEOHZ
OE HIGH to Output High-Z[10, 12]
tEOLZ
OE LOW to Output Low-Z
tEOV
OE LOW to Output Valid
3.5
0
3.5
0
3.5
[10, 12]
0
3.5
0
3.5
ns
ns
ns
ns
3.5
ns
Notes:
8. Tested initially and after any design or process changes that may affect these parameters.
9. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and
output loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) of AC Test Loads.
10. tCHZ, t CLZ, tEOHZ, and tEOLZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage.
11. At any given voltage and temperature, tCHZ (max.) is less than tCLZ (min.).
12. This parameter is sampled and not 100% tested.
9
CY7C1345B
Timing Diagrams
Write Cycle Timing[13, 14]
S ingle W rite
B urst W rite
Pipelined Write
tCH
Unselected
tCYC
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
tADH
tADS
ADSC initiated write
ADSC
tADVH
tADVS
ADV
tAS
ADD
ADV Must Be Inactive for ADSP Write
WD1
WD3
WD2
tAH
GW
tWS
tWH
WE
tCES
tWH
tWS
tCEH
CE1 masks ADSP
CE1
tCES
tCEH
Unselected with CE2
CE2
CE3
tCES
tCEH
OE
tDH
tDS
Data In
High-Z
1a
1a
2a
2c
2b
= UNDEFINED
2d
3a
= DON’T CARE
Notes:
13. WE is the combination of BWE, BW[3:0], and GW to define a write cycle (see Write Cycle Descriptions table).
14. WDx stands for Write Data to Address X.
10
High-Z
CY7C1345B
Timing Diagrams (continued)
Read Cycle Timing[13, 15]
Burst Read
Single Read
tCYC
Unselected
tCH
Pipelined Read
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
tADS
ADSC initiated read
ADSC
tADVS
tADH
Suspend Burst
ADV
tADVH
tAS
ADD
RD1
RD3
RD2
tAH
GW
tWS
tWS
tWH
WE
tCES
tCEH
tWH
CE1 masks ADSP
CE1
Unselected with CE2
CE2
tCES
tCEH
CE3
tCES
OE
Data Out
tCEH
tEOV
tCDV
tOEHZ
tDOH
2a
1a
1a
2c 2c
2b
2d
3a
tCLZ
tCHZ
= DON’T CARE
= UNDEFINED
Note:
15. RDx stands for Read Data from Address X.
11
CY7C1345B
Timing Diagrams (continued)
Read/Write Timing
tCYC
tCH
tCL
CLK
tAH
tAS
ADD
A
B
D
C
tADH
tADS
ADSP
tADH
tADS
ADSC
tADVH
tADVS
ADV
tCEH
tCES
CE1
tCEH
tCES
CE
tWEH
tWES
WE
ADSP ignored
with CE1 HIGH
OE
tEOHZ
tCLZ
Data
Q(A)
In/Out
Q(B)
Q
(B+1)
Q
(B+2)
Q
(B+3)
Q(B)
D(C)
D
(C+1)
D
(C+2)
D
(C+3)
Q(D)
tCDV
tDOH
tCHZ
Device originally
deselected
WE is the combination of BWE, BWS[1:0], and GW to define a write cycle (see Write Cycle Descriptions table).
CE is the combination of CE 2 and CE3. All chip selects need to be active in order to select
the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X,
Qx stands for Data-out X.
= DON’T CARE
12
= UNDEFINED
CY7C1345B
Timing Diagrams (continued)
Pipeline Timing
tCH
tCYC
tCL
CLK
tAS
ADD
RD1
tADS
RD2
RD3
WD1
RD4
WD2
WD3
WD4
tADH
ADSC initiated Reads
ADSC
ADSP initiated Reads
ADSP
ADV
tCEH
tCES
CE1
CE
tWES
tWEH
WE
ADSP ignored
with CE1 HIGH
OE
tCLZ
Data In/Out
1a
Out
2a
Out
3a
Out
1a
In
4a
Out
2a
In
3a
In
4a
D(C)
In
tCDV
tDOH
Back to Back Reads
tCHZ
Back to Back Writes
= UNDEFINED
= DON’T CARE
13
CY7C1345B
Timing Diagrams (continued)
OE Switching Waveforms
OE
tEOV
tEOHZ
I/Os
three-state
tEOLZ
14
CY7C1345B
Timing Diagrams (continued)
ZZ Mode Timing [16, 17]
CLK
ADSP
HIGH
ADSC
CE1
CE2
LOW
HIGH
CE3
ZZ
ICC
tZZS
ICC(active)
ICCZZ
tZZREC
I/Os
Three-state
Notes:
16. Device must be deselected when entering ZZ mode. See Cycle Description Table for all possible signal conditions to deselect the device.
17. I/Os are in three-state when exiting ZZ sleep mode.
15
CY7C1345B
Ordering Information
Speed
(MHz)
117
Ordering Code
CY7C1345B-117AC
CY7C1345B-117BGC
100
CY7C1345B-100AC
CY7C1345B-100BGC
CY7C1345B-100AI
CY7C1345B-100BGI
Package
Name
A101
BG119
A101
BG119
A101
BG119
Package Type
100-Lead Thin Quad Flat Pack
Operating
Range
Commercial
119-Ball BGA
100-Lead Thin Quad Flat Pack
119-Ball BGA
100-Lead Thin Quad Flat Pack
Industrial
119-Ball BGA
Document #: 38-00953-*B
Package Diagram
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
16
CY7C1345B
Package Diagram
119-Lead FBGA (14 x 22 x 2.4 mm) BG119
51-85115
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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