ASAHI KASEI [AKD4565] AKD4565 Evaluation board Rev.A for AK4565 GENERAL DESCRIPTION AKD4565 is an evaluation board for the 20bit 2ch A/D and D/A converter, AK4565. The AKD4565 can evaluate A/D converter and D/A converter separately in addition to loopback mode (A/D → D/A). The A/D section can be evaluated by interfacing with AKM’s DAC evaluation boards directly. The AKD4565 has the interface with AKM’s ADC evaluation boards. Therefore, it’s easy to evaluate the D/A section. The AKD4565 also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector. Ordering guide AKD4565 --- Evaluation board for AK4565 (Cable for connecting with printer port of IBM-AT, compatible PC and control software are packed with this.) FUNCTION • Compatible with 2 types of interface - Direct interface with AKM’s A/D & D/A converter evaluation boards - DIT/DIR with optical input/output • BNC connector for an external clock input • 10pin Header for serial control mode VA GND VT LIN JP13 RIN JP14 Opt In AK4353 (DIT) Opt Out AK4565 LOUT ROUT Control Data CS8412 (DIR) Clock Generator A/D, D/A Data 10pin Header 10pin Header Figure 1. AKD4565 Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual. <KM067001> 2002/01 -1- ASAHI KASEI [AKD4565] EVALATION BOARD MANUAL Operation sequence 1) Set up the power supply lines. [VA] (orange) = 2.3 ∼ 3.6V [VT] (orange) = 1.5 ∼ 3.6V [D2V] (orange) = 1.5 ∼ 3.6V [D5V] (red) = 3.6 ∼ 5.0V [AGND] (black) = 0V [DGND] (black) = 0V : for VA of AK4565 (typ. 2.5V) : for VT of AK4565 (typ. 2.5V) : for 74LVC541 (typ. 2.5V) : for logic (typ. 5.0V) : for analog ground : for logic ground Each supply line should be distributed from the power supply unit. VT and D2V must be same voltage level. 2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.) 3) Power on. The AK4565 and AK4353(DIT) should be reset once bringing SW1, 2 “L” upon power-up. Evaluation mode Applicable Evaluation Mode 1) Evaluation of loopback mode <Default> 2) Evaluation of D/A using A/D converted data 3) Evaluation of D/A using DIR (Optical Link) 4) Evaluation of A/D using D/A converted data 5) Evaluation of A/D using DIT (Optical Link) 6) All interface signals including master clock are fed externally. 1) Evaluation of loopback mode. <Default> Nothing should be connected to PORT3 and PORT4. In case of using external clock through a BNC connector (J1), select EXT on JP11 (CLK) and short JP12 (XTE). When SDTO0 is connected with SDTI, JP8 (SD0/1) selects SD0 side. When SDTO1 is connected with SDTI, JP8 (SD0/1) selects SD1 side. Does not support DIF1-0 = “01”. 64fs JP4 LRCK ADC DIR JP5 BCLK ADC DIR JP9 SDTI ADC DIR VD JP10 JP11 JP12 DIR CLK XTE GND DIR 32fs AK4565 JP3 (X_BCLK) SDTO0/SDTO1 (ADC) SDTI (DAC) 20bit MSB justified 16bit LSB justified 32fs 20bit MSB justified 20bit MSB justified 64fs I2S Compatible I2S Compatible 32fs or 64fs Table 1. AK4565 audio data I/F format and JP3 Setting <KM067001> XTL JP3 X_BCLK DIF0 0 0 1 EXT DIF1 0 1 1 2002/01 -2- ASAHI KASEI [AKD4565] 2) Evaluation of D/A using A/D converted data. It is possible to make evaluation in the form of analog inputs and analog outputs by interfacing with various AKM’s A/D evaluation boards with PORT3. MCLK, BCLK, LRCK and SDTO0/1 are sent from AKD4565 to AKM’s D/A evaluation boards. Nothing should be connected to PORT1, PORT4. In case of using external clock through a BNC connector (J1), select EXT on JP11 (CLK) and short JP12 (XTE). ADC DIR ADC DIR JP10 JP9 SDTI ADC DIR DIR VD JP11 CLK JP12 XTE GND XTL 64fs JP5 BCLK DIR 32fs JP4 LRCK EXT JP3 X_BCLK 3) Evaluation of D/A using DIR. (Optical link) PORT4 (DIR) is used. DIR generates MCLK, BCLK, LRCK and SDATA from the received data through optical connector (TORX176). Used for the evaluation using CD test disk. Nothing should be connected to PORT1 and PORT3. ADC DIR ADC DIR JP10 DIR JP9 SDTI ADC DIR VD JP11 CLK JP12 XTE GND XTL 64fs JP5 BCLK DIR 32fs JP4 LRCK EXT JP3 X_BCLK 4) Evaluation of A/D using D/A converted data. It is possible to make evaluation in the form of analog inputs and analog outputs by interfacing with various AKM’s D/A evaluation boards with PORT3. MCLK, BCLK and LRCK are sent from AKM’s D/A evaluation board to AKD4565. Nothing should be connected to PORT4. When SDTO0 is supplied via PORT1, JP8 (SD0/1) selects SD0 side. When SDTO1 is supplied via PORT1, JP8 (SD0/1) selects SD1 side. ADC DIR ADC DIR JP10 DIR JP9 SDTI ADC DIR VD JP11 CLK <KM067001> JP12 XTE GND XTL 64fs JP5 BCLK DIR 32fs JP4 LRCK EXT JP3 X_BCLK 2002/01 -3- ASAHI KASEI [AKD4565] 5) Evaluation of A/D using DIT. (Optical link) PORT1 (DIT) is used. DIT generates audio bi-phase signal from received data and which is output through optical connector (TOTX176). It is possible to connect AKM’s D/A converter evaluation boards on the digital-amplifier which equips DIR input. Nothing should be connected PORT3 and PORT4. In case of using external clock through a BNC connector (J1), select EXT on JP11 (CLK) and short JP12 (XTE). When SDTO0 is supplied via PORT1, JP8 (SD0/1) selects SD0 side. When SDTO1 is supplied via PORT1, JP8 (SD0/1) selects SD1 side. ADC DIR ADC DIR JP10 DIR JP9 SDTI ADC DIR VD JP11 CLK JP12 XTE GND XTL 64fs JP5 BCLK DIR 32fs JP4 LRCK EXT JP3 X_BCLK 6) All interfacing signals (MCLK, BCLK, LRCK) are fed from the external circuit through PORT3. Under the following set up, all external signals needed for the AK4565 to operate could be fed through PORT3. In case of interfacing external sources to D/A converter, JP7 (SDTO) should be open. And in case of using A/D data to externally, JP9 (SDTI) is set ADC side. When JP9 (SDTI) is open, the A/D data can be output from the PORT3, if JP7 (SDTO) is short. ADC DIR ADC DIR JP10 DIR JP9 SDTI ADC DIR VD JP11 CLK <KM067001> JP12 XTE GND XTL 64fs JP5 BCLK DIR 32fs JP4 LRCK EXT JP3 X_BCLK 2002/01 -4- ASAHI KASEI [AKD4565] DIP Switch set up [SW3] (MODE): Setting evaluation mode of CS8412(DIR) ON is “1”, OFF is “0”. AK4565 SW3 MODE DIF1 DIF0 M0 M1 M2 0 0 16bit LSB justified 1 0 1 0 1 20bit LSB justified N/A 1 0 20bit MSB justified 0 0 0 1 1 I2S Compatible 0 1 0 Table 2. AK4565 audio data I/F format and SW3 and JP6 Setting JP6 THR INV THR SW3 and AK4565 format must be the same audio data format. Other jumper pins set up 1. JP1 (GND) : Analog ground and Digital ground OPEN : Separated. SHORT : Common. (The connector “DGND” can be open.) <Default> 2. JP2 (VT) : D2V and VT OPEN : Separated. <Default> SHORT : Common. (The connector “VT” can be open.) 3. JP6 (PHASE) : Phase of BCLK using DIR THR : BCLK is coincides with AK4565. (16bit LSB justified and I2S compatible for DAC.) INV : BCLK is inverted. (20bit MSB justified for DAC.) 4. JP7 (SDTO) : When JP9 (SDTI) is open, the A/D data can be output from the PORT3. *Always open. When evaluation mode is “6)”, JP7 can be short. 5. JP8 (SD0/1) : Select SDTO0 or SDTO1 SD0 : Select SDTO0. SD1 : Select SDTO1. The function of the toggle SW Upper-side is “H” and lower-side is “L”. [SW1] (PDN): Power down of the AK4565. Keep “H” during normal operation. [SW2] (DIT): Power down of the AK4353. Keep “H” during normal operation. Indication for LED [LED1] (VERF): Monitor VERF pin of the CS8412. LED turns on when some error has occurred to the CS8412. [LED2] (PREM): Indicate whether the input data of the CS8412 is pre-emphasized or not. <KM067001> 2002/01 -5- ASAHI KASEI [AKD4565] Serial Control The AK4565 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT2 (CTRL) with PC by 10 wire flat cable packed with the AKD4565. Connect PC 10 wire flat cable 10pin Connector CSN CCLK CDTI AKD4565 10pin Header Figure 2. Connect of 10-wire flat cable <KM067001> 2002/01 -6- ASAHI KASEI [AKD4565] Input / Output circuits & Set-up jumper pin for Input / Output circuits (1) Input circuits J2 LIN JP13 INTL1 + R34 560 C37 10u INT1 INT0 EXT LIN C38 10u + LIN INTL0 C39 10u + EXTL C41 10u + J4 RIN JP14 C42 10u INT1 INT0 EXT RIN + R38 560 LIN + RIN INTR1 C44 10u INTR0 C45 10u + EXTR C46 10u + RIN Figure 3. LIN/RIN Input circuits 1. Analog signal is input to INTL1 and INTR1 pins via J2 and J4 connectors. JP13 LIN JP14 RIN INT1 INT1 INT0 INT0 EXT EXT LIN RIN 2. Analog signal is input to INTL0 and INTR0 pins via J2 and J4 connectors. JP13 LIN JP14 RIN INT1 INT1 INT0 INT0 EXT EXT LIN RIN <KM067001> 2002/01 -7- ASAHI KASEI [AKD4565] 3. Analog signal is input to EXTL and EXTR pins via J2 and J4 connectors. JP13 LIN JP14 RIN INT1 INT1 INT0 INT0 EXT EXT LIN RIN 4. Analog signal is input to LIN and RIN pins via J2 and J4 connectors. JP13 LIN JP14 RIN INT1 INT1 INT0 INT0 EXT EXT LIN RIN (2) Output circuits + Analog signal is output to LOUT and ROUT pins via J3 and J5 connectors. R35 220 J3 LOUT R37 220 J5 ROUT LOUT R36 10k + C40 22u ROUT C43 22u R39 10k Figure 4. LOUT/ROUT output circuits * AKM assumes no responsibility for the trouble when using the above circuit examples. <KM067001> 2002/01 -8- ASAHI KASEI [AKD4565] CONTROL SOFTWARE MANUAL Set-up of evaluation board and control software 1. Set up the AKD4565 according to previous term. 2. Connect IBM-AT compatible PC with AKD4565 by 10-line type flat cable (packed with AKD4565). Take care of the direction of 10pin header. (This control software does not operate on Windows NT, therefore please operate it on Windows95/98.) 3. Insert the floppy-disk labeled “AKD4565 Control Program ver 1.0” into the floppy-disk drive. 4. Access the floppy-disk drive and double-click the icon of “akd4565.exe” to set up the control program. 5. Then please evaluate according to the follows. Operation flow Keep the following operation flow. 1. Set up the control program according to explanation above. 2. Click “Port Setup” button. 3. Click “Write default” button. 4. Set up evaluation mode of AK4353. 5. Then set up the dialog and input data. Explanation of each buttons (1) AK4565 control 1. [Port Setup] : 2. [Write default] : 3. [Read]: 4. [Function1] : 5. [Function2] : 6. [Write] : Set up the printer port. Initialize the register of AK4565. Dialog to read data by keyboard operation. Dialog to write data by keyboard operation. Dialog to evaluate IPGA. Dialog to write data by mouse operation. (2) AK4353 control 1. [MSB] : 2. [LSB] : 3. [I2S] : MSB justified for DIT mode in AK4353. LSB justified for DIT mode in AK4353. When the AK4565 is selected to 20bit MSB justified and BICK=32fs, this mode is used. I2S compatible for DIT mode in AK4353. Note 1. Evaluation mode of AK4353 and AK4565 is the same mode. For example, when the AK4565 is evaluated by I2S compatible mode in audio data I/F format, please click “I2S” button. Note 2. The default of AK4353 is MCLK=256fs and I2S compatible mode. Note 3. MCLK of AK4353 is fixed to 256fs. <KM067001> 2002/01 -9- ASAHI KASEI [AKD4565] Explanation of each dialog 1. [Read Dialog] : Address Box: Dialog to write data by keyboard operation Input register address in 2 figures of hexadecimal. If you want to write the input data to AK4565, click “OK” button. If not, click “Cancel” button. 2. [Function1 Dialog] : Address Box: Data Box: Dialog to write data by keyboard operation Input register address in 2 figures of hexadecimal. Input register data in 2 figures of hexadecimal. If you want to write the input data to AK4565, click “OK” button. If not, click “Cancel” button. 3. [Function2 Dialog] : Dialog to evaluate IPGA This dialog corresponds to only addr=07H. Address Box: Input register address in 2 figures of hexadecimal. Start Data Box: Input start data in 2 figures of hexadecimal. End Data Box: Input end data in 2 figures of hexadecimal. Interval Box: Data is written to AK4565 by this interval. Step Box: Data changes by this step. Mode Select Box: If you check this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 If you do not check this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 If you want to write the input data to AK4565, click “OK” button. If not, click “Cancel” button. 4. [Write Dialog] : Dialog to write data by mouse operation There are dialogs corresponding to each register. Click the “Write” button corresponding to each register to set up the dialog. If you check the check box, data becomes “H” or “1”. If not, “L” or “0”. If you want to write the input data to AK4565, click “OK” button. If not, click “Cancel” button. Indication of data Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”. Blank is the part that is not defined in the datasheet. Attention on the operation If you set up Function1 or Function2 dialog, input data to all boxes. Attention dialog is indicated if you input data or address that is not specified in the datasheet or you click “OK” button before you input data. In that case set up the dialog and input data once more again. These operations does not need if you click “Cancel” button or check the check box. <KM067001> 2002/01 - 10 - ASAHI KASEI [AKD4565] MEASUREMENT RESULTS [Measurement condition] • Measurement unit: Audio Precision, System Two • MCLK : 256fs • BCLK : 64fs • fs : 48kHz • Bit : 20bit • Power Supply : VA=VD=VT=2.5V • Interface : DIR/DIT • Temperature : Room [Measurement Results] Parameter ADC Analog Input Characteristics S/(N+D) (-2.0dB Input) D-Range (A-weighted) S/N (A-weighted) Interchannel Isolation DAC Analog Output Characteristics S/(N+D) D-Range (A-weighted) S/N (A-weighted) Interchannel Isolation Input Pin Result (Lch / Rch) Unit INTL0 / INTR0 INTL1 / INTR1 EXTL / EXTR LIN / RIN INTL0 / INTR0 INTL1 / INTR1 EXTL / EXTR LIN / RIN INTL0 / INTR0 INTL1 / INTR1 EXTL / EXTR LIN / RIN INTL0 / INTR0 INTL1 / INTR1 EXTL / EXTR LIN / RIN 86.2 / 86.2 86.1 / 86.2 86.2 / 86.1 85.7 / 85.7 88.8 / 88.9 88.8 / 88.9 88.7 / 88.8 88.3 / 88.3 88.8 / 88.9 88.6 / 88.8 88.7 / 88.9 88.3 / 88.2 110.7 / 110.0 110.2 / 110.3 110.4 / 110.5 107.0 / 108.0 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB - 88.5 / 88.5 91.9 / 91.5 92.5 / 92.7 108.1 / 107.9 dB dB dB dB <KM067001> 2002/01 - 11 - ASAHI KASEI [AKD4565] [ADC Plot] AKM AK4565 ADC THD+N vs. fin (fs=48kHz,-2dBFS input) -60 -64 -68 -72 d B F S -76 -80 -84 -88 -92 -96 -100 20 50 100 200 500 1k 2k 5k 10k 20k -12.45 -0.5 Hz Figure 5. THD+N vs. Input Frequency AKM AK4565 ADC T HD+N vs. Input Level ( fs=48kHz, fin=1kHz) -60 -64 -68 -72 d B F S -76 -80 -84 -88 -92 -96 -100 -120 -108.05 -96.1 -84.15 -72.2 -60.25 -48.3 -36.35 -24.4 dBr Figure 6. THD+N vs. Input Level <KM067001> 2002/01 - 12 - ASAHI KASEI [AKD4565] AKM A K 4 5 6 5 A D C C rosstalk (fs=48kHz,fin=1kHz, -2dBFS Input) Upper@1kHz; Lch--->Rch, Lower@1kHz; Rch---->Lch -70 -75 -80 -85 -90 -95 d B -100 -105 -110 -115 -120 -125 -130 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 7. Crosstalk AKM AK4565 ADC Linearity (fs=48kHz, fin=1kHz) +0 -20 -40 d B F S -60 -80 -100 -120 -140 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBr Figure 8. Linearity <KM067001> 2002/01 - 13 - ASAHI KASEI [AKD4565] AKM AK4565 ADC Frequency Response (fs=48kHz,-2dBFS Input) -1.5 -1.6 -1.7 -1.8 d B F S -1.9 -2 -2.1 -2.2 -2.3 -2.4 20 50 100 200 500 1k 2k 5k 10k 20k 10k 20k Hz Figure 9. Frequency Response AKM AK4565 ADC FFT (fs=48kHz, fin=1kHz, -2dBr Input) FFT point=16384, Avg=8, window=Equiripple +0 -20 -40 -60 d B F S -80 -100 -120 -140 -160 -180 20 50 100 200 500 1k 2k 5k Hz Figure 10. FFT plot <KM067001> 2002/01 - 14 - ASAHI KASEI [AKD4565] AKM AK4565 ADC FFT (fs=48kHz, fin=1kHz, -60dBr Input) FFT point=16384, Avg=8, window=Equiripple +0 -20 -40 -60 d B F S -80 -100 -120 -140 -160 -180 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 11. FFT plot AKM AK4565 ADC FFT (No signal Input) FFT point=16384, Avg=8, window=Equiripple +0 -20 -40 -60 d B F S -80 -100 -120 -140 -160 -180 20 50 100 200 500 1k 2k Hz Figure 12. FFT plot <KM067001> 2002/01 - 15 - ASAHI KASEI [AKD4565] [DAC Plot] AKM AK4565 DAC T HD+N vs. Input Frequency (fs=48kHz, input level=0dBFS) -60 -65 -70 d B r A -75 -80 -85 -90 -95 -100 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 13. THD+N vs. Frequency AKM AK4565 DAC THD+N vs. Input Lever (fs=48kHz, fin=1kHz) -60 -64 -68 -72 d B r -76 A -84 -80 -88 -92 -96 -100 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Figure 14. THD+N vs. Input Level <KM067001> 2002/01 - 16 - ASAHI KASEI [AKD4565] AKM A K 4 5 6 5 D A C C rosstalk (fs=48kHz, Input Level=0dB) Upper@1kHz Lch--->Rch, Lower@1kHz Rch--->Lch -60 -65 -70 -75 -80 -85 d B -90 -95 -100 -105 -110 -115 -120 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 15. Crosstalk AKM AK4565 DAC Linearity ( fs=48kHz, fin=1kHz) +0 -20 -40 d B r A -60 -80 -100 -120 -140 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Figure 16. Linearity <KM067001> 2002/01 - 17 - ASAHI KASEI AKM [AKD4565] AK4565 DAC Frequency Response (fs=48kHz, Input Level=0dB) +1 +0.8 +0.6 +0.4 d B r +0.2 A -0.2 -0 -0.4 -0.6 -0.8 -1 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k 10k 20k Hz Figure 17. Frequency Response AKM AK4565 DAC FFT (fs=48kHz, fin=1kHz, 0dBFS Input) FFT point=16384, Avg=8, window=Equiripple +0 -20 -40 -60 d B r -80 -100 A -120 -140 -160 -180 20 50 100 200 500 1k 2k 5k Hz Figure 18. FFT plot <KM067001> 2002/01 - 18 - ASAHI KASEI [AKD4565] AKM AK4565 DAC FFT (fs=48kHz, fin=1kHz, -60dBFS Input) FFT point=16384, Avg=8, window=Equiripple +0 -20 -40 -60 d B r -80 -100 A -120 -140 -160 -180 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 19. FFT plot AKM AK4565 DAC FFT (No d ata Input) FFT point=16384, Avg=8, window=Equiripple +0 -20 -40 -60 d B r -80 -100 A -120 -140 -160 -180 20 50 100 200 500 1k 2k Hz Figure 20. FFT plot <KM067001> 2002/01 - 19 - ASAHI KASEI [AKD4565] AKM AK4565 DAC FFT (Out-band-noise) FFT points=16384, Avg=8, widow=Equiripple +0 -10 -20 -30 -40 -50 -60 -70 d B r A -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 100 200 500 1k 2k 5k 10k 20k 50k 100k Hz last.at2c Figure 21. FFT plot (Out-of-band Noise) <KM067001> 2002/01 - 20 - A B C DGND D JP1 GND E AGND E E U1 1 LOUT 2 ROUT 3 INTL1 4 INTR1 LOUT PDN ROUT CCLK INTL1 CSN INTR1 CDTI U2 28 INTL0 CDTO 24 INTR0 6 INTR0 BCLK 23 8 EXTR LIN RIN C MCLK EXTR LRCK 51 11 R3 51 R4 51 25 5 EXTL R2 26 INTL0 7 51 27 D EXTL R1 R5 51 R6 51 51 R8 51 LIN SDTI 20 10 RIN SDTO1 19 SDTO1 11 VCOM SDTO0 18 SDTO0 12 AGND VT 17 13 VA DGND 16 VD 15 C1 47u + + C6 10u 1 + C4 0.1u D2V C7 0.1u C9 0.1u 14 VREF VA C2 0.1u 2 A7 13 Y6 A6 7 CSN 14 Y5 A5 6 CDTI 15 Y4 A4 5 BCLK 16 Y3 A3 4 MCLK 17 Y2 A2 3 LRCK 18 Y1 A1 2 SDTI 10 GND G2 19 20 VCC G1 1 2VD C10 10u AK4565 VD 2 B R9 10 (short) VT L3 10u 1 JP2 VT 2 C12 47u 2 + C 74LVC541 2VD + 1 C11 47u CCLK Y7 8 L2 1 B PDN 12 L1 10u + C5 10u C8 0.1u + C3 2.2u 9 CDTO 21 9 A8 D 22 R7 Y8 D1 1S1588 R10 10k 1 2 74HC14 3 U3B 4 PDN 74HC14 1 H 3 L U3A C13 0.1u 2 SW1 PDN A A Title Size A3 Date: A B C D AKD4565 Document Number Rev AK4565 Friday, October 26, 2001 Sheet E A 1 of 3 A B C D E VD PORT1 5 5 6 6 R11 1k DIT VD E VD 4 3 2 1 IN VCC IF GND C14 0.1u E 1 D2 1S1588 R16 10k U3C 74HC14 5 H 1 3 L 9 C16 0.1u 8 R14 10k R15 1k C15 10u C17 0.1u CSN R18 5.1 R19 470 VD CCLK + U4 1 2 3 4 5 6 7 8 9 10 11 12 2 SW2 DIT 6 R13 10k R17 470 U3D 74HC14 SDTO D R22 51 C18 0.1u MCKO TX DVDD DVSS MCKI BICK SDTI LRCK PDN CSN SCL/CCLK SDA/CDTI DZF NC AVDD AVSS VCOM AOUTL AOUTR CAD0 CAD1 I2C TTL TST 24 23 22 21 20 19 18 17 16 15 14 13 PORT2 10 9 8 7 6 C19 + 10u + 2 R12 10k C20 0.1u 1 2 3 4 5 R20 470 CSN CCLK CDTI CDTO CDTI R21 51 U5A SN74LVC07A 2 CTRL C21 10u 1 CDTO D AK4353 VD U6 X_LRCK ADC DIR_LRCK DIR ADC X_BCLK C R24 51 CSN SDTO 1 2 3 4 5 10 9 8 7 6 SDTO 9 7 6 5 3 2 4 13 12 14 15 1 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 ROM U3E 74HC14 VD R27 11 SDTI U3F 74HC14 2 12 VERF DIR A + C32 10u LED2 PREM 2 U7 R31 1k C33 0.01u C35 0.1u DIR_LRCK DIR_BCLK C36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 2 JP11 CLK C Cd/F1 Cc/F0 Cb/E2 Ca/E1 C0/E0 VD+ DGND RXP RXN FSYNC SCK CS12/FCK U VERF Ce/F2 SDATA ERF M1 M0 VA+ AGND FILT MCK M2 M3 SEL CBL 28 27 26 25 24 23 22 21 20 19 18 17 16 15 + 1 2 C31 0.1u 5 SDTO1 X1 13 L4 1 5 4 3 2 1 6 MCLK 10u 2 5 GND VCC GND OUT SDTO0 U5C SN74LVC07A M0 R30 C27 10u R32 1k M2 4 3 2 74HCU04 C34 47n JP12 XTE 1 74HCU04 C29 (open) C30 (open) A J1 EXT U8C 6 5 74HCU04 CS8412 1M U8A U8B C28 0.1u M1 1 12.288MHz XTL 1 L5 47u PORT4 3 B R29 1k LED1 1 6 Title R33 51 Size A3 0.01u Date: A for SN74LVC07A U5B SN74LVC07A 4 SD1 VD VD 6 R26 1k JP8 SD0/1 DIR EXT GND C 2VD SD0 VD + C22 47u C25 0.1u X_LRCK R25 1k JP9 SDTI C24 0.1u for 74HCU04, 74HC14, 74HC4040 C26 0.1u DIR R28 1k C23 0.1u VD DIR_BCLK B fs 74HC4040 10k JP10 DIR JP3 X_BCLK X_BCLK JP7 SDTO ADC THR INV RST PORT3 MCLK BCLK LRCK SDTI ROM BCLK LRCK 10 CLK 11 JP5 BCLK DIR JP6 PHASE 10 32fs CCLK JP4 LRCK 64fs CDTI R23 51 B C D AKD4565 Document Number Rev Interface Friday, October 26, 2001 Sheet E A 2 of 3 A B C D E E E JP13 C37 10u + R34 560 INT1 INT0 EXT LIN + LIN INTL1 C38 10u D INTL0 C39 10u + J2 LIN + EXTL C41 10u C40 22u INTR1 C44 10u + RIN C42 10u + R38 560 C INT1 INT0 EXT RIN + JP14 J3 LOUT R37 220 J5 ROUT D R36 10k LIN + J4 RIN R35 220 LOUT ROUT C43 22u INTR0 C45 10u C R39 10k + EXTR C46 10u + RIN VD M2 M1 M0 B SW3 1 2 3 U8D 74HCU04 6 5 4 8 MODE 9 U5D SN74LVC07A 8 U8E 74HCU04 RP1 3 2 1 10 M2 M1 M0 11 9 U5E SN74LVC07A 11 B 10 U5F SN74LVC07A 12 13 U8F 74HCU04 47k 12 13 A A Title Size A3 Date: A B C D AKD4565 Document Number Rev Input/Output Friday, October 26, 2001 Sheet E A 3 of 3 IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. • Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. • AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: a. A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. • It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.