CY7C1360C CY7C1362C PRELIMINARY 9-Mbit (256K x 36/512K x 18) Pipelined SRAM Functional Description[1] Features • • • • • • • • • • • • • • • • Supports bus operation up to 250 MHz Available speed grades are 250, 200, and 166 MHz Registered inputs and outputs for pipelined operation 3.3V core power supply 2.5V/3.3V I/O operation Fast clock-to-output times — 2.8 ns (for 250-MHz device) — 3.0 ns (for 200-MHz device) — 3.5 ns (for 166-MHz device) Provide high-performance 3-1-1-1 access rate User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences Separate processor and controller address strobes Synchronous self-timed writes Asynchronous output enable Single Cycle Chip Deselect Offered in Lead-Free 100-pin TQFP, 119-ball BGA and 165-Ball fBGA packages TQFP Available with 3-Chip Enable and 2-Chip Enable IEEE 1149.1 JTAG-Compatible Boundary Scan “ZZ” Sleep Mode Option The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3[2]), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to two or four bytes wide as controlled by the Byte Write control inputs. GW when active LOW causes all bytes to be written. The CY7C1360C/CY7C1362C operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Logic Block Diagram – CY7C1360C (256K x 36) A0, A1, A ADDRESS REGISTER 2 A[1:0] MODE ADV CLK Q1 BURST COUNTER CLR AND Q0 LOGIC ADSC ADSP BWD DQD ,DQPD BYTE WRITE REGISTER DQD ,DQPD BYTE WRITE DRIVER BWC DQC ,DQPC BYTE WRITE REGISTER DQC ,DQPC BYTE WRITE DRIVER DQB ,DQPB BYTE WRITE REGISTER DQB ,DQPB BYTE WRITE DRIVER BWB BWA BWE GW CE1 CE2 CE3 OE ZZ SENSE AMPS OUTPUT REGISTERS OUTPUT BUFFERS E DQs DQPA DQPB DQPC DQPD DQA ,DQPA BYTE WRITE DRIVER DQA ,DQPA BYTE WRITE REGISTER ENABLE REGISTER MEMORY ARRAY INPUT REGISTERS PIPELINED ENABLE SLEEP CONTROL Notes: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. 2. CE3 is for A version of TQFP (3 Chip Enable option) and 165 fBGA package only. 119 BGA is offered only in 2 Chip Enable. Cypress Semiconductor Corporation Document #: 38-05540 Rev. *C • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised February 23, 2005 CY7C1360C CY7C1362C PRELIMINARY Logic Block Diagram – CY7C1362C (512K x 18) A0, A1, A ADDRESS REGISTER 2 A[1:0] MODE BURST Q1 COUNTER AND LOGIC CLR Q0 ADV CLK ADSC ADSP BWB DQB,DQPB WRITE DRIVER DQB,DQPB WRITE REGISTER SENSE AMPS MEMORY ARRAY BWA OUTPUT REGISTERS DQA,DQPA WRITE DRIVER DQA,DQPA WRITE REGISTER OUTPUT BUFFERS DQs DQPA DQPB E BWE GW CE1 CE2 CE3 ENABLE REGISTER INPUT REGISTERS PIPELINED ENABLE OE ZZ SLEEP CONTROL Selection Guide 250 MHz 200 MHz 166 MHz Unit Maximum Access Time 2.8 3.0 3.5 ns Maximum Operating Current 250 220 180 mA Maximum CMOS Standby Current 30 30 30 mA Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Document #: 38-05540 Rev. *C Page 2 of 31 CY7C1360C CY7C1362C PRELIMINARY Pin Configurations NC NC NC VDDQ VSSQ NC NC DQB DQB VSSQ VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSSQ DQB DQB DQPB NC VSSQ VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1362C (512K x 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA MODE A A A A A1 A0 NC / 72M NC / 36M VSS VDD NC / 18M A A A A A A A A CY7C1360C (256K X 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A A A A A1 A0 NC / 72M NC / 36M VSS VDD NC / 18M A A A A A A A A DQPC DQC DQc VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 NC NC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 100-pin TQFP Pinout (3 Chip Enables) (A version) Document #: 38-05540 Rev. *C A NC NC VDDQ VSSQ NC DQPA DQA DQA VSSQ VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA NC NC VSSQ VDDQ NC NC NC Page 3 of 31 CY7C1360C CY7C1362C PRELIMINARY Pin Configurations (continued) NC NC NC VDDQ VSSQ NC NC DQB DQB VSSQ VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSSQ DQB DQB DQPB NC VSSQ VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1362C (512K x 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC NC VSS VDD NC NC A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA MODE A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A CY7C1360C (256K X 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A A A A A1 A0 DQPC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 NC NC BWB BWA A VDD VSS CLK GW BWE OE ADSC ADSP ADV A A A A CE1 CE2 BWD BWC BWB BWA A VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 100-pin TQFP (2 Chip Enables) (AJ Version) Document #: 38-05540 Rev. *C A NC NC VDDQ VSSQ NC DQPA DQA DQA VSSQ VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA NC NC VSSQ VDDQ NC NC NC Page 4 of 31 CY7C1360C CY7C1362C PRELIMINARY Pin Configurations (continued) 119-ball BGA (2 Chip Enables with JTAG) 1 CY7C1360C (256K x 36) 3 4 5 A A ADSP A VDDQ 2 A B C NC/288M NC/144M CE2 A A A ADSC VDD A A A A NC/576M NC/1G D E DQC DQC DQPC DQC VSS VSS NC CE1 VSS VSS DQPB DQB DQB DQB F VDDQ DQC VSS OE VSS DQB VDDQ G H J K DQC DQC VDDQ DQD DQC DQC VDD DQD BWC VSS NC VSS ADV BWB VSS NC VSS DQB DQB VDD DQA DQB DQB VDDQ DQA BWA VSS DQA DQA DQA VDDQ VSS DQA DQA GW VDD CLK NC 6 A 7 VDDQ L DQD DQD M VDDQ DQD BWD VSS N DQD DQD VSS BWE A1 P DQD DQPD VSS A0 VSS DQPA DQA R NC A MODE VDD NC A NC T U NC VDDQ NC/72M TMS A TDI A TCK A TDO NC/36M NC ZZ VDDQ CY7C1362C (512K x 18) 1 2 3 4 5 6 7 A VDDQ A A ADSP A A VDDQ B NC/288M CE2 A A NC/576M NC/144M A A ADSC VDD A C A A NC/1G D DQB NC VSS NC VSS DQPA NC E NC DQB VSS CE1 VSS NC DQA OE ADV VSS DQA VDDQ GW VDD VSS VSS NC NC DQA VDD DQA NC VDDQ CLK VSS NC DQA NC BWA VSS DQA NC NC VDDQ F VDDQ NC VSS G H J NC DQB VDDQ DQB NC VDD BWB VSS NC K NC DQB VSS L M DQB VDDQ NC DQB VSS VSS N DQB NC VSS BWE A1 VSS DQA NC P NC DQPB VSS A0 VSS NC DQA R T U NC NC/72M VDDQ A A TMS MODE A TDI VDD NC/36M TCK NC A TDO A A NC NC ZZ VDDQ Document #: 38-05540 Rev. *C Page 5 of 31 CY7C1360C CY7C1362C PRELIMINARY Pin Configurations (continued) 165-ball fBGA (3 Chip Enable with JTAG) CY7C1360C (256K x 36) 1 A B C D E F G H J K L M N P R 2 NC / 288M A 3 4 5 6 7 8 9 10 11 CE1 BWC BWB CE3 BWE ADSC ADV A NC NC/144M A CE2 BWD BWA CLK NC / 576M VDDQ VSS VSS VSS VSS VDDQ VDDQ VSS VDD OE VSS VDD A NC DQC GW VSS VSS ADSP DQPC DQC VDDQ NC/1G DQB DQPB DQB DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB DQC DQC NC DQD DQC VDDQ VDD VSS VSS VSS VDD DQB DQB DQC VSS DQD VDDQ NC VDDQ VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ VDDQ NC VDDQ DQB NC DQA DQB ZZ DQA DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQPD DQD NC VDDQ VDDQ VDD VSS VSS NC VSS NC / 18M VSS NC VDD VSS VDDQ VDDQ DQA NC DQA DQPA NC NC / 72M A A TDI A1 TDO A A A A MODE NC / 36M A A TMS TCK A A A A 7 8 9 10 11 A A0 CY7C1362C (512K x 18) A B C D E F G H J K L M N P R 1 2 NC / 288M A 3 4 5 6 NC CE3 A CE1 CE2 BWB NC/144M NC BWA NC NC NC DQB VDDQ VSS VDD VSS VDDQ CLK BWE GW ADSC OE ADV ADSP A VSS VSS VSS VSS VSS VDD VDDQ VSS VDDQ NC/1G NC NC / 576M A DQPA DQA NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA NC NC DQB DQB VSS NC VDDQ NC VDDQ VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ NC VDDQ NC NC DQA DQA ZZ NC DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC DQB DQPB NC NC VDDQ VDDQ VDD VSS VSS NC VSS NC / 18M VSS NC VDD VSS VDDQ VDDQ DQA NC NC NC NC NC / 72M A A TDI A1 TDO A A A A MODE NC / 36M A A TMS A0 TCK A A A A Document #: 38-05540 Rev. *C Page 6 of 31 CY7C1360C CY7C1362C PRELIMINARY Pin Definitions I/O Description A0, A1, A Name InputSynchronous Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3[2]are sampled active. A1, A0 are fed to the two-bit counter.. BWA, BWB BWC, BWD InputSynchronous GW InputSynchronous Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the SRAM. Sampled on the rising edge of CLK. Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global Write is conducted (ALL bytes are written, regardless of the values on BWX and BWE). BWE InputSynchronous Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a Byte Write. CLK InputClock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. CE1 InputSynchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3[2] to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. CE2 InputSynchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3[2] to select/deselect the device. CE2 is sampled only when a new external address is loaded. CE3[2] InputSynchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. Not available for AJ package version. Not connected for BGA. Where referenced, CE3[2] is assumed active throughout this document for BGA. CE3 is sampled only when a new external address is loaded. OE InputAsynchronous Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. ADV InputSynchronous Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it automatically increments the address in a burst cycle. ADSP InputSynchronous Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1, A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. ADSC InputSynchronous Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1, A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ZZ InputAsynchronous ZZ “Sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. DQs, DQPX I/OSynchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a three-state condition. VDD Power Supply Power supply inputs to the core of the device. VSS Ground VSSQ VDDQ MODE TDO I/O Ground Ground for the core of the device. Ground for the I/O circuitry. I/O Power Supply Power supply for the I/O circuitry. InputStatic Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode pin has an internal pull-up. JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the Synchronous JTAG feature is not being utilized, this pin should be disconnected. This pin is not available on TQFP packages. Document #: 38-05540 Rev. *C Page 7 of 31 CY7C1360C CY7C1362C PRELIMINARY Pin Definitions (continued) Name I/O Description TDI JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG Synchronous feature is not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. TMS JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG Synchronous feature is not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. TCK JTAGClock NC – Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be connected to VSS. This pin is not available on TQFP packages. No Connects. Not internally connected to the die Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 2.8 ns (250-MHz device). The CY7C1360C/CY7C1362C supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486™ processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte Write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BWX) inputs. A Global Write Enable (GW) overrides all Byte Write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed Write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3[2]) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) CE1, CE2, CE3[2] are all asserted active, and (3) the Write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs (A) is stored into the address advancement logic and the address register while being presented to the memory array. The corresponding data is allowed to propagate to the input of the output registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 2.8 ns (250-MHz device) if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always three-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single Read cycles are supported. Once the SRAM is deselected at clock rise by Document #: 38-05540 Rev. *C the chip select and either ADSP or ADSC signals, its output will three-state immediately. Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1, CE2, CE3[2] are all asserted active. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The Write signals (GW, BWE, and BWX) and ADV inputs are ignored during this first cycle. ADSP-triggered Write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQs inputs is written into the corresponding address location in the memory array. If GW is HIGH, then the Write operation is controlled by BWE and BWX signals. The CY7C1360C/CY7C1362C provides Byte Write capability that is described in the Write Cycle Descriptions table. Asserting the Byte Write Enable input (BWE) with the selected Byte Write (BWX) input, will selectively write to only the desired bytes. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because the CY7C1360C/CY7C1362C is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQs inputs. Doing so will three-state the output drivers. As a safety precaution, DQs are automatically three-stated whenever a Write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC Write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) CE1, CE2, CE3[2] are all asserted active, and (4) the appropriate combination of the Write inputs (GW, BWE, and BWX) are asserted active to conduct a Write to the desired byte(s). ADSC-triggered Write accesses require a single clock cycle to complete. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The ADV input is ignored during this cycle. If a global Write is conducted, the data presented to the DQs is written into the corresponding address location in the memory core. If a Byte Write is conducted, only the selected bytes are written. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Page 8 of 31 CY7C1360C CY7C1362C PRELIMINARY Because the CY7C1360C/CY7C1362C is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQs inputs. Doing so will three-state the output drivers. As a safety precaution, DQs are automatically three-stated whenever a Write cycle is detected, regardless of the state of OE. Linear Burst Address Table (MODE = GND) First Address A1, A0 00 01 10 11 Burst Sequences The CY7C1360C/CY7C1362C provides a two-bit wraparound counter, fed by A1, A0, that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both Read and Write burst operations are supported. Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1, A0 00 01 10 11 Second Address A1, A0 01 00 11 10 Third Address A1, A0 10 11 00 01 Second Address A1, A0 01 10 11 00 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 00 01 10 Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, CE3[2], ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Fourth Address A1, A0 11 10 01 00 ZZ Mode Electrical Characteristics Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Sleep mode standby current Device operation to ZZ ZZ recovery time ZZ Active to sleep current ZZ Inactive to exit sleep current Test Conditions ZZ > VDD – 0.2V ZZ > VDD – 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled Min. Max. 50 2tCYC 2tCYC 2tCYC 0 Unit mA ns ns ns ns Truth Table [3, 4, 5, 6, 7, 8] Operation Address Used CE2 X CE3 X DQ ZZ ADSP ADSC ADV WRITE OE CLK L X L X X X L-H Three-State Deselect Cycle, Power Down None CE1 H Deselect Cycle, Power Down None L L X L Deselect Cycle, Power Down None L X H Deselect Cycle, Power Down None L L X L X X X X L-H Three-State L L X X X X L-H Three-State L H L X X X L-H Three-State Deselect Cycle, Power Down None L X H L H L X X X L-H Three-State Sleep Mode, Power Down None X X X H X X X X X X Three-State READ Cycle, Begin Burst External L H L L L X X X L L-H Q READ Cycle, Begin Burst External L H L L L X X X H L-H Three-State Notes: 3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. 4. WRITE = L when any one or more Byte Write Enable signals and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals, BWE, GW = H. 5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 6. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has only two chip selects CE1 and CE2. 7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to three-state. OE is a don't care for the remainder of the Write cycle 8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Three-State when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). Document #: 38-05540 Rev. *C Page 9 of 31 CY7C1360C CY7C1362C PRELIMINARY Truth Table (continued)[3, 4, 5, 6, 7, 8] Operation Address Used CE2 H CE3 L L L H WRITE Cycle, Begin Burst External CE1 L READ Cycle, Begin Burst External L H READ Cycle, Begin Burst ZZ ADSP ADSC ADV WRITE OE CLK L H L X L X L-H DQ D L X H L L-H Q External L H L L H L X H H L-H Three-State READ Cycle, Continue Burst Next X X X L H H L H L L-H Q READ Cycle, Continue Burst Next X X X L H H L H H L-H Three-State READ Cycle, Continue Burst Next H X X L X H L H L L-H Q READ Cycle, Continue Burst Next H X X L X H L H H L-H Three-State WRITE Cycle, Continue Burst Next X X X L H H L L X L-H D WRITE Cycle, Continue Burst Next H X X L X H L L X L-H D READ Cycle, Suspend Burst Current X X X L H H H H L L-H Q READ Cycle, Suspend Burst Current X X X L H H H H H L-H Three-State READ Cycle, Suspend Burst Current H X X L X H H H L L-H Q READ Cycle, Suspend Burst Current H X X L X H H H H L-H Three-State WRITE Cycle, Suspend Burst Current X X X L H H H L X L-H D WRITE Cycle, Suspend Burst Current H X X L X H H L X L-H D Partial Truth Table for Read/Write[5, 9] GW BWE BWD BWC BWB BWA Read Function (CY7C1360C) H H X X X X Read H L H H H H Write Byte A – (DQA and DQPA) Write Byte B – (DQB and DQPB) H L H H H L H L H H L H Write Bytes B, A H L H H L L Write Byte C – (DQC and DQPC) H L H L H H Write Bytes C, A H L H L H L Write Bytes C, B H L H L L H Write Bytes C, B, A H L H L L L Write Byte D – (DQD and DQPD) H L L H H H Write Bytes D, A H L L H H L Write Bytes D, B H L L H L H Write Bytes D, B, A H L L H L L Write Bytes D, C H L L L H H Write Bytes D, C, A H L L L H L Write Bytes D, C, B H L L L L H Write All Bytes H L L L L L Write All Bytes L X X X X X Note: 9. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active. Document #: 38-05540 Rev. *C Page 10 of 31 CY7C1360C CY7C1362C PRELIMINARY Truth Table for Read/Write[5, 9] Function (CY7C1362C) GW BWE BWB BWA Read H H X X Read H L H H Write Byte A – (DQA and DQPA) Write Byte B – (DQB and DQPB) H L H L H L L H Write Bytes B, A H L L L Write All Bytes H L L L Write All Bytes L X X X IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1360C/CY7C1362C incorporates a serial boundary scan test access port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This part operates in accordance with IEEE Standard 1149.1-1900, but doesn’t have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC-standard 3.3V or 2.5V I/O logic levels. The CY7C1360C/CY7C1362C contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. TAP Controller State Diagram 1 TEST-LOGIC RESET RUN-TEST/ IDLE Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test MODE SELECT (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block Diagram.) Test Data-Out (TDO) 0 0 The 0/1 next to each state represents the value of TMS at the rising edge of TCK. 1 SELECT DR-SCAN 1 SELECT IR-SCAN 0 1 0 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 1 1 EXIT1-IR 0 0 1 0 PAUSE-DR 0 PAUSE-IR 1 0 1 EXIT2-DR 0 EXIT2-IR 1 1 UPDATE-DR 1 The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Tap Controller State Diagram.) 1 EXIT1-DR 0 1 0 Document #: 38-05540 Rev. *C UPDATE-IR 1 0 Page 11 of 31 PRELIMINARY TAP Controller Block Diagram state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I/O ring. 0 Bypass Register 2 1 0 TDI Selection Circuitry Instruction Register 31 30 29 . . . 2 1 0 Selection Circuitry TDO Identification Register x . . . . . 2 1 0 Boundary Scan Register TCK TMS CY7C1360C CY7C1362C TAP CONTROLLER The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Overview Performing a TAP Reset A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR Document #: 38-05540 Rev. *C Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the I/O buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather, it performs a capture of the I/O ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. Page 12 of 31 CY7C1360C CY7C1362C PRELIMINARY hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required—that is, while data captured is shifted out, the preloaded data can be shifted in. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. BYPASS To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus These instructions are not implemented but are reserved for future use. Do not use these instructions. When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved TAP Timing 1 2 Test Clock (TCK) 3 t TH t TMSS t TMSH t TDIS t TDIH t TL 4 5 6 t CYC Test Mode Select (TMS) Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON’T CARE Document #: 38-05540 Rev. *C UNDEFINED Page 13 of 31 CY7C1360C CY7C1362C PRELIMINARY TAP AC Switching Characteristics Over the Operating Range[10, 11] Parameter Description Min. Max. Unit Clock tTCYC TCK Clock Cycle Time tTF TCK Clock Frequency tTH TCK Clock HIGH time 25 ns tTL TCK Clock LOW time 25 ns 50 ns 20 MHz Output Times tTDOV TCK Clock LOW to TDO Valid tTDOX TCK Clock LOW to TDO Invalid 5 ns 0 ns Set-up Times tTMSS TMS Set-up to TCK Clock Rise 5 ns tTDIS TDI Set-up to TCK Clock Rise 5 ns tCS Capture Set-up to TCK Rise 5 tTMSH TMS hold after TCK Clock Rise 5 tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Hold Times ns 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions Input pulse levels ................................................ VSS to 3.3V Input pulse levels ........................................... VSS to 2.5V Input rise and fall times ..................... ..............................1 ns Input rise and fall time .....................................................1 ns Input timing reference levels ...........................................1.5V Input timing reference levels................... ......................1.25V Output reference levels...................................................1.5V Output reference levels .................. ..............................1.25V Test load termination supply voltage...............................1.5V Test load termination supply voltage .................... ........1.25V 3.3V TAP AC Output Load Equivalent 2.5V TAP AC Output Load Equivalent 1.5V 1.25V 50W 50W TDO TDO Z O= 50W Z O= 50W 20pF 20pF TAP DC Electrical Characteristics And Operating Conditions (0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted) [12] Parameter Description Conditions VOH1 Output HIGH Voltage VOH2 Output HIGH Voltage VOL1 Output LOW Voltage IOL = 8.0 mA IOH = –4.0 mA Max. Unit 2.4 V IOH = –1.0 mA VDDQ = 2.5V 2.0 V IOH = –100 µA VDDQ = 3.3V 2.9 V VDDQ = 2.5V 2.1 VDDQ = 3.3V VDDQ = 2.5V IOL = 8.0 mA Notes: 10. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 11. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1ns. Document #: 38-05540 Rev. *C Min. VDDQ = 3.3V V 0.4 V 0.4 V Page 14 of 31 CY7C1360C CY7C1362C PRELIMINARY TAP DC Electrical Characteristics And Operating Conditions (0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted) (continued)[12] Parameter Description VOL2 Output LOW Voltage VIH Input HIGH Voltage VIL Input LOW Voltage IX Input Load Current Conditions IOL = 100 µA Min. VDDQ = 3.3V VDDQ = 2.5V Max. Unit 0.2 V 0.2 V 2.0 VDD + 0.3 V VDDQ = 2.5V 1.7 VDD + 0.3 V VDDQ = 3.3V –0.5 0.7 V VDDQ = 2.5V –0.3 0.7 V –5 5 µA VDDQ = 3.3V GND < VIN < VDDQ Identification Register Definitions Instruction Field Revision Number (31:29) Device Depth (28:24)[13] Device Width (23:18) Cypress Device ID (17:12) Cypress JEDEC ID Code (11:1) CY7C1360C (256KX36) CY7C1362C (512KX18) 000 000 Description Describes the version number 01011 01011 000000 000000 Defines memory type and architecture Defines width and density 100110 010110 00000110100 00000110100 1 1 ID Register Presence Indicator (0) Reserved for Internal Use Allows unique identification of SRAM vendor Indicates the presence of an ID register Scan Register Sizes Register Name Instruction Bit Size (x36) Bit Size (x18) 3 3 Bypass 1 1 ID 32 32 Boundary Scan Order (119-ball BGA package) 71 71 Boundary Scan Order (165-ball fBGA package) 71 71 Identification Codes Instruction Code Description EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Notes: 12. All voltages referenced to VSS (GND). 13. Bit #24 is “1” in the Register Definitions for both 2.5v and 3.3v versions of this device. Document #: 38-05540 Rev. *C Page 15 of 31 CY7C1360C CY7C1362C PRELIMINARY AC Test Loads and Waveforms[14] 3.3V I/O Test Load R = 317Ω 3.3V OUTPUT Z0 = 50Ω 10% R = 351Ω (a) INCLUDING JIG AND SCOPE 2.5V I/O Test Load (b) (c) 10% R =1538Ω (a) INCLUDING JIG AND SCOPE 90% 10% 90% GND 5 pF VT = 1.25V ALL INPUT PULSES VDDQ OUTPUT RL = 50Ω Z0 = 50Ω ≤ 1 ns ≤ 1 ns R = 1667Ω 2.5V OUTPUT 90% 10% 90% GND 5 pF VT = 1.5V ALL INPUT PULSES VDDQ OUTPUT RL = 50Ω (b) ≤ 1 ns ≤ 1 ns (c) Note: 14. Tested initially and after any design or process change that may affect these parameters. Document #: 38-05540 Rev. *C Page 16 of 31 CY7C1360C CY7C1362C PRELIMINARY 165-Ball fBGA Boundary Scan Order CY7C1360C (256K x 36) Bit# Ball ID Signal Name 1 B6 2 B7 3 4 CY7C1362C (512K x 18) Signal Name Bit# Ball ID Signal Name Bit# Ball ID R6 A0 1 B6 CLK 37 R6 A0 P6 A1 2 B7 GW 38 P6 A1 39 R4 A 3 A7 BWE 39 R4 A 40 P4 A 4 B8 OE 40 P4 A ADSC 41 R3 A 5 A8 ADSC 41 R3 A ADSP 42 P3 A 6 B9 ADSP 42 P3 A 43 R1 MODE 7 A9 ADV 43 R1 MODE 44 N1 DQPD 8 B10 A 44 Internal Internal Bit# Ball ID CLK 37 GW 38 A7 BWE B8 OE 5 A8 6 B9 7 A9 ADV 8 B10 A Signal Name 9 A10 A 45 L2 DQD 9 A10 A 45 Internal Internal 10 C11 DQPB 46 K2 DQD 10 A11 A 46 Internal Internal 11 E10 DQB 47 J2 DQD 11 Internal Internal 47 Internal Internal 12 F10 DQB 48 M2 DQD 12 Internal Internal 48 N1 DQPB 13 G10 DQB 49 M1 DQD 13 Internal Internal 49 M1 DQB 14 D10 DQB 50 L1 DQD 14 C11 DQPA 50 L1 DQB 15 D11 DQB 51 K1 DQD 15 D11 DQA 51 K1 DQB 16 E11 DQB 52 J1 DQD 16 E11 DQA 52 J1 DQB 17 F11 DQB 53 Internal Internal 17 F11 DQA 53 Internal Internal 18 G11 DQB 54 G2 DQC 18 G11 DQA 54 G2 DQB 19 H11 ZZ 55 F2 DQC 19 H11 ZZ 55 F2 DQB 20 J10 DQA 56 E2 DQC 20 J10 DQA 56 E2 DQB 21 K10 DQA 57 D2 DQC 21 K10 DQA 57 D2 DQB 22 L10 DQA 58 G1 DQC 22 L10 DQA 58 Internal Internal 23 M10 DQA 59 F1 DQC 23 M10 DQA 59 Internal Internal 24 J11 DQA 60 E1 DQC 24 Internal Internal 60 Internal Internal 25 K11 DQA 61 D1 DQC 25 Internal Internal 61 Internal Internal 26 L11 DQA 62 C1 DQPC 26 Internal Internal 62 Internal Internal 27 M11 DQA 63 B2 A 27 Internal Internal 63 B2 A 28 N11 DQPA 64 A2 A 28 Internal Internal 64 A2 A 29 R11 A 65 A3 CE1 29 R11 A 65 A3 CE1 30 R10 A 66 B3 CE2 30 R10 A 66 B3 CE2 31 P10 A 67 B4 BWD 31 P10 A 67 Internal Internal 32 R9 A 68 A4 BWC 32 R9 A 68 Internal Internal 33 P9 A 69 A5 BWB 33 P9 A 69 A4 BWB 34 R8 A 70 B5 BWA 34 R8 A 70 B5 BWA 71 A6 CE3 71 A6 CE3 35 P8 A 36 P11 A Document #: 38-05540 Rev. *C 35 P8 A 36 P11 A Page 17 of 31 CY7C1360C CY7C1362C PRELIMINARY 119-Ball BGA Boundary Scan Order CY7C1360C (256K x 36) Signal Name BIT# K4 H4 CLK GW 3 M4 4 F4 5 6 CY7C1362C (512K x 18) BALL ID Signal Name Bit# Ball ID Signal Name Bit# Ball ID Signal Name 37 P4 A0 1 38 N4 A1 2 K4 H4 CLK GW 37 P4 A0 38 N4 A1 BWE 39 R6 A OE 40 T5 A 3 M4 4 F4 BWE 39 R6 A OE 40 T5 A B4 ADSC 41 T3 A A4 ADSP 42 R2 A 5 6 B4 ADSC 41 T3 A A4 ADSP 42 R2 A 7 G4 ADV 43 R3 8 C3 A 44 P2 MODE DQPD 7 G4 ADV 43 R3 MODE 8 C3 A 44 Internal Internal 9 B3 A 45 P1 DQD 9 B3 A 45 Internal Internal 10 D6 DQPB 46 L2 DQD 10 T2 A 46 Internal Internal 11 H7 DQB 47 K1 DQD 11 Internal Internal 47 Internal Internal 12 G6 DQB 48 N2 DQD 12 Internal Internal 48 P2 DQPB 13 E6 DQB 49 N1 DQD 13 Internal Internal 49 N1 DQB 14 D7 DQB 50 M2 DQD 14 D6 DQPA 50 M2 DQB 15 E7 DQB 51 L1 DQD 15 E7 DQA 51 L1 DQB 16 F6 DQB 52 K2 DQD 16 F6 DQA 52 K2 DQB 17 G7 DQB 53 Internal Internal 17 G7 DQA 53 Internal Internal 18 H6 DQB 54 H1 DQC 18 H6 DQA 54 H1 DQB 19 T7 ZZ 55 G2 DQC 19 T7 ZZ 55 G2 DQB 20 K7 DQA 56 E2 DQC 20 K7 DQA 56 E2 DQB 21 L6 DQA 57 D1 DQC 21 L6 DQA 57 D1 DQB 22 N6 DQA 58 H2 DQC 22 N6 DQA 58 Internal Internal 23 P7 DQA 59 G1 DQC 23 P7 DQA 59 Internal Internal 24 N7 DQA 60 F2 DQC 24 Internal Internal 60 Internal Internal 25 M6 DQA 61 E1 DQC 25 Internal Internal 61 Internal Internal 26 L7 DQA 62 D2 DQPC 26 Internal Internal 62 Internal Internal 27 K6 DQA 63 C2 A 27 Internal Internal 63 C2 A 28 P6 DQPA 64 A2 A 28 Internal Internal 64 A2 A 29 T4 A 65 E4 CE1 29 T6 A 65 E4 CE1 Bit# Ball ID 1 2 30 A3 A 66 B2 CE2 30 A3 A 66 B2 CE2 31 C5 A 67 L3 BWD 31 C5 A 67 Internal Internal 32 B5 A 68 G3 BWC 32 B5 A 68 Internal Internal 33 A5 A 69 G5 BWB 33 A5 A 69 G3 BWB 34 C6 A 70 L5 BWA 34 C6 A 70 L5 BWA 71 Internal Internal 35 A6 A 71 Internal Internal 36 B6 A 35 A6 A 36 B6 A Document #: 38-05540 Rev. *C Page 18 of 31 CY7C1360C CY7C1362C PRELIMINARY Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA Operating Range Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VDD Relative to GND ...... –0.5V to +4.6V Range Ambient Temperature DC Voltage Applied to Outputs in Three-State ....................................–0.5V to VDDQ + 0.5V Commercial 0°C to +70°C Industrial DC Input Voltage...................................–0.5V to VDD + 0.5V Electrical Characteristics Over the Operating Range[15, 16] Parameter Description VDD Power Supply Voltage VDDQ I/O Supply Voltage VOH VOL VIH VIL IX Output HIGH Voltage Output LOW Voltage Input HIGH Input LOW Voltage[15] Voltage[15] VDD Test Conditions Min. Max. Unit 3.135 3.6 V VDDQ = 3.3V 3.135 VDD V VDDQ = 2.5V 2.375 2.625 V VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA 2.4 V VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA 2.0 V VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA 0.4 V VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA 0.4 V VDDQ = 3.3V 2.0 VDD + 0.3V V VDDQ = 2.5V 1.7 VDD + 0.3V V VDDQ = 3.3V –0.3 0.8 V VDDQ = 2.5V –0.3 0.7 V 5 µA 5 µA 30 µA Input Load Current except ZZ and MODE GND ≤ VI ≤ VDDQ –5 Input Current of MODE Input = VSS –30 Input = VDD Input Current of ZZ Input = VSS IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled IDD VDD Operating Supply Current VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC µA µA –5 Input = VDD ISB1 VDDQ 3.3V – 5%/+10% 2.5V – 5% to VDD –40°C to +85°C 5 µA 4.0-ns cycle, 250 MHz 250 mA 5-ns cycle, 200 MHz 220 mA 6-ns cycle, 166 MHz 180 mA 4.0-ns cycle, 250 MHz 130 mA 5-ns cycle, 200 MHz 120 mA 6-ns cycle, 166 MHz –5 Automatic CE Power-down Current—TTL Inputs VDD = Max, Device Deselected, VIN ≥ VIH or VIN ≤ VIL f = fMAX = 1/tCYC 110 mA ISB2 Automatic CE Power-down Current—CMOS Inputs VDD = Max, Device Deselected, All speeds VIN ≤ 0.3V or VIN > VDDQ – 0.3V, f=0 30 mA ISB3 Automatic CE Power-down Current—CMOS Inputs VDD = Max, Device Deselected, or 4.0-ns cycle, 250 MHz VIN ≤ 0.3V or VIN > VDDQ – 0.3V 5-ns cycle, 200 MHz f = fMAX = 1/tCYC 6-ns cycle, 166 MHz 120 mA 110 mA 100 mA Automatic CE Power-down Current—TTL Inputs VDD = Max, Device Deselected, VIN ≥ VIH or VIN ≤ VIL, f = 0 40 mA ISB4 All Speeds Shaded areas contain advance information. Notes: 15. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2). 16. TPower-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD. Document #: 38-05540 Rev. *C Page 19 of 31 CY7C1360C CY7C1362C PRELIMINARY Thermal Resistance[14] Parameter Description Test Conditions ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) 100 TQFP Package 119 BGA Package 165 fBGA Package Unit 29.41 34.1 16.8 °C/W 6.13 14.0 3 °C/W Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. Capacitance[14] Parameter Description 100 TQFP Package Test Conditions CIN Input Capacitance CCLK Clock Input Capacitance CI/O Input/Output Capacitance TA = 25°C, f = 1 MHz, VDD = 3.3V VDDQ = 2.5V 119 BGA Package 165 fBGA Package Unit 5 5 5 pF 5 5 5 pF 5 7 7 pF AC Test Loads and Waveforms 3.3V I/O Test Load R = 317Ω 3.3V OUTPUT Z0 = 50Ω INCLUDING JIG AND SCOPE 2.5V I/O Test Load GND R = 351Ω (b) (c) GND R =1538Ω INCLUDING JIG AND SCOPE (a) 90% 10% 90% 10% 5 pF VT = 1.25V ALL INPUT PULSES VDDQ OUTPUT RL = 50Ω Z0 = 50Ω ≤ 1 ns ≤ 1 ns R = 1667Ω 2.5V OUTPUT 90% 10% 90% 10% 5 pF VT = 1.5V (a) ALL INPUT PULSES VDDQ OUTPUT RL = 50Ω ≤ 1 ns ≤ 1 ns (b) (c) Switching Characteristics Over the Operating Range [17, 18] 250 MHz Parameter tPOWER Description VDD(Typical) to the First Access Min. [19] Max 200 MHz Min. Max 166 MHz Min. Max Unit 1 1 1 ms Clock tCYC Clock Cycle Time 4.0 5.0 6.0 ns tCH Clock HIGH 1.8 2.0 2.4 ns tCL Clock LOW 1.8 2.0 2.4 ns Output Times tCO Data Output Valid after CLK Rise tDOH Data Output Hold after CLK Rise 2.8 1.25 3.0 1.25 3.5 1.25 ns ns Notes: 17. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V. 18. Test conditions shown in (a) of AC Test Loads unless otherwise noted. Document #: 38-05540 Rev. *C Page 20 of 31 CY7C1360C CY7C1362C PRELIMINARY Switching Characteristics Over the Operating Range (continued)[17, 18] 250 MHz Parameter Description Min. tCLZ [20, 21, 22] Clock to Low-Z 1.25 tCHZ Clock to High-Z[20, 21, 22] 1.25 tOEV OE LOW to Output Valid tOELZ tOEHZ Max 200 MHz Min. 1.25 2.8 1.25 2.8 [20, 21, 22] OE LOW to Output Low-Z 0 [20, 21, 22] OE HIGH to Output High-Z Max 166 MHz Min. Unit 3.5 ns 3.5 ns 1.25 3.0 1.25 3.0 0 2.8 Max ns 0 3.0 ns 3.5 ns Set-up Times tAS Address Set-up before CLK Rise 1.4 1.5 1.5 ns tADS ADSC, ADSP Set-up before CLK Rise 1.4 1.5 1.5 ns tADVS ADV Set-up before CLK Rise 1.4 1.5 1.5 ns tWES GW, BWE, BWX Set-up before CLK Rise 1.4 1.5 1.5 ns tDS Data Input Set-up before CLK Rise 1.4 1.5 1.5 ns tCES Chip Enable Set-Up before CLK Rise 1.4 1.5 1.5 ns tAH Address Hold after CLK Rise 0.4 0.5 0.5 ns tADH ADSP, ADSC Hold after CLK Rise 0.4 0.5 0.5 ns tADVH ADV Hold after CLK Rise 0.4 0.5 0.5 ns tWEH GW, BWE, BWX Hold after CLK Rise 0.4 0.5 0.5 ns tDH Data Input Hold after CLK Rise 0.4 0.5 0.5 ns tCEH Chip Enable Hold after CLK Rise 0.4 0.5 0.5 ns Hold Times Shaded areas contain advance information. Notes: 19. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a Read or Write operation can be initiated. 20. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 21. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 22. This parameter is sampled and not 100% tested. Document #: 38-05540 Rev. *C Page 21 of 31 CY7C1360C CY7C1362C PRELIMINARY Switching Waveforms Read Cycle Timing[23] t CYC CLK t CH t ADS t CL t ADH ADSP tADS tADH ADSC tAS tAH A1 ADDRESS A2 tWES A3 Burst continued with new base address tWEH GW, BWE, BWx tCES Deselect cycle tCEH CE tADVS tADVH ADV ADV suspends burst. OE t OEHZ t CLZ Data Out (Q) Q(A1) High-Z tOEV tCO t OELZ tDOH Q(A2) t CHZ Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) t CO Burst wraps around to its initial state Single READ BURST READ DON’T CARE UNDEFINED Note: 23. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. Document #: 38-05540 Rev. *C Page 22 of 31 CY7C1360C CY7C1362C PRELIMINARY Switching Waveforms (continued) Write Cycle Timing[23, 24] t CYC CLK tCH tADS tCL tADH ADSP tADS ADSC extends burst tADH tADS tADH ADSC tAS tAH A1 ADDRESS A2 A3 Byte write signals are ignored for first cycle when ADSP initiates burst tWES tWEH BWE, BWX tWES tWEH GW tCES tCEH CE t t ADVS ADVH ADV ADV suspends burst OE tDS Data In (D) High-Z t OEHZ tDH D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) Data Out (Q) BURST READ Single WRITE BURST WRITE DON’T CARE Extended BURST WRITE UNDEFINED Note: 24. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW. Document #: 38-05540 Rev. *C Page 23 of 31 CY7C1360C CY7C1362C PRELIMINARY Switching Waveforms (continued) Read/Write Cycle Timing[23, 25, 26] tCYC CLK tCL tCH tADS tADH tAS tAH ADSP ADSC ADDRESS A1 A2 A3 A4 A5 A6 D(A5) D(A6) tWES tWEH BWE, BWX tCES tCEH CE ADV OE tDS tCO tDH tOELZ Data In (D) High-Z tCLZ Data Out (Q) High-Z Q(A1) Back-to-Back READs tOEHZ D(A3) Q(A2) Q(A4) Single WRITE Q(A4+1) Q(A4+2) BURST READ DON’T CARE Q(A4+3) Back-to-Back WRITEs UNDEFINED Notes: 25. The data bus (Q) remains in high-Z following a Write cycle, unless a new Read access is initiated by ADSP or ADSC. 26. GW is HIGH. Document #: 38-05540 Rev. *C Page 24 of 31 CY7C1360C CY7C1362C PRELIMINARY Switching Waveforms (continued) ZZ Mode Timing [27, 28] CLK t ZZ ZZ I t ZZREC t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) DESELECT or READ Only Outputs (Q) High-Z DON’T CARE Ordering Information Speed (MHz) 250 Ordering Code Package Name Part and Package Type Operating Range CY7C1360C-250AXC CY7C1362C-250AXC A101 Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 3 Chip Enables Commercial CY7C1360C-250AXI CY7C1362C-250AXI A101 Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 3 Chip Enables Industrial CY7C1360C-250AJXC A101 Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 2 Chip Enables Commercial A101 Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 2 Chip Enables Industrial BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables and JTAG Commercial BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables and JTAG Industrial CY7C1362C-250AJXC CY7C1360C-250AJXI CY7C1362C-250AJXI CY7C1360C-250BGC CY7C1362C-250BGC CY7C1360C-250BGI CY7C1362C-250BGI CY7C1360C-250BZC CY7C1362C-250BZC CY7C1360C-250BZI CY7C1362C-250BZI CY7C1360C-250BGXC BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) 3 Chip Enables and JTAG Commercial BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) 3 Chip Enables and JTAG Industrial BG119 Lead-Free 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables and Commercial JTAG BG119 Lead-Free 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables and JTAG CY7C1362C-250BGXC CY7C1360C-250BGXI CY7C1362C-250BGXI CY7C1360C-250BZXC CY7C1362C-250BZXC CY7C1360C-250BZXI CY7C1362C-250BZXI Industrial BB165D Lead-Free 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) Commercial 3 Chip Enables and JTAG BB165D Lead-Free 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) 3 Chip Enables and JTAG Industrial Notes: 27. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 28. DQs are in High-Z when exiting ZZ sleep mode. Document #: 38-05540 Rev. *C Page 25 of 31 PRELIMINARY CY7C1360C CY7C1362C Ordering Information (continued) Speed (MHz) 200 Ordering Code Package Name Part and Package Type Operating Range CY7C1360C-200AXC CY7C1362C-200AXC A101 Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 3 Chip Enables Commercial CY7C1360C-200AXI CY7C1362C-200AXI A101 Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 3 Chip Enables Industrial CY7C1360C-200AJXC A101 Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 2 Chip Enables Commercial A101 Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 2 Chip Enables Industrial BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables and JTAG Commercial BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables and JTAG Industrial CY7C1362C-200AJXC CY7C1360C-200AJXI CY7C1362C-200AJXI CY7C1360C-200BGC CY7C1362C-200BGC CY7C1360C-200BGI CY7C1362C-200BGI CY7C1360C-200BZC CY7C1362C-200BZC CY7C1360C-200BZI CY7C1362C-200BZI CY7C1360C-200BGXC BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) 3 Chip Enables and JTAG Commercial BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) 3 Chip Enables and JTAG Industrial BG119 Lead-Free 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables and Commercial JTAG BG119 Lead-Free 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables and JTAG CY7C1362C-200BGXC CY7C1360C-200BGXI CY7C1362C-200BGXI CY7C1360C-200BZXC CY7C1362C-200BZXC CY7C1360C-200BZXI CY7C1362C-200BZXI Document #: 38-05540 Rev. *C Industrial BB165D Lead-Free 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) Commercial 3 Chip Enables and JTAG BB165D Lead-Free 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) 3 Chip Enables and JTAG Industrial Page 26 of 31 PRELIMINARY CY7C1360C CY7C1362C Ordering Information (continued) Speed (MHz) 166 Ordering Code CY7C1360C-166AXC Package Name Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 3 Chip Enables Commercial A101 Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 3 Chip Enables Industrial A101 Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 2 Chip Enables Commercial A101 Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 2 Chip Enables Industrial BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables and JTAG Commercial BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables and JTAG Industrial CY7C1362C-166AXI CY7C1360C-166AJXC CY7C1362C-166AJXC CY7C1360C-166AJXI CY7C1362C-166AJXI CY7C1360C-166BGC Operating Range A101 CY7C1362C-166AXC CY7C1360C-166AXI Part and Package Type CY7C1362C-166BGC CY7C1360C-166BGI ICY7C1362C-166BGI CY7C1360C-166BZC CY7C1362C-166BZC CY7C1360C-166BZI ICY7C1362C-166BZI CY7C1360C-166BGXC BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) 3 Chip Enables and JTAG Commercial BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) 3 Chip Enables and JTAG Industrial BG119 Lead-Free 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables and JTAG Commercial BG119 Lead-Free 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables and JTAG Industrial CY7C1362C-166BGXC CY7C1360C-166BGXI ICY7C1362C-166BGXI CY7C1360C-166BZXC CY7C1362C-166BZXC CY7C1360C-166BZXI CY7C1362C-166BZXI BB165D Lead-Free 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) Commercial 3 Chip Enables and JTAG BB165D Lead-Free 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) 3 Chip Enables and JTAG Industrial Shaded areas contain advance information. Please contact your local sales representative for availability of these parts. Document #: 38-05540 Rev. *C Page 27 of 31 CY7C1360C CY7C1362C PRELIMINARY Package Diagrams 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 DIMENSIONS ARE IN MILLIMETERS. 16.00±0.20 1.40±0.05 14.00±0.10 81 100 80 1 20.00±0.10 22.00±0.20 0.30±0.08 0.65 TYP. 30 12°±1° (8X) SEE DETAIL A 51 31 50 0.20 MAX. 1.60 MAX. 0° MIN. STAND-OFF 0.05 MIN. 0.15 MAX. 0.25 0.10 R 0.08 MIN. 0.20 MAX. SEATING PLANE GAUGE PLANE 0°-7° R 0.08 MIN. 0.20 MAX. 0.60±0.15 0.20 MIN. 1.00 REF. DETAIL Document #: 38-05540 Rev. *C A 51-85050-*A Page 28 of 31 PRELIMINARY CY7C1360C CY7C1362C Package Diagrams (continued) 119-Lead PBGA (14 x 22 x 2.4 mm) BG119 51-85115-*B Document #: 38-05540 Rev. *C Page 29 of 31 CY7C1360C CY7C1362C PRELIMINARY Package Diagrams (continued) 165 FBGA 13 x 15 x 1.40 MM BB165D 51-85180-** i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05540 Rev. *C Page 30 of 31 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C1360C CY7C1362C PRELIMINARY Document History Page Document Title: CY7C1360C/CY7C1362C 9-Mbit (256K x 36/512K x 18) Pipelined SRAM Document Number: 38-05540 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 241690 See ECN RKF New data sheet *A 278130 See ECN RKF Changed Boundary Scan order to match the B rev of these devices. Changed TQFP pkg to Lead-free TQFP in Ordering Information section Added comment of Lead-free BG and BZ packages availability *B 248929 See ECN VBL Changed ISB1 and ISB3 from DC Characteristics table as follows: ISB1: 225 MHz -> 130 mA, 200 MHz -> 120 mA, 167 MHz -> 110 mA ISB3: 225 MHz -> 120 mA, 200 MHz -> 110 mA, 167 MHz -> 100 mA Changed IDDZZ to 50mA. Added BG and BZ pkg lead-free part numbers to ordering info section. *C 323636 See ECN PCI Changed frequency of 225 MHz into 250 MHz Added tCYC of 4.0 ns for 250 MHz Changed ΘJA and ΘJC for TQFP Package from 25 and 9 °C/W to 29.41 and 6.13 °C/W respectively Changed ΘJA and ΘJC for BGA Package from 25 and 6 °C/W to 34.1 and 14.0 °C/W respectively Changed ΘJA and ΘJC for FBGA Package from 27 and 6 °C/W to 16.8 and 3.0 °C/W respectively Modified address expansion as per JEDEC Standard Removed comment of Lead-free BG and BZ packages availability Document #: 38-05540 Rev. *C Page 31 of 31