AVAGO HCPL-7723 50 mbd 2 ns pwd high speed cmos optocoupler Datasheet

HCPL-7723/0723
50 MBd 2 ns PWD High Speed CMOS Optocoupler
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
Available in either 8-pin DIP or SO‑8 package style respectively, the HCPL-7723 or HCPL-0723 optocoupler utilize
the latest CMOS IC technology to achieve out­standing
speed performance of minimum 50 MBd data rate and
2 ns maximum pulse width distortion.
•
•
•
•
•
•
•
•
Basic building blocks of HCPL-7723/0723 are a CMOS
LED driver IC, a high speed LED and a CMOS detector
IC. A CMOS logic input signal controls the LED driver
IC, which supplies current to the LED. The detector
IC incorporates an integrated photodiode, a high speed
transimpedance amplifier, and a voltage comparator with
an output driver.
Functional Diagram
**VDD1
1
8
VDD2**
VI
2
7
NC*
6
VO
5
GND2
NC*
IO
3
LED1
GND1
4
SHIELD
* PIN 3 IS THE ANODE OF THE INTERNAL LED AND MUST BE LEFT
UNCONNECTED FOR GUARANTEED DATASHEET PERFORMANCE.
PIN 7 IS NOT CONNECTED INTERNALLY.
** A 0.1 µF BYPASS CAPACITOR MUST BE CONNECTED BETWEEN
PINS 1 AND 4, AND 5 AND 8.
+5 V CMOS compatibility
High speed: 50 MBd min.
2 ns max. pulse width distortion
22 ns max. prop. delay
16 ns max. prop. delay skew
10 kV/µs min. common mode rejection
–40 to 85°C temperature range
Safety and regulatory approvals:
UL recognized
– 5000 Vrms for 1 min. per UL1577 for HCPL-7723 for
option 020
– 3750 Vrms for 1 min. per UL1577 for HCPL-0723
CSA component acceptance notice #5
IEC/EN/DIN EN 60747-5-5
– Viorm = 630 Vpeak for HCPL-7723 option 060
– Viorm = 567 Vpeak for HCPL-0723 option 060
Applications
• Digital fieldbus isolation: CC-Link, DeviceNet, Profibus,
SDS, Isolated A/D or D/A conversion
• Multiplexed data transmission
• High speed digital input/output
• Computer peripheral interface
• Microprocessor system interface
TRUTH TABLE
(POSITIVE LOGIC)
VI, INPUT
LED1
VO, OUTPUT
H
L
OFF
ON
H
L
CAUTION: It is advised that normal static precautions be taken in handling and assembly of
this component to prevent damage and/or degradation, which may be induced by ESD.
Package Outline Drawings
HCPL-7723 8-Pin DIP Package
9.65 ± 0.25
(0.380 ± 0.010)
TYPE NUMBER
8
7
6
7.62 ± 0.25
(0.300 ± 0.010)
5
OPTION 060 CODE*
DATE CODE
A XXXXV
6.35 ± 0.25
(0.250 ± 0.010)
YYWW
1
1.19 (0.047) MAX.
2
3
4
1.78 (0.070) MAX.
5° TYP.
3.56 ± 0.13
(0.140 ± 0.005)
4.70 (0.185) MAX.
+ 0.076
- 0.051
+ 0.003)
(0.010
- 0.002)
0.254
0.51 (0.020) MIN.
2.92 (0.115) MIN.
1.080 ± 0.320
(0.043 ± 0.013)
2
0.65 (0.025) MAX.
2.54 ± 0.25
(0.100 ± 0.010)
DIMENSIONS IN MILLIMETERS AND (INCHES).
*OPTION 300 AND 500 NOT MARKED.
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
HCPL-7723 Package with Gull Wing Surface Mount Option 300
LAND PATTERN RECOMMENDATION
9.65 ± 0.25
(0.380 ± 0.010)
6
7
8
1.016 (0.040)
5
6.350 ± 0.25
(0.250 ± 0.010)
2
1
10.9 (0.430)
4
3
2.0 (0.080)
1.27 (0.050)
9.65 ± 0.25
(0.380 ± 0.010)
7.62 ± 0.25
(0.300 ± 0.010)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
+ 0.076
- 0.051
+ 0.003)
(0.010
- 0.002)
0.254
3.56 ± 0.13
(0.140 ± 0.005)
1.080 ± 0.320
(0.043 ± 0.013)
0.635 ± 0.130
2.54
(0.025 ± 0.005)
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
0.635 ± 0.25
(0.025 ± 0.010)
12° NOM.
HCPL-0723 Small Outline SO-8 Package
LAND PATTERN RECOMMENDATION
8
7
5
5.994 ± 0.203
(0.236 ± 0.008)
TYPE NUMBER
(LAST 3 DIGITS)
DATE CODE
XXXV
YWW
3.937 ± 0.127
(0.155 ± 0.005)
PIN ONE
6
1
2
3
0.406 ± 0.076
(0.016 ± 0.003)
7.49 (0.295)
4
1.9 (0.075)
1.270 BSC
(0.050)
0.64 (0.025)
* 5.080 ± 0.127
(0.200 ± 0.005)
3.175 ± 0.127
(0.125 ± 0.005)
7°
1.524
(0.060)
* TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)
5.207 ± 0.254 (0.205 ± 0.010)
45° X
0 ~ 7°
0.228 ± 0.025
(0.009 ± 0.001)
0.305 MIN.
(0.012)
DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.
OPTION NUMBER 500 NOT MARKED.
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
3
0.432
(0.017)
0.203 ± 0.102
(0.008 ± 0.004)
Device Selection Guide
8-Pin DIP (300 mil)
Small Outline SO-8
HCPL-7723
HCPL-0723
Ordering Information
HCPL-0723 and HCPL-7723 are UL Recognized with 3750 Vrms for 1 minute per UL1577.
Option
Part
RoHS
non RoHS
Surface
Gull
Tape
UL 5000 Vrms/
IEC/EN/DIN
Number
Compliant Compliant Package
Mount
Wing
& Reel 1 Minute rating EN 60747-5-5
-000E
no option
300 mil DIP-8
-300E
-300
X
X
-500E
-500
X
X
X
-020E
-020
X
HCPL-7723 -320E
-320
X
X
X
-520E
-520
X
X
X
X
-060E
-060
X
-360E
-360
X
X
X
-560E
-560
X
X
X
X
-000E
no option
SO-8
X
HCPL-0723 -500E
-500
X
X
-060E
-060
X
X
-560E
-560
X
X
X
Quantity
50 per tube
50 per tube
1000 per reel
50 per tube
50 per tube
1000 per reel
50 per tube
50 per tube
1000 per reel
100 per tube
1500 per reel
100 per tube
1500 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
HCPL-7723-560E to order product of Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/DIN
EN 60747-5-5 Safety Approval and RoHS compliant.
Example 2:
HCPL-0723 to order product of Small Outline SO-8 package in Tube packaging and non RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since July 15, 2001 and
RoHS compliant will use ‘–XXXE.’
4
Regulatory Information
The HCPL-7723/0723 have been approved by the following organizations:
UL
Recognized under UL1577, component recognition program, File E55361.
CSA
Approved under CSA Component Acceptance Notice #5, File CA88324.
IEC/EN/DIN EN 60747-5-5
Approved with Maximum Working Insulation Voltage:
Viorm = 567 Vpeak for HCPL-0723,
Viorm = 630 Vpeak for HCPL-7723
Solder Reflow Profile
Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.
Insulation and Safety Related Specifications
Parameter
Symbol
Value
7723
0723
Units
Conditions
Minimum External Air Gap
L(I01)
7.1
4.9
mm
(Clearance)
Measured from input terminals to output
terminals, shortest distance through air.
Minimum External Tracking
L(I02)
7.4
4.8
mm
(Creepage)
Measured from input terminals to output
terminals, shortest distance path along body.
Minimum Internal Plastic Gap
0.08
0.08
mm
Insulation thickness between emitter and
(Internal Clearance)
detector; also known as distance through
insulation.
Tracking Resistance
(Comparative Tracking Index)
CTI
Isolation Group
5
≥ 175
≥ 175
Volts
IIIa
IIIa
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
All Avago data sheets report the creepage and clearance
inherent to the optocoupler component itself. These
dimensions are needed as a starting point for the
equipment designer when determining the circuit insulation requirements. However, once mounted on a printed
circuit board, minimum creepage and clearance requirements must be met as specified for individual equipment
standards. For creepage, the shortest distance path along
the surface of a printed circuit board between the solder
fillets of the input and output leads must be considered.
There are recommended techniques such as grooves
and ribs, which may be used on a printed circuit board
to achieve desired creepage and clearances. Creepage
and clearance distances will also change depending
on factors such as pollution degree and insulation
level.
IEC/EN/DIN EN 60747-5-5 Insulation Characteristics (Option 060)
Characteristic
Description
Symbol
HCPL-7723 HCPL-0723
Unit
Installation classification per DIN VDE 0110, Table 1
for rated mains voltage ≤ 150 Vrms
I – IV
I – IV
for rated mains voltage ≤ 300 Vrms
I – III
I – III
for rated mains voltage ≤ 600 Vrms
I – IV
I – III
Climatic Classification
55/85/21
55/85/21
Pollution Degree (DIN VDE 0110/39)
2
2
VIORM
630
567
Vpeak
VPR
1181
1063
Vpeak
VPR
1008
907
Vpeak
VIOTM
8000
6000
Vpeak
Case Temperature
TS
175
150
°C
Input Current
IS, INPUT
230
150
mA
Output Power
PS, OUTPUT
600
600
mW
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b*
VIORM x 1.875 = VPR, 100% Production Test with tm=1 sec,
Partial discharge < 5 pC
Input to Output Test Voltage, Method a*
VIORM x 1.6 = VPR, Type and Sample Test, tm=10 sec, Partial discharge < 5 pC
Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec)
Safety-limiting values – maximum values allowed in the event of a failure
Insulation Resistance at TS, VIO = 500 V
RS
≥
109
≥
109
Ω
*Refer to the optocoupler section of the Isolation and Control Component Designer’s Catalog, under Product Safety Regulations section IEC/EN/
DIN EN 60747-5-5, for a detailed description of Method a and Method b partial discharge test profiles.
6
Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
Storage Temperature
TS
–55
125
°C
Ambient Operating Temperature[1]
TA
–40
85
°C
Supply Voltages
VDD1, VDD2
0
6.0
Volts
Input Voltage
VI
–0.5
VDD1 +0.5
Volts
Output Voltage
VO
–0.5
VDD2 +0.5
Volts
Average Output Current
IO 10
Lead Solder Temperature
260°C for 10 sec., 1.6 mm below seating plane
Solder Reflow Temperature Profile
See Solder Reflow Temperature Profile Section
mA
Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Units
Ambient Operating Temperature
TA
–40
85
°C
Supply Voltages
VDD1, VDD2
4.5
5.5
V
Logic High Input Voltage
VIH
2.0
VDD1
V
Logic Low Input Voltage
VIL
0.0
0.8
V
Input Signal Rise and Fall Times
tr, tf
1.0
ms
Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
All typical specifications are at TA = +25°C, VDD1 = VDD2 = +5 V.
Parameter
Symbol
Logic Low Input Supply Current[2]
Min.
Typ.
Max.
Units
Test Conditions
IDD1L
8.4
10
mA
VI = 0 V; Figure 1
Logic High Input Supply Current[2]
IDD1H
0.6
3
mA
VI = VDD1 ; Figure 2
Output Supply Current
IDD2L
2.1
5
mA
Figure 3
IDD2H
2.0
5
mA
Figure 4
10
µA
Input Current
II
–10
Logic High Output Voltage
VOH
4.4
5.0 V
IO = –20 µA, VI = VIH
4.0
4.8 V
IO = –4 mA, VI = VIH
0
0.1
V
IO = 20 µA, VI = VIL
0.5
1.0
V
IO = 4 mA, VI = VIL
Logic Low Output Voltage
VOL
7
Switching Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
All typical specifications are at TA = +25°C, VDD1 = VDD2 = +5 V.
Parameter
Symbol
Propagation Delay Time to Logic
Low Output[3]
Typ.
Max.
Units
Test Conditions
tPHL
16
22
ns
CL = 15 pF CMOS Signal Levels; Figure 5
Propagation Delay Time to Logic
High Output[3]
tPLH
16
22
ns
CL = 15 pF CMOS Signal Levels; Figure 5
Pulse Width
PW
Maximum Data Rate
Min.
20ns
CL = 15 pF CMOS Signal Levels
50
MBd
CL = 15 pF CMOS Signal Levels
ns
CL = 15 pF CMOS Signal Levels; Figure 6
ns
CL = 15 pF CMOS Signal Levels
Pulse Width Distortion[4] |tPHL - tPLH|
|PWD|
Propagation Delay Skew[5]
tPSK
Output Rise Time (10% – 90%)
tR
8 ns
CL = 15 pF CMOS Signal Levels
Output Fall Time (90% - 10%)
tF
6 ns
CL = 15 pF CMOS Signal Levels
1
2
16
Common Mode Transient Immunity
|CMH|
10
15 kV/µs
VCM = 1000 V, TA = 25°C,
at Logic High Output[6] VI = VDD1, VO > 0.8 VDD2
Common Mode Transient Immunity
|CML|
10
15 kV/µs
VCM = 1000 V, TA = 25°C,
at Logic Low Output[6] VI = 0 V, VO < 0.8 V
8
Package Characteristics
All Typical Specifications are at TA = 25°C.
Parameter
Input-Output Momentary
Withstand Voltage[7,8,9]
Symbol
–7723
VISO
Option 020
–0723
Min.
Typ.
Max.
Units
Test Conditions
3750
V rms
RH ≤ 50%, t = 1 min,
5000
TA = 25°C
3750
Input-Output Resistance[7]R I-O
10 12
Ω
VI-O = 500 V dc
Input-Output Capacitance
0.6 pF
f = 1 MHz
C I-O
Input Capacitance[10]C I
3.0 pF
Input IC Junction-to-Case
Thermal Resistance
–7723
θjci
–0723 145
°C/W
Thermocouple located at
160center underside of package
Output IC Junction-to-Case
Thermal Resistance
–7723
θjco
–0723
145 °C/W
135
Package Power Dissipation
PPD
150
mW
Notes:
1. Absolute Maximum ambient operating temperature means the device will not be damaged if operated under these conditions. It does not
guarantee functionality.
2. The LED is ON when VI is low and OFF when VI is high.
3. tPHL propagation delay is measured from the 50% level on the falling edge of the VI signal to the 50% level of the falling edge of the VO signal. tPLH propagation delay is measured from the 50% level on the rising edge of the VI signal to the 50% level of the rising edge of the VO
signal.
4. PWD is defined as |tPHL - tPLH|. %PWD (percent pulse width distortion) is equal to the PWD divided by pulse width.
5. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature
within the recommended operating conditions.
6. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common mode voltage slew rates apply to both rising
and falling common mode voltage edges.
7. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together.
8. In accordance with UL1577, each HCPL-0723 is proof tested by applying an insulation test voltage ≥ 4500 Vrms for 1 second (leakage detection current limit, II-O ≤ 5 µA). Each HCPL-7723 is proof tested by applying an insulation test voltage ≥ 4500 Vrms for 1 second (leakage detection current limit. II-O ≤ 5 µA.)
9. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to your equipment level safety specification or Avago Application Note 1074 entitled
“Optocoupler Input-Output Endurance Voltage.”
10. CI is the capacitance measured at pin 2 (VI).
9
0.6
IDD1H - LOGIC HIGH INPUT SUPPLY
CURRENT (mA)
IDD1L - LOGIC LOW INPUT SUPPLY
CURRENT (mA)
9.0
8.5
8.0
7.5
7.0
6.5
-40
-20
0
20
40
TA (°C)
60
80
IDD2H - LOGIC HIGH OUTPUT SUPPLY
CURRENT (mA)
IDD2L - LOGIC LOW OUTPUT SUPPLY
CURRENT (mA)
2.5
2.0
1.5
-40
-20
0
100
0
20
40
TA (°C)
60
80
100
PWD (ns)
Tphl, Tplh (ns)
18
16
14
T plh
T phl
12
-20
0
20
40
TA (°C)
Figure 5. Typical propagation delay vs. temperature
60
80
100
2
1.5
20
40
60
80
TA (°C)
Figure 4. Typical Logic High Output Supply Current vs. temperature
20
10
-20
2.5
1
22
-40
-40
3
20
40
60
80
TA (°C)
Figure 3. Typical Logic Low Output Supply Current vs. temperature
10
0.45
Figure 2. Typical Logic High Input Supply Current vs. temperature
3.0
1.0
0.5
0.4
100
Figure 1: Typical Logic Low Input Supply Current vs. temperature
0.55
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-40
-40
-20
-20
0
0
20
40
TA (°C)
60
Figure 6. Typical pulse width distortion vs. temperature
80
100
100
Application Information
Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew
Bypassing and PC Board Layout
The HCPL-7723/0723 optocouplers are extremely easy to
use. No external interface circuitry is required because
the HCPL-7723/0723 use high-speed CMOS IC technology allowing CMOS logic to be connected directly to the
inputs and outputs.
As shown in Figure 7, the only external components
required for proper operation are two bypass capacitors.
Capacitor values should be between 0.01 µF and 0.1 µF.
For each capacitor, the total lead length between both
ends of the capacitor and the power-supply pins should
not exceed 20 mm. Figure 8 illustrates the recommended
printed circuit board layout for the HCPL-7723/0723.
VDD1
VDD2
8
1
Propagation Delay is a figure of merit which describes
how quickly a logic signal propagates through a system
as illustrated in Figure 9. The propagation delay from low
to high (tPLH) is the amount of time required for an input
signal to propagate to the output, causing the output to
change from low to high. Similarly, the propagation delay
from high to low (tPHL) is the amount of time required for
the input signal to propagate to the output, causing the
output to change from high to low.
C1
C2
VI
720
YWW
2
NC 3
GND1
7 NC
6
VO
5
4
GND2
C1, C2 = 0.01 µF TO 0.1 µF
Figure 7. Functional diagram.
VDD1
VDD2
720
YWW
VI
C1
C2
VO
GND1
GND2
C1, C2 = 0.01 µF TO 0.1 µF
Figure 8. Recommended printed circuit board layout.
INPUT
VI
5 V CMOS
50%
tPLH
OUTPUT
VO
10%
90%
90%
Figure 9. Timing diagram to illustrate propagation delay, tplh and tphl.
11
0V
tPHL
10%
VOH
2.5 V CMOS
VOL
Pulse-width distortion (PWD) is the difference between
tPHL and tPLH and often determines the maximum data
rate capability of a transmission system. PWD can be
expressed in percent by dividing the PWD (in ns) by the
minimum pulse width (in ns) being transmitted. Typically,
PWD on the order of 20-30% of the minimum pulse width
is tolerable.
Propagation delay skew, tPSK, is an important parameter
to consider in parallel data applica­tions where synchronization of signals on parallel data lines is a concern. If
the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause
the data to arrive at the outputs of the optocouplers at
different times. If this difference in propagation delay
is large enough it will determine the maximum rate at
which parallel data can be sent through the optocouplers.
Propagation delay skew is defined as the difference
between the minimum and maximum propagation
delays, either tPLH or tPHL, for any given group of optocouplers which are operating under the same conditions
(i.e., the same drive current, supply voltage, output load,
and operating temperature). As illustrated in Figure 10,
if the inputs of a group of optocouplers are switched
either ON or OFF at the same time, tPSK is the difference
between the shortest propagation delay, either tPLH or
tPHL, and the longest propagation delay, either tPLH or
tPHL.
VI
As mentioned earlier, tPSK can determine the maximum
parallel data transmission rate. Figure 11 is the timing
diagram of a typical parallel data application with both
the clock and data lines being sent through the optocouplers. The figure shows data and clock signals at the
inputs and outputs of the optocouplers. In this case the
data is assumed to be clocked off of the rising edge of
the clock.
Propagation delay skew represents the uncertainty of
where an edge might be after being sent through an optocoupler. Figure 11 shows that there will be uncertainty
in both the data and clock lines. It is important that these
two areas of uncertainty not overlap, otherwise the clock
signal might arrive before all of the data outputs have
settled, or some of the data outputs may start to change
before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can
be sent through optocouplers in a parallel application is
twice tPSK. A cautious design should use a slightly longer
pulse width to ensure that any additional uncertainty in
the rest of the circuit does not cause a problem.
The HCPL-7723/0723 optocouplers offer the advantage of
guaranteed specifications for propagation delays, pulsewidth distortion, and propagation delay skew over the
recommended temperature and power supply ranges.
DATA
50%
INPUTS
VO
2.5 V,
CMOS
CLOCK
tPSK
VI
50%
DATA
OUTPUTS
VO
2.5 V,
CMOS
tPSK
CLOCK
tPSK
Figure 10. Timing diagram to illustrate propagation delay skew, tpsk.
For product information and a complete list of distributors, please go to our website:
Figure 11. Parallel data transmission example.
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries.
Data subject to change. Copyright © 2005-2013 Avago Technologies Limited. All rights reserved. Obsoletes AV01-0566EN
AV02-0643EN - February 26, 2013