HI-574A, HI-674A IGNS D ES W E T OR N D UC E D F T E PR O LI E S D N s AMIData TI TU MME duct Sheet ECO E SUBS 267XX F #pro R T / L L s S B r I NO I S te POS 3XX AND /conver 6 m 2 o L c il. IS nters ww.i wComplete, 12-Bit A/D Converters with August 7, 2008 FN3096.6 Features Microprocessor Interface • Complete 12-Bit A/D Converter with Reference and Clock The HI-X74(A) is a complete 12-bit, Analog-to-Digital Converter, including a +10V reference clock, three-state outputs and a digital interface for microprocessor control. Successive approximation conversion is performed by two monolithic dice housed in a 28 lead package. The bipolar analog die features the Intersil Dielectric Isolation process, which provides enhanced AC performance and freedom from latch-up. Custom design of each IC (bipolar analog and CMOS digital) has yielded improved performance over existing versions of this converter. The voltage comparator features high PSRR plus a high speed current-mode latch, and provides precise decisions down to 0.1 LSB of input overdrive. More than 2X reduction in noise has been achieved by using current instead of voltage for transmission of all signals between the analog and digital ICs. Also, the clock oscillator is current controlled for excellent stability over temperature. The HI-X74(A) offers standard unipolar and bipolar input ranges, laser trimmed for specified linearity, gain and offset accuracy. The low noise buried zener reference circuit is trimmed for minimum temperature coefficient. Power requirements are +5V and ±12V to ±15V, with typical dissipation of 385mW (HI-574A, HI-674A) at 12V. • Full 8-Bit, 12-Bit or 16-Bit Microprocessor Bus Interface • Bus Access Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 150ns • No Missing Codes Over Temperature • Minimal Setup Time for Control Signals • Fast Conversion Times - HI-574A (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25µs - HI-674A (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15µs • Low Noise, via Current-Mode Signal Transmission Between Chips • Byte Enable/Short Cycle (AO Input) - Guaranteed Break-Before-Make Action, Eliminating Bus Contention During Read Operation. Latched by Start Convert Input (To Set the Conversion Length) • Supply Voltage . . . . . . . . . . . . . . . . . . . . . . ±12V to ±15V • Pb-Free Available (RoHS Compliant) Applications • Military and Industrial Data Acquisition Systems • Electronic Test and Scientific Instrumentation • Process Control Systems Pinout HI-574A, HI-674A (28 LD PDIP, SBDIP) TOP VIEW 1 +5V SUPPLY, VLOGIC 1 28 STATUS, STS DATA MODE SEL, 12/8 2 27 DB11 CHIP SEL, CS 3 26 DB10 BYTE ADDR/SHORT CYCLE, AO 4 25 DB9 READ/CONVERT, R/C 5 24 DB8 CHIP ENABLE, CE 6 23 DB7 +12V/+15V SUPPLY, VCC 7 22 DB6 +10V REF, REF OUT 8 21 DB5 ANALOG COMMON, AC MSB DIGITAL DATA OUTPUTS 9 20 DB4 REFERENCE INPUT 10 19 DB3 -12V/-15V SUPPLY, VEE 11 18 DB2 BIPOLAR OFFSET 12 BIP OFF 17 DB1 10V INPUT 13 16 DB0 20V INPUT 14 15 DIG COMMON, DC LSB CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2001, 2008, 2012. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. HI-574A, HI-674A Ordering Information INL TEMPERATURE RANGE (°C) ±1.0 LSB 0 to +75 28 Ld PDIP E28.6 HI3-574AJN-5Z (Notes 1, 3) HI3-574AJN-5Z ±1.0 LSB 0 to +75 28 Ld PDIP (Pb-Free) E28.6 HI3-574AKN-5 ±0.5 LSB 0 to +75 28 Ld PDIP E28.6 HI3-574AKN-5Z (Notes 1, 3) HI3-574AKN-5Z ±0.5 LSB 0 to +75 28 Ld PDIP (Pb-Free) E28.6 HI1-574AJD-5 (Note 2) HI1-574AJD -5 ±1.0 LSB 0 to +75 28 Ld SBDIP (Pb-Free) D28.6 HI1-574AKD-5 (Note 2) HI1-574AKD -5 ±0.5 LSB 0 to +75 28 Ld SBDIP (Pb-Free) D28.6 HI1-574ASD-2 (Note 2) HI1-574ASD -2 ±1.0 LSB -55 to +125 28 Ld SBDIP (Pb-Free) D28.6 HI1-574ATD-2 (Note 2) HI1- 574ATD-2 ±0.5 LSB -55 to +125 28 Ld SBDIP (Pb-Free) D28.6 HI3-674AJN-5 HI3-674AJN-5 ±1.0 LSB 0 to +75 28 Ld PDIP E28.6 HI3-674AJN-5Z (Notes 1, 3) HI3-674AJN-5Z ±1.0 LSB 0 to +75 28 Ld PDIP (Pb-Free) E28.6 HI3-674AKN-5 ±0.5 LSB 0 to +75 28 Ld PDIP E28.6 HI3-674AKN-5Z (Notes 1, 3) HI3-674AKN-5Z ±0.5 LSB 0 to +75 28 Ld PDIP (Pb-Free) E28.6 HI1-674AKD-5 (Note 2) HI1-674AKD -5 ±0.5 LSB 0 to +75 28 Ld SBDIP (Pb-Free) D28.6 HI1-674ATD/883 (Note 2) HI1-674ATD /883 ±0.5 LSB -55 to +125 28 Ld SBDIP (Pb-Free) D28.6 PART NUMBER HI3-574AJN-5 PART MARKING HI3-574AJN-5 HI3-574AKN-5 HI3-674AKN-5 PACKAGE PKG. DWG. # NOTES: 1. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. 2. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020. 2 FN3096.6 August 7, 2008 HI-574A, HI-674A Functional Block Diagram BIT OUTPUTS MSB 12/8 CS AO LSB NIBBLE A (NOTE) CONTROL LOGIC NIBBLE B (NOTE) NIBBLE C (NOTE) THREE-STATE BUFFERS AND CONTROL R/C CE VLOGIC POWER-UP RESET DIGITAL COMMON 12 BITS CLK STS SAR OSCILLATOR STROBE DIGITAL CHIP ANALOG CHIP 12 BITS VCC VEE - DAC COMP + VREF IN 10k VREF OUT 5k + +10V REF - 5k 2.5k 10k 5k ANALOG COMMON BIP OFF 20V 10V INPUT INPUT NOTE: “Nibble” is a 4-bit digital word. 3 FN3096.6 August 7, 2008 HI-574A, HI-674A Absolute Maximum Ratings Thermal Information Supply Voltage VCC to Digital Common . . . . . . . . . . . . . . . . . . . . . . 0V to +16.5V VEE to Digital Common . . . . . . . . . . . . . . . . . . . . . . . 0V to -16.5V VLOGIC to Digital Common . . . . . . . . . . . . . . . . . . . . . . 0V to +7V Analog Common to Digital Common . . . . . . . . . . . . . . . . . . . .±1V Control Inputs (CE, CS, AO, 12/8, R/C) to Digital Common . . -0.5V to VLOGIC +0.5V Analog Inputs (REFIN, BIPOFF, 10VIN) to Analog Common . . . . . . . . . . ±16.5V 20VIN to Analog Common . . . . . . . . . . . . . . . . . . . . . . . . . . ±24V REFOUT . . . . .Indefinite Short To Common, Momentary Short To VCC Thermal Resistance (Typical, Note 4) θJA (°C/W) θJC (°C/W) SBDIP Package . . . . . . . . . . . . . . . . . . 55 18 PDIP Package* . . . . . . . . . . . . . . . . . . . 60 N/A Maximum Junction Temperature PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C SBDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C Maximum Storage Temperature Range PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C SBDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Operating Conditions Temperature Range HI3-574Axx-5, HI1-674Axx-5 . . . . . . . . . . . . . . . . . . 0°C to +75°C HI1-574AxD-2, HI1-674AxD-2 . . . . . . . . . . . . . . .-55°C to +125°C Die Characteristics Transistor Count HI-574A, HI-674A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1117 CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 4. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. DC and Transfer Accuracy Specifications Typical at +25°C with VCC = +15V or +12V, VLOGIC = +5V, VEE = -15V or -12V; Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. TEMPERATURE RANGE -5 (0°C to +75°C) J SUFFIX K SUFFIX UNITS 12 12 Bits ±1 ±1/2 LSB ±1 ±1/ LSB +25°C 12 12 Bits TMIN to TMAX 11 12 Bits ±2 ±1.5 LSB ±4 ±4 LSB ±0.15 ±0.1 % of FS +25°C (Max), With Fixed 50Ω Resistor From REF OUT To REF IN (Adjustable to Zero) ±0.25 ±0.25 % of FS TMIN to TMAX (No Adjustment At +25°C) ±0.475 ±0.375 % of FS TMIN to TMAX (With Adjustment To Zero +25°C) ±0.22 ±0.12 % of FS PARAMETER DYNAMIC CHARACTERISTICS Resolution (Max) Linearity Error +25°C (Max) 0°C to +75°C (Max) 2 Max Resolution For Which No Missing Codes Is Guaranteed Unipolar Offset (Max) Adjustable to Zero Bipolar Offset (Max) VIN = 0V (Adjustable to Zero) VIN = -10V Full Scale Calibration Error 4 FN3096.6 August 7, 2008 HI-574A, HI-674A DC and Transfer Accuracy Specifications Typical at +25°C with VCC = +15V or +12V, VLOGIC = +5V, VEE = -15V or -12V; Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) TEMPERATURE RANGE -5 (0°C to +75°C) PARAMETER J SUFFIX K SUFFIX UNITS Unipolar Offset ±2 ±1 LSB Bipolar Offset ±2 ±1 LSB Full Scale Calibration ±9 ±2 LSB ±2 ±1 LSB ±1/ ±1/ LSB Temperature Coefficients Guaranteed Max Change, TMIN to TMAX (Using Internal Reference) Power Supply Rejection Max Change In Full Scale Calibration +13.5V < VCC < +16.5V or +11.4V < VCC < +12.6V +4.5V < VLOGIC < +5.5V -16.5V < VEE < -13.5V or -12.6V < VEE < -11.4V 2 ±2 2 ±1 LSB ANALOG INPUTS Input Ranges Bipolar -5 to +5 (Note 6) V -10 to +10 (Note 7) V 0 to +10 (Note 6) V 0 to +20 (Note 7) V 10V Span 5k, ±25% Ω 20V Span 10k, ±25% Ω +4.5 to +5.5 V VCC +11.4 to +16.5 V VEE -11.4 to -16.5 V ILOGIC 7 Typ, 15 Max mA ICC +15V Supply 11 Typ, 15 Max mA IEE -15V Supply 21 Typ, 28 Max mA ±15V, +5V 515 Typ, 720 Max mW ±12V, +5V 385 Typ mW +10.00 ±0.05 Max V 2.0 Max mA Unipolar Input Impedance POWER SUPPLIES Operating Voltage Range VLOGIC Operating Current Power Dissipation Internal Reference Voltage TMIN to TMAX Output Current, Available For External Loads (External Load Should Not Change During Conversion). 5 FN3096.6 August 7, 2008 HI-574A, HI-674A 8 DC and Transfer Accuracy Specifications Typical at +25°C with VCC = +15V or +12V, VLOGIC = +5V, VEE = -15V or -12V; Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) TEMPERATURE RANGE -2 (-55°C to +125°C) PARAMETER S SUFFIX T SUFFIX UNITS 12 12 Bits +25°C ±1 ±1/2 LSB -55°C to +125°C (Max) ±1 ±1 LSB +25°C 12 12 Bits TMIN to TMAX 11 12 Bits ±2 ±1.5 LSB DYNAMIC CHARACTERISTICS Resolution (Max) Linearity Error Max Resolution For Which No Missing Codes Is Guaranteed Unipolar Offset (Max) Adjustable to Zero Bipolar Offset (Max) VIN = 0V (Adjustable to Zero) VIN = -10V ±4 ±4 LSB ±0.15 ±0.1 % of FS ±0.25 ±0.25 % of FS Full Scale Calibration Error +25°C (Max), With Fixed 50Ω Resistor From REF OUT To REF IN (Adjustable To Zero) TMIN to TMAX (No Adjustment At +25°C) ±0.75 ±0.50 % of FS TMIN to TMAX (With Adjustment To Zero At +25°C) ±0.50 ±0.25 % of FS Unipolar Offset ±2 ±1 LSB Bipolar Offset ±2 ±2 LSB Full Scale Calibration ±20 ±10 LSB ±2 ±1 LSB ±1/ ±1/ LSB Temperature Coefficients Guaranteed Max Change, TMIN to TMAX (Using Internal Reference) Power Supply Rejection Max Change In Full Scale Calibration +13.5V < VCC < +16.5V or +11.4V < VCC < +12.6V +4.5V < VLOGIC < +5.5V -16.5V < VEE < -13.5V or -12.6V < VEE < -11.4V 2 ±2 2 ±1 LSB ANALOG INPUTS Input Ranges Bipolar -5 to +5 (Note 6) V -10 to +10 (Note 7) V 0 to +10 (Note 6) V 0 to +20 (Note 7) V 10V Span 5k, ±25% Ω 20V Span 10k, ±25% Ω Unipolar Input Impedance POWER SUPPLIES Operating Voltage Range VLOGIC +4.5 to +5.5 V VCC +11.4 to +16.5 V VEE -11.4 to -16.5 V 6 FN3096.6 August 7, 2008 HI-574A, HI-674A DC and Transfer Accuracy Specifications Typical at +25°C with VCC = +15V or +12V, VLOGIC = +5V, VEE = -15V or -12V; Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) TEMPERATURE RANGE -2 (-55°C to +125°C) S SUFFIX PARAMETER T SUFFIX UNITS Operating Current ILOGIC 7 Typ, 15 Max mA ICC +15V Supply 11 Typ, 15 Max mA IEE -15V Supply 21 Typ, 28 Max mA ±15V, +5V 515 Typ, 720 Max mW ±12V, +5V 385 Typ mW +10.00 ±0.05 Max V 2.0 Max mA Power Dissipation Internal Reference Voltage TMIN to TMAX Output current, available for external loads (external load should not change during conversion). Digital Specifications All Models, Over Full Temperature Range; Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. PARAMETER MIN TYP MAX Logic “1” +2.4V - +5.5V Logic “0” -0.5V - +0.8V Current - ±0.1µA ±5µA Capacitance - 5pF - Logic Inputs (CE, CS, R/C, AO,12/8) Logic Outputs (DB11-DB0, STS) Logic “0” (ISINK - 1.6mA) - - +0.4V Logic “1” (ISOURCE - 500µA) +2.4V - - Logic “1” (ISOURCE - 10µA) +4.5V - - Leakage (High-Z State, DB11-DB0 Only) - ±0.1µA ±5µA Capacitance - 5pF - Timing Specifications (HI-574A) +25°C, Note 5, Unless Otherwise Specified. SYMBOL PARAMETER MIN TYP MAX UNITS - - 200 ns CONVERT MODE tDSC STS Delay from CE tHEC CE Pulse Width 50 - - ns tSSC CS to CE Setup 50 - - ns tHSC CS Low During CE High 50 - - ns tSRC R/C to CE Setup 50 - - ns tHRC R/C Low During CE High 50 - - ns tSAC AO to CE Setup 0 - - ns tHAC AO Valid During CE High tC Conversion Time 7 50 - - ns 12-Bit Cycle TMIN to TMAX 15 20 25 μs 8-Bit Cycle TMIN to TMAX 10 13 17 μs FN3096.6 August 7, 2008 HI-574A, HI-674A Timing Specifications (HI-574A) +25°C, Note 5, Unless Otherwise Specified. (Continued) SYMBOL PARAMETER MIN TYP MAX UNITS - 75 150 ns 25 - - ns READ MODE tDD Access Time from CE tHD Data Valid After CE Low tHL Output Float Delay - 100 150 ns tSSR CS to CE Setup 50 - - ns tSRR R/C to CE Setup 0 - - ns tSAR AO to CE Setup 50 - - ns tHSR CS Valid After CE Low 0 - - ns tHRR R/C High After CE Low 0 - - ns tHAR AO Valid After CE Low 50 - - ns STS Delay After Data Valid 300 - 1200 ns MIN TYP MAX UNITS tHS Timing Specifications (HI-674A) +25°C, Note 5, Unless Otherwise Specified. SYMBOL PARAMETER CONVERT MODE tDSC STS Delay from CE - - 200 ns tHEC CE Pulse Width 50 - - ns tSSC CS to CE Setup 50 - - ns tHSC CS Low During CE High 50 - - ns tSRC R/C to CE Setup 50 - - ns tHRC R/C Low During CE High 50 - - ns tSAC AO to CE Setup 0 - - ns tHAC AO Valid During CE High 50 - - ns 12-Bit Cycle TMIN to TMAX 8 12 15 µs 8-Bit Cycle TMIN to TMAX 5 8 10 µs tC Conversion Time READ MODE tDD Access Time from CE tHD Data Valid After CE Low tHL Output Float Delay - 75 150 ns 25 - - ns - 100 150 ns tSSR CS to CE Setup 50 - - ns tSRR R/C to CE Setup 0 - - ns tSAR AO to CE Setup 50 - - ns tHSR CS Valid After CE Low 0 - - ns tHRR R/C High After CE Low 0 - - ns tHAR AO Valid After CE Low 50 - - ns STS Delay After Data Valid 25 - 850 ns tHS NOTES: 5. Time is measured from 50% level of digital transitions. Tested with a 50pF and 3kΩ load. 6. For the “10V Input”, Pin 13. 7. For the “20V Input”, Pin 14. 8 FN3096.6 August 7, 2008 HI-574A, HI-674A Pin Descriptions DESCRIPTION The HI-X74AK grade is guaranteed for maximum nonlinearity of ±1/2 LSB. For this grade, this means that an analog value which falls exactly in the center of a given code width will result in the correct digital output code. Values nearer the upper or lower transition of the code width may produce the next upper or lower digital output code. The HI-X74AJ is guaranteed to ±1 LSB max error. For this grade, an analog value which falls within a given code width will result in either the correct code for that region or either adjacent one. PIN SYMBOL 1 VLOGIC 2 12/8 Data Mode Select - Selects between 12-bit and 8-bit output modes. 3 CS Chip Select - Chip Select high disables the device. 4 AO Byte Address/Short Cycle - See Table 3 for operation. 5 R/C Read/Convert - See Table 3 for operation. 6 CE Chip Enable - Chip Enable low disables the device. 7 VCC Positive Supply (+12V/+15V) 8 REF OUT +10V Reference 9 AC Analog Common 10 REF IN 11 VEE 12 BIP OFF Bipolar Offset 13 10V Input 10V Input - Used for 0V to 10V and -5V to +5V input ranges. 14 20V Input 20V Input - Used for 0V to 20V and -10V to +10V input ranges. 15 DC Digital Common 16 DB0 Data Bit 0 (LSB) 17 DB1 Data Bit 1 18 DB2 Data Bit 2 19 DB3 Data Bit 3 20 DB4 Data Bit 4 Bipolar Offset 21 DB5 Data Bit 5 22 DB6 Data Bit 6 23 DB7 Data Bit 7 24 DB8 Data Bit 8 25 DB9 Data Bit 9 Similarly, in the bipolar mode, the major carry transition (0111 1111 1111 to 1000 0000 0000) should occur for an analog value 1/2 LSB below analog common. The bipolar offset error and temperature coefficient specify the initial deviation and maximum change in the error over temperature. 26 DB10 Data Bit 10 Full Scale Calibration Error 27 DB11 Data Bit 11 (MSB) 28 STS Status Bit - Status high implies a conversion is in progress. The last transition (from 1111 1111 1110 to 1111 1111 1111) should occur for an analog value 11/2 LSB below the nominal full scale (9.9963V for 10.000V full scale). The full scale calibration error is the deviation of the actual level at the last transition from the ideal level. This error, which is typically 0.05 to 0.1% of full scale, can be trimmed out as shown in Figures 1 and 2. The full scale calibration error over temperature is given with and without the initial error trimmed out. The temperature coefficients for each grade indicate the maximum change in the full scale gain from the initial value using the internal 10V reference. Logic supply pin (+5V) Reference Input Negative Supply (-12V/-15V). Definitions of Specifications Linearity Error Linearity error refers to the deviation of each individual code from a line drawn from “zero” through “full scale”. The point used as “zero” occurs 1/2 LSB (1.22mV for 10V span) before the first code transition (all zeros to only the LSB “on”). “Full scale” is defined as a level 11/2 LSB beyond the last code transition (to all ones). The deviation of a code from the true straight line is measured from the middle of each particular code. 9 Note that the linearity error is not user-adjustable. Differential Linearity Error (No Missing Codes) A specification which guarantees no missing codes requires that every code combination appear in a monotonic increasing sequence as the analog input level is increased. Thus every code must have a finite width. For the HI-X74AK grade, which guarantees no missing codes to 12-bit resolution, all 4096 codes must be present over the entire operating temperature ranges. The HI-X74AJ grade guarantees no missing codes to 11-bit resolution over temperature; this means that all code combinations of the upper 11 bits must be present; in practice very few of the 12-bit codes are missing. Unipolar Offset The first transition should occur at a level 1/2 LSB above analog common. Unipolar offset is defined as the deviation of the actual transition from that point. This offset can be adjusted as discussed on the following pages. The unipolar offset temperature coefficient specifies the maximum change of the transition point over temperature, with or without external adjustment. FN3096.6 August 7, 2008 HI-574A, HI-674A Temperature Coefficients The temperature coefficients for full-scale calibration, unipolar offset, and bipolar offset specify the maximum change from the initial (25°C) value to the value at TMIN or TMAX . Power Supply Rejection The standard specifications for the HI-X74A assume use of +5.00V and ±15.00V or ±12.00V supplies. The only effect of power supply error on the performance of the device will be a small change in the full scale calibration. This will result in a linear change in all lower order codes. The specifications show the maximum change in calibration from the initial value with the supplies at the various limits. Code Width A fundamental quantity for A/D converter specifications is the code width. This is defined as the range of analog input values for which a given digital output code will occur. The nominal value of a code width is equivalent to 1 least significant bit (LSB) of the full scale range or 2.44mV out of 10V for a 12-bit ADC. Quantization Uncertainty Analog-to-digital converters exhibit an inherent quantization uncertainty of ±1/2 LSB. This uncertainty is a fundamental characteristic of the quantization process and cannot be reduced for a converter of given resolution. Left-Justified Data The data format used in the HI-X74A is left-justified. This means that the data represents the analog input as a fraction of full-scale, ranging from 0 to 4095 . This implies a binary 4096 point to the left of the MSB. Applying the HI-X74A For each application of this converter, the ground connections, power supply bypassing, analog signal source, digital timing and signal routing on the circuit board must be optimized to assure maximum performance. These areas are reviewed in the following sections, along with basic operating modes and calibration requirements. Physical Mounting and Layout Considerations LAYOUT Unwanted, parasitic circuit components, (L, R, and C) can make 12-bit accuracy impossible, even with a perfect A/D converter. The best policy is to eliminate or minimize these parasitics through proper circuit layout, rather than try to quantify their effects. The recommended construction is a double-sided printed circuit board with a ground plane on the component side. Other techniques, such as wire-wrapping or point-to-point wiring on vector board, will have an unpredictable effect on accuracy. 10 In general, sensitive analog signals should be routed between ground traces and kept well away from digital lines. If analog and digital lines must cross, they should do so at right angles. Power Supplies Supply voltages to the HI-X74A (+15V, -15V and +5V) must be “quiet” and well regulated. Voltage spikes on these lines can affect the converter’s accuracy, causing several LSBs to flicker when a constant input is applied. Digital noise and spikes from a switching power supply are especially troublesome. If switching supplies must be used, outputs should be carefully filtered to assure “quiet” DC voltage at the converter terminals. Further, a bypass capacitor pair on each supply voltage terminal is necessary to counter the effect of variations in supply current. Connect one pair from pin 1 to 15 (VLOGIC supply), one from pin 7 to 9 (VCC to Analog Common) and one from pin 11 to 9 (VEE to Analog Common). For each capacitor pair, a 10µF tantalum type in parallel with a 0.1µF ceramic type is recommended. Ground Connections Pins 9 and 15 should be tied together at the package to guarantee specified performance for the converter. In addition, a wide PC trace should run directly from pin 9 to (usually) +15V common, and from pin 15 to (usually) the +5V Logic Common. If the converter is located some distance from the system’s “single point” ground, make only these connections to pins 9 and 15: Tie them together at the package, and back to the system ground with a single path. This path should have low resistance. (Code dependent currents flow in the VCC , VEE and VLOGIC terminals, but not through the HI-X74A’s Analog Common or Digital Common). Analog Signal Source HI-574A and HI-674A The device chosen to drive the HI-X74A analog input will see a nominal load of 5kΩ (10V range) or 10kΩ (20V range). However, the other end of these input resistors may change ±400mV with each bit decision, creating abrupt changes in current at the analog input. Thus, the signal source must maintain its output voltage while furnishing these step changes in load current, which occur at 1.6μs and 950ns intervals for the HI-574A and HI-674A, respectively. This requires low output impedance and fast settling by the signal source. The output impedance of an op amp, for example, has an open loop value which, in a closed loop, is divided by the loop gain available at a frequency of interest. The amplifier should have acceptable loop gain at 600kHz for use with the HI-X74A. To check whether the output properties of a signal source are suitable, monitor the HI-X74A’s input (pin 13 or 14) with an oscilloscope while a conversion is in progress. Each of the twelve disturbances should subside in 1μs or less for the HI-574A and 500ns or less for the HI-674A. (The comparator decision is made about 1.5µs and 850ns after each code change from the SAR for the HI-574A and HI-674A, respectively.) FN3096.6 August 7, 2008 HI-574A, HI-674A If the application calls for a Sample/Hold to precede the converter, it should be noted that not all Sample/Holds are compatible with the HI-574A in the manner described above. These will require an additional wideband buffer amplifier to lower their output impedance. A simpler solution is to use the Intersil HA-5320 Sample/Hold, which was designed for use with the HI-574A. STS 28 2 12/8 OFFSET R1 100K CS HIGH BITS 24-27 4 AO MIDDLE BITS 5 R/C 6 CE 20-23 LOW BITS +15V -15V 3 GAIN 16-19 10 REF IN 100Ω 8 REF OUT 100Ω +5V 1 13 10VIN +15V 7 14 20VIN† -15V 11 12 BIP OFF 0V TO +10V ANALOG INPUTS 0V TO +20V DIG COM 15 9 ANA COM † When driving the 20V (pin 14) input, minimize capacitance on pin 13. FIGURE 1. UNIPOLAR CONNECTIONS STS 28 2 12/8 3 CS HIGH BITS 24-27 4 AO MIDDLE BITS 5 R/C 6 16-19 CE R2 10 REF IN 100Ω 100Ω ±5V ANALOG INPUTS ±10V 8 REF OUT 12 BIP OFF R1 OFFSET Whether controlled by a processor or operating in the stand-alone mode, the HI-X74A offers four standard input ranges: 0V to +10V, 0V to +20V, ±5V and ±10V. The maximum errors for gain and offset are listed under Specifications. If required, however, these errors may be adjusted to zero as explained below. Power supply and ground connections have been discussed in an earlier section. 13 10VIN 14 20VIN† 9 ANA COM +5V 1 +15V 7 -15V 11 DIG COM 15 † When driving the 20V (pin 14) input, minimize capacitance on pin 13. FIGURE 2. BIPOLAR CONNECTIONS 11 Refer to Figure 1. The resistors shown (see Note below) are for calibration of offset and gain. If this is not required, replace R2 with a 50Ω, 1% metal film resistor and remove the network on pin 12. Connect pin 12 to pin 9. Then, connect the analog signal to pin 13 for the 0V to 10V range, or to pin 14 for the 0V to 20V range. Inputs to +20V (5V over the power supply) are no problem - the converter operates normally. Calibration consists of adjusting the converter’s most negative output to its ideal value (offset adjustment), then, adjusting the most positive output to its ideal value (gain adjustment). To understand the procedure, note that in principle, one is setting the output with respect to the midpoint of an increment of analog input, as denoted by two adjacent code changes. Nominal value of an increment is one LSB. However, this approach is impractical because nothing “happens” at a midpoint to indicate that an adjustment is complete. Therefore, calibration is performed in terms of the observable code changes instead of the midpoint between code changes. 20-23 LOW BITS GAIN The HI-X74A is a “complete” A/D converter, meaning it is fully operational with addition of the power supply voltages, a Start Convert signal, and a few external components as shown in Figures 1 and 2. Nothing more is required for most applications. Unipolar Connections and Calibration R2 100K Range Connections and Calibration Procedures For example, midpoint of the first LSB increment should be positioned at the origin, with an output code of all 0’s. To do this, apply an input of +1/2 LSB (+1.22mV for the 10V range; +2.44mV for the 20V range). Adjust the Offset potentiometer R1 until the first code transition flickers between 0000 0000 0000 and 0000 0000 0001. Next, perform a Gain Adjust at positive full scale. Again, the ideal input corresponding to the last code change is applied. This is 11/2 LSBs below the nominal full scale (+9.9963V for 10V range; +19.9927V for 20V range). Adjust the Gain potentiometer R2 for flicker between codes 1111 1111 1110 and 1111 1111 1111. Bipolar Connections and Calibration Refer to Figure 2. The gain and offset errors listed under Specifications may be adjusted to zero using potentiometers R1 and R2 (see Note below). If this isn’t FN3096.6 August 7, 2008 HI-574A, HI-674A required, either or both pots may be replaced by a 50Ω, 1% metal film resistor. Connect the Analog signal to pin 13 for a ±5V range, or to pin 14 for a ±10V range. Calibration of offset and gain is similar to that for the unipolar ranges as discussed above. First apply a DC input voltage 1/2 LSB above negative full scale (i.e., -4.9988V for the ±5V range, or -9.9976V for the ±10V range). Adjust the offset potentiometer R1 for flicker between output codes 0000 0000 0000 and 0000 0000 0001. Next, apply a DC input voltage 11/2 LSBs below positive full scale (+4.9963V for ±5V range; +9.9927V for ±10V range). Adjust the Gain potentiometer R2 for flicker between codes 1111 1111 1110 and 1111 1111 1111. NOTE: The 100Ω potentiometer R2 provides Gain Adjust for the 10V and 20V ranges. In some applications, a full scale of 10.24V (LSB equals 2.5mV) or 20.48V (LSB equals 5.0mV) is more convenient. For these, replace R2 by a 50Ω, 1% metal film resistor. Then, to provide Gain Adjust for the 10.24V range, add a 200Ω potentiometer in series with pin 13. For the 20.48V range, add a 500Ω potentiometer in series with pin 14. TABLE 1. HI-574A STAND-ALONE MODE TIMING SYMBOL “Stand-Alone Operation” The simplest control interface calls for a single control line connected to R/C. Also, CE and 12/8 are wired high, CS and AO are wired low, and the output data appears in words of 12 bits each. The R/C signal may have any duty cycle within (and including) the extremes shown in Figures 7 and 8. In general, data may be read when R/C is high unless STS is also high, indicating a conversion is in progress. Timing parameters particular to this mode of operation are listed in Tables 1 and 2. 12 MIN TYP MAX UNITS tHRL Low R/C Pulse Width 50 - - ns tDS STS Delay from R/C - - 200 ns 25 - - ns STS Delay after Data Valid 300 - 1200 ns tHRH High R/C Pulse Width 150 - - ns tDDR Data Access Time - - 150 ns tHDR tHS Data Valid after R/C Low Time is measured from 50% level of digital transitions. Tested with a 50pF and 3kΩ load. TABLE 2. HI-674A STAND-ALONE MODE TIMING SYMBOL PARAMETER MIN TYP MAX UNITS tHRL Low R/C Pulse Width 50 - - ns tDS STS Delay from R/C - - 200 ns Data Valid after R/C Low 25 - - ns tHS STS Delay after Data Valid 25 - 850 ns tHRH High R/C Pulse Width 150 - - ns tDDR Data Access Time - - 150 ns tHDR Controlling the HI-X74A The HI-X74A includes logic for direct interface to most microprocessor systems. The processor may take full control of each conversion, or the converter may operate in the “stand-alone” mode, controlled only by the R/C input. Full control consists of selecting an 8-bit or 12-bit conversion cycle, initiating the conversion, and reading the output data when ready-choosing either 12 bits at once or 8 followed by 4, in a left-justified format. The five control inputs are all TTL/CMOS-compatible: (12/8, CS, AO , R/C and CE). Table 3 illustrates the use of these inputs in controlling the converter’s operations. Also, a simplified schematic of the internal control logic is shown in Figure 6. PARAMETER Time is measured from 50% level of digital transitions. Tested with a 50pF and 3kΩ load. Conversion Length A Convert Start transition (see Table 1) latches the state of AO , which determines whether the conversion continues for 12 bits (AO low) or stops with 8 bits (AO high). If all 12 bits are read following an 8-bit conversion, the last three LSBs will read ZERO and DB3 will read ONE. AO is latched because it is also involved in enabling the output buffers (see ““Reading the Output Data” on page 13). No other control inputs are latched. TABLE 3. TRUTH TABLE FOR HI-X74A CONTROL INPUTS CE CS R/C 12/8 AO 0 X X X X None X 1 X X X None ↑ 0 0 X 0 Initiate 12-bit conversion ↑ 0 0 X 1 Initiate 8-bit conversion 1 ↓ 0 X 0 Initiate 12-bit conversion 1 ↓ 0 X 1 Initiate 8-bit conversion 1 0 ↓ X 0 Initiate 12-bit conversion 1 0 ↓ X 1 Initiate 8-bit conversion 1 0 1 1 X Enable 12-bit Output 1 0 1 0 0 Enable 8 MSBs Only 1 0 1 0 1 Enable 4 LSBs Plus 4 Trailing Zeroes OPERATION FN3096.6 August 7, 2008 HI-574A, HI-674A Conversion Start A conversion may be initiated as shown in Table 3 by a logic transition on any of three inputs: CE, CS or R/C. The last of the three to reach the correct state starts the conversion, so one, two or all three may be dynamically controlled. The nominal delay from each is the same, and if necessary, all three may change state simultaneously. However, to ensure that a particular input controls the start of conversion, the other two should be set up at least 50ns earlier. See the HI-X74A Timing Specifications, Convert Mode. This variety of HI-X74A control modes allows a simple interface in most system applications. The Convert Start timing relationships are illustrated in Figure 3. The output signal STS indicates status of the converter by going high only while a conversion is in progress. While STS is high, the output buffers remain in a high impedance state and data cannot be read. Also, an additional Start Convert will not reset the converter or re-initiate a conversion while STS is high. Reading the Output Data The output data buffers remain in a high impedance state until four conditions are met: R/C high, STS low, CE high and CS low. At that time, data lines become active according to the state of inputs 12/8 and AO . Timing constraints are illustrated in Figure 4. 12 output lines become active simultaneously, for interface to a 12-bit or 16-bit data bus. The AO input is ignored. With 12/8 low, the output is organized in two 8-bit bytes, selected one at a time by AO . This allows an 8-bit data bus to be connected as shown in Figure 5. AO is usually tied to the least significant bit of the address bus, for storing the HI-X74A output in two consecutive memory locations. (With AO low, the 8 MSBs only are enabled. With AO high, 4 MSBs are disabled, bits 4 through 7 are forced low, and the 4 LSBs are enabled). This two byte format is considered “left justified data,” for which a decimal (or binary!) point is assumed to the left of byte 1: BYTE 1 • X X X X X BYTE 2 X X X X X X MSB X 0 0 0 0 LSB Further, AO may be toggled at any time without damage to the converter. Break-before-make action is guaranteed between the two data bytes, which assures that the outputs strapped together in Figure 5 will never be enabled at the same time. A read operation usually begins after the conversion is complete and STS is low. For earliest access to the data, however, the read should begin no later than (tDD + tHS) before STS goes low. See Figure 4. The 12/8 input will be tied high or low in most applications, though it is fully TTL/CMOS-compatible. With 12/8 high, all CS R/C AO CE tHEC CE tSSC CS tHSC tSRC AO tSAC STS tHAC DB11-DB0 HIGH IMPEDANCE tSRR tSAR tHAR tHS tC tDSC tHSR tHRR R/C tHRC STS tSSR DB11-DB0 HIGH IMPEDANCE tDD tHD DATA VALID tHL See HI-X74A Timing Specifications for more information. See HI-X74A Timing Specifications for more information. FIGURE 3. CONVERT START TIMING FIGURE 4. READ CYCLE TIMING 13 FN3096.6 August 7, 2008 HI-574A, HI-674A AO ADDRESS BUS STS 28 1 2 12/8 DB11 (MSB) 27 3 26 4 AO 25 5 24 6 23 7 8 HI-X74A 22 21 9 20 10 19 11 18 12 17 13 DB0 (LSB) 16 DIG. 15 COM. 14 DATA BUS FIGURE 5. INTERFACE TO AN 8-BIT DATA BUS NIBBLE B ZERO OVERRIDE NIBBLE A, B INPUT BUFFERS 12/8 NIBBLE C READ CONTROL CS AO STATUS R/C CE CONVERT EOC9 CONTROL CURRENT CONTROLLED OSCILLATOR STROBE CLOCK CK D POWER UP RESET Q Q RESET AO LATCH EOC13 FIGURE 6. HI-X74A CONTROL LOGIC 14 FN3096.6 August 7, 2008 HI-574A, HI-674A tHRL R/C tDS STS tC tHDR DB11-DB0 tHS DATA VALID DATA VALID FIGURE 7. LOW PULSE FOR R/C - OUTPUTS ENABLED AFTER CONVERSION R/C tHRH tDS STS tDDR DB11-DB0 HIGH-Z tHDR DATA VALID tC HIGH-Z FIGURE 8. HIGH PULSE FOR R/C - OUTPUTS ENABLED WHILE R/C HIGH, OTHERWISE HIGH-Z 15 FN3096.6 August 7, 2008 HI-574A, HI-674A Die Characteristics DIE DIMENSIONS: PASSIVATION: Analog: 3070mm x 4610mm Digital: 1900mm x 4510mm METALLIZATION: Type: Nitride Over Silox Nitride Thickness: 3.5kÅ ±0.5kÅ Silox Thickness: 12kÅ ±1.5kÅ WORST CASE CURRENT DENSITY: Digital Type: Nitrox Thickness: 10kÅ ±2kÅ 1.3 x 105 A/cm2 Metal 1: AlSiCu Thickness: 8kÅ ±1kÅ Metal 2: AlSiCu Thickness: 16kÅ ±2kÅ Analog Type: Al Thickness: 16kÅ ±2kÅ Metallization Mask Layout DB11 STS VLOGIC VLOGIC 12/8 CS AO HI-574A, HI-674A R/C DB10 CE VCC DB9 VREFOUT ANALOG COMMON DB8 ANALOG COMMON DB7 ANALOG COMMON DB6 VREFIN DB5 DB4 DB3 DB2 16 DB1 DB0 DIGITAL COMMON 10V IN 20V IN BIPOLAR OFFSET VEE FN3096.6 August 7, 2008 HI-574A, HI-674A Ceramic Dual-In-Line Metal Seal Packages (SBDIP) D28.6 MIL-STD-1835 CDIP2-T28 (D-10, CONFIGURATION C) LEAD FINISH c1 -A- 28 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE -DBASE METAL E b1 M (b) M -Bbbb S C A - B S SECTION A-A D S D BASE PLANE Q S2 -C- SEATING PLANE A L S1 eA A A b2 b e eA/2 c aaa M C A - B S D S ccc M C A - B S D S INCHES (c) NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. Dimension Q shall be measured from the seating plane to the base plane. SYMBOL MIN MILLIMETERS MAX MIN MAX NOTES A - 0.232 - 5.92 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 1.490 - 37.85 - E 0.500 0.610 15.49 - e 12.70 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC - eA/2 0.300 BSC 7.62 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 5 S1 0.005 - 0.13 - 6 S2 0.005 - 0.13 - 7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2 N 28 28 8 Rev. 0 5/18/94 6. Measure dimension S1 at all four corners. 7. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 8. N is the maximum number of terminal positions. 9. Braze fillets shall be concave. 10. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 11. Controlling dimension: INCH. 17 FN3096.6 August 7, 2008 HI-574A, HI-674A Dual-In-Line Plastic Packages (PDIP) E28.6 (JEDEC MS-011-AB ISSUE B) N 28 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 SYMBOL -B- -C- A2 SEATING PLANE e B1 D1 A1 eC B 0.010 (0.25) M C A B S MAX NOTES - 0.250 - 6.35 4 0.015 - 0.39 - 4 A2 0.125 0.195 3.18 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.030 0.070 0.77 1.77 8 eA C 0.008 0.015 0.204 0.381 - D 1.380 1.565 D1 0.005 - A L D1 MIN A E BASE PLANE MAX A1 -AD MILLIMETERS MIN C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 35.1 39.7 5 - 5 0.13 E 0.600 0.625 15.24 15.87 6 E1 0.485 0.580 12.32 14.73 5 e 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC 6 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. eB - 0.700 - 17.78 7 L 0.115 0.200 2.93 5.08 4 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. N 28 28 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 9 Rev. 1 12/00 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 18 FN3096.6 August 7, 2008