CY7C093794V CY7C093894V CY7C09289V CY7C09369V CY7C09379V CY7C09389VFLEx18™ 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM CY7C0837AV CY7C0830AV/CY7C0831AV CY7C0832AV/CY7C0833AV FLEx18™ 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM Features Functional Description • True dual-ported memory cells that allow simultaneous access of the same memory location • Synchronous pipelined operation • Family of 512-Kbit, 1-Mbit, 2-Mbit, 4-Mbit and 9-Mbit devices • Pipelined output mode allows fast operation • 0.18-micron CMOS for optimum speed and power • High-speed clock to data access • 3.3V low power — Active as low as 225 mA (typ) — Standby as low as 55 mA (typ) • Mailbox function for message passing • Global master reset • Separate byte enables on both ports • Commercial and industrial temperature ranges • IEEE 1149.1-compatible JTAG boundary scan • 144-ball FBGA (13 mm × 13 mm) (1.0 mm pitch) • 120TQFP (14 mm x 14 mm x 1.4 mm) • Lead(Pb)-free packages available • Counter wrap around control — Internal mask register controls counter wrap-around — Counter-interrupt flags to indicate wrap-around — Memory block retransmit operation • Counter readback on address lines The FLEx18™ family includes 512-Kbit, 1-Mbit, 2-Mbit, 4-Mbit and 9-Mbit pipelined, synchronous, true dual-port static RAMs that are high-speed, low-power 3.3V CMOS. Two ports are provided, permitting independent, simultaneous access to any location in memory. The result of writing to the same location by more than one port at the same time is undefined. Registers on control, address, and data lines allow for minimal set-up and hold time. During a Read operation, data is registered for decreased cycle time. Each port contains a burst counter on the input address register. After externally loading the counter with the initial address, the counter will increment the address internally (more details to follow). The internal Write pulse width is independent of the duration of the R/W input signal. The internal Write pulse is self-timed to allow the shortest possible cycle times. A HIGH on CE0 or LOW on CE1 for one clock cycle will power down the internal circuitry to reduce the static power consumption. One cycle with chip enables asserted is required to reactivate the outputs. Additional features include: readback of burst-counter internal address value on address lines, counter-mask registers to control the counter wrap-around, counter interrupt (CNTINT) flags, readback of mask register value on address lines, retransmit functionality, interrupt flags for message passing, JTAG for boundary scan, and asynchronous Master Reset (MRST). The CY7C0833AV device in this family has limited features. Please see Address Counter and Mask Register Operations[15] on page 6 for details. • Mask register readback on address lines • Dual Chip Enables on both ports for easy depth expansion Table 1. Product Selection Guide Density 512-Kbit (32K x 18) 1-Mbit (64K x 18) 2-Mbit (128K x 18) 4-Mbit (256K x 18) 9-Mbit (512K x 18) CY7C0837AV CY7C0830AV CY7C0831AV CY7C0832AV CY7C0833AV Max. Speed (MHz) 167 167 167 167 133 Max. Access Time - clock to Data (ns) 4.0 4.0 4.0 4.0 4.7 Part Number Typical operating current (mA) Package Cypress Semiconductor Corporation Document #: 38-06059 Rev. *Q • 225 225 225 225 270 144 FBGA 120 TQFP 144 FBGA 120 TQFP 144 FBGA 120 TQFP 144 FBGA 144 FBGA 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 10, 2006 [+] Feedback CY7C0837AV CY7C0830AV/CY7C0831AV CY7C0832AV/CY7C0833AV Logic Block Diagram[1] OEL R/WL OER R/WR B0L B0R B1L B1R CE0L CE1L DQ9L–DQ17L DQ0L–DQ8L CE0R CE1R I/O Control 9 I/O Control 9 9 9 Addr. Read Back DQ9R–DQ17R DQ0R–DQ8R Addr. Read Back True Dual-Ported RAM Array A0L–A18L 19 19 Mask Register CNT/MSKL ADSL Counter/ Address Register CNTENL CNTRSTL CLKL Mask Register Address Address Decode Decode Mirror Reg INTL Interrupt Logic CNT/MSKR ADS Counter/ Address Register CNTEN CNTRSTR Mirror Reg CNTINTL MRST Reset Logic TMS TDI TCK JTAG TDO Interrupt Logic A0R–A18R CLKR CNTINTR INTR Note: 1. CY7C0837AV has 15 address CY7C0830AV has 16 address bits, CY7C0831AV has 17 address bits, CY7C0832AV has 18 address bits and CY7C0833AV has 19 address bits. Document #: 38-06059 Rev. *Q Page 2 of 28 [+] Feedback CY7C0837AV CY7C0830AV/CY7C0831AV CY7C0832AV/CY7C0833AV Pin Configurations 144-ball BGA Top View CY7C0837AV / CY7C0830AV / CY7C0831AV CY7C0832AV / CY7C0833AV 1 2 3 4 5 6 7 8 9 10 11 12 A DQ17L DQ16L DQ14L DQ12L DQ10L DQ9L DQ9R DQ10R DQ12R DQ14R DQ16R DQ17R B A0L A1L DQ15L DQ13L DQ11L MRST NC DQ11R DQ13R DQ15R A1R A0R C A2L A3L CE1L [6] INTL CNTINTL [8] ADSL [7] ADSR [7] CNTINTR [8] INTR CE1R [6] A3R A2R D A4L A5L CE0L [7] NC VDD VDD VDD VDD NC CE0R [7] A5R A4R E A6L A7L B1L NC VDD VSS VSS VDD NC B1R A7R A6R F A8L A9L CL NC VSS VSS VSS VSS NC CR A9R A8R G A10L A11L B0L NC VSS VSS VSS VSS NC B0R A11R A10R H A12L A13L OEL NC VDD VSS VSS VDD NC OER A13R A12R J A14L A15L [2] RWL NC VDD VDD VDD VDD NC RWR A15R [2] A14R K A16L [3] A17L [4] CNT/MSKL [6] TDO CNTRSTL [6] TCK TMS CNTRSTR [6] TDI CNT/MSKR [6] A17R [4] A16R [3] L A18L [5] NC DQ6L DQ4L DQ2L CNTENL [7] CNTENR [7] DQ2R DQ4R DQ6R NC A18R [5] M DQ8L DQ7L DQ5L DQ3L DQ1L DQ0L DQ0R DQ1R DQ3R DQ5R DQ7R DQ8R Notes: 2. Leave this ball unconnected for CY7C0837AV. 3. Leave this ball unconnected for CY7C0837AV and CY7C0830AV. 4. Leave this ball unconnected for CY7C0837AV, CY7C0830AV and CY7C0831AV. 5. Leave this ball unconnected for CY7C0837AV, CY7C0830AV, CY7C0831AV and CY7C0832AV. 6. These balls are not applicable for CY7C0833AV device. They need to be tied to VDD. 7. These balls are not applicable for CY7C0833AV device. They need to be tied to VSS. 8. These balls are not applicable for CY7C0833AV device. They need to be no connected. Document #: 38-06059 Rev. *Q Page 3 of 28 [+] Feedback CY7C0837AV CY7C0830AV/CY7C0831AV CY7C0832AV/CY7C0833AV Pin Configurations (continued) 120-pin Thin Quad Flat Pack (TQFP) Top View A2L A3L VSS VDD A4L A5L A6L A7L CE1L B0L B1L OEL CE0L VDD VSS R/WL CLKL VSS ADSL CNTENL CNTRSTL CNT/MSKL A8L A9L A10L A11L A12L VSS VDD INTR DQ9R DQ10R DQ11R DQ15L DQ14L DQ13L VDD VSS DQ12L DQ11L DQ10L DQ9L INTL CNTINTL CNTINTR DQ12R VSS VDD DQ13R DQ14R DQ15R DQ16R DQ17R A0R A1R 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 A2R A3R VSS VDD A4R A5R A6R A7R CE1R B0R B1R OER CE0R VDD VSS R/WR CLKR MRST ADSR CNTENR CNTRSTR CNT/MSKR A8R A9R A10R A11R A12R VSS VDD A13R VDD DQ4R DQ5R DQ6R DQ7R DQ8R A17R[10] A16R[9] A15R A14R DQ1R DQ2R DQ3R VSS DQ8L DQ7L DQ6L DQ5L DQ4L VDD VSS DQ3L DQ2L DQ1L DQ0L DQ0R A14L A15L A16L[9] A17L[10] 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 A13L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 A1L A0L DQ17L DQ16L CY7C0830AV / CY7C0831AV / CY7C0832AV Notes: 9. Leave this pin unconnected for CY7C0830AV. 10. Leave this pin unconnected for CY7C0830AV and CY7C0831AV. Document #: 38-06059 Rev. *Q Page 4 of 28 [+] Feedback CY7C0837AV CY7C0830AV/CY7C0831AV CY7C0832AV/CY7C0833AV Pin Definitions Left Port Right Port Description A0L–A18L[1] A0R–A18R[1] Address Inputs. ADSL[7] ADSR[7] Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW for the part using the externally supplied address on the address pins and for loading this address into the burst address counter. CE0L[7] CE0R[7] Active LOW Chip Enable Input. [6] [6] Active HIGH Chip Enable Input. CE1L CE1R CLKR Clock Signal. Maximum clock input rate is fMAX. CNTENR[7] Counter Enable Input. Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK. The increment is disabled if ADS or CNTRST are asserted LOW. CNTRSTL[6] CNTRSTR[6] Counter Reset Input. Asserting this signal LOW resets to zero the unmasked portion of the burst address counter of its respective port. CNTRST is not disabled by asserting ADS or CNTEN. CNT/MSKL[6] CNT/MSKR[6] Address Counter Mask Register Enable Input. Asserting this signal LOW enables access to the mask register. When tied HIGH, the mask register is not accessible and the address counter operations are enabled based on the status of the counter control signals. DQ0L–DQ17L[1] DQ0R–DQ17R[1] Data Bus Input/Output. OEL OER Output Enable Input. This asynchronous signal must be asserted LOW to enable the DQ data pins during Read operations. INTL INTR Mailbox Interrupt Flag Output. The mailbox permits communications between ports. The upper two memory locations can be used for message passing. INTL is asserted LOW when the right port writes to the mailbox location of the left port, and vice versa. An interrupt to a port is deasserted HIGH when it reads the contents of its mailbox. CNTINTL[8] CNTINTR[8] Counter Interrupt Output. This pin is asserted LOW when the unmasked portion of the counter is incremented to all “1s.” R/WL R/WR Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to Read from the dual port memory array. B0L–B1L B0R–B1R Byte Select Inputs. Asserting these signals enables Read and Write operations to the corresponding bytes of the memory array. CLKL CNTENL [7] MRST Master Reset Input. MRST is an asynchronous input signal and affects both ports. Asserting MRST LOW performs all of the reset functions as described in the text. A MRST operation is required at power-up. TMS JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State machine transitions occur on the rising edge of TCK. TDI JTAG Test Data Input. Data on the TDI input will be shifted serially into selected registers. TCK JTAG Test Clock Input. TDO JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally three-stated except when captured data is shifted out of the JTAG TAP. VSS Ground Inputs. VDD Power Inputs. Byte Select Operation Control Pin Effect B0 DQ0–8 Byte Control B1 DQ9–17 Byte Control Document #: 38-06059 Rev. *Q Page 5 of 28 [+] Feedback CY7C0837AV CY7C0830AV/CY7C0831AV CY7C0832AV/CY7C0833AV Master Reset The counter register contains the address used to access the RAM array. It is changed only by the Counter Load, Increment, Counter Reset, and by master reset (MRST) operations. The FLEx18 family devices undergo a complete reset by taking its MRST input LOW. The MRST input can switch asynchronously to the clocks. An MRST initializes the internal burst counters to zero, and the counter mask registers to all ones (completely unmasked). MRST also forces the Mailbox Interrupt (INT) flags and the Counter Interrupt (CNTINT) flags HIGH. MRST must be performed on the FLEx18 family devices after power-up. The mask register value affects the Increment and Counter Reset operations by preventing the corresponding bits of the counter register from changing. It also affects the counter interrupt output (CNTINT). The mask register is changed only by the Mask Load and Mask Reset operations, and by the MRST. The mask register defines the counting range of the counter register. It divides the counter register into two regions: zero or more “0s” in the most significant bits define the masked region, one or more “1s” in the least significant bits define the unmasked region. Bit 0 may also be “0,” masking the least significant counter bit and causing the counter to increment by two instead of one. Mailbox Interrupts The upper two memory locations may be used for message passing and permit communications between ports. Table 2 shows the interrupt operation for both ports of CY7C0833AV. The highest memory location, 7FFFF is the mailbox for the right port and 7FFFE is the mailbox for the left port. Table 2 shows that in order to set the INTR flag, a Write operation by the left port to address 7FFFF will assert INTR LOW. At least one byte has to be active for a Write to generate an interrupt. A valid Read of the 7FFFF location by the right port will reset INTR HIGH. At least one byte has to be active in order for a Read to reset the interrupt. When one port Writes to the other port’s mailbox, the INT of the port that the mailbox belongs to is asserted LOW. The INT is reset when the owner (port) of the mailbox Reads the contents of the mailbox. The interrupt flag is set in a flow-thru mode (i.e., it follows the clock edge of the writing port). Also, the flag is reset in a flow-thru mode (i.e., it follows the clock edge of the reading port). The mirror register is used to reload the counter register on increment operations (see “retransmit,” below). It always contains the value last loaded into the counter register, and is changed only by the Counter Load, and by the MRST instructions. Table 3 summarizes the operation of these registers and the required input control signals. The MRST control signal is asynchronous. All the other control signals in Table 3 (CNT/MSK, CNTRST, ADS, CNTEN) are synchronized to the port’s CLK. All these counter and mask operations are independent of the port’s chip enable inputs (CE0 and CE1). Counter enable (CNTEN) inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast, interleaved memory applications. A port’s burst counter is loaded when the port’s address strobe (ADS) and CNTEN signals are LOW. When the port’s CNTEN is asserted and the ADS is deasserted, the address counter will increment on each LOW to HIGH transition of that port’s clock signal. This will Read/Write one word from/into each successive address location until CNTEN s deasserted. The counter can address the entire memory array, and will loop back to the start. Counter reset (CNTRST) is used to reset the unmasked portion of the burst counter to i0s. A counter-mask register is used to control the counter wrap. Each port can read the other port’s mailbox without resetting the interrupt. And each port can write to its own mailbox without setting the interrupt. If an application does not require message passing, INT pins should be left open. Address Counter and Mask Register Operations[15] This section describes the features only apply to 512Kbit,1Mbit, 2Mbit, and 4Mbit devices. It does not apply to 9Mbit device. Each port of these devices has a programmable burst address counter. The burst counter contains three registers: a counter register, a mask register, and a mirror register. Table 2. Interrupt Operation Example [1, 11, 12, 13, 14, 16] FUNCTION LEFT PORT RIGHT PORT R/WL CEL A0L–A18L INTL R/WR CER A0R–A18R INTR Set Right INTR Flag L L 3FFFF X X X X L Reset Right INTR Flag X X X X H L 3FFFF H Set Left INTL Flag X X X L L L 3FFFE X Reset Left INTL Flag H L 3FFFE H X X X X Set Right INTR Flag L L 3FFFF X X X X L Notes: 11. CE is internal signal. CE = LOW if CE0 = LOW and CE1 = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK and can be deasserted after that. Data will be out after the following CLK edge and will be three-stated after the next CLK edge. 12. OE is “Don’t Care” for mailbox operation. 13. At least one of BE0, BE1 must be LOW. 14. A18x is a NC for CY7C0832AV, therefore the Interrupt Addresses are 3FFFF and 3FFFE. A18x and A17x are NC for CY7C0831AV, therefore the Interrupt addresses are 1FFFF and 1FFFE; A18x, A17x and A16x are NC for CY7C0830AV, therefore the Interrupt Addresses are FFFF and FFFE;A18x, A17x, A16x and A15x are NC for CY7C0837AV, therefore the Interrupt Addresses are 7FFF and 7FFE. 15. This section describes the CY7C0832AV, CY7C0831AV, CY7C0830AV and CY7C0837AV having 18, 17, 16 and 15 address bits. 16. “X” = “Don’t Care,” “H” = HIGH, “L” = LOW. Document #: 38-06059 Rev. *Q Page 6 of 28 [+] Feedback CY7C0837AV CY7C0830AV/CY7C0831AV CY7C0832AV/CY7C0833AV Counter Reset Operation All unmasked bits of the counter are reset to “0.” All masked bits remain unchanged. The mirror register is loaded with the value of the burst counter. A Mask Reset followed by a Counter Reset will reset the counter and mirror registers to 00000, as will master reset (MRST). Counter Load Operation The address counter and mirror registers are both loaded with the address value presented at the address lines. memory space. The address counter is then loaded with an initial value of 8h. The base address bits (in this case, the 6th address through the 16th address) are loaded with an address value but do not increment once the counter is configured for increment operation. The counter address will start at address 8h. The counter will increment its internal address value till it reaches the mask register value of 3Fh. The counter wraps around the memory block to location 8h at the next count. CNTINT is issued when the counter reaches its maximum value Counter Hold Operation Counter Increment Operation Once the address counter register is initially loaded with an external address, the counter can internally increment the address value, potentially addressing the entire memory array. Only the unmasked bits of the counter register are incremented. The corresponding bit in the mask register must be a “1” for a counter bit to change. The counter register is incremented by 1 if the least significant bit is unmasked, and by 2 if it is masked. If all unmasked bits are “1,” the next increment will wrap the counter back to the initially loaded value. If an Increment results in all the unmasked bits of the counter being “1s,” a counter interrupt flag (CNTINT) is asserted. The next Increment will return the counter register to its initial value, which was stored in the mirror register. The counter address can instead be forced to loop to 00000 by externally connecting CNTINT to CNTRST.[18] An increment that results in one or more of the unmasked bits of the counter being “0” will deassert the counter interrupt flag. The example in Figure 2 shows the counter mask register loaded with a mask value of 0003Fh unmasking the first 6 bits with bit “0” as the LSB and bit “16” as the MSB. The maximum value the mask register can be loaded with is 3FFFFh. Setting the mask register to this value allows the counter to access the entire The value of all three registers can be constantly maintained unchanged for an unlimited number of clock cycles. Such operation is useful in applications where wait states are needed, or when address is available a few cycles ahead of data in a shared bus interface. Counter Interrupt The counter interrupt (CNTINT) is asserted LOW when an increment operation results in the unmasked portion of the counter register being all “1s.” It is deasserted HIGH when an Increment operation results in any other value. It is also de-asserted by Counter Reset, Counter Load, Mask Reset and Mask Load operations, and by MRST. Counter Readback Operation The internal value of the counter register can be read out on the address lines. Readback is pipelined; the address will be valid tCA2 after the next rising edge of the port’s clock. If address readback occurs while the port is enabled (CE0 LOW and CE1 HIGH), the data lines (DQs) will be three-stated. Figure 1 shows a block diagram of the operation. Table 3. Address Counter and Counter-Mask Register Control Operation (Any Port)[16, 17] CLK MRST CNT/MSK CNTRST ADS CNTEN Operation Description X L X X X X Master Reset Reset address counter to all 0s and mask register to all 1s. H H L X X Counter Reset Reset counter unmasked portion to all 0s. H H H L L Counter Load Load counter with external address value presented on address lines. H H H L H Counter Readback Read out counter internal value on address lines. H H H H L Counter Increment Internally increment address counter value. H H H H H Counter Hold Constantly hold the address value for multiple clock cycles. H L L X X Mask Reset Reset mask register to all 1s. H L H L L Mask Load Load mask register with value presented on the address lines. H L H L H Mask Readback Read out mask register value on address lines. H L H H X Reserved Operation undefined Notes: 17. Counter operation and mask register operation is independent of chip enables. 18. CNTINT and CNTRST specs are guaranteed by design to operate properly at speed grade operating frequency when tied together. Document #: 38-06059 Rev. *Q Page 7 of 28 [+] Feedback CY7C0837AV CY7C0830AV/CY7C0831AV CY7C0832AV/CY7C0833AV Retransmit Retransmit is a feature that allows the Read of a block of memory more than once without the need to reload the initial address. This eliminates the need for external logic to store and route data. It also reduces the complexity of the system design and saves board space. An internal “mirror register” is used to store the initially loaded address counter value. When the counter unmasked portion reaches its maximum value set by the mask register, it wraps back to the initial value stored in this “mirror register.” If the counter is continuously configured in increment mode, it increments again to its maximum value and wraps back to the value initially stored into the “mirror register.” Thus, the repeated access of the same data is allowed without the need for any external logic. Mask Reset Operation The mask register is reset to all “1s,” which unmasks every bit of the counter. Master reset (MRST) also resets the mask register to all “1s.” Mask Load Operation The mask register is loaded with the address value presented at the address lines. Not all values permit correct increment Document #: 38-06059 Rev. *Q operations. Permitted values are of the form 2n – 1 or 2n – 2. From the most significant bit to the least significant bit, permitted values have zero or more “0s,” one or more “1s,” or one “0.” Thus 3FFFF, 003FE, and 00001 are permitted values, but 3F0FF, 003FC, and 00000 are not. Mask Readback Operation The internal value of the mask register can be read out on the address lines. Readback is pipelined; the address will be valid tCM2 after the next rising edge of the port’s clock. If mask readback occurs while the port is enabled (CE0 LOW and CE1 HIGH), the data lines (DQs) will be three-stated. Figure 1 shows a block diagram of the operation. Counting by Two When the least significant bit of the mask register is “0,” the counter increments by two. This may be used to connect the x18 devices as a 36-bit single port SRAM in which the counter of one port counts even addresses and the counter of the other port counts odd addresses. This even-odd address scheme stores one half of the 36-bit data in even memory locations, and the other half in odd memory locations. Page 8 of 28 [+] Feedback CY7C0837AV CY7C0830AV/CY7C0831AV CY7C0832AV/CY7C0833AV CNT/MSK CNTEN Decode Logic ADS CNTRST MRST Bidirectional Address Lines Mask Register Counter/ Address Register Address RAM Decode Array CLK From Address Lines Load/Increment 17 Mirror 1 From Mask Register Increment Logic Wrap 17 From Mask From Counter 17 To Readback and Address Decode 0 0 17 Counter 1 17 17 Bit 0 +1 Wrap Detect 1 +2 Wrap 0 1 0 17 To Counter Figure 1. Counter, Mask, and Mirror Logic Block Diagram[1] Document #: 38-06059 Rev. *Q Page 9 of 28 [+] Feedback CY7C0837AV CY7C0830AV/CY7C0831AV CY7C0832AV/CY7C0833AV Example: Load Counter-Mask Register = 3F CNTINT H 0 0 0s 216 215 H X X Xs 216 215 Max Address Register L H 1 1 1 X X X X 216 215 Unmasked Address X 0 0 1 0 0 Xs X 1 1 1 Mask Register bit-0 0 26 25 24 23 22 21 20 216 215 Max + 1 Address Register 1 26 25 24 23 22 21 20 Masked Address Load Address Counter = 8 0 1 1 1 1 1 Address Counter bit-0 26 25 24 23 22 21 20 Xs X 0 0 1 0 0 0 26 25 24 23 22 21 20 Figure 2. Programmable Counter-Mask Register Operation[1, 19] IEEE 1149.1 Serial Boundary Scan (JTAG)[20] The FLEx18 family devices incorporate an IEEE 1149.1 serial boundary scan test access port (TAP). The TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1-compliant TAPs. The TAP operates using JEDEC-standard 3.3V I/O logic levels. It is composed of three input connections and one output connection required by the test logic defined by the standard. Performing a TAP Reset A reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This reset does not affect the operation of the devices, and may be performed while the device is operating. An MRST must be performed on the devices after power-up. Performing a Pause/Restart When a SHIFT-DR PAUSE-DR SHIFT-DR is performed the scan chain will output the next bit in the chain twice. For example, if the value expected from the chain is 1010101, the device will output a 11010101. This extra bit will cause some testers to report an erroneous failure for the devices in a scan test. Therefore the tester should be configured to never enter the PAUSE-DR state. Boundary Scan Hierarchy for 9-Mbit Device Internally, the CY7C0833AV have two DIEs. Each DIE contain all the circuitry required to support boundary scan testing. The circuitry includes the TAP, TAP controller, instruction register, and data registers. The circuity and operation of the DIE boundary scan are described in detail below. The scan chain of each DIE are connected serially to form the scan chain of the CY7C0833AV as shown in Figure 3. TMS and TCK are connected in parallel to each DIE to drive all TAP controllers in unison. In many cases, each DIE will be supplied with the same instruction. In other cases, it might be useful to supply different instructions to each DIE. One example would be testing the device ID of one DIE while bypassing the others. Each pin of FLEx18 family is typically connected to multiple DIEs. For connectivity testing with the EXTEST instruction, it is desirable to check the internal connections between DIEs as well as the external connections to the package. This can be accomplished by merging the netlist of the devices with the netlist of the user’s circuit board. To facilitate boundary scan testing of the devices, Cypress provides the BSDL file for each DIE, the internal netlist of the device, and a description of the device scan chain. The user can use these materials to easily integrate the devices into the board’s boundary scan environment. Further information can be found in the Cypress application note Using JTAG Boundary Scan For System in a Package (SIP) Dual-Port SRAMs. Notes: 19. The “X” in this diagram represents the counter upper bits 20. Boundary scan is IEEE 1149.1-compatible. See “Performing a Pause/Restart” for deviation from strict 1149.1 compliance Document #: 38-06059 Rev. *Q Page 10 of 28 [+] Feedback CY7C0837AV CY7C0830AV/CY7C0831AV CY7C0832AV/CY7C0833AV TDO TDO D2 TDI TDO D1 TDI TDI Figure 3. Scan Chain for 9Mb Device Table 4. Identification Register Definitions Instruction Field Value Description Revision Number (31:28) 0h Reserved for version number. Cypress Device ID (27:12) C090h Defines Cypress part number for CY7C0832AV C091h Defines Cypress part number for CY7C0831AV C093h Defines Cypress part number for CY7C0830AV C094h Defines Cypress part number for CY7C0837AV. Cypress JEDEC ID (11:1) 034h Allows unique identification of the DP family device vendor. ID Register Presence (0) 1 Indicates the presence of an ID register. Table 5. Scan Registers Sizes Register Name Bit Size Instruction 4 Bypass 1 Identification 32 Boundary Scan n[21] Table 6. Instruction Identification Codes Instruction Code Description EXTEST 0000 Captures the Input/Output ring contents. Places the BSR between the TDI and TDO. BYPASS 1111 Places the BYR between TDI and TDO. IDCODE 1011 Loads the IDR with the vendor ID code and places the register between TDI and TDO. HIGHZ 0111 Places BYR between TDI and TDO. Forces all device output drivers to a High-Z state. CLAMP 0100 Controls boundary to 1/0. Places BYR between TDI and TDO. SAMPLE/PRELOAD 1000 Captures the input/output ring contents. Places BSR between TDI and TDO. NBSRST 1100 Resets the non-boundary scan logic. Places BYR between TDI and TDO. RESERVED All other codes Other combinations are reserved. Do not use other than the above. Notes: 21. See details in the device BSDL file. Document #: 38-06059 Rev. *Q Page 11 of 28 [+] Feedback CY7C0837AV CY7C0830AV/CY7C0831AV CY7C0832AV/CY7C0833AV Maximum Ratings[22] Output Current into Outputs (LOW)............................. 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage........................................... > 2000V (JEDEC JESD22-A114-2000B) Storage Temperature ................................. –65°C to +150°C Latch-up Current..................................................... > 200 mA Ambient Temperature with Operating Range Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential ............... –0.5V to +4.6V Range Ambient Temperature VDD DC Voltage Applied to Outputs in High-Z State..........................–0.5V to VDD + 0.5V Commercial 0°C to +70°C 3.3V±165 mV –40°C to +85°C 3.3V±165 mV DC Input Voltage...............................–0.5V to VDD + 0.5V[23] Industrial Electrical Characteristics Over the Operating Range -167 Parameter Description VOH Output HIGH Voltage (VDD = Min., IOH= –4.0 mA) VOL Output LOW Voltage (VDD = Min., IOL= +4.0 mA) -133 -100 Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit 2.4 2.4 2.4 0.4 2.0 V 0.4 2.0 0.4 V 0.8 V VIH Input HIGH Voltage VIL Input LOW Voltage 2.0 IOZ Output Leakage Current –10 10 –10 10 –10 10 µA IIX1 Input Leakage Current Except TDI, TMS, MRST –10 10 –10 10 –10 10 µA IIX2 Input Leakage Current TDI, TMS, MRST –0.1 1.0 –0.1 1.0 –0.1 1.0 ICC Operating Current for CY7C0837AV (VDD = Max., IOUT = 0 mA), Outputs CY7C0830AV Disabled CY7C0831AV CY7C0832AV ISB1[24] 0.8 225 300 Standby Current (Both Ports TTL Level) CEL and CER ≥ VIH, f = fMAX 90 115 ISB2[24] Standby Current (One Port TTL Level) CEL | CER ≥ VIH, f = fMAX 160 ISB3[24] Standby Current (Both Ports CMOS Level) CEL and CER ≥ VDD – 0.2V, f = 0 ISB4[24] Standby Current (One Port CMOS Level) CEL | CER ≥ VIH, f = fMAX ISB5 Operating Current (VDD = Max, IOUT = 0 mA, f = 0) Outputs Disabled mA 225 300 270 400 200 310 mA 90 115 90 115 mA 210 160 210 160 210 mA 55 75 55 75 55 75 mA 160 210 160 210 160 210 mA 70 100 70 100 mA CY7C0833AV CY7C0833AV V 0.8 mA Notes: 22. The voltage on any input or I/O pin can not exceed the power pin during power-up. 23. Pulse width < 20 ns. 24. ISB1, ISB2, ISB3 and ISB4 are not applicable for CY7C0833AV because it can not be powered down by using chip enable pins. Document #: 38-06059 Rev. *Q Page 12 of 28 [+] Feedback CY7C0837AV CY7C0830AV/CY7C0831AV CY7C0832AV/CY7C0833AV Capacitance [25] Part Number Parameter Description Test Conditions Max. Unit 13 pF 10 pF Input Capacitance 22 pF Output Capacitance 20 pF CY7C0837AV CY7C0830AV CY7C0831AV CY7C0832AV CIN Input Capacitance COUT Output Capacitance CY7C0833AV CIN COUT TA = 25°C, f = 1 MHz, VDD = 3.3V AC Test Load and Waveforms 3.3V Z0 = 50Ω R = 50Ω R1 = 590 Ω OUTPUT OUTPUT C = 10 pF C = 5 pF VTH = 1.5V (a) Normal Load (Load 1) 3.0V ALL INPUT PULSES (b) Three-state Delay (Load 2) 90% 90% 10% 10% Vss R2 = 435 Ω < 2 ns < 2 ns Switching Characteristics Over the Operating Range -167 Parameter Description -133 -100 CY7C0837AV CY7C0830AV CY7C0831AV CY7C0832AV CY7C0837AV CY7C0830AV CY7C0831AV CY7C0832AV CY7C0833AV CY7C0833AV Min. Min. Min. Min. Max. 133 Max. 133 Max. Unit 100 MHz fMAX2 Maximum Operating Frequency tCYC2 Clock Cycle Time 6.0 7.5 7.5 10 ns tCH2 Clock HIGH Time 2.7 3.0 3.0 4.0 ns tCL2 Clock LOW Time 2.7 3.0 3.0 4.0 ns [26] 167 Max. Clock Rise Time 2.0 2.0 2.0 3.0 ns tF[26] Clock Fall Time 2.0 2.0 2.0 3.0 ns tSA Address Set-up Time 2.3 2.5 2.5 3.0 ns tHA Address Hold Time 0.6 0.6 0.6 0.6 ns tSB Byte Select Set-up Time 2.3 2.5 2.5 3.0 ns tHB Byte Select Hold Time 0.6 0.6 0.6 0.6 ns tSC Chip Enable Set-up Time 2.3 2.5 NA NA ns tHC Chip Enable Hold Time 0.6 0.6 NA NA ns tSW R/W Set-up Time 2.3 2.5 2.5 3.0 ns tHW R/W Hold Time 0.6 0.6 0.6 0.6 ns tR Notes: 25. COUT also references CI/O. 26. Except JTAG signals (tr and tf < 10 ns [max.]). Document #: 38-06059 Rev. *Q Page 13 of 28 [+] Feedback CY7C0837AV CY7C0830AV/CY7C0831AV CY7C0832AV/CY7C0833AV Switching Characteristics Over the Operating Range (continued) -167 Parameter Description -133 -100 CY7C0837AV CY7C0830AV CY7C0831AV CY7C0832AV CY7C0837AV CY7C0830AV CY7C0831AV CY7C0832AV CY7C0833AV CY7C0833AV Min. Min. Min. Min. Max. Max. Max. Max. Unit tSD Input Data Set-up Time 2.3 2.5 2.5 3.0 ns tHD Input Data Hold Time 0.6 0.6 0.6 0.6 ns tSAD ADS Set-up Time 2.3 2.5 NA NA ns tHAD ADS Hold Time 0.6 0.6 NA NA ns tSCN CNTEN Set-up Time 2.3 2.5 NA NA ns tHCN CNTEN Hold Time 0.6 0.6 NA NA ns tSRST CNTRST Set-up Time 2.3 2.5 NA NA ns tHRST CNTRST Hold Time 0.6 0.6 NA NA ns tSCM CNT/MSK Set-up Time 2.3 2.5 NA NA ns tHCM CNT/MSK Hold Time 0.6 0.6 NA NA ns tOE Output Enable to Data Valid tOLZ[27,28] OE to Low Z 0 4.0 4.4 4.7 5.0 tOHZ[27,28] OE to High Z 0 tCD2 Clock to Data Valid tCA2 tCM2 tDC Data Output Hold After Clock HIGH tCKHZ[27,28] tCKLZ[27, 28] Clock HIGH to Output High Z 0 4.0 0 4.4 Clock HIGH to Output Low Z 1.0 4.0 1.0 4.4 tSINT Clock to INT Set Time 0.5 6.7 0.5 7.5 0.5 7.5 0.5 10 ns tRINT Clock to INT Reset Time 0.5 6.7 0.5 7.5 0.5 7.5 0.5 10 ns tSCINT Clock to CNTINT Set Time 0.5 5.0 0.5 5.7 NA NA NA NA ns tRCINT Clock to CNTINT Reset time 0.5 5.0 0.5 5.7 NA NA NA NA ns 0 4.0 ns 4.4 4.7 5.0 ns 4.0 4.4 4.7 5.0 ns Clock to Counter Address Valid 4.0 4.4 NA NA ns Clock to Mask Register Readback Valid 4.0 4.4 NA NA ns 1.0 0 ns 1.0 1.0 1.0 4.7 1.0 4.7 1.0 ns 5.0 ns 5.0 ns Port to Port Delays tCCS Clock to Clock Skew 5.2 6.0 6.0 8.0 ns 7.0 7.5 7.5 10 ns Master Reset Timing tRS Master Reset Pulse Width tRS Master Reset Set-up Time 6.0 6.0 6.0 8.5 ns tRSR Master Reset Recovery Time 6.0 7.5 7.5 10 ns tRSF Master Reset to Outputs Inactive 10.0 10.0 10.0 10.0 ns tRSCNTINT Master Reset to Counter Interrupt Flag Reset Time 10.0 10.0 NA NA ns Notes: 27. This parameter is guaranteed by design, but it is not production tested. 28. Test conditions used are Load 2. Document #: 38-06059 Rev. *Q Page 14 of 28 [+] Feedback CY7C0837AV CY7C0830AV/CY7C0831AV CY7C0832AV/CY7C0833AV JTAG Timing and Switching Waveforms CY7C0837AV/CY7C0830AV CY7C0831AV/CY7C0832AV CY7C0833AV Parameter Description Min. Max. Unit 10 MHz fJTAG Maximum JTAG TAP Controller Frequency tTCYC TCK Clock Cycle Time 100 ns tTH TCK Clock HIGH Time 40 ns tTL TCK Clock LOW Time 40 ns tTMSS TMS Set-up to TCK Clock Rise 10 ns tTMSH TMS Hold After TCK Clock Rise 10 ns tTDIS TDI Set-up to TCK Clock Rise 10 ns tTDIH TDI Hold After TCK Clock Rise 10 tTDOV TCK Clock LOW to TDO Valid tTDOX TCK Clock LOW to TDO Invalid 0 tTH Test Clock TCK ns 30 tTMSS ns ns tTL tTCYC tTMSH Test Mode Select TMS tTDIS tTDIH Test Data-In TDI Test Data-Out TDO tTDOX tTDOV Document #: 38-06059 Rev. *Q Page 15 of 28 [+] Feedback CY7C0837AV CY7C0830AV/CY7C0831AV CY7C0832AV/CY7C0833AV Switching Waveforms Master Reset tRS MRST tRSF ALL ADDRESS/ DATA LINES tRSS ALL OTHER INPUTS tRSR INACTIVE ACTIVE TMS CNTINT INT TDO Read Cycle[11, 29, 30, 31, 32] tCH2 tCYC2 tCL2 CLK CE tSC tHC tSB tHB tSW tSA tHW tHA tSC tHC BE0–BE1 R/W ADDRESS An DATAOUT An+1 1 Latency An+2 tDC tCD2 Qn tCKLZ An+3 Qn+1 tOHZ Qn+2 tOLZ OE tOE Notes: 29. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge. 30. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH. 31. The output is disabled (high-impedance state) by CE = VIH following the next rising edge of the clock. 32. Addresses do not have to be accessed sequentially since ADS = CNTEN = VIL with CNT/MSK = VIH constantly loads the address on the rising edge of the CLK. Numbers are for reference only. Document #: 38-06059 Rev. *Q Page 16 of 28 [+] Feedback CY7C0837AV CY7C0830AV/CY7C0831AV CY7C0832AV/CY7C0833AV Switching Waveforms (continued) Bank Select Read[33, 34] tCH2 tCYC2 tCL2 CLK tHA tSA ADDRESS(B1) A0 A1 A3 A2 A4 A5 tHC tSC CE(B1) tCD2 tHC tSC tCD2 tHA tSA A0 ADDRESS(B2) tDC A1 tCKHZ Q3 Q1 Q0 DATAOUT(B1) tCD2 tCKHZ tDC tCKLZ A3 A2 A4 A5 tHC tSC CE(B2) tSC tCD2 tHC DATAOUT(B2) tCKHZ tCD2 Q4 Q2 tCKLZ tCKLZ Read-to-Write-to-Read (OE = LOW)[32, 35, 36, 37, 38] tCH2 tCYC2 tCL2 CLK CE tSC tHC tSW tHW R/W tSW tHW An ADDRESS tSA An+1 An+2 An+3 An+4 tSD tHD tHA DATAIN An+2 tCD2 tCKHZ Dn+2 tCD2 Qn DATAOUT Qn+3 tCKLZ READ NO OPERATION WRITE READ Notes: 33. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress FLEx18 device from this data sheet. ADDRESS(B1) = ADDRESS(B2). 34. ADS = CNTEN= BE0 – BE1 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH. 35. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals. 36. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. 37. CE0 = OE = BE0 – BE1 = LOW; CE1 = R/W = CNTRST = MRST = HIGH. 38. CE0 = BE0 – BE1 = R/W = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK. Document #: 38-06059 Rev. *Q Page 17 of 28 [+] Feedback CY7C0837AV CY7C0830AV/CY7C0831AV CY7C0832AV/CY7C0833AV Switching Waveforms (continued) Read-to-Write-to-Read (OE Controlled)[32, 35, 37, 38] tCH2 tCYC2 tCL2 CLK CE tSC tHC tSW tHW R/W ADDRESS tSW tHW An tSA An+1 An+2 tHA An+3 An+4 An+5 tSD tHD Dn+2 DATAIN Dn+3 tCD2 DATAOUT tCD2 Qn Qn+4 tOHZ OE READ Read with Address Counter tCH2 WRITE READ Advance[37] tCYC2 tCL2 CLK tSA ADDRESS tHA An tSAD tHAD ADS tSAD tHAD tSCN tHCN CNTEN tSCN DATAOUT tHCN Qx–1 READ EXTERNAL ADDRESS Document #: 38-06059 Rev. *Q tCD2 Qx tDC Qn READ WITH COUNTER Qn+1 COUNTER HOLD Qn+2 Qn+3 READ WITH COUNTER Page 18 of 28 [+] Feedback CY7C0837AV CY7C0830AV/CY7C0831AV CY7C0832AV/CY7C0833AV Switching Waveforms (continued) Write with Address Counter Advance[38] tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS INTERNAL ADDRESS An tSAD tHAD tSCN tHCN An+1 An+2 An+3 An+4 ADS CNTEN Dn DATAIN tSD tHD WRITE EXTERNAL ADDRESS Document #: 38-06059 Rev. *Q Dn+1 Dn+1 WRITE WITH COUNTER Dn+2 WRITE COUNTER HOLD Dn+3 Dn+4 WRITE WITH COUNTER Page 19 of 28 [+] Feedback CY7C0837AV CY7C0830AV/CY7C0831AV CY7C0832AV/CY7C0833AV Switching Waveforms (continued) Counter Reset[39, 40] tCYC2 tCH2 tCL2 CLK tSA INTERNAL ADDRESS Ax tSW tHW tSD tHD An 1 0 Ap Am An ADDRESS tHA Ap Am R/W ADS CNTEN tSRST tHRST CNTRST DATAIN D0 tCD2 tCD2 [41] DATAOUT Q0 COUNTER RESET WRITE ADDRESS 0 tCKLZ READ ADDRESS 0 READ ADDRESS 1 Qn Q1 READ ADDRESS An READ ADDRESS Am Notes: 39. CE0 = BE0 – BE1 = LOW; CE1 = MRST = CNT/MSK = HIGH. 40. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset. 41. Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value. Document #: 38-06059 Rev. *Q Page 20 of 28 [+] Feedback CY7C0837AV CY7C0830AV/CY7C0831AV CY7C0832AV/CY7C0833AV Switching Waveforms (continued) Readback State of Address Counter or Mask Register[42, 43, 44, 45] tCYC2 tCH2 tCL2 CLK tCA2 or tCM2 tSA tHA EXTERNAL ADDRESS A0–A16 An* An INTERNAL ADDRESS An+1 An An+2 An+3 An+4 tSAD tHAD ADS tSCN tHCN CNTEN tCD2 DATAOUT Qx-1 Qn READBACK COUNTER INTERNAL ADDRESS INCREMENT Qx-2 LOAD EXTERNAL ADDRESS tCKHZ tCKLZ Qn+1 Qn+2 Qn+3 Notes: 42. CE0 = OE = BE0 – BE1 = LOW; CE1 = R/W = CNTRST = MRST = HIGH. 43. Address in output mode. Host must not be driving address bus after tCKLZ in next clock cycle. 44. Address in input mode. Host can drive address bus after tCKHZ. 45. An * is the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines. Document #: 38-06059 Rev. *Q Page 21 of 28 [+] Feedback CY7C0837AV CY7C0830AV/CY7C0831AV CY7C0832AV/CY7C0833AV Switching Waveforms (continued) Left_Port (L_Port) Write to Right_Port (R_Port) Read[46, 47, 48] tCH2 tCYC2 tCL2 CLKL tHA tSA L_PORT ADDRESS An tSW tHW R/WL tCKHZ tSD L_PORT tCKLZ Dn DATAIN CLKR tHD tCYC2 tCL2 tCCS tCH2 R_PORT ADDRESS tSA tHA An R/WR tCD2 R_PORT Qn DATAOUT tDC Notes: 46. CE0 = OE = ADS = CNTEN = BE0 – BE1 = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. 47. This timing is valid when one port is writing, and other port is reading the same location at the same time. If tCCS is violated, indeterminate data will be Read out. 48. If tCCS < minimum specified value, then R_Port will Read the most recent data (written by L_Port) only (2 * tCYC2 + tCD2) after the rising edge of R_Port's clock. If tCCS > minimum specified value, then R_Port will Read the most recent data (written by L_Port) (tCYC2 + tCD2) after the rising edge of R_Port's clock. Document #: 38-06059 Rev. *Q Page 22 of 28 [+] Feedback CY7C0837AV CY7C0830AV/CY7C0831AV CY7C0832AV/CY7C0833AV Switching Waveforms (continued) Counter Interrupt and Retransmit[14, 41, 49, 50, 51, 52] tCH2 tCYC2 tCL2 CLK tSCM tHCM CNT/MSK ADS CNTEN COUNTER INTERNAL ADDRESS 3FFFC 3FFFD 3FFFE tSCINT 3FFFF Last_Loaded Last_Loaded +1 tRCINT CNTINT Notes: 49. CE0 = OE = BE0 – BE1 = LOW; CE1 = R/W = CNTRST = MRST = HIGH. 50. CNTINT is always driven. 51. CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value. 52. The mask register assumed to have the value of 3FFFFh. Document #: 38-06059 Rev. *Q Page 23 of 28 [+] Feedback CY7C0837AV CY7C0830AV/CY7C0831AV CY7C0832AV/CY7C0833AV Switching Waveforms (continued) MailBox Interrupt Timing[53, 54, 55, 56, 57] tCH2 tCYC2 tCL2 CLKL tSA L_PORT ADDRESS tHA 7FFFF An+1 An An+2 An+3 tSINT tRINT INTR tCH2 tCYC2 tCL2 CLKR tSA R_PORT ADDRESS tHA Am+1 Am 7FFFF Am+3 Am+4 Table 7. Read/Write and Enable Operation (Any Port)[1, 16, 58, 59, 60] Inputs OE CE0 CE1 R/W DQ0 – DQ17 X H X X High-Z Deselected X X L X High-Z Deselected X L H L DIN Write L L H H DOUT Read L H X High-Z Outputs Disabled H CLK Outputs X Operation Notes: 53. CE0 = OE = ADS = CNTEN = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. 54. Address “7FFFF” is the mailbox location for R_Port of the 9Mb device. 55. L_Port is configured for Write operation, and R_Port is configured for Read operation. 56. At least one byte enable (BE0 – BE1) is required to be active during interrupt operations. 57. Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock. 58. OE is an asynchronous input signal. 59. When CE changes state, deselection and Read happen after one cycle of latency. 60. CE0 = OE = LOW; CE1 = R/W = HIGH. Document #: 38-06059 Rev. *Q Page 24 of 28 [+] Feedback CY7C0837AV CY7C0830AV/CY7C0831AV CY7C0832AV/CY7C0833AV Ordering Information 512K × 18 (9-Mbit) 3.3V Synchronous CY7C0833AV Dual-Port SRAM Speed (MHz) Ordering Code 133 CY7C0833AV-133BBC 100 CY7C0833AV-100BBI Package Name Package Type Operating Range BB144 144-ball Leaded Ball Grid Array 13 mm × 13 mm with 1.0-mm pitch Commercial CY7C0833AV-133BBI BB144 144-ball Leaded Ball Grid Array 13 mm × 13 mm with 1.0-mm pitch Industrial CY7C0833AV-100BBC BB144 144-ball Leaded Ball Grid Array 13 mm × 13 mm with 1.0-mm pitch Commercial BB144 144-ball Leaded Ball Grid Array 13 mm × 13 mm with 1.0-mm pitch Industrial 256K × 18 (4-Mbit) 3.3V Synchronous CY7C0832AV Dual-Port SRAM Speed (MHz) 167 Ordering Code CY7C0832AV-167BBC Package Name BB144 A120 Package Type Operating Range 144-ball Leaded Ball Grid Array 13 mm × 13 mm with 1.0-mm pitch Commercial 167 CY7C0832AV-167AC 133 CY7C0832AV-133BBC BB144 144-ball Leaded Ball Grid Array 13 mm × 13 mm with 1.0-mm pitch Commercial CY7C0832AV-133BBI BB144 144-ball Leaded Ball Grid Array 13 mm × 13 mm with 1.0-mm pitch Industrial 133 CY7C0832AV-133AC A120 120-pin Leaded Thin Quad Flat Pack 14 mm x 14 mm Commercial CY7C0832AV-133AI A120 120-pin Leaded Thin Quad Flat Pack 14 mm x 14 mm Industrial 120-pin Leaded Thin Quad Flat Pack 14 mm x 14 mm Commercial 128K × 18 (2-Mbit) 3.3V Synchronous CY7C0831AV Dual-Port SRAM Speed (MHz) Ordering Code Package Name Operating Range 167 CY7C0831AV-167BBC 167 CY7C0831AV-167AC 133 CY7C0831AV-133BBC BB144 144-ball Leaded Ball Grid Array 13 mm × 13 mm with 1.0-mm pitch Commercial CY7C0831AV-133BBXC BW144 144-ball Lead(Pb)-Free Ball Grid Array 13 mm × 13 mm with 1.0-mm pitch CY7C0831AV-133BBI BB144 144-ball Leaded Ball Grid Array 13 mm × 13 mm with 1.0-mm pitch Industrial CY7C0831AV-133BBXI BW144 144-ball Lead(Pb)-Free Ball Grid Array 13 mm × 13 mm with 1.0-mm pitch Industrial 120-pin Leaded Thin Quad Flat Pack 14 mm x 14 mm Commercial 120-pin Lead(Pb)-Free Thin Quad Flat Pack 14 mm x 14 mm Commercial 120-pin Leaded Thin Quad Flat Pack 14 mm x 14 mm Industrial 133 CY7C0831AV-133AC CY7C0831AV-133AXC CY7C0831AV-133AI BB144 Package Type A120 A120 AZ0AE A120 144-ball Leaded Ball Grid Array 13 mm × 13 mm with 1.0-mm pitch Commercial 120-pin Leaded Thin Quad Flat Pack 14 mm x 14 mm Commercial Commercial 64K × 18 (1-Mbit) 3.3V Synchronous CY7C0830AV Dual-Port SRAM Speed (MHz) 167 Ordering Code CY7C0830AV-167BBC Package Name BB144 A120 Package Type Operating Range 144-ball Leaded Ball Grid Array 13 mm × 13 mm with 1.0-mm pitch Commercial 167 CY7C0830AV-167AC 133 CY7C0830AV-133BBC BB144 144-ball Leaded Ball Grid Array 13 mm × 13 mm with 1.0-mm pitch Commercial CY7C0830AV-133BBI BB144 144-ball Leaded Ball Grid Array 13 mm × 13 mm with 1.0-mm pitch Industrial 133 CY7C0830AV-133AC A120 120-pin Leaded Thin Quad Flat Pack 14 mm x 14 mm Commercial CY7C0830AV-133AI A120 120-pin Leaded Thin Quad Flat Pack 14 mm x 14 mm Industrial 120-pin Leaded Thin Quad Flat Pack 14 mm x 14 mm Commercial 32K × 18 (512-Kbit) 3.3V Synchronous CY7C0837AV Dual-Port SRAM Speed (MHz) Ordering Code Package Name Package Type Operating Range 167 CY7C0837AV-167BBC BB144 144-ball Leaded Ball Grid Array 13 mm × 13 mm with 1.0-mm pitch Commercial 133 CY7C0837AV-133BBC BB144 144-ball Leaded Ball Grid Array 13 mm × 13 mm with 1.0-mm pitch Commercial CY7C0837AV-133BBI BB144 144-ball Leaded Ball Grid Array 13 mm × 13 mm with 1.0-mm pitch Industrial Document #: 38-06059 Rev. *Q Page 25 of 28 [+] Feedback CY7C0837AV CY7C0830AV/CY7C0831AV CY7C0832AV/CY7C0833AV Package Diagrams TOP VIEW 144 Leaded FBGA (13 x 13 x 1.6 mm) BB144 144 Lead(Pb)-free FBGA (13 x 13 x 1.6 mm) BOTTOM BW144 VIEW Ø0.05 M C Ø0.25 M C A B A1 CORNER +0.10 Ø0.50 (144X) -0.05 2 3 4 5 6 7 8 9 10 11 12 12 11 10 9 8 7 6 5 4 3 2 1 1.00 A B C D E F G H J K L M 5.50 13.00±0.10 13.00±0.10 A 11.00 1 A B C D E F G H J K L M 5.50 A 1.00 13.00±0.10 B 11.00 0.15 C 1.60MAX. 0.70±0.05 // 0.25 C B 0.15(4X) 13.00±0.10 DIMENSIONS IN MILLIMETERS REFERENCE JEDEC: PUBLICATION 95 DESIGN GUIDE 4.14D PKG. WEIGHT: 0.53 gms C Document #: 38-06059 Rev. *Q 0.40±0.05 0.36 SEATING PLANE 51-85141-*B Page 26 of 28 [+] Feedback CY7C0837AV CY7C0830AV/CY7C0831AV CY7C0832AV/CY7C0833AV Package Diagrams (continued) 120-Pin Leaded Thin Quad Flatpack (14 x 14 x 1.4 mm) A120 120-Pin Lead(Pb)-Free Thin Quad Flatpack (14 x 14 x 1.4 mm) AZ0AE 51-85100-** FLEx18 is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-06059 Rev. *Q Page 27 of 28 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C0837AV CY7C0830AV/CY7C0831AV CY7C0832AV/CY7C0833AV Document History Page Document Title: FLEx18™ 3.3V 32K/64K/128K/256K/512K x 18 Synchronous Dual-Port RAM Document Number: 38-06059 Issue Date Orig. of Change 111473 11/27/01 DSG Change from Spec number: 38-01056 to 38-06059 111942 12/21/01 JFU Updated capacitance values Updated switching parameters and ISB3 REV. ECN NO. ** *A Description of Change Updated “Read-to-Write-to-Read (OE Controlled)” waveform Revised static discharge voltage Revised footnote regarding ISB3 *B 113741 04/02/02 KRE Updated Isb values Updated ESD voltage Corrected 0853 pins L3 and L12 *C 114704 04/24/02 KRE Added discussion of Pause/Restart for JTAG boundary scan *D 115336 07/01/02 KRE Revised speed offerings for all densities *E 122307 12/27/02 RBI Power up requirements added to Maximum Ratings Information *F 123636 1/27/03 KRE Revise tcd2, tOE, tOHZ, tCKHZ, tCKLZ for the CY7C0853V to 4.7 ns *G 126053 08/11/03 SPN Separated out 4M and 9M data sheets Updated Isb and ICC values *H 129443 11/03/03 RAZ Updated Isb and ICC values *I 231993 See ECN YDT Removed “A particular port can write to a certain location while another port is reading that location.” from Functional Description. *J 231813 See ECN WWZ Removed x36 devices (CY7C0852/CY7C0851) from this datasheet. Added 0.5M, 1M and 9M x18 devices to it. Changed title to FLEx18 3.3V 32K/64K/128K/256K/512K x18 Synchronous Dual-Port RAM. Changed datasheet to accommodate the removals and additions. Removed general JTAG description. Updated JTAG ID codes for all devices. Added 144FBGA package for all devices. Updated selection guide table and moved to the front page. Updated block diagram to reflect x18 configuration. Added preliminary status back due to the addition of the new devices. *K 311054 See ECN RYQ Minor Change: Correct the revision indicated on the footer. *L 329111 See ECN SPN Updated Marketing part numbers Updated tRSF *M 330561 See ECN RUY Added Byte Select Operation Table *N 375198 See ECN YDT Removed Preliminary status Added ISB5 Changed tRSCNTINT to 10ns *O 391525 See ECN SPN Updated Counter reset section to reflect what is loaded into the mirror register *P 414109 See ECN LIJ Corrected Ordering Codes for 0831 devices in the 133 Mhz speed bin. Added CY7C0833AV-133BBI. *Q 461113 SEE ECN YDT Document #: 38-06059 Rev. *Q Changed VDDIO to VDD (typo) Added lead(Pb)-free parts Corrected typo in DC table Page 28 of 28 [+] Feedback