AD OP270FZ Dual very low noise precision operational amplifier Datasheet

Dual Very Low Noise Precision
Operational Amplifier
OP270
Data Sheet
FUNCTIONAL BLOCK DIAGRAMS
Very low noise density of 5 nV/√Hz at 1 kHz maximum
Excellent input offset voltage of 75 μV maximum
Low offset voltage drift of 1 μV/°C maximum
Very high gain of 1500 V/mV minimum
Outstanding CMR of 106 dB minimum
Slew rate of 2.4 V/μs typical
Gain bandwidth product of 5 MHz typical
Industry-standard 8-lead dual pinout
–IN A
1
16
OUT A
+IN A
2
15
NC
NC 3
14
NC
V–
13
V+
12
NC
4
NC 5
OP270
+IN B
6
11
NC
–IN B
7
10
OUT B
NC 8
9
NC
NC = NO CONNECT
00325-001
FEATURES
OUT A
1
–IN A
2
+IN A
3
V–
4
A
OP270
B
8
V+
7
OUT B
6
–IN B
5
+IN B
00325-002
Figure 1. 16-Lead SOIC
(S-Suffix)
Figure 2. 8-Lead PDIP (P-Suffix)
8-Lead CERDIP
(Z-Suffix)
GENERAL DESCRIPTION
The OP270 is a high performance, monolithic, dual operational
amplifier with exceptionally low voltage noise density (5 nV/√Hz
maximum at 1 kHz). It offers comparable performance to the
industry-standard OP27 from Analog Devices, Inc.
consumption of the dual OP270 is one-third less than two OP27
devices, a significant advantage for power conscious applications.
The OP270 is unity-gain stable with a gain bandwidth product
of 5 MHz and a slew rate of 2.4 V/μs.
The OP270 features an input offset voltage of less than 75 μV
and an offset drift of less than 1 μV/°C, guaranteed over the full
military temperature range. Open-loop gain of the OP270 is more
than 1,500,000 into a 10 kΩ load, ensuring excellent gain accuracy
and linearity, even in high gain applications. The input bias
current is less than 20 nA, which reduces errors due to signal
source resistance. With a common-mode rejection (CMR) of
greater than 106 dB and a power supply rejection ratio (PSRR)
of less than 3.2 μV/V, the OP270 significantly reduces errors
due to ground noise and power supply fluctuations. The power
The OP270 offers excellent amplifier matching, which is
important for applications such as multiple gain blocks, low
noise instrumentation amplifiers, dual buffers, and low noise
active filters.
Rev. F
The OP270 conforms to the industry-standard 8-lead CERDIP
and PDIP pinouts.
For higher speed applications, the ADA4004-2 or the AD8676
are recommended. For a quad op amp, see the OP470 data sheet.
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OP270* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
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DOCUMENTATION
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Application Notes
• Symbols and Footprints
• AN-649: Using the Analog Devices Active Filter Design
Tool
DISCUSSIONS
• AN-940: Low Noise Amplifier Selection Guide for Optimal
Noise Performance
View all OP270 EngineerZone Discussions.
Data Sheet
SAMPLE AND BUY
• OP270: Dual Very Low Noise Precision Operational
Amplifier Data Sheet
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TOOLS AND SIMULATIONS
• OP270 SPICE Macro Model
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OP270
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Voltage and Current Noise ........................................................ 12
Functional Block Diagrams ............................................................. 1
Total Noise and Source Resistance ........................................... 12
General Description ......................................................................... 1
Noise Measurements .................................................................. 14
Revision History ............................................................................... 2
Capacitive Load Driving and Power Supply Considerations .... 15
Specifications..................................................................................... 3
Unity-Gain Buffer Applications ............................................... 15
Electrical Specifications ............................................................... 4
Low Phase Error Amplifier ....................................................... 16
Absolute Maximum Ratings............................................................ 5
Five-Band, Low Noise, Stereo Graphic Equalizer .................. 16
ESD Caution .................................................................................. 5
Digital Panning Control ............................................................ 17
Typical Performance Characteristics ............................................. 6
Dual Programmable Gain Amplifier ....................................... 17
Test Circuits ..................................................................................... 11
Outline Dimensions ....................................................................... 19
Applications Information .............................................................. 12
Ordering Guide .......................................................................... 20
REVISION HISTORY
10/15—Rev. E to Rev. F
Changes to General Description Section ...................................... 1
Changes to Supply Voltage Parameter and Differential Input
Voltage Parameter, Table 3 .............................................................. 5
Deleted Table 4; Renumbered Sequentially .................................. 5
2/10—Rev. D to Rev. E
Change to Input Noise Current Density Parameter, Table 1 ...... 3
Change to Figure 18 ......................................................................... 8
2/09—Rev. C to Rev. D
Updated Format .................................................................. Universal
Reorganized Layout ............................................................ Universal
Changes to Figure 7 .......................................................................... 6
Changes to Figure 22 ........................................................................ 9
Deleted Applications Heading ...................................................... 11
Changes to Figure 44 ...................................................................... 17
Changes to Figure 46 ...................................................................... 18
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 20
4/03—Rev. B to Rev. C
Deletion of OP270A model ............................................... Universal
Edits to Features.................................................................................1
Changes to Specifications .................................................................2
Deletion of Wafer Limits and Dice Characteristics ......................4
Changes to Absolute Maximum Ratings ........................................4
Changes to Ordering Guide .............................................................4
Changes to Equations in Noise Measurements section............. 10
Change to Figure 10 ....................................................................... 11
Updated Outline Dimensions ....................................................... 14
11/02—Rev. A to Rev. B
Updated Ordering Guide .............................................................. 15
9/02—Rev. 0 to Rev. A
Edits to Absolute Maximum Ratings ..............................................5
Edits to Ordering Guide ................................................................ 15
2/01—Revision 0: Initial Version
Rev. F | Page 2 of 20
Data Sheet
OP270
SPECIFICATIONS
VS = ±15 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
Input Offset Voltage
Input Offset Current
Input Bias Current
Input Noise Voltage1
Input Noise Voltage Density2
Input Noise Current Density
Large-Signal Voltage Gain
Symbol
VOS
IOS
IB
en p-p
en
en
en
in
in
in
AVO
Input Voltage Range3
Output Voltage Swing
Common-Mode Rejection
Power Supply Rejection
Ratio
Slew Rate
Supply Current
(All Amplifiers)
Gain Bandwidth Product
Channel Separation1
IVR
VO
CMR
PSRR
Input Capacitance
Input Resistance
Differential Mode
Common Mode
Settling Time
CIN
RIN
RINCM
tS
SR
ISY
GBP
CS
Test Conditions
VCM = 0 V
VCM = 0 V
0.1 Hz to 10 Hz
fO = 10 Hz
fO = 100 Hz
fO = 1 kHz
fO = 10 Hz
fO = 100 Hz
fO = 1 kHz
VO = ±10 V,
RL = 10 kΩ
VO = ±10 V,
RL = 2 kΩ
RL ≥ 2 kΩ
VCM = ±11 V
VS = ±4.5 V
to ±18 V
OP270E
Typ
10
1
5
80
3.6
3.2
3.2
1.1
0.7
0.6
1500 2300
Min
Max
150
15
40
200
6.5
5.5
5.0
OP270G
Typ
50
5
15
80
3.6
3.2
3.2
1.1
0.7
0.6
750 1500
Min
Max
250
20
60
Unit
μV
nA
nA
nV p-p
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
pA/√Hz
pA/√Hz
V/mV
1200
500
900
350
700
V/mV
±12
±12
106
±12.5
±13.5
125
0.56
±12
±12
100
±12
±12
90
3.2
±12.5
±13.5
120
1.0
5.6
±12.5
±13.5
110
1.5
5.6
V
V
dB
μV/V
2.4
4
6.5
2.4
4
6.5
2.4
4
6.5
V/μs
mA
1.7
AV = +1, 10 V,
step to 0.01%
OP270F
Typ
20
3
10
80
3.6
3.2
3.2
1.1
0.7
0.6
1000 1700
Min
750
No load
VO = ±20 V p-p,
fO = 10 Hz
Max
75
10
20
200
6.5
5.5
5.0
125
5
175
1.7
1.7
5
175
5
175
MHz
dB
3
3
3
pF
0.4
20
5
0.4
20
5
0.4
20
5
MΩ
GΩ
μs
1
Guaranteed but not 100% tested.
Sample tested.
3
Guaranteed by CMR test.
2
Rev. F | Page 3 of 20
125
OP270
Data Sheet
ELECTRICAL SPECIFICATIONS
VS = ±15 V, −40°C ≤ TA ≤ 85°C, unless otherwise noted.
Table 2.
Parameter
Input Offset Voltage
Average Input Offset
Voltage Drift
Input Offset Current
Input Bias Voltage
Large-Signal Voltage Gain
Symbol
VOS
TCVOS
Test Conditions
IOS
IB
AVO
VCM = 0 V
VCM = 0 V
VO = ±10 V,
RL = 10 kΩ
VO = ±10 V,
RL = 2 kΩ
AVO
Input Voltage Range1
Output Voltage Swing
Common-Mode Rejection
Power Supply Rejection
Ratio
Supply Current
(All Amplifiers)
1
IVR
VO
CMR
PSRR
RL ≥ 2 kΩ
VCM = ±11 V
VS = ±4.5 V to ±18 V
ISY
No load
Min
OP270E
Typ
Max
25
150
0.2
1
1000
1.5
6
1800
500
±12
±12
100
Min
30
60
OP270F
Typ
Max
45
275
0.4
2
600
5
15
1400
900
300
±12.5
±13.5
120
0.7
±12
±12
94
4.4
Min
400
700
225
670
V/mV
±12
±12
90
5.6
±12.5
±13.5
115
1.8
10
±12.5
±13.5
100
2.0
1.5
V
V
dB
μV/V
7.2
4.4
7.2
4.4
7.2
mA
Rev. F | Page 4 of 20
50
80
Unit
μV
μV/°C
15
19
1250
Guaranteed by CMR test.
40
70
OP270G
Typ
Max
100
400
0.7
3
nA
nA
V/mV
Data Sheet
OP270
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage
Differential Input Voltage1
Differential Input Current1
Input Voltage
Output Short-Circuit Duration
Storage Temperature Range
Lead Temperature Range (Soldering, 60 sec)
Junction Temperature (TJ)
Operating Temperature Range
1
Rating
±18 V
±1.0 V
±25 mA
Supply voltage
Continuous
−65°C to +150°C
300°C
−65°C to +150°C
−40°C to +85°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
The OP270 inputs are protected by back-to-back diodes. To achieve low noise
performance, current-limiting resistors are not used. If the differential voltage
exceeds +10 V, the input current should be limited to ±25 mA.
Rev. F | Page 5 of 20
OP270
Data Sheet
10
CURRENT NOISE DENSITY (pA/√Hz)
TA = 25°C
VS = ±15V
5
4
3
1/f CORNER = 5Hz
2
1
1
10
100
TA = 25°C
VS = ±15V
1
1/f CORNER = 200Hz
00352-007
10
9
8
7
6
00352-004
VOLTAGE NOISE DENSITY (nV/√Hz)
TYPICAL PERFORMANCE CHARACTERISTICS
0.1
10
1k
100
FREQUENCY (Hz)
Figure 3. Voltage Noise Density vs. Frequency
10k
Figure 6. Current Noise Density vs. Frequency
40
TA = 25°C
VS = ±15V
30
4
20
VOLTAGE (µV)
AT 10kHz
AT 1kHz
3
0
–20
0
±5
±10
±15
–30
–75
±20
00352-008
1
10
–10
2
00352-005
VOLTAGE NOISE DENSITY (nV/√Hz)
5
1k
FREQUENCY (Hz)
–50
–25
SUPPLY VOLTAGE (V)
Figure 4. Voltage Noise Density vs. Supply Voltage
25
50
75
100
125
Figure 7. Input Offset Voltage vs. Temperature
5
00352-006
TA = 25°C
VS = ±15V
4
3
2
1
0
00352-009
NOISE VOLTAGE (100nV/DIV)
CHANGE IN OFFSET VOLTAGE (µA)
0.1Hz TO 10Hz NOISE
TA = 25°C
TS = ±15V
0
TEMPERATURE (°C)
0
1
2
3
4
TIME (Minutes)
TIME (1 sec/DIV)
Figure 8. Warm-Up Offset Voltage Drift
Figure 5. 0.1 Hz to 10 Hz Input Voltage Noise
Rev. F | Page 6 of 20
5
Data Sheet
7
OP270
130
VS = ±15V
VCM = 0V
110
6
100
90
5
CMR (dB)
4
80
70
60
50
40
3
2
–75
00352-010
30
–50
–25
0
25
50
75
100
00352-013
INPUT BIAS CURRENT (nA)
TA = 25°C
VS = ±15V
120
20
10
125
1
10
100
TEMPERATURE (°C)
Figure 9. Input Bias Current vs. Temperature
3
2
1
–25
0
25
50
75
100
5
4
+125°C
+25°C
2
125
–55°C
3
0
±5
TEMPERATURE (°C)
8
TOTAL SUPPLY CURRENT (mA)
4
3
–7.5
VS = ±15V
–5.0
–2.5
0
2.5
5.0
7.5
10.0
6
5
4
3
2
0
–75
12.5
00352-015
1
00352-012
INPUT BIAS CURRENT (nA)
5
–10.0
±20
7
6
2
±15
Figure 13. Total Supply Current vs. Supply Voltage
TA = +25°C
VS = ±15V
–12.5
±10
SUPPLY VOLTAGE (V)
Figure 10. Input Offset Current vs. Temperature
7
1M
00352-014
TOTAL SUPPLY CURRENT (mA)
4
–50
100k
6
VS = ±15V
VCM = 0V
0
–75
10k
Figure 12. CMR vs. Frequency
00352-011
INPUT OFFSET CURRENT (nA)
5
1k
FREQUENCY (Hz)
–50
–25
0
25
50
75
100
TEMPERATURE (°C)
COMMON-MODE VOLTAGE (V)
Figure 11. Input Bias Current vs. Common-Mode Voltage
Figure 14. Total Supply Current vs. Temperature
Rev. F | Page 7 of 20
125
Data Sheet
140
25
TA = 25°C
120
80
TA = 25°C
VS = ±15V
20
PHASE SHIFT (Degrees)
OP270
100
PHASE
+PSR
60
40
0
10
1
10
100
1k
10k
100k
1M
10M
140
PHASE
MARGIN = 62°
160
5
GAIN
180
0
–5
00352-016
20
120
–10
100M
1
2
FREQUENCY (Hz)
3
4
5
6
7
8
00352-019
–PSR
80
15
OPEN-LOOP GAIN (dB)
PSR (dB)
100
9 10
FREQUENCY (MHz)
Figure 15. PSR vs. Frequency
Figure 18. Open-Loop Gain and Phase Shift vs. Frequency
140
5000
TA = 25°C
VS = ±15V
120
OPEN-LOOP GAIN (V/mA)
OPEN-LOOP GAIN (dB)
4000
100
80
60
40
3000
2000
00352-017
10
100
1k
10k
100k
1M
10M
0
100M
0
±5
±10
FREQUENCY (Hz)
±15
±20
±25
SUPPLY VOLTAGE (V)
Figure 16. Open-Loop Gain vs. Frequency
80
Figure 19. Open-Loop Gain vs. Supply Voltage
80
TA = 25°C
VS = ±15V
8
PHASE MARGIN (Degrees)
40
20
70
7
Ф
60
6
5
GBP
50
0
–20
1k
00352-018
CLOSED-LOOP GAIN (dB)
60
10k
100k
1M
4
40
–75
10M
FREQUENCY (Hz)
Figure 17. Closed-Loop Gain vs. Frequency
GAIN BANDWIDTH PRODUCT (MHz)
1
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
150
00352-021
0
00352-020
1000
20
Figure 20. Phase Margin and Gain Bandwidth Product vs. Temperature
Rev. F | Page 8 of 20
Data Sheet
OP270
OUTPUT IMPEDANCE (Ω)
24
20
16
12
8
00352-022
4
0
1k
10k
100k
1M
TA = 25°C
VS = ±15V
AV = 1
75
50
AV = 10
AV = 100
25
0
1k
10M
10k
FREQUENCY (Hz)
Figure 21. Maximum Output Swing vs. Frequency
15
SLEW RATE (V/µs)
12
NEGATIVE
SWING
10
9
8
VS = ±15V
2.6
2.5
–SR
2.4
+SR
7
5
100
1k
2.2
–75
10k
00352-026
2.3
6
–50
LOAD RESISTANCE (Ω)
75
100
125
CHANNEL SEPARATION (dB)
170
20
10
160
150
140
130
120
110
100
90
200
50
180
30
0
25
190
TA = 25°C
VS = ±15V
VIN = 100mV
AV = +1
40
0
Figure 25. Slew Rate vs. Temperature
00352-024
SMALL-SIGNAL OVERSHOOT (%)
50
–25
TEMPERATURE (°C)
Figure 22. Maximum Output Voltage vs. Load Resistance
0
10M
2.7
13
00352-023
MAXIMUM OUTPUT VOLTAGE (V)
POSITIVE
SWING
11
1M
Figure 24. Output Impedance vs. Frequency
2.8
TA = 25°C
VS = ±15V
14
100k
FREQUENCY (Hz)
400
600
800
TA = 25°C
VS = ±15V
VO = 20V p-p TO 10kHz
80
70
1000
CAPACITIVE LOAD (pF)
1
10
100
00352-027
MAXIMUM OUTPUT SWING (V)
100
TA = 25°C
VS = ±15V
THD = 1%
00352-025
28
1k
10k
100k
FREQUENCY (Hz)
Figure 23. Small-Signal Overshoot vs. Capacitive Load
Figure 26. Channel Separation vs. Frequency
Rev. F | Page 9 of 20
1M
OP270
TA = 25°C
VS = ±15V
AV = +1
RL = 2kΩ
TA = 25°C
VS = ±15V
VO = 20V p-p
RL = 2kΩ
AV = 10
0.01
0.001
10
100
1k
50mV
200ns
10k
FREQUENCY (Hz)
Figure 29. Small-Signal Transient Response
Figure 27. Total Harmonic Distortion vs. Frequency
TA = 25°C
VS = ±15V
AV = +1
RL = 2kΩ
5V
20µs
Figure 28. Large-Signal Transient Response
Rev. F | Page 10 of 20
00352-030
00352-028
AV = 1
00352-029
TOTAL HARMONIC DISTORTION (%)
0.1
Data Sheet
Data Sheet
OP270
TEST CIRCUITS
5kΩ
500Ω
1/2
OP270
V1 20Vp-p
5kΩ
50Ω
1/2
OP270
CHANNEL SEPARATION = 20 LOG
Figure 30. Channel Separation Test Circuit
+18V
8
100kΩ
2
3
1/2
OP270
1
1/2
OP270
7
200kΩ
6
5
4
–18V
Figure 31. Burn-In Circuit
Rev. F | Page 11 of 20
00325-032
100kΩ
V1
V2/1000
00325-031
V2
OP270
Data Sheet
APPLICATIONS INFORMATION
The OP270 is a very low noise dual op amp, exhibiting a typical
voltage noise density of only 3.2 nV/√Hz at 1 kHz. Because the
voltage noise is inversely proportional to the square root of the
collector current, the exceptionally low noise characteristic of
the OP270 is achieved in part by operating the input transistors
at high collector currents. Current noise, however, is directly
proportional to the square root of the collector current. As a
result, the outstanding voltage noise density performance of the
OP270 is gained at the expense of current noise performance,
which is normal for low noise amplifiers.
Figure 33 also shows the relationship between total noise and
source resistance, but at 10 Hz. Total noise increases more
quickly than shown in Figure 32 because current noise is
inversely proportional to the square root of frequency. In
Figure 33, the current noise of the OP270 dominates the total
noise when RS is greater than 5 kΩ.
Figure 32 and Figure 33 show that to reduce total noise, source
resistance must be kept to a minimum. In applications with a
high source resistance, the OP200, with lower current noise
than the OP270, can provide lower total noise.
100
TOTAL NOISE (nV/√Hz)
To obtain the best noise performance in a circuit, it is vital to
understand the relationships among voltage noise (en), current
noise (in), and resistor noise (et).
TOTAL NOISE AND SOURCE RESISTANCE
The total noise of an op amp can be calculated by
E n  (e n ) 2  (i n R s ) 2  (e t ) 2
where:
En is the total input-referred noise.
en is the op amp voltage noise.
in is the op amp current noise.
et is the source resistance thermal noise.
RS is the source resistance.
OP270
RESISTOR
NOISE ONLY
1
100
1k
10k
Figure 33. Total Noise vs. Source Resistance
(Including Resistor Noise) at 10 Hz
Figure 34 shows peak-to-peak noise vs. source resistance over
the 0.1 Hz to 10 Hz range. At low values of RS, the voltage noise
of the OP270 is the major contributor to peak-to-peak noise,
with current noise becoming the major contributor as RS
increases. The crossover point between the OP270 and the
OP200 for peak-to-peak noise is at a source resistance of 17 kΩ.
1k
OP200
PEAK-TO-PEAK NOISE (nV)
100
OP200
10
100
OP270
RESISTOR
NOISE ONLY
00352-035
Figure 32 shows the relationship between total noise at 1 kHz
and source resistance. When RS is less than 1 kΩ, the total noise
is dominated by the voltage noise of the OP270. As RS rises
above 1 kΩ, total noise increases and is dominated by resistor
noise rather than by the voltage or current noise of the OP270.
When RS exceeds 20 kΩ, the current noise of the OP270
becomes the major contributor to total noise.
OP270
00352-033
10
100
RESISTOR
NOISE ONLY
1
100
1k
100k
SOURCE RESISTANCE (Ω)
The total noise is referred to the input and at the output is
amplified by the circuit gain.
TOTAL NOISE (nV/√Hz)
OP200
10
00352-034
VOLTAGE AND CURRENT NOISE
10k
100k
1k
10k
100k
SOURCE RESISTANCE (Ω)
Figure 34. Peak-to-Peak Noise (0.1 Hz to 10 Hz) vs. Source Resistance
(Including Resistor Noise)
SOURCE RESISTANCE (Ω)
Figure 32. Total Noise vs. Source Resistance
(Including Resistor Noise) at 1 kHz
Rev. F | Page 12 of 20
Data Sheet
OP270
For reference, typical source resistances of some signal sources are listed in Table 4.
Table 4. Typical Source Resistances
Device
Strain Gage
Magnetic Tapehead, Microphone
Source Impedance
<500 Ω
<1500 Ω
Magnetic Phonograph Cartridge
<1500 Ω
Linear Variable Differential Transformer
<1500 Ω
Comments
Typically used in low frequency applications.
Low IB is very important to reduce self-magnetization problems when
direct coupling is used. OP270 IB can be disregarded.
Low IB is important to reduce self-magnetization problems in direct-coupled
applications. OP270 does not introduce any self-magnetization problems.
Used in rugged servo-feedback applications. The bandwidth of interest is
400 Hz to 5 kHz.
R3
1.24kΩ
R1
5Ω
OP270
DUT
C1
2µF
C4
0.22µF
OP27E
R5
909Ω
R6
600Ω
R4
200Ω
D1, D2
1N4148
OP27E
R10
65.4kΩ
R9
306Ω
R8
10kΩ
C2
0.032µF
R11
65.4kΩ
OP42E
C3
0.22µF
R13
5.9kΩ
R12
10kΩ
Figure 35. Peak-to-Peak Voltage Noise Test Circuit (0.1 Hz to 10 Hz)
Rev. F | Page 13 of 20
R14
4.99kΩ
eOUT
C5
1µF
GAIN = 50,000
VS = ±15V
00325-036
R2
5Ω
OP270
Data Sheet
NOISE MEASUREMENTS
Noise Measurement—Noise Voltage Density
Peak-to-Peak Voltage Noise
The circuit of Figure 37 shows a quick and reliable method for
measuring the noise voltage density of dual op amps. The first
amplifier is in unity gain, with the final amplifier in a noninverting
gain of 101. Because the noise voltages of the amplifiers are
uncorrelated, they add in rms to yield
The device has to be warmed up for at least five minutes.
As shown in the warm-up drift curve (see Figure 8), the
offset voltage typically changes 2 μV due to increasing chip
temperature after power-up. In the 10 sec measurement
interval, these temperature-induced effects can exceed tens
of nanovolts.

For similar reasons, the device has to be well shielded from
air currents. Shielding also minimizes thermocouple effects.

Sudden motion in the vicinity of the device can also feed
through to increase the observed noise.

The test time to measure noise of 0.1 Hz to 10 Hz should
not exceed 10 sec. As shown in the noise-tester frequency
response curve of Figure 36, the 0.1 Hz corner is defined by
only one pole. The test time of 10 sec acts as an additional
pole to eliminate noise contribution from the frequency
band below 0.1 Hz.
Power should be supplied to the test circuit by well bypassed
low noise supplies, such as batteries. Such supplies will minimize output noise introduced via the amplifier supply pins.
100
 e
nA
2  e nB 2 
The OP270 is a monolithic device with two identical amplifiers.
Therefore, the noise voltage densities of the amplifiers match,
giving



e OUT  101 2e n 2  101 2e n
R1
100Ω

R2
10kΩ
1/2
OP270
1/2
OP270
eOUT
TO SPECTRUM ANALYZER
eOUT (nV/√Hz) ≈ 101 (√2en)
VS = ±15V
Figure 37. Noise Voltage Density Test Circuit
Noise Measurement—Current Noise Density
The test circuit shown in Figure 38 can be used to measure current
noise density. The formula relating the voltage output to the current
noise density is
2

 e nOUT 

  40 nV / Hz
 G 
in 
RS

2
where:
G is a gain of 10,000.
RS = 100 kΩ source resistance.
80
R3
1.24kΩ
R1
5Ω
60
R2
100kΩ
OP270
DUT
40
OP27E
enOUT
TO SPECTRUM ANALYZER
R5
8.06kΩ
20
0
0.01
R4
200Ω
00352-037

A noise voltage density test is recommended when measuring
noise on several units. A 10 Hz noise voltage density measurement correlates well with a 0.1 Hz to 10 Hz peak-to-peak
noise reading because both results are determined by the
white noise and the location of the 1/f corner frequency.
GAIN (dB)

e OUT  101
0.1
1
10
100
GAIN = 10,000
VS = ±15V
Figure 38. Current Noise Density Test Circuit
FREQUENCY (Hz)
Figure 36. 0.1 Hz to 10 Hz Peak-to-Peak Voltage Noise
Test Circuit Frequency Response
Rev. F | Page 14 of 20
00325-039

00325-038
The circuit of Figure 35 is a test setup for measuring peak-topeak voltage noise. To measure the 200 nV peak-to-peak noise
specification of the OP270 in the 0.1 Hz to 10 Hz range, the
following precautions must be observed:
Data Sheet
OP270
CAPACITIVE LOAD DRIVING AND POWER SUPPLY
CONSIDERATIONS
The OP270 is unity-gain stable and capable of driving large
capacitive loads without oscillating. Nonetheless, good supply
bypassing is highly recommended. Proper supply bypassing
reduces problems caused by supply line noise and improves the
capacitive load driving capability of the OP270.
In the standard feedback amplifier, the output resistance of the
op amp combines with the load capacitance to form a low-pass
filter that adds phase shift in the feedback network and reduces
stability. A simple circuit to eliminate this effect is shown in
Figure 39. The components C1 and R3 decouple the amplifier
from the load capacitance and provide additional stability. The
values of C1 and R3 shown in Figure 39 are for a load capacitance
of up to 1000 pF when used with the OP270.
UNITY-GAIN BUFFER APPLICATIONS
When Rf ≤ 100 Ω and the input is driven with a fast, large signal
pulse (>1 V), the output waveform looks like the one in Figure 40.
During the fast feedthrough-like portion of the output, the input
protection diodes effectively short the output to the input, and
a current, limited only by the output short-circuit protection, is
drawn by the signal generator. With Rf ≥ 500 Ω, the output is
capable of handling the current requirements (IL ≤ 20 mA at 10 V);
the amplifier stays in its active mode and a smooth transition occurs.
When Rf > 3 kΩ, a pole created by Rf and the input capacitance
(3 pF) of the amplifier creates additional phase shift and reduces
phase margin. A small capacitor (20 pF to 50 pF) in parallel with
Rf helps eliminate this problem.
Rf
V+
C3
0.1µF
+ C2
10µF
OP270
C1
200pF
R1
OP270
R3
50Ω
Figure 40. Pulsed Operation
VOUT
C1
1000pF
C5
0.1µF
V–
C4
+ 10µF
PLACE SUPPLY DECOUPLING
CAPACITOR AT OP270
00325-040
VIN
00325-041
R2
2.4V/µs
Figure 39. Driving Large Capacitive Loads
Rev. F | Page 15 of 20
OP270
Data Sheet
0
LOW PHASE ERROR AMPLIFIER
The simple amplifier depicted in Figure 41 utilizes a monolithic
dual operational amplifier and a few resistors to substantially
reduce phase error compared with conventional amplifier
designs. At a given gain, the frequency range for a specified
phase accuracy is more than a decade greater than that of a
standard single op amp amplifier.
R2 = R1
R2
K2
1/2
OP270E
A2
V2
SINGLE OP AMP.
CONVENTIONAL DESIGN
–2
–3
CASCADED
(TWO STAGES)
–4
–5
LOW PHASE ERROR
AMPLIFIER
–7
0.001
VIN
1
The graphic equalizer circuit shown in Figure 43 provides 15 dB
of boost or cut over a five-band range. Signal-to-noise ratio over
a 20 kHz bandwidth is better than 100 dB and referred to a 3 V
rms input. Larger inductors can be replaced by active inductors,
but consequently reduces the signal-to-noise ratio.
C1
0.47µF
1/2
OP270E
R2
3.3kΩ
1/2
OP270E
R1
K1
R3
680Ω
VO = (K1 + 1)VIN
00325-042
VO
ASSUME A1 AND A2 ARE MATCHED.
ωT
AO(s) =
s
0.5
FIVE-BAND, LOW NOISE, STEREO GRAPHIC
EQUALIZER
R1
47kΩ
R1
0.01
0.1
0.005
0.05
FREQUENCY RATIO (1/βω)(ω/ωT)
Figure 42. Phase Error Comparison
VIN
1/2
OP270E
A1
00352-043
–6
R5
680Ω
Figure 41. Low Phase Error Amplifier
Figure 42 compares the phase error performance of the low
phase error amplifier with a conventional single op amp
amplifier and a cascaded two-stage amplifier. The low phase
error amplifier shows a much lower phase error, particularly for
frequencies where ω/βωT < 0.1. For example, a phase error of
−0.1° occurs at 0.002 ω/βωT for the single op amp amplifier, but
at 0.11 ω/βωT for the low phase error amplifier.
R7
680Ω
L1
TANTALUM
1H
60Hz
R13
3.3kΩ
R6
1kΩ
C3
1µF
+
L2
TANTALUM
600mH
200Hz
R8
1kΩ
L3
800Hz
180mH
R9
680Ω
C5
0.047µF
+
R10
1kΩ
L4
3kHz
60mH
R11
680Ω
C6
0.022µF
+
R12
1kΩ
L5
10kHz
10mH
Figure 43. Five-Band, Low Noise Graphic Equalizer
Rev. F | Page 16 of 20
VOUT
R4
1kΩ
C2
6.8µF
+
C4
0.22µF
+
R14
100Ω
00325-044
R2
PHASE SHIFT (Degrees)
The low phase error amplifier performs second-order frequency compensation through the response of Op Amp A2 in
the feedback loop of A1. Both op amps must be extremely well
matched in frequency response. At low frequencies, the A1
feedback loop forces V2/(K1 + 1) = VIN. The A2 feedback loop
forces VO/(K1 + 1) = V2/(K1 + 1), yielding an overall transfer
function of VO/VIN = K1 + 1. The dc gain is determined by the
resistor divider at the output, VO, and is not directly affected by
the resistor divider around A2. Note that, like a conventional
single op amp amplifier, the dc gain is set by resistor ratios only.
Minimum gain for the low phase error amplifier is 10.
–1
Data Sheet
OP270
+5V
DIGITAL PANNING CONTROL
+15V
21
Figure 44 uses a DAC8221 (a dual 12-bit CMOS DAC) to pan a
signal between two channels. One channel is formed by the
current output of DAC A driving one-half of an OP270 in a
current-to-voltage converter configuration. The other channel
is formed by the complementary output current of DAC A,
which normally flows to ground through the AGND pin. This
complementary current is converted to a voltage by the other
half of the OP270, which also holds AGND at virtual ground.
VDD
0.01µF
RFBA
3
+
10µF
–
VIN
4 VREF A
DAC A
IOUTA
AGND
2
1
2
3
8
1/2
OP270GP
1
4
DAC DATA BUS
PINS 6 (MSB) TO 17 (LSB)
0.1µF
NC
22 VREF B
DAC B
18
19
20
23
IOUTB
24
–15V
+
10µF
–
6
5
DAC A/DAC B
WRITE
CONTROL
RFBB
OUT
1/2
OP270GP
7
OUT
CS
WR
DGND
5
DUAL PROGRAMMABLE GAIN AMPLIFIER
00325-045
Gain error due to mismatching between the internal DAC
ladder resistors and the current-to-voltage feedback resistors is
eliminated by using feedback resistors internal to the DAC8221.
Only DAC A passes a signal; DAC B provides the second
feedback resistor. With VREFB unconnected, the current-tovoltage converter, using RFBB, is accurate and not influenced by
digital data reaching DAC B. Distortion of the digital panning
control is less than 0.002% over the 20 Hz to 20 kHz audio
range. Figure 45 shows the complementary outputs for a 1 kHz
input signal and a digital ramp applied to the DAC data input.
DAC8221P
Figure 44. Digital Panning Control
The dual OP270 and the DAC8221 (a dual 12-bit CMOS DAC)
can be combined to form a space-saving, dual programmable
amplifier. The digital code present at the DAC, which is easily
set by a microprocessor, determines the ratio between the internal
feedback resistor and the resistance that the DAC ladder presents
to the op amp feedback loop. Gain of each amplifier is
A OUT
VO
4096

V IN
n
If the digital code present at the DAC consists of all 0s, the
feedback loop opens, causing the op amp output to saturate. A
20 MΩ resistor placed in parallel with the DAC feedback loop
eliminates this problem with only a very small reduction in gain
accuracy.
Rev. F | Page 17 of 20
5V
5V
1ms
Figure 45. Digital Panning Control Output
00352-046
A OUT
where n is the decimal equivalent of the 12-bit digital code
present at the DAC.
OP270
Data Sheet
+15V
+5V
0.01µF
21
VDD
DAC8221P
VINA
VREF A 4
RFBA
3
+
10µF
–
20MΩ
DAC A
IOUTA 2
2
8
1/2
OP270EZ
3
1
VOUTA
4
AGND 1
VINB
0.1µF
RFBB
23
–15V
DAC B
IOUTB 24
6
20MΩ
5
1/2
OP270GP
+
10µF
–
7
VOUTB
DAC DATA BUS
PINS 6 (MSB) TO 17 (LSB)
VREF B 22
18
19
20
00325-047
WRITE
CONTROL
DGND
5
Figure 46. Dual Programmable Gain Amplifier
V+
BIAS
OUT
+IN
V–
Figure 47. Simplified Schematic
(One of Two Amplifiers Is Shown)
Rev. F | Page 18 of 20
00325-003
–IN
Data Sheet
OP270
OUTLINE DIMENSIONS
0.005 (0.13)
MIN
8
0.055 (1.40)
MAX
5
0.310 (7.87)
0.220 (5.59)
1
4
0.100 (2.54) BSC
0.320 (8.13)
0.290 (7.37)
0.405 (10.29) MAX
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.070 (1.78)
0.030 (0.76)
SEATING
PLANE
15°
0°
0.015 (0.38)
0.008 (0.20)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 48. 8-Lead Ceramic Dual In-Line Package [CERDIP]
Z-Suffix
(Q-8)
Dimensions shown in inches and (millimeters)
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
5
1
4
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.100 (2.54)
BSC
0.210 (5.33)
MAX
0.060 (1.52)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
0.005 (0.13)
MIN
0.430 (10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 49. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
P-Suffix
(N-8)
Dimensions shown in inches and (millimeters)
Rev. F | Page 19 of 20
070606-A
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
OP270
Data Sheet
10.50 (0.4134)
10.10 (0.3976)
9
16
7.60 (0.2992)
7.40 (0.2913)
8
1.27 (0.0500)
BSC
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
0.51 (0.0201)
0.31 (0.0122)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
0.25 (0.0098)
2.65 (0.1043)
2.35 (0.0925)
SEATING
PLANE
45°
8°
0°
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013- AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
032707-B
1
Figure 50. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
S-Suffix
(RW-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1
OP270EZ
OP270FZ
OP270GP
OP270GPZ
OP270GS
OP270GS-REEL
OP270GSZ
OP270GSZ-REEL
1
2
TA = +25°C
VOS Max (μV)
75
150
250
θJC
(°C/W)
12
12
37
θJA2
(°C/W)
134
134
96
250
27
92
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
8-Lead CERDIP
8-Lead CERDIP
8-Lead PDIP
8-Lead PDIP
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
Package
Option
Q-8 (Z-Suffix)
Q-8 (Z-Suffix)
N-8 (P-Suffix)
N-8 (P-Suffix)
RW-16 (S-Suffix)
RW-16 (S-Suffix)
RW-16 (S-Suffix)
RW-16 (S-Suffix)
The OP270GPZ, OP270GSZ, and OP270GSZ-REEL are RoHS compliant parts.
θJA is specified for worst-case mounting conditions, that is, θJA is specified for device in socket for CERDIP and PDIP packages; θJA is specified for device soldered to
printed circuit board for SOIC package.
©2001–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00325-0-10/15(F)
Rev. F | Page 20 of 20