Freescale Semiconductor Data Sheet: Technical Data MC9S08FL16 Series Covers: MC9S08FL16 and MC9S08FL8 Features: 8-Bit S08 Central Processor Unit (CPU) • Up to 20 MHz CPU at 4.5 V to 5.5 V across temperature range of –40 °C to 85 °C • HC08 instruction set with added BGND instruction • Support for up to 32 interrupt/reset sources On-Chip Memory • Up to 16 KB flash read/program/erase over full operating voltage and temperature • Up to 1024-byte random-access memory (RAM) • Security circuitry to prevent unauthorized access to RAM and flash contents Power-Saving Modes • Two low power stop modes; reduced power wait mode • Allows clocks to remain enabled to specific peripherals in stop3 mode Clock Source Options • Oscillator (XOSC) — Loop-control Pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 39.0625 kHz or 1 MHz to 16 MHz • Internal Clock Source (ICS) — Internal clock source module containing a frequency-locked-loop (FLL) controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supports bus frequencies up to 10 MHz System Protection • Watchdog computer operating properly (COP) reset with option to run from dedicated 1 kHz internal clock source or bus clock • Low-voltage detectionwith reset or interrupt; selectable trip points • Illegal opcode detection with reset Document Number: MC9S08FL16 Rev. 3, 11/2010 MC9S08FL16 32-Pin LQFP 873A-03 • Illegal address detection with reset • Flash block protection Development Support • Single-wire background debug interface • Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints). • On-chip in-circuit emulator (ICE) debug module containing two comparators and nine trigger modes. Peripherals • IPC — Interrupt priority controller to provide hardware based nested interrupt mechanism • ADC — 12-channel, 8-bit resolution; 2.5 s conversion time; automatic compare function; 1.7 mV/C temperature sensor; internal bandgap reference channel; operation in stop; optional hardware trigger; fully functional from 4.5 V to 5.5 V • TPM — One 4-channel and one 2-channel timer/pulse-width modulators (TPM) modules; selectable input capture, output compare, or buffered edge- or center-aligned PWM on each channel • MTIM16 — One 16-bit modulo timer with optional prescaler • SCI — One serial communications interface module with optional 13-bit break; LIN extensions Input/Output • 30 GPIOs including 1 output-only pin and 1 input-only pin Package Options • 32-pin SDIP • 32-pin LQFP This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © Freescale Semiconductor, Inc., 2009-2010. All rights reserved. 32-Pin SDIP 1376-02 Table of Contents 1 2 3 4 5 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 System Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 9 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.2 Parameter Classification . . . . . . . . . . . . . . . . . . . 9 5.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 9 5.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . 10 5.5 ESD Protection and Latch-Up Immunity . . . . . . 11 5.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 12 5.7 Supply Current Characteristics . . . . . . . . . . . . . 17 5.8 External Oscillator (XOSC) and ICS Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 5.9.1 Control Timing . . . . . . . . . . . . . . . . . . . . . 5.9.2 TPM Module Timing . . . . . . . . . . . . . . . . 5.10 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . 5.11 Flash Specifications. . . . . . . . . . . . . . . . . . . . . . 5.12 EMC Performance . . . . . . . . . . . . . . . . . . . . . . . 5.12.1Radiated Emissions . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . Package Information . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Mechanical Drawings. . . . . . . . . . . . . . . . . . . . . 5.9 6 7 19 21 22 23 24 26 27 27 27 28 28 Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. Rev Date Description of Changes 1 March 18, 2009 2 July 20, 2009 Updated Section 5.12, “EMC Performance.” and corrected Figure 1 and Table 1. Corrected default trim value to 31.25 kHz. 3 Nov. 29, 2010 Updated Table 7. Initial public release. Related Documentation Find the most current versions of all documents at: http://www.freescale.com Reference Manual (MC9S08FL16RM) Contains extensive product information including modes of operation, memory, resets and interrupts, register definition, port pins, CPU, and all module information. MC9S08FL16 Series Data Sheet, Rev. 3 2 Freescale Semiconductor MCU Block Diagram 1 MCU Block Diagram The block diagram, Figure 1, shows the structure of MC9S08FL16 series MCU. PTA0/ADP0 16-BIT MODULO TIMER HCS08 CORE TCLK PTA1/ADP1 (MTIM16) BDC 2-CH TIMER/PWM TPM2CH[1:0] MODULE (TPM2) HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT PORT A PTA2/ADP2 CPU PTA4/BKGD/MS PTA5/IRQ/TCLK/RESET PTA6/TPM2CH0 RESET PTA7/TPM2CH1 IRQ IRQ INTERRUPT PRIORITY CONTROLLER (IPC) LVD PTB0/RxD/ADP4 PTB1/TxD/ADP5 ON-CHIP ICE AND DEBUG MODUE (DBG) SERIAL COMMUNICATIONS INTERFACE (SCI) TxD RxD USER FLASH MC9S08FL16 — 16,384 BYTES MC9S08FL8 — 8,192 BYTES 4-CH TIMER/PWM PTB2/ADP6 PORT B COP PTA3/ADP3 PTB4/TPM1CH0 PTB5/TPM1CH1 TPM1CH[3:0] MODULE (TPM1) USER RAM MC9S08FL16 — 1,024 BYTES MC9S08FL8 — 768 BYTES PTB3/ADP7 PTB6/XTAL PTB7/EXTAL PTC0/ADP8 20 MHz INTERNAL CLOCK SOURCE (ICS) PTC1/ADP9 PORT C PTC2/ADP10 EXTAL XTAL EXTERNAL OSCILLATOR SOURCE (XOSC) VDD VSS PTC3/ADP11 PTC4 PTC5 VOLTAGE REGULATOR PTC6 PTC7 VREFH VREFL VDDA VSSA 12-CH 8-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) ADP[11:0] PTD0 PORT D PTD1 NOTE 1. PTA4 is output only when used as port pin. 2. PTA5 is input only when used as port pin. PTD2/TPM1CH2 PTD3/TPM1CH3 PTD4 PTD5 Figure 1. MC9S08FL16 Series Block Diagram MC9S08FL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 3 System Clock Distribution 2 System Clock Distribution MC9S08FL16 series use ICS module as clock sources. The ICS module can use internal or external clock source as reference to provide up to 20 MHz CPU clock. The output of ICS module includes, • OSCOUT — XOSC output provides external reference clock to ADC. • ICSFFCLK — ICS fixed frequency clock reference (around 32.768 kHz) provides double of the fixed lock signal to TPMs and MTIM16. • ICSOUT — ICS CPU clock provides double of the bus clock which is basic clock reference of peripherals. • ICSLCLK — Alternate BDC clock provides debug signal to BDC module. The TCLK pin is an extra external clock source. When TCLK is enabled, it can provide alternate clock source to TPMs and MTIM16. The on-chip 1 kHz clock provides clock source of COP module. TCLK 1 kHz COP TPM1 TPM2 MTIM16 ADC FLASH RAM IPC OSCOUT ICSFFCLK 2 FIXED CLOCK (XCLK) ICS ICSOUT 2 BUS CLOCK ICSLCLK XOSC CPU SCI BDC EXTAL XTAL Figure 2. System Clock Distribution Diagram MC9S08FL16 Series Data Sheet, Rev. 3 4 Freescale Semiconductor Pin Assignments 3 Pin Assignments This section shows the pin assignments for the MC9S08FL16 series devices. PTC5 PTC4 PTA5/IRQ/TCLK/RESET PTD2/TPM1CH2 PTA4/BKGD/MS PTD0 PTD1 VDD VSS PTB7/EXTAL PTB6/XTAL PTB5/TPM2CH1 PTD3/TPM1CH3 PTB4/TPM1CH0 PTC3/ADP11 PTC2/ADP10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 PTC6 PTC7 PTA0/ADP0 PTD5 PTA1/ADP1 PTA2/ADP2 PTA3/ADP3 PTA6/TPM2CH0 PTA7/TPM2CH1 PTB0/RxD/ADP4 PTB1/TxD/ADP5 PTB2/ADP6 PTD4 PTB3/ADP7 PTC0/ADP8 PTC1/ADP9 Figure 3. MC9S08FL16 Series 32-Pin SDIP Package MC9S08FL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 5 PTA5/IRQ/TCLK/RESET PTC4 PTC5 PTC6 PTC7 PTA0/ADP0 31 30 29 28 27 26 25 PTD5 PTD2/TPM1CH2 32 Pin Assignments 24 PTA1/ADP1 2 23 PTA2/ADP2 PTD1 3 22 PTA3/ADP3 VDD 4 21 PTA6/TPM2CH0 VSS 5 20 PTA7/TPM2CH1 PTB7/EXTAL 6 19 PTB0/RxD/ADP4 PTB6/XTAL 7 18 PTB1/TxD/ADP5 PTB5/TPM1CH1 8 PTA4/BKGD/MS 1 14 15 PTC0/ADP8 PTB3/ADP7 16 13 PTC1/ADP9 PTD4 12 11 PTC3/ADP11 PTC2/ADP10 10 PTB4/TPM1CH0 17 PTB2/ADP6 PTD3/TPM1CH3 9 PTD0 Figure 4. MC9S08FL16 Series 32-Pin LQFP Package Table 1. Pin Availability by Package Pin-Count Pin Number <-- Lowest 32-SDIP 32-LQFP Port Pin I/O 1 29 PTC5 I/O 2 30 PTC4 I/O Priority Alt 1 I/O IRQ I --> Highest Alt 2 I/O Alt 3 I/O TCLK I RESET I MS I 3 31 PTA5 I 4 32 PTD2 I/O 5 1 PTA4 O 6 2 PTD0 I/O 7 3 PTD1 I/O 8 4 VDD I 9 5 VSS I 10 6 PTB7 I/O EXTAL I 11 7 PTB6 I/O XTAL O 12 8 PTB5 I/O TPM1CH1 I/O 13 9 PTD3 I/O TPM1CH3 I/O 14 10 PTB4 I/O TPM1CH0 I/O 15 11 PTC3 I/O TPM1CH2 I/O BKGD ADP11 I I MC9S08FL16 Series Data Sheet, Rev. 3 6 Freescale Semiconductor Pin Assignments Table 1. Pin Availability by Package Pin-Count (continued) Pin Number <-- Lowest 32-SDIP 32-LQFP Port Pin I/O 16 12 PTC2 17 13 18 19 20 21 Alt 1 Priority I/O --> Highest Alt 2 I/O I/O ADP10 I PTC1 I/O ADP9 I 14 PTC0 I/O ADP8 I 15 PTB3 I/O ADP7 I 16 PTD4 I/O 17 PTB2 I/O ADP6 I Alt 3 I/O 22 18 PTB1 I/O TxD I/O ADP5 I 23 19 PTB0 I/O RxD I ADP4 I 24 20 PTA7 I/O TPM2CH1 I/O 25 21 PTA6 I/O TPM2CH0 I/O 26 22 PTA3 I/O ADP3 I 27 23 PTA2 I/O ADP2 I 28 24 PTA1 I/O ADP1 I 29 25 PTD5 I/O 30 26 PTA0 I/O ADP0 I 31 27 PTC7 I/O 32 28 PTC6 I/O NOTE When an alternative function is first enabled, it is possible to get a spurious edge to the module. User software must clear out any associated flags before interrupts are enabled. Table 1 illustrates the priority if multiple modules are enabled. The highest priority module will have control over the pin. Selecting a higher priority pin function with a lower priority function already enabled can cause spurious edges to the lower priority module. Disable all modules that share a pin before enabling another module. MC9S08FL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 7 Memory Map 4 Memory Map Figure 5 shows the memory map for the MC9S08FL16 series. On-chip memory in the MC9S08FL16 series of MCUs consists of RAM, flash program memory for nonvolatile data storage, plus I/O and control/status registers. The registers are divided into two groups: • Direct-page registers (0x0000 through 0x003F) • High-page registers (0x1800 through 0x187F) $0000 $0000 DIRECT PAGE REGISTERS $003F $0040 $033F $0340 RAM 768 BYTES DIRECT PAGE REGISTERS $003F $0040 RAM 1024 BYTES $043F $0440 UNIMPLEMENTED $17FF $1800 HIGH PAGE REGISTERS $187F $1880 UNIMPLEMENTED $17FF $1800 HIGH PAGE REGISTERS $187F $1880 UNIMPLEMENTED UNIMPLEMENTED $BFFF $C000 FLASH 16384 BYTES $DFFF $E000 FLASH 8192 BYTES $FFFF $FFFF MC9S08FL8 MC9S08FL16 Figure 5. MC9S08FL16 Series Memory Map MC9S08FL16 Series Data Sheet, Rev. 3 8 Freescale Semiconductor Electrical Characteristics 5 Electrical Characteristics 5.1 Introduction This section contains electrical and timing specifications for the MC9S08FL16 series of microcontrollers available at the time of publication. 5.2 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the following classification is used and the parameters are tagged accordingly in the tables where appropriate: Table 2. Parameter Classifications P Those parameters are guaranteed during production testing on each individual device. C Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations. NOTE The classification is shown in the column labeled “C” in the parameter tables where appropriate. 5.3 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table 3 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pullup resistor associated with the pin is enabled. MC9S08FL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 9 Electrical Characteristics Table 3. Absolute Maximum Ratings Rating Symbol Value Unit Supply voltage VDD –0.3 to 5.8 V Maximum current into VDD IDD 120 mA Digital input voltage VIn –0.3 to VDD + 0.3 V Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 ID 25 mA Tstg –55 to 150 C Storage temperature range 1 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins, except for PTA5 are internally clamped to VSS and VDD. 3 Power supply must maintain regulation within operating V DD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). 5.4 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. Table 4. Thermal Characteristics Rating Operating temperature range (packaged) Symbol Value Unit TA TL to TH –40 to 85 C Thermal resistance Single-layer board 32-pin SDIP 32-pin LQFP JA 60 85 C/W Thermal resistance Four-layer board 32-pin SDIP 32-pin LQFP JA 35 56 C/W The average chip-junction temperature (TJ) in C can be obtained from: MC9S08FL16 Series Data Sheet, Rev. 3 10 Freescale Semiconductor Electrical Characteristics TJ = TA + (PD JA) Eqn. 1 where: TA = Ambient temperature, C JA = Package thermal resistance, junction-to-ambient, C/W PD = Pint PI/O Pint = IDD VDD, Watts — chip internal power PI/O = Power dissipation on input and output pins — user determined For most applications, PI/O far much smaller than Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: PD = K (TJ + 273 C) Eqn. 2 Solving Equation 1 and Equation 2 for K gives: K = PD (TA + 273 C) + JA (PD)2 Eqn. 3 where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring PD (at equilibrium) for an known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively for any value of TA. 5.5 ESD Protection and Latch-Up Immunity Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, normal handling precautions must be taken to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. During the device qualification, ESD stresses were performed for the human body model (HBM) and the charge device model (CDM). A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless instructed otherwise in the device specification. Table 5. ESD and Latch-Up Test Conditions Model Human body Description Symbol Value Unit Series resistance R1 1500 Storage capacitance C 100 pF Number of pulses per pin — 3 — Minimum input voltage limit — –2.5 V Maximum input voltage limit — 7.5 V Latch-up MC9S08FL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 11 Electrical Characteristics Table 6. ESD and Latch-Up Protection Characteristics Rating1 No. 1 5.6 Symbol Min Max Unit 1 Human body model (HBM) VHBM 2000 — V 2 Charge device model (CDM) VCDM 500 — V 3 Latch-up current at TA = 85 C ILAT 100 — mA Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. DC Characteristics This section includes information about power supply requirements and I/O pin characteristics. Table 7. DC Characteristics Num C 1 P Operating voltage C 2 P 3 Characteristic D C 4 P Output high voltage Output high current Output low voltage 5 D Output low current 6 P 7 All I/O pins, low-drive strength All I/O pins, high-drive strength Max total IOH for all ports All I/O pins, low-drive strength All I/O pins, high-drive strength Symbol Condition Min. Typical1 Max. Unit — — 4.5 — 5.5 V ILoad = –2 mA VDD – 1.5 — — ILoad = –10 mA VDD – 1.5 — — — — — 100 ILoad = 2 mA — — 1.5 ILoad = 10 mA — — 1.5 VOH IOHT V VOL mA V Max total IOL for all ports IOLT — — — 100 mA Input high voltage All digital inputs VIH — 0.65 VDD — — V P Input low voltage All digital inputs VIL — — — 0.35 VDD V 8 C Input hysteresis All digital inputs Vhys — 0.06 VDD — — mV 9 Input P leakage current All input only pins (per pin) |IIn| VIn = VDD or VSS — 0.1 1 A 10 Hi-Z (off-state) P leakage current All input/output (per pin) |IOZ| VIn = VDD or VSS — 0.1 1 A 11a Pullup, C pulldown resistors All digital inputs, when enabled (all I/O pins other than PTA5/IRQ/TCLK/RESET) RPU, RPD — 17.5 36.5 52.5 k 11b Pullup, C pulldown resistors (PTA5/IRQ/TCLK/RESET) RPU, RPD (Note2) — 17.5 36.5 52.5 k MC9S08FL16 Series Data Sheet, Rev. 3 12 Freescale Semiconductor Electrical Characteristics Table 7. DC Characteristics (continued) Num C 12 Characteristic DC injection C current 3, 4, 5 2 3 4 5 6 7 8 Typical1 Max. Unit –0.2 — 0.2 mA –5 — 5 mA — — — 8 pF VRAM — — 0.6 1.0 V Condition IIC VIN < VSS, VIN > VDD CIn Single pin limit Total MCU limit, includes sum of all stressed pins 13 C Input capacitance, all pins 14 C RAM retention voltage 6 15 C POR re-arm voltage VPOR — 0.9 1.4 2.0 V 16 D POR re-arm time tPOR — 10 — — s 17 Low-voltage detection threshold — high range P VLVD17 VDD falling VDD rising — 3.9 4.0 4.0 4.1 4.1 4.2 Low-voltage warning threshold — high range 1 C VDD falling VDD rising VLVW3 — 4.5 4.6 4.6 4.7 4.7 4.8 Low-voltage warning threshold — high range 0 7 V P VDD falling LVW2 VDD rising — 4.2 4.3 4.3 4.4 4.4 4.5 18 1 Min. Symbol Low-voltage inhibit reset/recover hysteresis 19 C 20 C Bandgap voltage reference8 V V V Vhys — — 100 — mV VBG — — 1.21 — V Typical values are measured at 25 C. Characterized, not tested. The specified resistor value is the actual value internal to the device. The pullup or pulldown value may appear higher when measured externally on the pin. All functional non-supply pins, except for PTA5 are internally clamped to VSS and VDD. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If the positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure that external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). Maximum is highest voltage that POR is guaranteed. When VDD is in between the minimun of this parameter and 4.5 V, the CPU, RAM, LVD and flash are full functional, but the performance of other modules may be reduced. Factory trimmed at VDD = 5.0 V, Temp = 25 C MC9S08FL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 13 Electrical Characteristics Typical IOH vs. VDD-VOH VDD = 5 V (High Drive) 50.000 45.000 40.000 35.000 -40C 0C 25C 55C 85C mA 30.000 25.000 20.000 15.000 10.000 5.000 0.000 0 0.3 0.5 0.8 1 1.3 2 V Figure 6. Typical IOH Vs VDD–VOH (VDD = 5.0 V) (High Drive) MC9S08FL16 Series Data Sheet, Rev. 3 14 Freescale Semiconductor Electrical Characteristics Typical IOH vs. VDD-VOH VDD = 5V (Low Drive) 10.000 9.000 8.000 mA 7.000 -40C 6.000 0C 5.000 25C 4.000 55C 85C 3.000 2.000 1.000 0.000 0 0.3 0.5 0.8 1 1.3 2 V Figure 7. Typical IOH Vs VDD–VOH (VDD = 5.0 V) (Low Drive) MC9S08FL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 15 Electrical Characteristics Typical IOL vs. VOL VDD = 5 V (High Drive) 50.000 45.000 40.000 mA 35.000 -40C 30.000 0C 25.000 25C 20.000 55C 85C 15.000 10.000 5.000 0.000 0 0.3 0.5 0.8 1 1.3 2 V Figure 8. Typical IOH Vs VOL (VDD = 5.0 V) (High Drive) MC9S08FL16 Series Data Sheet, Rev. 3 16 Freescale Semiconductor Electrical Characteristics Typical IOL vs. VOL VDD = 5V (Low Drive) 14.000 12.000 10.000 -40C 0C mA 8.000 25C 6.000 55C 85C 4.000 2.000 0.000 0 0.3 0.5 0.8 1 1.3 2 V Figure 9. Typical IOH Vs VOL (VDD = 5.0 V) (Low Drive) 5.7 Supply Current Characteristics This section includes information about power supply current in various operating modes. MC9S08FL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 17 Electrical Characteristics Table 8. Supply Current Characteristics Num C Parameter Symbol P RIDD 5 Typical1 Max 5.66 5.75 5.80 — P 1 MHz 1.61 1.65 1.78 C 10 MHz 2.79 2.86 2.88 Wait mode supply current FEI mode, all modules off 2 5 WIDD C 1 MHz Unit Temp –40 C 25 C 85 C mA — –40 C 25 C 85 C — –40 C 25 C 85 C A 1.05 1.06 1.06 — –40 C 25 C 85 C C Stop2 mode supply current S2IDD — 5 1.06 — A –40 to 85 C C Stop3 mode supply current no clocks active S3IDD — 5 1.17 — A –40 to 85 C 4 C ADC adder to stop3 — — 5 163.88 — A 25 C 5 C ICS adder to stop3 EREFSTEN = 1 — — 5 1.25 — A 25 C 6 C LVD adder to stop3 — — 5 161.3 — A 25 C 3 1 VDD (V) 10 MHz Run supply current FEI mode, all modules off 1 Bus Freq Data in Typical column was characterized at 5.0 V, 25 C or is typical recommended value. MC9S08FL16 Series Data Sheet, Rev. 3 18 Freescale Semiconductor Electrical Characteristics 5.8 External Oscillator (XOSC) and ICS Characteristics Refer to Figure 11 for crystal or resonator circuits. Table 9. XOSC and ICS Specifications (Temperature Range = –40 to 85 C Ambient) Num C Characteristic 1 Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1) Low range (RANGE = 0) High range (RANGE = 1) FEE or FBE mode2 C High range (RANGE = 1), high gain (HGO = 1), FBELP mode High range (RANGE = 1), low power (HGO = 0), FBELP mode 2 D Load capacitors 3 D Symbol Min Typical1 Max Unit flo fhi fhi fhi 32 1 1 1 — — — — 38.4 5 16 8 kHz MHz MHz MHz C1 C2 Feedback resistor Low range (32 kHz to 38.4 kHz) See Note3 RF 10 1 High range (1 MHz to 16 MHz) 4 D Series resistor — Low range Low gain (HGO = 0) High gain (HGO = 1) RS 5 Series resistor — High range Low Gain (HGO = 0) High Gain (HGO = 1) D 8 MHz 4 MHz 1 MHz RS 6 Crystal startup time4, 5 Low range, low power Low range, high power C High range, low power High range, high power t CSTL t CSTH M M — — 0 100 — — k — — — 0 0 0 0 10 20 — — — — 200 400 5 15 — — — — ms k 7 T Internal reference start-up time tIRST — 60 100 s 8 Square wave input clock frequency (EREFS = 0, ERCLKEN = 1) D FEE or FBE mode2 FBELP mode fextal 0.03125 0 — — 5 20 MHz MHz 9 P Average internal reference frequency — trimmed fint_t — 31.25 — kHz 10 6 P DCO output frequency range — trimmed Low range (DRS = 00) fdco_t 16 — 20 MHz 11 C fdco_t — –1.0 to 0.5 0.5 2 1 %fdco 12 C FLL acquisition time4,7 1 ms Total deviation of DCO output from trimmed frequency4 Over full voltage and temperature range Over fixed voltage and temperature range of 0 to 70C tAcquire MC9S08FL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 19 Electrical Characteristics Table 9. XOSC and ICS Specifications (Temperature Range = –40 to 85 C Ambient) (continued) Num C 13 C 1 2 3 4 5 6 7 8 Characteristic Long term jitter of DCO output clock (averaged over 2 ms interval) 8 Symbol Min Typical1 Max Unit CJitter — 0.02 0.2 %fdco Data in Typical column was characterized at 5.0 V, 25 C or is typical recommended value. When ICS is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25 kHz to 39.0625 kHz. See crystal or resonator manufacturer’s recommendation. This parameter is characterized and not tested on each device. Proper PC board layout procedures must be followed to achieve specifications. The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device. This specification applies to any time the FLL reference source or reference divider is changed, trim value changed, DMX32 bit is changed, DRS bit is changed, or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval. XOSC EXTAL XTAL RF C1 RS Crystal or Resonator C2 Figure 10. Typical Crystal or Resonator Circuit MC9S08FL16 Series Data Sheet, Rev. 3 20 Freescale Semiconductor Electrical Characteristics 1.00% 0.50% Deviation (%) 0.00% -60 -40 -20 0 20 40 60 80 100 120 -0.50% -1.00% TBD -1.50% -2.00% Temperature Figure 11. Deviation of DCO Output from Trimmed Frequency (20 MHz, 5.0 V) 5.9 AC Characteristics This section describes timing characteristics for each peripheral system. MC9S08FL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 21 Electrical Characteristics 5.9.1 Control Timing Table 10. Control Timing Symbol Min Typical1 Max Unit Bus frequency (tcyc = 1/fBus) fBus dc — 10 MHz D Internal low power oscillator period tLPO 700 — 1300 s 3 D External reset pulse width2 textrst 100 — — ns 4 D Reset low drive trstdrv 34 tcyc — — ns 5 D BKGD/MS setup time after issuing background debug force reset to enter user or BDM modes tMSSU 500 — — ns 6 D BKGD/MS hold time after issuing background debug force reset to enter user or BDM modes3 tMSH 100 — — s 7 D IRQ pulse width Asynchronous path2 Synchronous path4 tILIH, tIHIL 100 1.5 tcyc — — — — ns 8 D Keyboard interrupt pulse width Asynchronous path2 Synchronous path4 100 1.5 tcyc — — — — — — 16 23 — — — — 5 9 — — Num C 1 D 2 9 Rating tILIH, tIHIL Port rise and fall time — Low output drive (PTxDS = 0) (load = 50 pF)5 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) tRise, tFall Port rise and fall time — High output drive (PTxDS = 1) (load = 50 pF)5 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) tRise, tFall ns ns C ns Typical values are based on characterization data at VDD = 5.0 V, 25 C unless otherwise stated. This is the shortest pulse that is guaranteed to be recognized as a reset pin request. 3 To enter BDM mode following a POR, BKGD/MS must be held low during the power-up and for a hold time of tMSH after VDD rises above VLVD. 4 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized. 5 Timing is shown with respect to 20% V DD and 80% VDD levels. Temperature range –40 C to 85 C. 1 2 textrst RESET PIN Figure 12. Reset Timing MC9S08FL16 Series Data Sheet, Rev. 3 22 Freescale Semiconductor Electrical Characteristics tIHIL KBIPx IRQ/KBIPx tILIH Figure 13. IRQ/KBIPx Timing 5.9.2 TPM Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table 11. TPM Input Timing No. C 1 D 2 Function Symbol Min Max Unit External clock frequency fTCLK 0 fBus/4 Hz D External clock period tTCLK 4 — tcyc 3 D External clock high time tclkh 1.5 — tcyc 4 D External clock low time tclkl 1.5 — tcyc 5 D Input capture pulse width tICPW 1.5 — tcyc tTCLK tclkh TCLK tclkl Figure 14. Timer External Clock tICPW TPMCHn TPMCHn tICPW Figure 15. Timer Input Capture Pulse MC9S08FL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 23 Electrical Characteristics 5.10 ADC Characteristics Table 12. 8-Bit ADC Operating Conditions Characteristic Conditions Absolute Symb Min Typical1 Max Unit VDDA 4.5 — 5.5 V 2 VDDA –100 0 100 mV 2 VSSA –100 0 100 mV Supply voltage Delta to VDD (VDD – VDDA) Ground voltage Delta to VSS (VSS – VSSA) Input voltage — VADIN VREFL — VREFH V Input capacitance — CADIN — 4.5 5.5 pF Input resistance — RADIN — 3 5 k Analog source resistance 8-bit mode (all valid fADCK) RAS — — 10 k 0.4 — 8.0 0.4 — 4.0 ADC conversion High speed (ADLPC = 0) clock frequency Low power (ADLPC = 1) fADCK Comment External to MCU MHz Typical values assume VDDA = 5.0 V, Temp = 25 C, fADCK= 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 DC potential difference. 1 SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZADIN Pad leakage due to input protection ZAS RAS SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN ADC SAR ENGINE + VADIN VAS + – CAS – RADIN INPUT PIN INPUT PIN RADIN RADIN INPUT PIN CADIN Figure 16. ADC Input Impedance Equivalency Diagram MC9S08FL16 Series Data Sheet, Rev. 3 24 Freescale Semiconductor Electrical Characteristics Table 13. 8-Bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) Symb Min Typ1 Max Unit T Supply Current ADLPC=1 ADLSMP=1 ADCO=1 IDDA — 133 — A T Supply Current ADLPC=1 ADLSMP=0 ADCO=1 IDDA — 218 — A T Supply Current ADLPC=0 ADLSMP=1 ADCO=1 IDDA — 327 — A P Supply Current ADLPC=0 ADLSMP=0 ADCO=1 IDDA — 0.582 1 mA C Supply Current Stop, Reset, Module Off IDDA — 0.011 1 A ADC Asynchronous Clock Source High Speed (ADLPC = 0) 2 3.3 5 P 1.25 2 3.3 Conversion Time (Including sample time) Short Sample (ADLSMP = 0) — 20 — — 40 — — 3.5 — — 23.5 — — 3.266 — — 3.638 — VTEMP25 — 1.396 — mV C Characteristic P Conditions Low Power (ADLPC = 1) Long Sample (ADLSMP = 1) fADACK tADC Short Sample (ADLSMP = 0) P Sample Time Long Sample (ADLSMP = 1) tADS MHz ADCK cycles ADCK cycles Temp Sensor Slope –40C– 25C D Temp Sensor Voltage 25 C P Total Unadjusted Error 8-bit mode ETUE — 0.5 1.0 LSB2 P Differential Non-Linearity 8-bit mode3 DNL — 0.3 0.5 LSB2 T Integral Non-Linearity 8-bit mode INL — 0.3 0.5 LSB2 P Zero-Scale Error 8-bit mode EZS — 0.5 0.5 LSB2 T Full-Scale Error 8-bit mode EFS — 0.5 0.5 LSB2 D m 25C– 125C Comment tADACK = 1/fADACK See reference manual for conversion time variances mV/C Includes quantization VADIN = VSSA VADIN = VDDA MC9S08FL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 25 Electrical Characteristics Table 13. 8-Bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued) C Characteristic D Quantization Error D Input Leakage Error Symb Min Typ1 Max Unit 8-bit mode EQ — — 0.5 LSB2 8-bit mode EIL — 0.1 1 LSB2 Conditions Comment Pad leakage2 * RAS Typical values assume VDDA = 5.0 V, Temp = 25 C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 Based on input pad leakage current. Refer to pad electricals. 1 5.11 Flash Specifications This section provides details about program/erase times and program-erase endurance for the flash memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see the Memory section. Table 14. Flash Characteristics C Characteristic Symbol Min Typical Max Unit 5.5 V D Supply voltage for program/erase –40 C to 85 C Vprog/erase 4.5 D Supply voltage for read operation VRead 4.5 — 5.5 V fFCLK 150 — 200 kHz tFcyc 5 — 6.67 s 1 D Internal FCLK frequency D Internal FCLK period (1/FCLK) P P P P Byte program time (random Byte program time (burst location)2 mode)2 — tprog 9 tFcyc tBurst 4 tFcyc Page erase time2 tPage 4000 tFcyc Mass erase time2 tMass 20,000 tFcyc Byte program Page erase current3 current3 RIDDBP — 4 — mA RIDDPE — 6 — mA — 10,000 — cycles 5 100 — years 4 C Program/erase endurance TL to TH = –40 C to 85 C T = 25 C C Data retention5 tD_ret 1 The frequency of this clock is controlled by a software setting. These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 3 The program and erase currents are additional to the standard run I . These values are measured at room temperatures DD with VDD = 5.0 V, bus frequency = 4.0 MHz. 4 Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on how Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory. 2 MC9S08FL16 Series Data Sheet, Rev. 3 26 Freescale Semiconductor Ordering Information 5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory. 5.12 EMC Performance Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance. 5.12.1 Radiated Emissions Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller are measured in a TEM cell in two package orientations (the North and East). The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal to the reported emissions levels. Table 15. Radiated Emissions, Electric Field Parameter Radiated emissions, electric field 1 Symbol Conditions Frequency fOSC/fBUS VRE_TEM VDD = 5.0 V TA = 25 C package type 32-pin LQFP 0.15 – 50 MHz 4 MHz crystal 19 MHz bus 50 – 150 MHz Level1 (Max) Unit 9 dBV 5 150 – 500 MHz 2 500 – 1000 MHz 1 IEC Level N — SAE Level 1 — Data based on qualification test results. 6 Ordering Information This section contains ordering information for MC9S08FL16 series devices. See below for an example of the device numbering system. Table 16. Device Numbering System Memory Device Number1 Available Packages2 FLASH RAM MC9S08FL16 16 KB 1024 MC9S08FL8 8 KB 768 32 SDIP 32 LQFP MC9S08FL16 Series Data Sheet, Rev. 3 Freescale Semiconductor 27 Package Information 1 See the reference manual, MC9S08FL16 Series Reference Manual, for a complete description of modules included on each device. 2 See Table 17 for package information. Example of the device numbering system: MC 9 S08 FL 16 C XX Status (MC = Fully Qualified) Package designator (see Table 17) Temperature range (C =–40 C to 85 C) Memory (9 = Flash-based) Core Approximate flash size in KB Family 7 Package Information Table 17. Package Descriptions Pin Count 7.1 Package Type Abbreviation Designator Case No. Document No. 32 Low Quad Flat Package LQFP LC 873A-03 98ASH70029A 32 Shrink Dual In-line Package SDIP BM 1376-02 98ASA99330D Mechanical Drawings The following pages are mechanical drawings for the packages described in Table 17. MC9S08FL16 Series Data Sheet, Rev. 3 28 Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009-2010. All rights reserved. MC9S08FL16 Rev. 3 11/2010