ALSC AS7C4096A-12JIN 5.0v 512k x 8 cmos sram Datasheet

May 2005
Preliminary
AS7C4096A
®
5.0V 512K × 8 CMOS SRAM
• Equal access and cycle times
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• JEDEC standard packages
Features
• Pin compatible to AS7C4096
• Industrial and commercial temperature
• Organization: 524,288 words × 8 bits
• Center power and ground pins
• High speed
- 400 mil 36-pin SOJ
- 44-pin TSOP 2
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
- 10/12/15/20 ns address access time
- 5/6 ns output enable access time
• Low power consumption: ACTIVE
- 880mW/max @ 10 ns
• Low power consumption: STANDBY
- 55mW/max CMOS
Pin arrangements
Logic block diagram
36-pin SOJ (400 mil)
VCC
GND
524,288 × 8
Array
(4,194,304)
I/O1
Sense amp
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Row decoder
Input buffer
I/O8
Control
Circuit
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A18
A17
A16
A15
OE
I/O8
I/O7
GND
VCC
I/O6
I/O5
A14
A13
A12
A11
A10
NC
WE
OE
CE
NC
NC
A0
A1
A2
A3
A4
CE
I/O1
I/O2
VCC
GND
I/O3
I/O4
WE
A5
A6
A7
A8
A9
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A18
A17
A16
A15
OE
I/O8
I/O7
GND
VCC
I/O6
I/O5
A14
A13
A12
A11
A10
NC
NC
NC
A10
A11
A12
A13
A14
A15
A16
A17
A18
Column decoder
A0
A1
A2
A3
A4
CE
I/O1
I/O2
VCC
GND
I/O3
I/O4
WE
A5
A6
A7
A8
A9
44-pin TSOP 2
Selection guide
Maximum address access time
Maximum outputenable access time
Maximum operating current
Maximum CMOS standby current
5/27/05, v. 1.1
–10
10
5
160
10
Alliance Semiconductor
–12
12
6
140
10
–15
15
6
120
10
–20
20
6
100
10
Unit
ns
ns
mA
mA
P. 1 of 10
Copyright © Alliance Semiconductor. All rights reserved.
AS7C4096A
®
Functional description
The AS7C4096A is a high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as
524,288 words × 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are
desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6 ns are ideal
for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory
systems.
When CE is high the device enters standby mode. The device is guaranteed not to exceed 55mW power consumption in CMOS
standby mode.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O1–I/O8 is written
on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins
only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write
enable is active, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5.0V supply voltage. This device is available as
per industry standard 400-mil 36-pin SOJ and 44-pin TSOP 2 packages.
Absolute maximum ratings
Parameter
Voltage on VCC relative to GND
Voltage on any pin relative to GND
Power dissipation
Storage temperature (plastic)
Temperature with VCC applied
DC current into output (low)
Symbol
Vt1
Vt2
PD
Tstg
Tbias
IOUT
Min
–0.5
–0.5
–
–65
–55
–
Max
+7.0
VCC +0.5
1.0
+150
+125
20
Unit
V
V
W
°C
°C
mA
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
WE
OE
Data
Mode
H
X
X
High Z
Standby (ISB, ISB1)
L
H
H
High Z
Output disable (ICC)
L
H
L
DOUT
Read (ICC)
L
L
X
DIN
Write (ICC)
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P. 2 of 10
AS7C4096A
®
Recommended operating condition
Parameter
Symbol
VCC(10/12/15/20)
VIH*
VIL**
TA
TA
Supply voltage
Input voltage
commercial
industrial
Ambient operating
temperature
Min
4.5
2.2
–0.5
0
–40
Nominal
5.0
–
–
–
–
Max
5.5
VCC + 0.5
0.8
70
85
Unit
V
V
V
°C
°C
*
VIH max = VCC + 1.5V for pulse width less than 5 nS.
**
VIL min = –1.0V for pulse width less than 5 nS.
.
DC operating characteristics (over the operating range)1
Parameter
Input leakage
current
Symbol
|ILI|
–10
–12
–15
–20
Min Max Min Max Min Max Min Max Unit Notes
Test conditions
VCC = Max, VIN = GND to VCC
–
1
–
1
–
1
–
1
µA
Output leakage
current
|ILO|
VCC = Max, CE = VIH
VOUT= GND to VCC
–
1
–
1
–
1
–
1
µA
Operating power
supply current
ICC
VCC = Max, CE < VIL
f = fMax, IOUT = 0mA
–
160
–
140
–
120
–
100
mA
ISB
VCC = Max, CE > VIH
f = fMax, IOUT = 0mA
–
60
–
55
–
50
–
40
mA
ISB1
VCC = Max,
CE ≥ VCC – 0.2V,
VIN ≤ 0.2V or VIN ≥ VCC – 0.2V,
f=0
–
10
–
10
–
10
–
10
mA
IOL = 6 mA, VCC = Min
–
0.4
–
0.4
–
0.4
–
0.4
IOL = 8 mA, VCC = Min
–
0.5
–
0.5
–
0.5
–
0.5
IOH = –4 mA, VCC = Min
2.4
–
2.4
–
2.4
–
2.4
–
Standby power
supply current
VOL
Output voltage
VOH
V
4
V
4
Capacitance (f = 1MHz, Ta = 25° C, VCC = NOMINAL)4
Parameter
Symbol
Signals
Test conditions
Max
Unit
Input capacitance
CIN
A, CE, WE, OE
VIN = 0V
5
pF
I/O capacitance
CI/O
I/O
VIN = VOUT = 0V
7
pF
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P. 3 of 10
AS7C4096A
®
Read cycle (over the operating range)2,8
Parameter
–10
Max
Min
–12
Max
Min
–15
Max
Min
–20
Max
Symbol
Min
Unit Notes
Read cycle time
tRC
10
–
12
–
15
–
20
–
ns
Address access time
tAA
–
10
–
12
–
15
–
20
ns
2
Chip enable (CE) access time
tACE
–
10
–
12
–
15
–
20
ns
2
Output enable (OE) access time
tOE
–
5
–
6
–
6
–
6
ns
Output hold from address change
tOH
3
–
3
–
3
–
3
–
ns
4
CE Low to output in low Z
tCLZ
3
–
3
–
3
–
3
–
ns
3,4
CE High to output in high Z
tCHZ
–
5
–
6
–
7
–
9
ns
3,4
OE Low to output in low Z
tOLZ
0
–
0
–
0
–
0
–
ns
3,4
OE High to output in high Z
tOHZ
–
5
–
6
–
7
–
9
ns
3,4
Power up time
tPU
0
–
0
–
0
–
0
–
ns
3,4
Power down time
tPD
–
10
–
12
–
15
–
20
ns
3,4
Key to switching waveforms
Rising input
Falling input
Undefined/don’t care
Read waveform 1 (address controlled)2,5,6,8
tRC
Address
tAA
tOH
DOUT
Data valid
Read waveform 2 (CE, OE controlled)2,5,7,8
tRC1
CE
tOE
OE
tOLZ
tOHZ
tACE
tCHZ
DOUT
Data valid
tCLZ
Supply
current
5/27/05, v. 1.1
tPU
tPD
50%
50%
Alliance Semiconductor
ICC
ISB
P. 4 of 10
AS7C4096A
®
Write cycle (over the operating range)9
–10
Symbol Min
Max
Parameter
–12
Min
Max
–15
Min
Max
–20
Min
Max
Unit Notes
Write cycle time
tWC
10
–
12
–
15
–
20
–
ns
Chip enable (CE) to write end
tCW
7
–
8
–
10
–
12
–
ns
Address setup to write end
tAW
7
–
8
–
10
–
12
–
ns
Address setup time
tAS
0
–
0
–
0
–
0
–
ns
Write pulse width (OE = high)
tWP1
7
–
8
–
10
–
12
–
ns
Write pulse width (OE = low
tWP2
10
–
12
–
15
–
20
–
ns
Address hold from end of write
tAH
0
–
0
–
0
–
0
–
ns
Write recovery time
tWR
0
–
0
–
0
–
0
–
ns
Data valid to write end
tDW
5
–
6
–
7
–
9
–
ns
Data hold time
tDH
0
–
0
–
0
–
0
–
ns
3,4
Write enable to output in high Z
tWZ
2
5
2
6
2
7
2
9
ns
3,4
Output active from write end
tOW
3
–
3
–
3
–
3
–
ns
3,4
Write waveform 1 (WE controlled)9
tWC
tWR
tAH
tAW
Address
tWP
WE
tAS
tDW
DIN
tDH
Data valid
tWZ
tOW
DOUT
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P. 5 of 10
AS7C4096A
®
Write waveform 2 (CE controlled)9
tWC
tWR
tAH
tAW
Address
tAS
tCW
CE
tWP
WE
tDW
DIN
tDH
Data valid
AC test conditions
-
Output load: see Figure B.
Input pulse level: GND to VCC - 0.5V. See Figures A and B.
Input rise and fall times: 2 ns. See Figure A.
Input and output timing reference levels: 1.5V.
VCC - 0.5V
GND
90%
10%
90%
10%
2 ns
Figure A: Input pulse
DOUT
255Ω
+5.0V
Thevenin equivalent:
480Ω
168Ω
C10
DOUT
+1.728V
GND
Figure B: 5.0V Output load
Notes
1
2
3
4
5
6
7
8
9
10
During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
For test conditions, see AC Test Conditions.
tCLZ and tCHZ are specified with CL = 5pF as in Figure B. Transition is measured ±500 mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is HIGH for read cycle.
CE and OE are LOW for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
All write cycle timings are referenced from the last valid address to the first transitioning address.
C = 30pF, except at high Z and low Z parameters, where C = 5pF.
5/27/05, v. 1.1
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P. 6 of 10
AS7C4096A
®
Package dimensions
c
44434241403938 37 36 35 34333231 30 29 28 2726 2524 23
44-pin TSOP 2
A
A1
A2
b
c
d
E1
E
e
L
E1 E
1 2 3 4 5 6 7 8 9 10 111213 14 15 16 17 1819 20 21 22
d
A2
A
A1
e
b
e
L
0–5°
D
b1
36-pin SOJ
E1 E2
A
A1
b
Pin 1
Seating
Plane
c
A2
E
5/27/05, v. 1.1
Alliance Semiconductor
A
A1
A2
b
b1
c
D
e
E
E1
E2
44-pin TSOP 2
Min(mm) Max(mm)
1.2
0.05
0.15
0.95
1.05
0.30
0.45
0.21
0.12
18.31
18.52
10.06
10.26
11.68
11.94
0.80 (typical)
0.40
0.60
36-pin SOJ 400
Min(mils) Max(mils)
0.128
0.148
0.025
–
0.105
0.115
0.015
0.020
0.026
0.032
0.007
0.013
.920
.930
0.045
0.055
0.370 BSC
0.395
0.405
0.435
0.445
P. 7 of 10
AS7C4096A
®
Ordering codes
Package
SOJ
TSOP 2
Version
Commercial
Industrial
Commercial
Industrial
10 ns
AS7C4096A-10JC
AS7C4096A-10JI
AS7C4096A-10TC
AS7C4096A-10TI
12 ns
AS7C4096A-12JC
AS7C4096A-12JI
AS7C4096A-12TC
AS7C4096A-12TI
15 ns
AS7C4096A-15JC
AS7C4096A-15JI
AS7C4096A-15TC
AS7C4096A-15TI
20 ns
AS7C4096A-20JC
AS7C4096A-20JI
AS7C4096A-20TC
AS7C4096A-20TI
Note: Add suffix ‘N’ to the above part number for Lead Free Parts. (Ex: AS7C4096A - 10 TIN)
Part numbering system
AS7C
4096A
–XX
SRAM
prefix
Device
number
Access time
5/27/05, v. 1.1
J or T
Packages:
J: SOJ 400 mil
T: TSOP 2
X
Temperature ranges:
C: Commercial, 0°C to 70°C
I: Industrial, –40°C to 85°C
Alliance Semiconductor
X
N=Lead Free Parts
P. 8 of 10
AS7C4096A
®
Revision History
Rev. No.
v1.0
v1.1
History
Initial release
11/08/04
Included ICC, ISB & ISB1 parameters
Corrected the following: TOE, VIH, VOL & tWZ
5/27/05, v. 1.1
Revised Date
Alliance Semiconductor
05/27/05
P. 9 of 10
®
AS7C4096A
®
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Fax: 408 - 855 - 4999
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: AS7C4096A
Document Version: v. 1.1
www.alsc.com
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trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make
changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document.
The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at
any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in
this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any
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