DATASHEET
ISL6532B
FN9120
Rev 3.00
Jul 2004
ACPI Regulator/Controller for Dual Channel DDR Memory Systems
The ISL6532B provides a complete ACPI compliant power
solution for up to 4 DIMM dual channel DDR/DDR2 memory
systems. Included are both a synchronous buck controller
and integrated LDO to supply VDDQ with high current during
S0/S1 states and standby current during S3 state. During
Run mode, a fully integrated sink-source regulator generates
an accurate (VDDQ/2) high current VTT voltage without the
need for a negative supply. A buffered version of the VDDQ/2
reference is provided as VREF.
The switching PWM controller drives two N-Channel
MOSFETs in a synchronous-rectified buck converter
topology. The synchronous buck converter uses voltagemode control with fast transient response. Both the switching
regulator and integrated standby LDO provide a maximum
static regulation tolerance of 2% over line, load, and
temperature ranges. The output is user-adjustable by means
of external resistors down to 0.8V.
Switching the memory core output between the PWM
regulator and the standby LDO during state transitions is
accomplished smoothly via the internal ACPI control
circuitry. The NCH signal provides synchronized switching of
a backfeed blocking switch during the transitions eliminating
the need to route 5V Dual to the memory supply.
An integrated soft-start feature brings VDDQ into regulation
in a controlled manner when returning to S0/S1 state from
S4/S5 or mechanical off states. During S0 the PGOOD
signal indicates that all supplies are within spec and
operational.
Each output is monitored for under and over-voltage events.
Current limiting is included on the VTT and VDDQ standby
regulators. Thermal shutdown is integrated.
Pinout
• 250kHz Constant Frequency Operation
• Tight Output Voltage Regulation
- Both Outputs: 2% Over Temperature
• 5V or 3.3V Down Conversion
• Fully-Adjustable Outputs with Wide Voltage Range: Down
to 0.8V supports DDR and DDR2 Specifications
• Simple Single-Loop Voltage-Mode PWM Control Design
• Fast PWM Converter Transient Response
• Over Current Protection on VTT and Under/Over-Voltage
Monitoring of Both Outputs
• Integrated Thermal Shutdown Protection
• QFN Package Option
- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad
Flat No Leads - Product Outline
- QFN Near Chip Scale Package Footprint; Improves
PCB Efficiency, Thinner in Profile
• Pb-free available
Applications
• Single and Dual Channel DDR Memory Power Systems in
ACPI compliant PCs
• Embedded processor and I/O supplies
15 NCH
GND 2
• Integrated VREF Buffer
• PWM Controller Drives Low Cost N-Channel MOSFETs
• ASIC power supplies
20 19 18 17 16
5VSBY 1
• Generates 2 Regulated Voltages
- Synchronous Buck PWM Controller with Standby LDO
- 3A Integrated Sink/Source Linear Regulator with
Accurate VDDQ/2 Divider Reference
- Glitch-free Transitions During State Changes
• ACPI Compliant Sleep State Control
• Graphics cards - GPU and memory supplies
S3#
S5#
P12V
LGATE
UGATE
ISL6532B (QFN)
TOP VIEW
Features
14 PGOOD
• DSP supplies
Ordering Information
VTT 3
13 GND
VTT 4
12 COMP
PART NUMBER
11 FB
FN9120 Rev 3.00
Jul 2004
6
7
8
9
10
VDDQ
VTTSNS
P5VSBY
VREF_OUT
VREF_IN
VDDQ 5
TEMP. RANGE
(oC)
PACKAGE
ISL6532BCR
0 to 70
20 Ld 6x6 QFN
L20.6x6
ISL6532BCRZ
(See Note)
0 to 70
20 Ld 6x6 QFN
(Pb-free)
L20.6x6
PKG. DWG. #
*Add “-T” suffix to part number for tape and reel packaging.
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination finish, which
is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J Std-020B.
Page 1 of 15
ISL6532B
FN9120 Rev 3.00
Jul 2004
Block Diagram
P3V3SBY
SLP_S3#
VDDQ S3
REGULATOR
SLP_S5#
5VSBY
VOLTAGE
REFERENCE
0.800V
NCH
0.680V (-15%)
VDDQ(2)
0.920V (+15%)
5V
VTTSNS
POR
VTT
REG
VTT(2)
S3
S0
DISABLE
{
SLEEP,
SOFT-START,
PGOOD,
AND FAULT
LOGIC
12V
POR
PWM ENABLE
S0/S3
P12V
SOFT-START
RU
PWM
EA1
VREF_IN
COMP
OSCILLATOR
{
PWM
LOGIC
UGATE
250kHz
UV/OV
RL
LGATE
UV/OV
Page 2 of 15
VREF_OUT
PGOOD
FB
COMP
GND
ISL6532B
Simplified Power System Diagram
12V
5VSBY
5V
SLEEP
STATE
LOGIC
SLP_S3
SLP_S5
Q1
VDDQ
PWM
CONTROLLER
+
Q2
5VSBY/3V3SBY
STANDBY
LDO
ISL6532B
VREF
VTT
REGULATOR
VTT
+
Typical Application - 5V or 3.3V Input
5VSBY
+12V
+3.3V
VDDQ
+5V OR +3.3V
P12V
PGOOD
P5VSBY
5VSBY
CBP
S3#
SLP_S3
RNCH
NCH
S5#
SLP_S5
VREF_OUT
VREF
+
CIN
VREF_IN
CSS
UGATE
+
VDDQ
LOUT
ISL6532B
VTT
Q1
LGATE
VTT
VDDQ
VTT
VDDQ
2.5V
+
Q2
CVDDQ
+
CVTT
VTTSNS
FB
COMP
GND
FN9120 Rev 3.00
Jul 2004
Page 3 of 15
ISL6532B
Typical Application - Input From 5V Dual
5VSBY
+12V
+3.3V
VDDQ
S3#
SLP_S3
RNCH
NCH
S5#
SLP_S5
VREF
5V DUAL
P12V
PGOOD
P5VSBY
5VSBY
CBP
+
VREF_OUT
VREF_IN
UGATE
Q1
CSS
VDDQ
LOUT
ISL6532B
VTT
CIN
LGATE
VTT
VDDQ
VTT
VDDQ
2.5V
+
Q2
CVDDQ
+
CVTT
VTTSNS
FB
COMP
GND
FN9120 Rev 3.00
Jul 2004
Page 4 of 15
ISL6532B
Absolute Maximum Ratings
Thermal Information
5VSBY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +7V
P12V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14V
UGATE, LGATE, NCH . . . . . . . . . . . . . . GND - 0.3V to P12V + 0.3V
All other Pins . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5VSBY + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 2
Thermal Resistance (Typical, Notes 1, 2) JA (oC/W) JC (oC/W)
QFN Package . . . . . . . . . . . . . . . . . . .
32
5
Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Recommended Operating Conditions
Supply Voltage on 5VSBY . . . . . . . . . . . . . . . . . . . . . . . . +5V 10%
Supply Voltage on P12V . . . . . . . . . . . . . . . . . . . . . . . . +12V 10%
Supply Voltage on 3V3SBY . . . . . . . . . . . . . . . . . . . . . +3.3V 10%
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Junction Temperature Range . . . . . . . . . . . . . . . . . . 0oC to 125oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams and Typical Application Schematics
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
5VSBY SUPPLY CURRENT
Nominal Supply Current
ICC_S0
S3# & S5# HIGH, UGATE/LGATE Open
3.00
5.25
7.25
mA
ICC_S3
S3# LOW, S5# HIGH, UGATE/LGATE
Open
3.50
-
4.75
mA
ICC_S5
S5# LOW, S3# Don’t Care,
UGATE/LGATE Open
300
-
800
A
Rising 5VSBY POR Threshold
4.00
-
4.35
V
Falling 5VSBY POR Threshold
3.60
-
3.95
V
Rising P12V POR Threshold
10.0
-
10.5
V
Falling P12V POR Threshold
8.80
-
9.75
V
POWER-ON RESET
OSCILLATOR AND SOFT-START
PWM Frequency
fOSC
220
250
280
kHz
Ramp Amplitude
VOSC
-
1.5
-
V
Error Amp Reset Time
tRESET
S5# LOW to S5# HIGH
6.5
-
9.5
ms
tSS
S5# LOW to S5# HIGH
6.5
-
9.5
ms
-
0.800
-
V
-2.0
-
+2.0
%
-
80
-
dB
GBWP
15
-
-
MHz
SR
-
6
-
V/s
S3# Transition Level
VS3
-
1.5
-
V
S5# Transition Level
VS5
-
1.5
-
V
VDDQ Soft-Start Interval
REFERENCE VOLTAGE
Reference Voltage
VREF
System Accuracy
PWM CONTROLLER ERROR AMPLIFIER
DC Gain
Gain-Bandwidth Product
Slew Rate
Guaranteed By Design
STATE LOGIC
FN9120 Rev 3.00
Jul 2004
Page 5 of 15
ISL6532B
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams and Typical Application Schematics (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PWM CONTROLLER GATE DRIVERS
UGATE and LGATE Source
IGATE
-
-0.8
-
A
UGATE and LGATE Sink
IGATE
-
0.8
-
A
-
-
6
mA
9.0
9.5
10
V
P5VSBY = 5.0V
-
-
650
mA
P5VSBY = 3.3V
-
-
550
mA
NCH BACKFEED CONTROL
NCH Current Sink
INCH
NCH Trip Level
VNCH
NCH = 0.8V
VDDQ STANDBY LDO
Output Drive Current
VTT REGULATOR
Upper Divider Impedance
RU
-
2.5
-
k
Lower Divider Impedance
RL
-
2.5
-
k
IVREF_OUT
-
-
2
mA
-3
-
3
A
-3.3
-
3.3
A
VREF_OUT Buffer Source Current
Maximum VTT Load Current
IVTT_MAX
Periodic load applied with 30% duty cycle
and 10ms period using ISL6532EVAL1
evaluation board (see Application Note
AN1055)
VTT Over Current Trip
ITRIP_VTT
By Design
PGOOD
PGOOD Rising Threshold
VVTTSNS/VVDDQ S3# & S5# HIGH
-
57.5
-
%
PGOOD Falling Threshold
VVTTSNS/VVDDQ S3# & S5# HIGH
-
45.0
-
%
PROTECTION
VDDQ OV Level
VFB/VREF
S3# & S5# HIGH
-
115
-
%
VDDQ UV Level
VFB/VREF
S3# & S5# HIGH
-
85
-
%
By Design
-
140
-
°C
Thermal Shutdown Limit
TSD
Functional Pin Description
P5VSBY (Pin 8)
5VSBY (Pin 1)
This pin provides the VDDQ output power during the S3 sleep
state. The regulator is capable of providing standby VDDQ
power from either a 5V or 3.3V source.
5VSBY is the bias supply of the ISL6532B. It is typically
connected to the 5V standby rail of an ATX power supply.
During S4/S5 sleep states the ISL6532B enters a reduced
power mode and draws less than 1mA (ICC5) from the 5VSBY
supply. This pin should be locally bypassed using a 0.1F
capacitor.
P12V (Pin 18)
P12V provides the gate drive current to the switching
MOSFETs of the PWM power stage. The VTT regulation circuit
is also powered by P12V. P12V is only required during
S0/S1/S2 operation. P12V is typically connected to the +12V
rail of an ATX power supply.
FN9120 Rev 3.00
Jul 2004
GND (Pin 2, 13, 21)
The GND terminals of the ISL6532B provide the return path for
the VTT LDO, Standby LDO and switching MOSFET gate
drivers. High ground currents are conducted directly through
the exposed paddle of the QFN package which must be
electrically connected to the ground plane through a path as
low in inductance as possible.
UGATE (Pin 20)
UGATE drives the upper (control) FET of the VDDQ
synchronous buck switching regulator. UGATE is driven
between GND and P12V.
Page 6 of 15
ISL6532B
LGATE (Pin 19)
LGATE drives the lower (synchronous) FET of the VDDQ
synchronous buck switching regulator. LGATE is driven
between GND and P12V.
FB (Pin 11) and COMP (Pin 12)
The VDDQ switching regulator employs a single voltage control
loop. FB is the negative input to the voltage loop error
amplifier. The positive input of the error amplifier is connected
to a precision 0.8V reference and the output of the error
amplifier is connected to the COMP pin. The VDDQ output
voltage is set by an external resistor divider connected to FB.
With a properly selected divider, VDDQ can be set to any
voltage between the power rail (reduced by converter losses)
and the 0.8V reference. Loop compensation is achieved by
connecting an AC network across COMP and FB.
The FB pin is also monitored for under and over-voltage
events.
VDDQ (Pins 5, 6)
The VDDQ pins should be connected externally together to the
regulated VDDQ output. During S0/S1 states, the VDDQ pins
serve as inputs to the VTT regulator and to the VTT Reference
precision divider. During S3 (Suspend to RAM) state, the
VDDQ pins serve as an output from the integrated standby
LDO.
The calculated capacitance, CSS, will charge the output
capacitor bank on the VTT rail in a controlled manner without
reaching the current limit of the VTT LDO.
NCH (Pin 15)
NCH is an open-drain output that controls the MOSFET
blocking backfeed from VDDQ to the input rail during sleep
states. A 2k or larger resistor is to be tied between the 12V
rail and the NCH pin. Until the voltage on the NCH pin reaches
the NCH trip level, the PWM is disabled.
If NCH is not actively utilized, it still must be tied to the 12V rail
through a resistor. For systems using 5V dual as the input to
the switching regulator, a time constant, in the form of a
capacitor, can be added to the NCH pad to delay start of the
PWM switcher until the 5V dual has switched from 5VSBY to
5VATX.
PGOOD (Power Good) (Pin 14)
Power Good is an open-drain logic output that changes to a
logic low if the VTT regulator is out of regulation in S0/S1/S2
state. PGOOD will always be low in any state other than
S0/S1/S2.
S5# (Pin 17)
This pin accepts the SLP_S5# sleep state signal.
S3# (Pin 16)
VTT (Pins 3, 4)
This pin accepts the SLP_S3# sleep state signal.
The VTT pins should be connected together. During S0/S1
states, the VTT pins serve as the outputs of the VTT linear
regulator. During any sleep state, the VTT regulator is disabled.
Functional Description
VTTSNS (Pin 7)
The ISL6532B provides complete control, drive, protection and
ACPI compliance for a regulator powering DDR memory
systems. It is primarily designed for computer applications
powered from an ATX power supply. A 250kHz Synchronous
Buck Regulator with a precision 0.8V reference provides the
proper Core voltage to the system memory of the computer. An
internal LDO regulator with the ability to both sink and source
current and an externally available buffered reference that
tracks the VDDQ output by 50% provides the VTT termination
voltage.
VTTSNS is used as the feedback for control of the VTT linear
regulator. Connect this pin to the VTT output at the physical
point of desired regulation.
VREF_OUT (Pin 9)
VREF_OUT is a buffered version of VTT and also acts as the
reference voltage for the VTT linear regulator. It is
recommended that a minimum capacitance of 0.1F be
connected between VDDQ and VREF_OUT and also between
VREF_OUT and GND for proper operation.
VREF_IN (Pin 10)
A capacitor, CSS, connected between VREF_IN and ground is
required. This capacitor and the parallel combination of the
Upper and Lower Divider Impedance (RU||RL), sets the time
constant for the start up ramp when transitioning from S3 to
S0/S1/S2.
The minimum value for CSS can be found through the following
equation:
C VTTOUT V DDQ
C SS -----------------------------------------------10 2A R U R L
FN9120 Rev 3.00
Jul 2004
Overview
ACPI compliance is realized through the SLP_S3 and SLP_S5
sleep signals and through monitoring of the 12V ATX bus.
Initialization
The ISL6532B automatically initializes upon receipt of input
power. Special sequencing of the input supplies is not
necessary. The Power-On Reset (POR) function continually
monitors the input bias supply voltages. The POR monitors the
bias voltage at the 5VSBY and P12V pins. The POR function
initiates soft-start operation after the bias supply voltages
exceed their POR thresholds.
Page 7 of 15
ISL6532B
ACPI State Transitions
Cold Start (S5/S4 to S0 Transition)
At the onset of a mechanical start, the ISL6532B receives it’s
bias voltage from the 5V Standby bus (5VSBY). As soon as the
SLP_S3 and SLP_S5 signals have transitioned HIGH, the
ISL6532B starts an internal counter. Following a cold start or
any subsequent S5 state, state transitions are ignored until the
system enters S0/S1. None of the regulators will begin the soft
start procedure until the 5V Standby bus has exceeded POR,
the 12V bus has exceeded POR and VNCH has exceeded the
trip level.
Once all of these conditions are met, the PWM error amplifier
will first be reset by internally shorting the COMP pin to the FB
pin. This reset lasts for 2048 clock cycles which is typically
8.2ms (one clock cycle = 1/fOSC). The digital soft start
sequence will then begin.
The PWM error amplifier reference input is clamped to a level
proportional to the soft-start voltage. As the soft-start voltage
slews up, the PWM comparator generates PHASE pulses of
increasing width that charge the output capacitor(s). The internal
VTT LDO will also soft start through the reference that tracks
the output of the PWM regulator. The soft start lasts for 2048
clock cycles, which is typically 8.2ms. This method provides a
rapid and controlled output voltage rise.
Figure 1 shows the soft start sequence for a typical cold start.
Due to the soft start capacitance, CSS, on the VREF_IN pin,
the S5 to S0 transition profile of the VTT rail will have a more
rounded features at the start and end of the soft start whereas
the VDDQ profile has distinct starting and ending points to the
ramp up.
S3
S5
12VATX 2V/DIV
5VSBY
1V/DIV
VDDQ
500mV/DIV
VTT
500mV/DIV
PGOOD
5V/DIV
2048 CLOCK
CYCLES
12V POR
2048 CLOCK
CYCLES
SOFT START ENDS
SOFT START
PGOOD COMPARATOR
INITIATES
ENABLED
FIGURE 1. TYPICAL COLD START
By directly monitoring 12VATX and the SLP_S3 and SLP_S5
signals, the ISL6532B can achieve PGOOD status significantly
faster than other devices that depend on the
Latched_Backfeed_Cut signal for timing.
Active to Sleep (S0 to S3 Transition)
When SLP_S3 goes LOW with SLP_S5 still HIGH, the
ISL6532B will disable the VTT linear regulator. The VDDQ
standby regulator will be enabled and the VDDQ switching
regulator will be disabled. NCH is pulled low to disable the
backfeed blocking MOSFET. PGOOD will also transition LOW.
When VTT is disabled, the internal reference for the VTT
regulator is internally shorted to the VTT rail. This allows the
VTT rail to float. When floating, the voltage on the VTT rail will
depend on the leakage characteristics of the memory and
MCH I/O pins. It is important to note that the VTT rail may not
bleed down to 0V.
The VDDQ rail will be supported in the S3 state through the
standby VDDQ LDO. When S3 transitions LOW, the Standby
regulator is immediately enabled. The switching regulator is
disabled synchronous to the switching waveform. The shut off
time will range between 4 and 8s. The standby LDO is
capable of supporting up to 650mA of load with P5VSBY tied
to the 5V Standby Rail. The standby LDO may receive input
from either the 3.3V Standby rail or the 5V Standby rail through
the P5VSBY pin. It is recommended that the 5V Standby rail
be used as the current delivery capability of the LDO is greater.
Sleep to Active (S3 to S0 Transition)
When SLP_S3 transitions from LOW to HIGH with SLP_S5
held HIGH and after the 12V rail exceeds POR, the ISL6532B
will enable the VDDQ switching regulator, disable the VDDQ
standby regulator, enable the VTT LDO and force the NCH pin
to a high impedance state turning on the blocking MOSFET.
The internal short between the VTT reference and the VTT rail
is released. Upon release of the short, the capacitor on
VREF_IN is then charged up through the internal resistor
divider network. The VTT output will follow this capacitor
charge-up, acting as the S3 to S0 transition soft start for the
VTT rail. The PGOOD comparator is enabled only after 2048
clock cycles, or typically 8.2ms, have passed following the S3
transition to a HIGH state.
Figure 2 illustrates a typical state transition from S3 to S0. It
should be noted that the soft start profile of the VTT LDO
output will vary according to the value of the capacitor on the
VREF_IN pin.
Active to Shutdown (S0 to S4/S5 Transition)
When the system transitions from active, S0, state to
shutdown, S4/S5, state, the ISL6532B IC disables all
regulators and forces the PGOOD pin and the NCH pin LOW.
VTT Over Current Protection
The internal VTT LDO is protected from fault conditions
through a 3.3A current limit. This current limit protects the
ISL6532B if the LDO is sinking or sourcing current. During an
FN9120 Rev 3.00
Jul 2004
Page 8 of 15
ISL6532B
VDDQ
S3
S5
12VATX 2V/DIV
VDDQ
VTT FLOATING
500mV/DIV
VTT
500mV/DIV
VTT
500mV/DIV
INTERNAL DELAY
PGOOD
5V/DIV
12V POR
FIGURE 2. TYPICAL S3 TO S0 STATE TRANSITION
overcurrent event on the VTT LDO, only the VTT LDO is
disabled. Once the over current condition on the VTT rail is
removed, VTT will recover.
Over/Under Voltage Protection.
Both the internal VTT LDO and the VDDQ regulator are
protected from faults through internal Over/Under voltage
detection circuitry. If either rail falls below 85% of the targeted
voltage, then an undervoltage event is tripped. An under voltage
will disable all regulators for a period of 3 soft-start cycles, after
which a normal soft-start is initiated. If the output remains under
85% of target, the regulators will continue to be disabled and
soft-started in a hiccup mode until the fault is cleared. See
Figure 3.
If either rail exceeds 115% of the targeted voltage, then all
outputs are immediately disabled. The ISL6532B will not reenable the outputs until either the bias voltage is toggled in
order to initiate a POR or the SLP_S5 signal is forced LOW
and then back to HIGH.
Thermal Protection (S0/S3 State)
If the ISL6532B IC junction temperature reaches a nominal
temperature of 140oC, all regulators will be disabled. The
ISL6532B will not re-enable the outputs until the junction
temperature drops below 110oC and either the bias voltage is
toggled in order to initiate a POR or the SLP_S5 signal is
forced LOW and then back to HIGH.
Shoot-Through Protection
A shoot-through condition occurs when both the upper and
lower MOSFETs are turned on simultaneously, effectively
shorting the input voltage to ground. To protect from a shootthrough condition, the ISL6532B incorporates specialized
circuitry which insures that complementary MOSFETs are not
ON simultaneously.
FN9120 Rev 3.00
Jul 2004
DELAY INTERVAL
2048 CLOCK
CYCLES
PGOOD COMPARATOR
ENABLED
T1
T0
T2
TIME
FIGURE 3. VTT/VDDQ LDO UNDER VOLTAGE PROTECTION
RESPONSES
The adaptive shoot-through protection utilized by the VDDQ
regulator looks at the lower gate drive pin, LGATE, and the
upper gate drive pin, UGATE, to determine whether a
MOSFET is ON or OFF. If the voltage from UGATE or from
LGATE to GND is less than 0.8V, then the respective MOSFET
is defined as being OFF and the other MOSFET is allowed to
be turned ON. This method allows the VDDQ regulator to both
source and sink current.
Since the voltage of the MOSFET gates are being measured to
determine the state of the MOSFET, the designer is
encouraged to consider the repercussions of introducing
external components between the gate drivers and their
respective MOSFET gates before actually implementing such
measures. Doing so may interfere with the shoot-through
protection.
Application Guidelines
Layout Considerations
Layout is very important in high frequency switching converter
design. With power devices switching efficiently at 250kHz, the
resulting current transitions from one device to another cause
voltage spikes across the interconnecting impedances and
parasitic circuit elements. These voltage spikes can degrade
efficiency, radiate noise into the circuit, and lead to device
over-voltage stress. Careful component layout and printed
circuit board design minimizes these voltage spikes.
As an example, consider the turn-off transition of the upper
MOSFET. Prior to turn-off, the MOSFET is carrying the full
load current. During turn-off, current stops flowing in the
MOSFET and is picked up by the lower MOSFET. Any
Page 9 of 15
ISL6532B
12VATX
ISL6532B
NCH
The switching components should be placed close to the
ISL6532B first. Minimize the length of the connections between
the input capacitors, CIN, and the power switches by placing
them nearby. Position both the ceramic and bulk input
capacitors as close to the upper MOSFET drain as possible.
Position the output inductor and output capacitors between the
upper and lower MOSFETs and the load.
The critical small signal components include any bypass
capacitors, feedback components, and compensation
components. Place the PWM converter compensation
components close to the FB and COMP pins. The feedback
resistors should be located as close as possible to the FB pin
with vias tied straight to the ground plane as required.
Feedback Compensation - PWM Buck Converter
Figure 5 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(VOUT) is regulated to the Reference voltage level. The error
amplifier output (VE/A) is compared with the oscillator (OSC)
triangular wave to provide a pulse-width modulated (PWM)
wave with an amplitude of VIN at the PHASE node. The PWM
wave is smoothed by the output filter (LO and CO).
FN9120 Rev 3.00
Jul 2004
5VSBY
P5VSBY
5VSBY
GND
CIN
CBP
UGATE
Q1 LOUT
LGATE
COMP
Q2
C2
COUT1
C1
R2
R1
FB
R4
C3 R3
VDDQ(2)
VDDQ
VTT(2)
VTT
COUT2
GND PAD
VDDQ
LOAD
In order to dissipate heat generated by the internal VTT LDO,
the ground pad, pin 21, should be connected to the internal
ground plane through at least four vias. This allows the heat to
move away from the IC and also ties the pad to the ground
plane through a low impedance path.
VIN_DDR
GND
There are two sets of critical components in the ISL6532B
switching converter. The switching components are the most
critical because they switch large amounts of energy, and
therefore tend to generate large amounts of noise. Next are the
small signal components which connect to sensitive nodes or
supply critical bypass current and signal coupling.
A multi-layer printed circuit board is recommended. Figure 4
shows the connections of the critical components in the
converter. Note that capacitors CIN and COUT could each
represent numerous physical capacitors. Dedicate one solid
layer, usually a middle layer of the PC board, for a ground
plane and make all critical component ground connections with
vias to this layer. Dedicate another solid layer as a power
plane and break this plane into smaller islands of common
voltage levels. Keep the metal runs from the PHASE terminals
to the output inductor short. The power plane should support
the input power and output power nodes. Use copper filled
polygons on the top and bottom circuit layers for the phase
nodes. Use the remaining printed circuit layers for small signal
wiring. The wiring traces from the GATE pins to the MOSFET
gates should be kept short and wide enough to easily handle
the 1A of drive current.
CBP
P12V
LOAD
parasitic inductance in the switched current path generates a
large voltage spike during the switching interval. Careful
component selection, tight layout of the critical components,
and short, wide traces minimizes the magnitude of voltage
spikes.
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 4. PRINTED CIRCUIT BOARD POWER PLANES
AND ISLANDS
The modulator transfer function is the small-signal transfer
function of VOUT/VE/A . This function is dominated by a DC
Gain and the output filter (LO and CO), with a double pole
break frequency at FLC and a zero at FESR . The DC Gain of
the modulator is simply the input voltage (VIN) divided by the
peak-to-peak oscillator voltage VOSC .
Modulator Break Frequency Equations
1
F LC = ------------------------------------------2 x L O x C O
1
F ESR = -------------------------------------------2 x ESR x C O
The compensation network consists of the error amplifier
(internal to the ISL6532B) and the impedance networks ZIN
and ZFB. The goal of the compensation network is to provide a
closed loop transfer function with the highest 0dB crossing
frequency (f0dB) and adequate phase margin. Phase margin is
the difference between the closed loop phase at f0dB and 180
degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R1 , R2 ,
R3 , C1 , C2 , and C3) in Figure 5. Use these guidelines for
locating the poles and zeros of the compensation network:
Page 10 of 15
ISL6532B
VIN
PWM
COMPARATOR
LO
-
VOSC
DRIVER
+
PHASE
VDDQ
CO
ESR
(PARASITIC)
ZFB
VE/A
-
ZIN
+
ERROR
AMP
REFERENCE
DETAILED COMPENSATION COMPONENTS
ZFB
C1
C2
C3
FB
+
R4
ISL6532B
REFERENCE
R
V DDQ = 0.8 1 + ------1-
R 4
FZ1 FZ2
FP1
FP2
80
OPEN LOOP
ERROR AMP GAIN
60
40
20
20LOG
(R2/R1)
20LOG
(VIN/VOSC)
0
COMPENSATION
GAIN
MODULATOR
GAIN
-20
-40
-60
CLOSED LOOP
GAIN
FLC
10
100
1K
FESR
10K
100K
1M
10M
FREQUENCY (Hz)
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
1. Pick Gain (R2/R1) for desired converter bandwidth.
2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC).
3. Place 2ND Zero at Filter’s Double Pole.
4. Place 1ST Pole at the ESR Zero.
5. Place 2ND Pole at Half the Switching Frequency.
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
Compensation Break Frequency Equations
1
F Z1 = -----------------------------------2 x R 2 x C 2
1
F P1 = -------------------------------------------------------- C 1 x C 2
2 x R 2 x ----------------------
C1 + C2
1
F Z2 = ------------------------------------------------------2 x R 1 + R 3 x C 3
1
F P2 = -----------------------------------2 x R 3 x C 3
Figure 6 shows an asymptotic plot of the DC-DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 6. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at FP2 with the capabilities of the error
amplifier. The Closed Loop Gain is constructed on the graph of
FN9120 Rev 3.00
Jul 2004
100
R3
R1
COMP
The compensation gain uses external impedance networks
ZFB and ZIN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
VDDQ
ZIN
R2
Figure 6 by adding the Modulator Gain (in dB) to the
Compensation Gain (in dB). This is equivalent to multiplying
the modulator transfer function to the compensation transfer
function and plotting the gain.
GAIN (dB)
DRIVER
OSC
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Output Voltage Selection
The output voltage of the VDDQ PWM converter can be
programmed to any level between VIN and the internal
reference, 0.8V. An external resistor divider is used to scale
the output voltage relative to the reference voltage and feed it
back to the inverting input of the error amplifier, see Figure 6.
However, since the value of R1 affects the values of the rest of
the compensation components, it is advisable to keep its value
less than 5k. Depending on the value chosen for R1, R4 can
be calculated based on the following equation:
R1 0.8V
R4 = ----------------------------------V DDQ – 0.8V
If the output voltage desired is 0.8V, simply route VDDQ back
to the FB pin through R1, but do not populate R4.
The output voltage for the internal VTT linear regulator is set
internal to the ISL6532B to track the VDDQ voltage by 50%.
There is no need for external programming resistors.
Component Selection Guidelines
Output Capacitor Selection - PWM Buck Converter
An output capacitor is required to filter the inductor current and
supply the load transient current. The filtering requirements are
Page 11 of 15
ISL6532B
a function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew rate
(di/dt) and the magnitude of the transient load current. These
requirements are generally met with a mix of capacitors and
careful layout.
Output Capacitor Selection - LDO Regulator
DDR memory systems are capable of producing transient load
rates above 1A/ns. High frequency capacitors initially supply the
transient and slow the current load rate seen by the bulk
capacitors. The bulk filter capacitor values are generally
determined by the ESR (Effective Series Resistance) and
voltage rating requirements rather than actual capacitance
requirements.
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function of
the ripple current. The ripple voltage and current are
approximated by the following equations:
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for switchingregulator applications for the bulk capacitors. The bulk
capacitor’s ESR will determine the output ripple voltage and the
initial voltage drop after a high slew-rate transient. An aluminum
electrolytic capacitor’s ESR value is related to the case size with
lower ESR available in larger case sizes. However, the
Equivalent Series Inductance (ESL) of these capacitors
increases with case size and can reduce the usefulness of the
capacitor to high slew-rate transient loading. Unfortunately, ESL
is not a specified parameter. Work with your capacitor supplier
and measure the capacitor’s impedance with frequency to select
a suitable component. In most cases, multiple electrolytic
capacitors of small case size perform better than a single large
case capacitor.
The output capacitors used in LDO regulators are used to
provide dynamic load current. The amount of capacitance and
type of capacitor should be chosen with this criteria in mind.
Output Inductor Selection
I =
VIN - VOUT
Fs x L
x
VOUT
VIN
VOUT = I x ESR
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce the
converter’s response time to a load transient.
One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6532B will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
The response time to a transient is different for the application
of load and the removal of load. The following equations give
the approximate response time interval for application and
removal of a transient load:
tRISE =
L x ITRAN
VIN - VOUT
tFALL =
L x ITRAN
VOUT
where: ITRAN is the transient load current step, tRISE is the
response time to the application of load, and tFALL is the
response time to the removal of load. The worst case response
time can be either at the application or removal of load. Be
sure to check both of these equations at the minimum and
maximum output levels for the worst case response time.
Input Capacitor Selection - PWM Buck Converter
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic capacitors
for high frequency decoupling and bulk capacitors to supply
the current needed each time the upper MOSFET turns on.
Place the small ceramic capacitors physically close to the
MOSFETs, between the drain of upper MOSFET and the
source of lower MOSFET.
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
FN9120 Rev 3.00
Jul 2004
Page 12 of 15
ISL6532B
ratings above the maximum input voltage and largest RMS
current required by the circuit. Their voltage rating should be at
least 1.25 times greater than the maximum input voltage, while
a voltage rating of 1.5 times is a conservative guideline. For
worst cases, the RMS current rating requirement for the input
capacitor of a buck regulator is approximately 1/2 the DC
output load current.
The maximum RMS current required by the regulator may be
closely approximated through the following equation:
I RMS
MAX
=
2
V OUT
2
1 V IN – V OUT V OUT
---------------- I OUT
+ ------ -------------------------------- ----------------
V IN
V IN
12 L f sw
MAX
For a through hole design, several electrolytic capacitors may
be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised with
regard to the capacitor surge current rating. These capacitors
must be capable of handling the surge-current at power-up.
Some capacitor series available from reputable manufacturers
are surge current tested.
MOSFET Selection - PWM Buck Converter
The ISL6532B requires 2 N-Channel power MOSFETs for
switching power and a third MOSFET to block backfeed from
VDDQ to the Input in S3 Mode. These should be selected based
upon rDS(ON) , gate supply requirements, and thermal
management requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss components;
conduction loss and switching loss. The conduction losses are
the largest component of power dissipation for both the upper
and the lower MOSFETs. These losses are distributed
between the two MOSFETs according to duty factor. The
switching losses seen when sourcing current will be different
from the switching losses seen when sinking current. When
sourcing current, the upper MOSFET realizes most of the
switching losses. The lower switch realizes most of the
switching losses when the converter is sinking current (see the
equations below). These equations assume linear voltagecurrent transitions and do not adequately model power loss
due the reverse-recovery of the upper and lower MOSFET’s
body diode. The gate-charge losses are dissipated in part by
the ISL6532B and do not significantly heat the MOSFETs.
However, large gate-charge increases the switching interval,
tSW which increases the MOSFET switching losses. Ensure
that both MOSFETs are within their maximum junction
temperature at high ambient temperature by calculating the
temperature rise according to package thermal-resistance
specifications. A separate heatsink may be necessary
depending upon MOSFET power, package type, ambient
temperature and air flow.
Approximate Losses while Sourcing current
2
1
P UPPER = Io r DS ON D + --- Io V IN t SW f s
2
PLOWER = Io2 x rDS(ON) x (1 - D)
Approximate Losses while Sinking current
PUPPER = Io2 x rDS(ON) x D
2
1
P LOWER = Io r DS ON 1 – D + --- Io V IN t SW f s
2
Where: D is the duty cycle = VOUT / VIN ,
tSW is the combined switch ON and OFF time, and
fs is the switching frequency.
FN9120 Rev 3.00
Jul 2004
Page 13 of 15
ISL6532B
ISL6532B Application Circuit
Materials and circuit board description, can be found in
Application Note AN1055.
Figure 7 shows an application circuit utilizing the ISL6532B.
Detailed information on the circuit, including a complete Bill-of-
5VSBY
VCC12
+3.3V
C17,18
1F
VDDQ
VREF
S5
SLP_S5#
S3
SLP_S3#
C4,5
1F
VREF_OUT
UGATE
C19
0.47F
+
C1-3
2200F
VDDQ
2.5V
L2
2.1H
ISL6532B
LGATE
C20 +
220F
+
Q1,3
VREF_IN
VDDQ
1.25V
L1
2.1H
NCH
C26
0.1F
C27
0.1F
VTT
P12V
PGOOD
P5VSBY
PGOOD
Q5
C16
1F
5VSBY
R2
10.0k
VCC5
R1
4.99k
Q2,4
VDDQ
VDDQ
VTT
VTT
C21
220F
GND
C9-12
22F
1.74k
COMP
GND
C6-8
1800F
R4
FB
VTTSNS
+
C15
1000pF
C14
6.8nF
R3
19.1k
C13
56nF
R5
22.6
R6
825
FIGURE 7. DDR SDRAM AND AGP VOLTAGE REGULATOR USING THE ISL6532B
© Copyright Intersil Americas LLC 2003-2004. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9120 Rev 3.00
Jul 2004
Page 14 of 15
ISL6532B
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L20.6x6
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VJJB ISSUE C)
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.80
0.90
1.00
-
A1
-
-
0.05
-
A2
-
-
1.00
A3
b
0.28
D
0.33
9
0.40
5, 8
6.00 BSC
D1
D2
9
0.20 REF
-
5.75 BSC
3.55
3.70
9
3.85
7, 8
E
6.00 BSC
-
E1
5.75 BSC
9
E2
3.55
e
3.70
3.85
7, 8
0.80 BSC
-
k
0.25
-
-
-
L
0.35
0.60
0.75
8
L1
-
-
0.15
10
N
20
2
Nd
5
3
Ne
5
3
P
-
-
0.60
9
-
-
12
9
Rev. 1 10/02
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
FN9120 Rev 3.00
Jul 2004
Page 15 of 15