LINER LTC1197LIS8 10-bit, 500ksps adcs in msop with auto shutdown Datasheet

LTC1197/LTC1197L
LTC1199/LTC1199L
10-Bit, 500ksps ADCs in
MSOP with Auto Shutdown
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FEATURES
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DESCRIPTIO
8-Pin MSOP and SO Packages
10-Bit Resolution at 500ksps
Single Supply: 5V or 3V
Low Power at Full Speed:
25mW Typ at 5V
2.2mW Typ at 2.7V
Auto Shutdown Reduces Power Linearly
at Lower Sample Rates
10-Bit Upgrade to 8-Bit LTC1196/LTC1198
SPI and MICROWIRETM Compatible Serial I/O
Low Cost
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APPLICATIO S
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High Speed Data Acquisition
Portable or Compact Instrumentation
Low Power or Battery-Operated Instrumentation
The LTC ®1197/LTC1197L/LTC1199/LTC1199L are
10-bit A/D converters with sampling rates up to 500kHz.
They have 2.7V (L) and 5V versions and are offered in
8-pin MSOP and SO packages. Power dissipation is typically only 2.2mW at 2.7V (25mW at 5V) during full speed
operation. The automatic power down reduces supply
current linearly as sample rate is reduced. These 10-bit,
switched-capacitor, successive approximation ADCs include a sample-and-hold. The LTC1197/LTC1197L have a
differential analog input with an adjustable reference pin.
The LTC1199/LTC1199L offer a software-selectable
2-channel MUX.
The 3-wire serial I/O, MSOP and SO-8 packages, 2.7V
operation and extremely high sample rate-to-power ratio
make these ADCs ideal choices for compact, low power
high speed systems.
These circuits can be used in ratiometric applications or
with external references. The high impedance analog
inputs and the ability to operate with reduced spans below
1V full scale (LTC1197/LTC1197L) allow direct connection to signal sources in many applications, eliminating
the need for gain stages.
, LTC and LT are registered trademarks of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
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TYPICAL APPLICATIO
Supply Current vs Sampling Frequency
Single 2.7V Supply, 250ksps, 10-Bit Sampling ADC
10000
1µF
LTC1197L
1
2
ANALOG INPUT
0V TO 2.7V RANGE 3
4
CS
VCC
+IN
CLK
– IN
DOUT
GND
VREF
8
7
6
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
SUPPLY CURRENT (µA)
1000
2.7V
VCC = 5V
fCLK = 7.2MHz
100
10
VCC = 2.7V
fCLK = 3.5MHz
1
5
1197/99 TA01
0.1
0.01
0.1
10
100
1
SAMPLING FREQUENCY (kHz)
1000
1197/99 G03
1
LTC1197/LTC1197L
LTC1199/LTC1199L
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ABSOLUTE
RATI GS
(Notes 1, 2)
Supply Voltage (VCC) ............................................... 12V
Voltage
Analog Input ..................... GND – 0.3V to VCC + 0.3V
Digital Input ................................ GND – 0.3V to 12V
Digital Output .................... GND – 0.3V to VCC + 0.3V
Power Dissipation .............................................. 500mW
Storage Temperature Range ................. – 65°C to 150°C
Operating Temperature Range
LTC1197C/LTC1197LC
LTC1199C/LTC1199LC........................... 0°C to 70°C
LTC1197I/LTC1197LI
LTC1199I/LTC1199LI ........................ – 45°C to 85°C
Lead Temperature (Soldering, 10 sec)................. 300°C
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PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
TOP VIEW
CS
+IN
–IN
GND
8
7
6
5
1
2
3
4
VCC
CLK
DOUT
VREF
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 210°C/W
LTC1197CMS8
LTC1197IMS8
LTC1197LCMS8
LTC1197LIMS8
CS 1
8 VCC
+IN 2
7 CLK
– IN 3
6 DOUT
GND 4
5 VREF
TOP VIEW
8
7
6
5
1
2
3
4
VCC
CLK
DOUT
DIN
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 210°C/W
LTBL
LTJA
1197
1197I
CS 1
8 VCC
CH0 2
7 CLK
CH1 3
6 DOUT
GND 4
5 DIN
LTC1199CS8
LTC1199IS8
LTC1199LCS8
LTC1199LIS8
S8 PACKAGE
8-LEAD PLASTIC SO
MS8 PART MARKING
S8 PART MARKING
TJMAX = 150°C, θJA = 175°C/W
LTCM
LTWC
1197L
1197LI
ORDER PART
NUMBER
TOP VIEW
LTC1199CMS8
LTC1199IMS8
LTC1199LCMS8
LTC1199LIMS8
LTFL
LTWB
S8 PART MARKING
TJMAX = 150°C, θJA = 175°C/W
ORDER PART
NUMBER
CS
CH0
CH1
GND
LTC1197CS8
LTC1197IS8
LTC1197LCS8
LTC1197LIS8
S8 PACKAGE
8-LEAD PLASTIC SO
MS8 PART MARKING
LTKV
LTKW
ORDER PART
NUMBER
TOP VIEW
1199L
1199LI
1199
1199I
Consult factory for parts specified with wider operating temperature ranges.
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RECO
E DED OPERATI G CO DITIO S The ● denotes the specifications which apply over
the full operating temperature range, otherwise specifications are at TA = 25°C.
SYMBOL PARAMETER
VCC
CONDITIONS
MIN
Supply Voltage
LTC1197
TYP
MAX
MIN
LTC1199
TYP
MAX
4
9
4
6
0.05
7.2
0.05
7.2
UNITS
V
VCC = 5V Operation
fCLK
Clock Frequency
tCYC
Total Cycle Time
14
16
CLK
tSMPL
Analog Input Sampling Time
1.5
1.5
CLK
thCS
Hold Time CS Low After Last CLK↑
13
13
ns
2
●
MHz
LTC1197/LTC1197L
LTC1199/LTC1199L
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RECO
E DED OPERATI G CO DITIO S The ● denotes the specifications which apply over
the full operating temperature range, otherwise specifications are at TA = 25°C.
SYMBOL PARAMETER
CONDITIONS
MIN
LTC1197
TYP
MAX
MIN
LTC1199
TYP
MAX
UNITS
VCC = 5V Operation
tsuCS
Setup Time CS↓ Before First CLK↑
(See Figures 1, 2)
thDI
Hold Time DIN After CLK↑
tsuDI
26
ns
LTC1199
26
ns
Setup Time DIN Stable Before CLK↑
LTC1199
26
ns
tWHCLK
CLK High Time
fCLK = fCLK(MAX)
40%
40%
1/fCLK
tWLCLK
CLK Low Time
fCLK = fCLK(MAX)
40%
40%
1/fCLK
tWHCS
CS High Time Between Data Transfer Cycles
32
32
ns
tWLCS
CS Low Time During Data Transfer
13
15
CLK
SYMBOL PARAMETER
VCC
26
CONDITIONS
MIN
Supply Voltage
LTC1197L
TYP
MAX
MIN
LTC1199L
TYP
MAX
2.7
4
2.7
4
0.01
3.5
0.01
3.5
UNITS
V
VCC = 2.7V Operation
fCLK
Clock Frequency
tCYC
Total Cycle Time
14
16
CLK
tSMPL
Analog Input Sampling Time
1.5
1.5
CLK
thCS
Hold Time CS Low After Last CLK↑
40
40
ns
tsuCS
Setup Time CS↓ Before First CLK↑
(See Figures 1, 2)
78
78
ns
thDI
Hold Time DIN After CLK↑
LTC1199L
78
ns
tsuDI
Setup Time DIN Stable Before CLK↑
LTC1199L
78
ns
tWHCLK
CLK High Time
fCLK = fCLK(MAX)
40%
40%
1/fCLK
tWLCLK
CLK Low Time
fCLK = fCLK(MAX)
40%
40%
1/fCLK
tWHCS
CS High Time Between Data Transfer Cycles
96
96
ns
tWLCS
CS Low Time During Data Transfer
13
15
CLK
●
MHz
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CO VERTER A D
ULTIPLEXER CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 5V, VREF = 5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
PARAMETER
CONDITIONS
Offset Error
MIN
LTC1197
TYP
MAX
MIN
LTC1199
TYP
MAX
±2
●
UNITS
±2
LSB
●
±1
±1
LSB
Gain Error
●
±4
±4
LSB
No Missing Codes Resolution
●
Linearity Error
(Note 3)
10
Analog Input Range
10
Bits
V
– 0.05V to VCC + 0.05V
Reference Input Range
LTC1197, VCC ≤ 6V
LTC1197, VCC > 6V
Analog Input Leakage Current
(Note 4)
0.2
0.2
●
VCC + 0.05V
6
±1
V
V
±1
µA
3
LTC1197/LTC1197L
LTC1199/LTC1199L
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CO VERTER A D
ULTIPLEXER CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 2.7V, VREF = 2.5V (LTC1197L), fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
PARAMETER
CONDITIONS
Offset Error
Linearity Error
(Note 3)
MIN
LTC1197L
TYP
MAX
MIN
LTC1199L
TYP
MAX
±2
±2
LSB
●
±1
±1
LSB
±4
LSB
Gain Error
●
No Missing Codes Resolution
●
±4
10
10
Analog Input Range
Bits
V
– 0.05V to VCC + 0.05V
Reference Input Range
LTC1197L
Analog Input Leakage Current
(Note 4)
UNITS
●
0.2
VCC + 0.05V
V
±1
●
±1
µA
LTC1199
TYP
MAX
UNITS
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DYNAMIC ACCURACY
VCC = 5V, VREF = 5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
LTC1197
TYP
MAX
MIN
S/(N + D) Signal-to-Noise Plus
Distortion Ratio
100kHz Input Signal
60
60
dB
THD
Total Harmonic Distortion
First 5 Harmonics
100kHz Input Signal
– 64
– 64
dB
Peak Harmonic or Spurious Noise
100kHz Input Signal
– 68
– 68
dB
Intermodulation Distortion
fIN1 = 97.046kHz, fIN2 = 102.905kHz
2nd Order Terms
3rd Order Terms
– 65
– 70
– 65
– 70
dB
dB
IMD
VCC = 2.7V, VREF = 2.5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
LTC1197L
TYP
MAX
MIN
LTC1199L
TYP
MAX
UNITS
S/(N + D) Signal-to-Noise Plus
Distortion Ratio
50kHz Input Signal
58
58
dB
THD
Total Harmonic Distortion
First 5 Harmonics
50kHz Input Signal
– 60
– 60
dB
Peak Harmonic or Spurious Noise
50kHz Input Signal
– 63
– 63
dB
Intermodulation Distortion
fIN1 = 48.5kHz, fIN2 = 51.5kHz
2nd Order Terms
3rd Order Terms
– 60
– 65
– 60
– 65
dB
dB
IMD
4
LTC1197/LTC1197L
LTC1199/LTC1199L
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DIGITAL AND DC ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply
over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VREF = 5V, unless otherwise noted.
MIN
LTC1197
TYP
MAX
CONDITIONS
VIH
High Level Input Voltage
VCC = 5.25V
●
VIL
Low Level Input Voltage
VCC = 4.75V
●
IIH
High Level Input Current
VIN = VCC
●
IIL
Low Level Input Current
VIN = 0V
●
VOH
High Level Output Voltage
VCC = 4.75V, IO = 10µA
VCC = 4.75V, IO = 360µA
●
●
VOL
Low Level Output Voltage
VCC = 4.75V, IO = 1.6mA
●
0.4
0.4
V
IOZ
Hi-Z Output Leakage
CS = High
●
±3
±3
µA
ISOURCE
Output Source Current
VOUT = 0V
ISINK
Output Sink Current
VOUT = VCC
IREF
Reference Current (LTC1197)
CS = VCC
fSMPL = fSMPL(MAX)
●
●
0.001
0.5
3
1
ICC
Supply Current
CS = VCC
fSMPL = fSMPL(MAX)
●
●
0.001
4.5
3
8
PD
Power Dissipation
fSMPL = fSMPL(MAX)
2.4
MIN
LTC1199
TYP
MAX
SYMBOL PARAMETER
V
0.8
4.5
2.4
UNITS
2.4
0.8
V
2.5
2.5
µA
– 2.5
– 2.5
µA
4.74
4.72
4.5
2.4
– 25
45
4.74
4.72
V
V
– 25
mA
45
mA
µA
mA
0.001
5
22.5
µA
mA
3
8.5
25
mW
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 2.7V, VREF = 2.5V, unless otherwise noted.
MIN
LTC1197L
TYP
MAX
CONDITIONS
VIH
High Level Input Voltage
VCC = 3.6V
●
VIL
Low Level Input Voltage
VCC = 2.7V
●
0.45
0.45
V
IIH
High Level Input Current
VIN = VCC
●
2.5
2.5
µA
IIL
Low Level Input Current
VIN = 0V
●
– 2.5
– 2.5
µA
VOH
High Level Output Voltage
VCC = 2.7V, IO = 10µA
VCC = 2.7V, IO = 360µA
●
●
VOL
Low Level Output Voltage
VCC = 2.7V, IO = 400µA
●
0.3
0.3
V
IOZ
Hi-Z Output Leakage
CS = High
●
±3
±3
µA
ISOURCE
Output Source Current
VOUT = 0V
– 6.5
– 6.5
mA
ISINK
Output Sink Current
VOUT = VCC
11
11
mA
IREF
Reference Current (LTC1197L)
CS = VCC
fSMPL = fSMPL(MAX)
●
●
0.001
0.250
3.0
0.5
ICC
Supply Current
CS = VCC
fSMPL = fSMPL(MAX)
●
●
0.001
0.8
3
2
PD
Power Dissipation
fSMPL = fSMPL(MAX)
1.9
2.3
2.1
MIN
LTC1199L
TYP
MAX
SYMBOL PARAMETER
1.9
2.60
2.45
2.2
2.3
2.1
UNITS
V
2.60
2.45
V
V
µA
mA
0.001
0.8
2.2
3
2
µA
mA
mW
5
LTC1197/LTC1197L
LTC1199/LTC1199L
AC CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 5V, VREF = 5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
tCONV
Conversion Time (See Figures 1, 2)
●
fSMPL(MAX)
Maximum Sampling Frequency
●
tdDO
Delay Time, CLK↑ to DOUT Data Valid CLOAD = 20pF
LTC1197
TYP
MAX
MIN
LTC1199
TYP
MAX
1.4
500
UNITS
µs
1.4
450
kHz
68
78
100
68
78
100
ns
ns
75
150
75
150
ns
40
68
40
68
ns
●
tdis
Delay Time, CS↑ to DOUT Hi-Z
ten
Delay Time, CLK↓ to DOUT Enabled
CLOAD = 20pF
●
thDO
Time Output Data Remains
Valid After CLK↑
CLOAD = 20pF
●
tr
DOUT Rise Time
CLOAD = 20pF
●
10
20
10
20
ns
tf
DOUT Fall Time
CLOAD = 20pF
●
10
20
10
20
ns
CIN
Input Capacitance
Analog Input On Channel
Analog Input Off Channel
Digital Input
●
15
55
15
20
5
5
55
ns
20
5
5
pF
pF
pF
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 2.7V, VREF = 2.5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
tCONV
Conversion Time (See Figures 1, 2)
●
fSMPL(MAX)
Maximum Sampling Frequency
●
tdDO
Delay Time, CLK↑ to DOUT Data Valid CLOAD = 20pF
LTC1197L
TYP
MAX
MIN
LTC1199L
TYP
MAX
2.9
250
2.9
210
UNITS
µs
kHz
130
180
250
130
180
250
ns
ns
●
tdis
Delay Time, CS↑ to DOUT Hi-Z
●
120
250
120
250
ns
ten
Delay Time, CLK↓ to DOUT Enabled
CLOAD = 20pF
●
100
200
100
200
ns
thDO
Time Output Data Remains
Valid After CLK↑
CLOAD = 20pF
●
tr
DOUT Rise Time
CLOAD = 20pF
●
tf
DOUT Fall Time
CLOAD = 20pF
●
CIN
Input Capacitance
Analog Input On Channel
Analog Input Off Channel
Digital Input
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to GND.
6
30
120
30
15
40
15
40
20
5
5
120
ns
15
40
ns
15
40
ns
20
5
5
pF
pF
pF
Note 3: Integral nonlinearity is defined as deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 4: Channel leakage current is measured after the channel selection.
LTC1197/LTC1197L
LTC1199/LTC1199L
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TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Clock Rate*
14
70
SUPPLY CURRENT (mA)
14
12
10
8
6
VCC = 5V
4
2
VCC = 2.7V
100
1000
FREQUENCY (kHz)
60
ACTIVE
MODE
10
10000
50
8
40
6
30
4
20
SHUTDOWN
MODE
2
0
10
12
0
0
1
2
3
5
6
7
4
SUPPLY VOLTAGE (V)
1197/99 G01
SHUTDOWN CURRENT (nA)
SUPPLY CURRENT (mA)
fCLK = 3.5MHz
TA = 25°C
VCC = 9V
16
10000
80
16
1000
SUPPLY CURRENT (µA)
20
18
VCC = 5V
fCLK = 7.2MHz
100
10
VCC = 2.7V
fCLK = 3.5MHz
1
10
8
9
0.1
0.01
0
INL Plot
DNL Plot
VCC = VREF = 5V
fCLK = 7.2MHz
TA = 25°C
LTC1197 4096 Point FFT
0
VCC = VREF = 5V
fCLK = 7.2MHz
TA = 25°C
0.5
– 20
AMPLITUDE (dB)
DNL (LSBs)
fSMPL = 500kHz
fIN = 97.045898kHz
–10
0.5
– 0.5
1000
1197/99 G03
1.0
0
0.1
10
100
1
SAMPLING FREQUENCY (kHz)
1197/99 G02
1.0
INL (LSBs)
Supply Current
vs Sampling Frequency
Supply Current vs Supply Voltage
0
– 30
– 40
– 50
– 60
– 70
– 0.5
– 80
– 90
–1.0
–1.0
0
128 256 384 512 640 768 896 1024
CODE
0
1197/99 G04
ENOBs vs Frequency
9
– 10
VCC = 2.7V
fSMPL = 250kHz
VCC = 5V
fSMPL = 500kHz
TA = 25°C
4
– 20
– 30
– 40
VCC = 2.7V
fSMPL = 250kHz
– 50
3
– 60
2
1
10
100
FREQUENCY (kHz)
1000
– 30
– 40
– 50
– 60
– 70
– 90
– 80
0
250
– 80
VCC = 5V
fSMPL = 500kHz
– 70
1
200
fSMPL = 500kHz
fIN1 = 97.045898kHz
fIN2 = 102.905273kHz
–10
AMPLITUDE (dB)
5
100
150
FREQUENCY (kHz)
Intermodulation Distortion Plot
0
– 20
THD (dB)
ENOBs
6
50
1197/99 G06
THD vs Frequency
0
7
0
1197/99 G26
10
8
–100
128 256 384 512 640 768 896 1024
CODE
–100
10
1197/99 G07
100
FREQUENCY (kHz)
1000
1197/99 G08
0
50
100
150
FREQUENCY (kHz)
200
250
1197/99 G09
*Part is continuously sampling, spending only a minimum amount of time in shutdown.
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LTC1197/LTC1197L
LTC1199/LTC1199L
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TYPICAL PERFOR A CE CHARACTERISTICS
LTC1197L Change in Linearity
vs Supply Voltage
2.0
VREF = 2.5V
fCLK = 3.5MHz
0.8
1.5
CHANGE IN OFFSET (LSBs)
0.6
0.4
0.2
0
– 0.2
– 0.4
– 0.6
0.5
0
– 0.5
–1.0
–1.5
– 1.0
– 2.0
1
3
4
2
SUPPLY VOLTAGE (V)
5
3
4
2
SUPPLY VOLTAGE (V)
0
– 0.2
– 0.4
– 0.6
9
0
– 0.5
–1.0
0.5
0
– 0.5
–1.0
– 2.0
– 2.0
0
1
2
3
4
5
6
7
SUPPLY VOLTAGE (V)
8
0
9
7
3
5
6
4
SUPPLY VOLTAGE (V)
9
2.0
VCC = 5V
fCLK = 7.2MHz
TA = 25°C
2.0
VCC = 5V
fCLK = 7.2MHz
TA = 25°C
1.5
GAIN ERROR (LSBs)
OFFSET ERROR (LSBs)
8
LTC1197 Gain Error
vs Reference Voltage
2.5
VCC = 5V
fCLK = 7.2MHz
TA = 25°C
0.5
2
1197/99 G15
LTC1197 Offset Error
vs Reference Voltage
1.0
1
1197/99 G14
2.0
LINEARITY ERROR (LSBs)
1.0
–1.5
1197/99 G13
1.5
VREF = 4V
fCLK = 7MHz
TA = 25°C
1.5
0.5
LTC1197 Linearity Error
vs Reference Voltage
5
2.0
–1.5
8
3
4
2
SUPPLY VOLTAGE (V)
LTC1197 Change in Gain Error
vs Supply Voltage
1.0
– 0.8
– 1.0
1
0
1197/99 G12
CHANGE IN GAIN ERROR (LSBs)
CHANGE IN OFFSET (LSBs)
CHANGE IN LINEARITY (LSBs)
0.2
7
3
5
6
4
SUPPLY VOLTAGE (V)
– 0.4
– 0.6
5
VREF = 4V
fCLK = 7MHz
TA = 25°C
1.5
0.4
2
0
– 0.2
– 1.0
1
0
2.0
VREF = 4V
fCLK = 7MHz
TA = 25°C
1
0.2
LTC1197 Change in Offset
vs Supply Voltage
1.0
0
0.4
1197/99 G11
LTC1197 Change in Linearity
vs Supply Voltage
0.6
0.6
– 0.8
1197/99 G10
0.8
VREF = 2.5V
fCLK = 3.5MHz
0.8
1.0
– 0.8
0
1.0
VREF = 2.5V
fCLK = 3.5MHz
CHANGE IN GAIN ERROR (LSBs)
1.0
CHANGE IN LINEARITY (LSBs)
LTC1197L Change in Gain Error
vs Supply Voltage
LTC1197L Change in Offset
vs Supply Voltage
1.5
1.0
1.0
0.5
0.5
0
0
1
3
4
2
REFERENCE VOLTAGE (V)
5
1197/99 F16
8
0
0
0
1
3
4
2
REFERENCE VOLTAGE (V)
5
1197/99 G17
0
1
3
4
2
REFERENCE VOLTAGE (V)
5
1197/99 F18
LTC1197/LTC1197L
LTC1199/LTC1199L
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TYPICAL PERFOR A CE CHARACTERISTICS
Linearity vs Temperature
0
0
VCC = 5V
VREF = 5V
fCLK = 7.2MHz
VCC = 5V
VREF = 5V
fCLK = 7.2MHz
– 0.1
– 0.2
0.3
0.2
– 0.3
– 0.4
– 0.4
– 0.5
– 0.6
– 0.7
– 0.6
– 0.8
– 1.0
– 0.8
0.1
– 1.2
– 0.9
0
–55
– 30
–5
45
70
20
TEMPERATURE (°C)
95
– 1.0
–55
120
–5
45
70
20
TEMPERATURE (°C)
– 30
95
1197/99 G19
10
LEAKAGE CURRENT (nA)
LOGIC THRESHOLD (V)
MINIMUM CLOCK FREQUENCY (kHz)
VREF = 5V
VCC = 5V
4
1
3
2
0
5 25 45 65 85 105 125
TEMPERATURE (°C)
6
8
4
SUPPLY VOLTAGE (V)
COM
1
10000
VREF = 2.5V
TA = 25°C
10
9
8
7
6
5
4
3
2
1
0
1000
SOURCE RESISTANCE (Ω)
125
1197/99 G24
MAXIMUM CLOCK FREQUENCY (kHz)
MAXIMUM CLOCK FREQUENCY (MHz)
+ INPUT
75
100
50
TEMPERATURE (°C)
10000
11
RSOURCE+
25
0
Maximum Clock Frequency†
vs Source Resistance
Maximum Clock Frequency
vs Supply Voltage
VCC = VREF = 5V
TA = 25°C
0.1
100
10
1197/99 G23
Acquisition Time
vs Source Resistance
VIN
OFF CHANNEL
0.1
0.001
2
0
1197/99 G22
10
ON CHANNEL
1
0.01
1
0.1
– 55 – 35 – 15
120
100
TA = 25°C
10
95
Input Channel Leakage Current
vs Temperature
5
VREF = 5V
VCC = 5V
100
–5
45
70
20
TEMPERATURE (°C)
– 30
1197/99 G21
Digital Input Threshold
vs Supply Voltage
1000
ACQUISITION TIME (µs)
– 1.4
–55
120
1197/99 G20
Minimum Clock Frequency for
0.1LSB Error* vs Temperature
100
VCC = 5V
VREF = 5V
fCLK = 7.2MHz
– 0.2
GAIN ERROR (LSBs)
OFFSET VOLTAGE (LSBs)
LINEARITY ERROR (LSBs)
0.4
Gain Error vs Temperature
Offset vs Temperature
0.5
0
1
2
3 4 5 6 7 8
SUPPLY VOLTAGE (V)
10
1197/99 G26
1197/99 G25
*As the CLK frequency is decreased from 2MHz, minimum CLK frequency (∆error ≤ 0.1LSB)
represents the frequency at which a 0.1LSB shift in any code translation from its 2MHz value
is first detected.
9
VREF = VCC = 5V
TA = 25°C
1000
VIN
+ INPUT
– INPUT
RSOURCE–
100
100
1000
SOURCE RESISTANCE (Ω)
10000
1197/99 G27
† Maximum
CLK frequency represents the clock frequency at which a 0.1LSB shift in the error
at any code transition from its 3.5MHz value is first detected.
9
LTC1197/LTC1197L
LTC1199/LTC1199L
U
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CS (Pin 1): Chip Select Input. A logic low on this input
enables the LTC1197/LTC1197L/LTC1199/LTC1199L.
Power shutdown is activated when CS is brought high.
+ IN, CH0 (Pin 2): Analog Input. This input must be free of
noise with respect to GND.
– IN, CH1 (Pin 3): Analog Input. This input must be free of
noise with respect to GND.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
VREF (Pin 5): LTC1197/LTC1197L Reference Input. The
reference input defines the span of the A/D converter and
must be kept free of noise with respect to GND.
DIN (Pin 5): LTC1199/LTC1199L Digital Data Input. The
A/D configuration word is shifted into this input.
DOUT (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
CLK (Pin 7): Shift Clock. This clock synchronizes the serial
data transfer.
VCC (Pin 8): Positive Supply. This supply must be kept
free of noise and ripple by bypassing directly to the
analog ground plane. For LTC1199/LTC1199L, VREF is
tied internally to this pin.
W
BLOCK DIAGRA
VCC
CS (DIN) CLK
BIAS AND
SHUTDOWN CIRCUIT
+ IN (CH0)
CSMPL
– IN (CH1)
SERIAL PORT
DOUT
–
+
SAR
MICROPOWER
COMPARATOR
CAPACITIVE DAC
GND
10
VREF
PIN NAMES IN PARENTHESES
REFER TO THE LTC1199/LTC1199L
LTC1197/LTC1197L
LTC1199/LTC1199L
TEST CIRCUITS
Voltage Waveforms for DOUT Rise and Fall Times, tr, tf
Load Circuit for tdDO, tr, tf, tdis and ten
TEST POINT
VOH
DOUT
VOL
VCC tdis WAVEFORM 2, ten
3k
DOUT
tr
tdis WAVEFORM 1
20pF
tf
1197/99 TC04
1197/99 TC01
Voltage Waveforms for DOUT Delay Time, tdDO
Voltage Waveforms for tdis
VIH
CLK
VIH
CS
tdDO
thDO
VOH
DOUT
DOUT
WAVEFORM 1
(SEE NOTE 1)
90%
tdis
VOL
1197/99 TC02
DOUT
WAVEFORM 2
(SEE NOTE 2)
10%
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL
1197/99 TC05
LTC1197/LTC1197L ten Voltage Waveforms
CS
CLK
LTC1199/LTC1199L ten Voltage Waveforms
CS
1
2
3
4
DIN
CLK
DOUT
ten
START
1
2
3
4
5
6
1197/99 TC03
DOUT
ten
1197/99 TC06
11
LTC1197/LTC1197L
LTC1199/LTC1199L
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APPLICATIO S I FOR ATIO
OVERVIEW
SERIAL INTERFACE
The LTC1197/LTC1197L/LTC1199/LTC1199L are 10-bit
switched-capacitor A/D converters. These sampling ADCs
typically draw 5mA of supply current when sampling up to
500kHz (800µA at 2.7V sampling up to 250kHz). Supply
current drops linearly as the sample rate is reduced (see
Supply Current vs Sample Rate in the Typical Performance Characteristics). The ADCs automatically power
down when not performing a conversion, drawing only
leakage current. They are packaged in 8-pin MSOP and SO
packages. The LTC1197L/LTC1199L operate on a single
supply ranging from 2.7V to 4V. The LTC1197 operates on
a single supply ranging from 4V to 9V while the LTC1199
operates from 4V to 6V.
The LTC1199/LTC1199L communicate with microprocessors and other external circuitry via a synchronous, half
duplex, 4-wire serial interface while the LTC1197/
LTC1197L use a 3-wire interface (see Operating Sequence
in Figures 1 and 2). These interfaces are compatible with
both SPI and MICROWIRE protocols without requiring any
additional glue logic (see MICROPROCESSOR INTERFACES: Motorola SPI).
DATA TRANSFER
The CLK synchronizes the data transfer with each bit being
transmitted and captured on the rising CLK edge in both
transmitting and receiving systems. The LTC1199/
LTC1199L first receives input data and then transmits
back the A/D conversion result (half duplex). Because of
the half-duplex operation, DIN and DOUT may be tied
together allowing transmission over just three wires: CS,
CLK and DATA (DIN/DOUT).
These ADCs contain a 10-bit, switched-capacitor ADC, a
sample-and-hold and a serial port (see Block Diagram).
Although they share the same basic design, the LTC1197/
LTC1197L and LTC1199/LTC1199L differ in some respects. The LTC1197/LTC1197L have a differential input
and have an external reference input pin. They can measure signals floating on a DC common mode voltage and
can operate with reduced spans down to 200mV. Reducing the span allows it to achieve 200µV resolution. The
LTC1199/LTC1199L have a 2-channel input multiplexer
with the reference connected to the supply (VCC) pin. They
can convert the input voltage of either channel with respect to ground or the difference between the voltages of
the two channels.
Data transfer is initiated by a falling chip select (CS) signal.
After CS falls the LTC1199/LTC1199L look for a start bit on
the DIN input. After the start bit is received, the 3-bit input
word is shifted into the DIN input which configures the
LTC1199/LTC1199L and starts the conversion. After two
null bits, the result of the conversion is output on the DOUT
line in MSB-first format. At the end of the data exchange
CS should be brought high. This resets the LTC1199/
LTC1199L in preparation for the next data exchange.
Bringing CS high after the conversion also minimizes
supply current if CLK is left running.
tCYC (14 CLKs )*
CS
tsuCS
CLK
1
2
3
4
5
6
7
8
9
10
12
11
13
14
1
tdDO
HI-Z
DOUT
tSMPL
(1.5 CLKs)
NULL
BITS
B9
B8
B7
B6
B5
B4
B3
B2
tCONV
(10.5 CLKs)
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW,
THE ADC WILL OUTPUT ZEROS INDEFINITELY
Figure 1. LTC1197/LTC1197L Operating Sequence
12
B1
B0*
Hi-Z
POWER
DOWN
1197/99 F01
LTC1197/LTC1197L
LTC1199/LTC1199L
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APPLICATIO S I FOR ATIO
tCYC (16 CLKs)*
CS
tsuCS
CLK
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
1
ODD/
SIGN
START
DIN
DON’T CARE
SGL/
DIFF
DOUT
11
DUMMY
tdDO
ten
HI-Z
NULL
BITS
Hi-Z
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0*
tCONV
(10.5 CLKs)
tSMPL
(1.5 CLKs)
POWER
DOWN
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW,
THE ADC WILL OUTPUT ZEROS INDEFINITELY
1197/99 F02
Figure 2. LTC1199/LTC1199L Operating Sequence
The LTC1197/LTC1197L do not require a configuration
input word and have no DIN pin. A falling CS initiates data
transfer as shown in the LTC1197/LTC1197L operating
sequence. After CS falls, the second CLK pulse enables
DOUT. After two null bits, the A/D conversion result is output
on the DOUT line in MSB-first format. Bringing CS high
resets the LTC1197/LTC1197L for the next data exchange
and minimizes the supply current if CLK is continuously
running.
INPUT DATA WORD (LTC1199/LTC1199L ONLY)
The LTC1199 4-bit data word is clocked into the DIN input
on the rising edge of the clock after CS goes low and the
start bit has been recognized. Further inputs on the DIN pin
are then ignored until the next CS cycle. The input word is
defined as follows:
transfer and all leading zeros that precede this logical one
will be ignored. After the start bit is received the remaining
bits of the input word will be clocked in. Further inputs on
the DIN pin are then ignored until the next CS cycle.
Multiplexer (MUX) Address
The bits of the input word following the start bit assign the
MUX configuration for the requested conversion. For a
given channel selection, the converter will measure the
voltage between the two channels indicated by the “+” and
“–” signs in the selected row of the following table. In
single-ended mode, all input channels are measured with
respect to GND. Only the + inputs have sample-and-holds.
Signals applied at the – inputs must not change more than
the required accuracy during the conversion.
Multiplexer Channel Selection
START
SGL/
DIFF
ODD/
SIGN
DUMMY
1197/99 AI01
MUX
ADDRESS
Start Bit
MUX ADDRESS
SGL/DIFF ODD/SIGN
1
0
1
1
0
0
0
1
CHANNEL #
1
0
+
+
–
+
–
+
GND
–
–
1197/99 AI02
The first “logical one” clocked into the DIN input after CS
goes low is the start bit. The start bit initiates the data
13
LTC1197/LTC1197L
LTC1199/LTC1199L
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Dummy Bit
Unipolar Transfer Curve
The dummy bit is a placeholder that extends the acquisition time of the ADC. This bit can be either high or low and
does not affect the conversion of the ADC.
1111111111
1111111110
•
•
•
Operation with DIN and DOUT Tied Together
0000000001
0000000000
VIN
VREF
VREF – 1LSB
VREF – 2LSB
1LSB
0V
The LTC1199/LTC1199L can be operated with DIN and
DOUT tied together. This eliminates one of the lines
required to communicate to the microprocessor (MPU).
Data is transmitted in both directions on a single wire. The
processor pin connected to this data line should be
configurable as either an input or an output. The LTC1199/
LTC1199L will take control of the data line and drive it low
on the 4th falling CLK edge after the start bit is received
(see Figure 3). Therefore the processor port line must be
switched to an input before this happens to avoid a
conflict.
1197/99 AI03
Unipolar Output Code
In the Typical Applications section, there is an example of
interfacing the LTC1199/LTC1199L with DIN and DOUT
tied together to the Intel 8051 MPU.
OUTPUT CODE
INPUT VOLTAGE
INPUT VOLTAGE
(VREF = 5.000V)
1111111111
1111111110
•
•
0000000001
0000000000
VREF – 1LSB
VREF – 2LSB
•
•
1LSB
0V
4.99512V
4.99023V
•
•
4.88mV
0V
1197/99 AI04
ACHIEVING MICROPOWER PERFORMANCE
Unipolar Transfer Curve
The LTC1197/LTC1197L/LTC1199/LTC1199L are permanently configured for unipolar only. The input span and
code assignment for this conversion type are shown in the
following figures for a 5V reference.
With typical operating currents of 5mA (LTC1197/
LTC1199) at 5V and 0.8mA (LTC1197L/LTC1199L) at
2.7V it is possible for these ADCs to achieve true
micropower performance by taking advantage of the
automatic shutdown between conversions. In systems
CS
1
2
3
START
SGL/DIFF
ODD/SIGN
4
CLK
DATA (DIN/DOUT)
DUMMY
MPU CONTROLS DATA LINE AND SENDS
MUX ADDRESS TO LTC1199/LTC1199L
PROCESSOR MUST RELEASE
DATA LINE AFTER 4TH RISING CLK
AND BEFORE THE 4TH FALLING CLK
NULL BITS
B8
LTC1199/LTC1199L CONTROL DATA LINE
AND SEND A/D RESULT BACK TO MPU
LTC1199/LTC1199L TAKE CONTROL OF
DATA LINE ON 4TH FALLING CLK
Figure 3. LTC1199/LTC1199L Operation with DIN and DOUT Tied Together
14
B9
1197/99 F03
LTC1197/LTC1197L
LTC1199/LTC1199L
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that convert continuously, the LTC1197/LTC1197L/
LTC1199/LTC1199L will draw their normal operating power
continuously. Several things must be taken into account
to achieve micropower operation.
Shutdown
Figures 1 and 2 show the operating sequence of the
LTC1197/LTC1197L/LTC1199/LTC1199L. The converter
draws power when the CS pin is low and powers itself
down when that pin is high. If the CS pin is not taken all the
way to ground when it is low and not taken to VCC when it
is high, the input buffers of the converter will draw current.
This current may be tens of microamps. It is worthwhile to
bring the CS pin all the way to ground when it is low and
all the way to VCC when it is high to obtain the lowest
supply current.
When the CS pin is high (= supply voltage), the converter
is in shutdown mode and draws only leakage current. The
status of the DIN and CLK inputs have no effect on supply
current during this time. There is no need to stop DIN and
CLK with CS = high, except the MPU may benefit.
Minimize CS Low Time
In systems that have significant time between conversions, lowest power drain will occur with the minimum CS
low time. Bringing CS low, transferring data as quickly as
possible, and then returning CS high will result in the
lowest possible current drain. This minimizes the amount
of time the device draws power. Even though the device
draws more power at high clock rates, the net power is less
because the device is on for a shorter time.
DOUT Loading
Capacitive loading on the digital output can increase
power consumption. A 100pF capacitor on the DOUT pin
can add 200µA to the supply current at a 7.2MHz clock
frequency. The extra 200µA goes into charging and discharging the load capacitor. The same goes for digital lines
driven at a high frequency by any logic. The C • V • f currents
must be evaluated and the troublesome ones minimized.
Lower Supply Voltage
For lower supply voltages, LTC offers the LTC1197L/
LTC1199L. These pin compatible devices offer specified
performance to 2.7V supplies.
OPERATING ON OTHER THAN 5V SUPPLIES
The LTC1197 operates from 4V to 9V supplies and the
LTC1199 operates from 4V to 6V supplies. The LTC1197L/
LTC1199L operate from 2.7V to 4V supplies. To use these
parts at other than 5V supplies a few things must be kept
in mind.
Bypassing
At higher supply voltages, bypass capacitors on VCC and
VREF if applicable, need to be increased beyond what is
necessary for 5V. For a 9V supply a 10µF tantalum in
parallel with a 0.1µF ceramic is recommended.
Input Logic Levels
The input logic levels of CS, CLK and DIN are made to meet
TTL threshold levels on a 5V supply. When the supply
voltage varies, the input logic levels also change. For the
ADC to sample and convert correctly, the digital inputs
have to meet logic low and high levels relative to the
operating supply voltage (see typical curve of Digital Input
Logic Threshold vs Supply Voltage). If achieving micropower consumption is desirable, the digital inputs
must go rail-to-rail between VCC and ground (see ACHIEVING MICROPOWER PERFORMANCE section).
Clock Frequency
The maximum recommended clock frequency is 7.2MHz
for the LTC1197/LTC1199 running off a 5V supply and
3.5MHz for the LTC1197L/LTC1199L running off a 2.7V
supply. With the supply voltage changing, the maximum
clock frequency for the devices also changes (see the
typical curve of Maximum Clock Rate vs Supply Voltage).
If the maximum clock frequency is used, care must be
taken to ensure that the device converts correctly.
15
LTC1197/LTC1197L
LTC1199/LTC1199L
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Mixed Supplies
SAMPLE-AND-HOLD
It is possible to have a microprocessor running off a 5V
supply and communicate with the ADC operating on 3V or
9V supplies. The requirement to achieve this is that the
outputs of CS, CLK and DIN from the MPU have to be able
to trip the equivalent inputs of the ADC and the output of
the ADC must be able to toggle the equivalent input of the
MPU (see typical curve of Digital Input Logic Threshold vs
Supply Voltage). With the LTC1197 operating on a 9V
supply, the output of DOUT may go between 0V and 9V. The
9V output may damage the MPU running off a 5V supply.
The way to solve this problem is to have a resistor divider
on DOUT (Figure 4) and connect the center point to the
MPU input. It should be noted that to get full shutdown, the
CS input of the ADC must be driven to the VCC voltage. This
would require adding a level shift circuit to the CS signal
in Figure 4.
The LTC1197/LTC1197L/LTC1199/LTC1199L provide a
built-in sample-and-hold (S /H) function to acquire signals. The S /H of the LTC1197/LTC1197L acquires input
signals for the “+” input relative to the “–” input during the
tSMPL time (see Figure 1). However the S /H of the LTC1199/
LTC1199L can sample input signals from the “+” input
relative to ground and from the “–” input relative to ground
in addition to acquiring signals from the “+” input relative
to the “–” input (see Figure 5) during tSMPL.
9V
OPTIONAL
LEVEL SHIFT
CS
VCC
+IN
CLK
–IN
DOUT
GND
VREF
5V
P1.4
P1.3
4.7k
P1.2
6V
4.7k
LTC1197
1197/99 F04
Figure 4. Interfacing a 9V-Powered LTC1197 to a 5V System
BOARD LAYOUT CONSIDERATIONS
Grounding and Bypassing
The LTC1197/LTC1197L/LTC1199/LTC1199L should be
used with an analog ground plane and single point grounding techniques. The GND pin should be tied directly to the
ground plane. The VCC pin should be bypassed to the
ground plane using a 1µF tantalum capacitor with leads as
short as possible. All analog inputs should be referenced
directly to the single point ground. Digital inputs and
outputs should be shielded from and/or routed away from
the reference and analog circuitry.
16
The sample-and-hold of the LTC1199/LTC1199L allows
conversion of rapidly varying signals. The input voltage is
sampled during the tSMPL time as shown in Figure 5. The
sampling interval begins as the ODD/SGN bit is shifted in
and continues until the falling CLK edge after the dummy
bit is received. On this falling edge, the S/H goes into hold
mode and the conversion begins.
Differential Inputs
9V 4.7µF
MPU
(e.g. 8051)
DIFFERENTIAL INPUTS
COMMON MODE RANGE
0V TO 6V
Single-Ended Inputs
With differential inputs, the ADC no longer converts just a
single voltage but rather the difference between two voltages. In this case, the voltage on the selected “+” input is
still sampled and held and therefore may be rapidly time
varying just as in single-ended mode. However, the voltage on the selected “–” input must remain constant and be
free of noise and ripple throughout the conversion time.
Otherwise, the differencing operation may not be performed accurately. The conversion time is 10.5 CLK cycles.
Therefore, a change in the “–” input voltage during this
interval can cause conversion errors. For a sinusoidal
voltage on the “–” input this error would be:
VERROR (MAX) = VPEAK • 2 • π • f(“–”) • 10.5/fCLK
Where f(“–”) is the frequency of the “–” input voltage,
VPEAK is its peak amplitude and fCLK is the frequency of the
CLK. In most cases VERROR will not be significant. For a
60Hz signal on the “–” input to generate a 1/4LSB error
(1.22mV) with the converter running at CLK = 7.2MHz, its
peak value would have to be 2.22V.
LTC1197/LTC1197L
LTC1199/LTC1199L
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SAMPLE
HOLD
“+” INPUT MUST
SETTLE DURING
THIS TIME
CS
tSMPL
tCONV
CLK
DIN
START
SGL/DIFF
ODD/SGN
DUMMY
DON‘T CARE
DOUT
1ST BIT TEST “–” INPUT MUST
SETTLE DURING THIS TIME
“+” INPUT
“–” INPUT
1197/99 F05
Figure 5. LTC1199/LTC1199L “+” and “–” Input Settling Windows
ANALOG INPUTS
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1197/
LTC1197L/LTC1199/LTC1199L have capacitive switching
input current spikes. These current spikes settle quickly
and do not cause a problem if source resistances are less
than 200Ω or high speed op amps are used (e.g., the
LT ®1224, LT1191, LT1226 or LT1215). However, if large
source resistances are used or if slow settling op amps
drive the inputs, take care to ensure that the transients
caused by the current spikes settle completely before the
conversion begins.
“+” Input Settling
The input capacitor of the LTC1197/LTC1197L is switched
onto the “+” input in the falling edge of CS and the sample
time continues until the second falling CLK edge (see
Figure 1). However, the input capacitor of the LTC1199/
LTC1199L is switched onto “+” input after ODD/SGN is
clocked into the ADC and remains there until the fourth
falling CLK edge (see Figure 5). The sample time is 1.5 CLK
cycles before conversion starts. The voltage on the “+”
VIN +
RSOURCE +
“+”
INPUT
C1
VIN –
RSOURCE –
LTC1197/LTC1197L
LTC1199/LTC1199L
RON = 200Ω
“–”
INPUT
C2
CIN = 20pF
1197/99 F06
Figure 6. Analog Equivalent Circuit
input must settle completely within tSMPL for the ADC to
perform an accurate conversion. Minimizing RSOURCE+
and C1 will improve the input settling time (see Figure 6).
If a large “+” input source resistance must be used, the
sample time can be increased by using a slower CLK
frequency.
“–” Input Settling
At the end of tSMPL, the input capacitor switches to the
“–” input and conversion starts (see Figures 1 and 5).
During the conversion the “+” input voltage is effectively
“held” by the sample-and-hold and will not affect the
17
LTC1197/LTC1197L
LTC1199/LTC1199L
U
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APPLICATIO S I FOR ATIO
conversion result. However, it is critical that the “–” input
voltage settles completely during the first CLK cycle of the
conversion time and be free of noise. Minimizing RSOURCE–
and C2 will improve settling time (see Figure 6). If a large
“–” input source resistance must be used, the time allowed
for settling can be extended by using a slower CLK
frequency.
across the resistor. The magnitude of the DC current is
approximately IDC = 20pF(VIN /tCYC) and is roughly proportional to VIN. When running at the minimum cycle time
of 2µs, the input current equals 50µA at VIN = 5V. In this
case a filter resistor of 10Ω will cause 0.1LSB of full-scale
error. If a larger filter resistor must be used, errors can be
eliminated by increasing the cycle time.
Input Op Amps
Input Leakage Current
When driving the analog inputs with an op amp it is
important that the op amp settle within the allowed time
(see Figure 5). Again, the “+” and “–” input sampling times
can be extended as described above to accommodate
slower op amps. High speed op amps such as the LT1224,
LT1191, LT1226 or LT1215 can be made to settle well even
with the minimum settling window of 200ns which occurs
at the maximum clock rate of 7.2MHz.
Input leakage currents can also create errors if the source
resistance gets too large. For instance, the maximum
input leakage specification of 1µA (at 85°C) flowing through
a source resistance of 1k will cause a voltage drop of 1mV
or 0.2LSB. This error will be much reduced at lower
temperatures because leakage drops rapidly (see typical
curve of Input Channel Leakage Current vs Temperature).
REFERENCE INPUTS
Source Resistance
The analog inputs of the LTC1197/LTC1197L/LTC1199/
LTC1199L look like a 20pF capacitor (CIN) in series with a
200Ω resistor (RON) as shown in Figure 6. CIN gets
switched between the selected “+” and “–” inputs once
during each conversion cycle. Large external source resistors and capacitors will slow the settling of the inputs. It is
important that the overall RC time constants be short
enough to allow the analog inputs to completely settle
within the allowed time.
The voltage on the reference input of the LTC1197/
LTC1197L defines the voltage span of the A/D converter.
The reference input transient capacitive switching currents are due to the switched-capacitor conversion technique used in these ADCs (see Figure 8). During each bit
test of the conversion (every CLK cycle), a capacitive
current spike will be generated on the reference pin by the
ADC. These current spikes settle quickly and do not cause
a problem.
Reduced Reference Operation
RC Input Filtering
It is possible to filter the inputs with an RC network as
shown in Figure 7. For large values of CF (e.g., 1µF), the
capacitive input switching currents are averaged into a net
DC current. Therefore, a filter should be chosen with a
small resistor and large capacitor to prevent DC drops
RFILTER
The minimum reference voltage of the LTC1199 is 4V and
the minimum reference voltage of the LTC1199L is 2.7V
because the VCC supply and reference are internally tied
together. However, the LTC1197/LTC1197L can operate
with reference voltages below 1V.
REF
5
IDC
“+”
VIN
ROUT
CF
LTC1199
VREF
“–”
1197/99 F07
Figure 7. RC Input Filtering
18
LTC1197
EVERY CLK CYCLE
RON
GND
4
5pF TO 25pF
1197/99 F08
Figure 8. Reference Input Equivalent Circuit
LTC1197/LTC1197L
LTC1199/LTC1199L
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APPLICATIO S I FOR ATIO
The effective resolution of the LTC1197/LTC1197L can be
increased by reducing the input span of the converter. The
LTC1197/LTC1197L exhibits good linearity and gain over
a wide range of reference voltages (see typical curves of
Linearity and Full-Scale Error vs Reference Voltage). However, care must be taken when operating at low values of
VREF because of the reduced LSB step size and the
resulting higher accuracy requirement placed on the converter. The following factors must be considered when
operating at low VREF values.
1. Offset
2. Noise
3. Conversion speed (CLK frequency)
Offset with Reduced VREF
The offset of the LTC1197/LTC1197L has a larger effect on
the output code when the ADC is operated with reduced
reference voltage. The offset (which is typically a fixed
voltage) becomes a larger fraction of an LSB as the size of
the LSB is reduced. The typical curve of LTC1197 Offset
Error vs Reference Voltage shows how offset in LSBs is
related to reference voltage for a typical value of VOS. For
example, a VOS of 1mV which is 0.2LSB with a 5V reference
becomes 1LSB with a 1V reference and 5LSBs with a 0.2V
reference. If this offset is unacceptable, it can be corrected
digitally by the receiving system or by offsetting the “–”
input of the LTC1197/LTC1197L.
Noise with Reduced VREF
The total input referred noise of the LTC1197/LTC1197L
can be reduced to approximately 200µV peak-to-peak
using a ground plane, good bypassing, good layout techniques and minimizing noise on the reference inputs. This
noise is insignificant with a 5V reference but will become
a larger fraction of an LSB as the size of the LSB is reduced.
For operation with a 5V reference, the 200µV noise is
only 0.04LSB peak-to-peak. In this case, the LTC1197/
LTC1197L noise will contribute virtually no uncertainty
to the output code. However, for reduced references, the
noise may become a significant fraction of an LSB and
cause undesirable jitter in the output code. For example,
with a 1V reference, this same 200µV noise is 0.2LSB
peak-to-peak. This will reduce the range of input voltages over which a stable output code can be achieved. If
the reference is further reduced to 200mV, the 200µV of
noise becomes equal to 1LSB and a stable code may be
difficult to achieve. In this case, averaging readings may
be necessary.
This noise data was taken in a very clean setup. Any setupinduced noise (noise or ripple on VCC, VREF or VIN) will add
to the internal noise. The lower the reference voltage to be
used, the more critical it becomes to have a clean, noisefree setup.
Conversion Speed with Reduced VREF
With reduced reference voltages the LSB step size is
reduced and the LTC1197/LTC1197L internal comparator
overdrive is reduced. Therefore, it may be necessary to
reduce the maximum CLK frequency when low values of
VREF are used.
Input Divider
It is OK to use an input divider on the reference input of the
LTC1197/LTC1197L as long as the reference input can be
made to settle within the bit time at which the clock is
running. When using a larger value resistor divider on the
reference input, the “–” input should be matched with an
equivalent resistance.
Bypassing Reference Input with Divider
Bypassing the reference input with a divider is also possible. However, care must be taken to make sure that the
DC voltage on the reference input will not drop too much
below the intended reference voltage.
19
LTC1197/LTC1197L
LTC1199/LTC1199L
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APPLICATIO S I FOR ATIO
Signal-to-Noise Ratio
Effective Number of Bits
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency to
the RMS amplitude of all other frequency components at
the A/D output. This includes distortion as well as noise
products and for this reason it is sometimes referred to
as signal-to-noise + distortion [S/(N + D)]. The output is
band limited to frequencies from DC to one half the
sampling frequency. Figure 9 shows spectral content
from DC to 250kHz which is 1/2 the 500kHz sampling
rate.
The effective number of bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
0
ENOB = [S/(N + D) –1.76]/6.02
where S/(N + D) is expressed in dB. At the maximum
sampling rate of 500kHz, the LTC1197 maintains 9.5
ENOBs or better to 200kHz. Above 200kHz, the ENOBs
gradually decline, as shown in Figure 10, due to increasing
second harmonic distortion. The noise floor remains
approximately 100dB.
fSMPL = 500kHz
fIN = 97.045898kHz
–10
AMPLITUDE (dB)
– 20
– 30
– 40
– 50
– 60
– 70
– 80
– 90
–100
0
50
100
150
FREQUENCY (kHz)
200
250
1197/99 G06
Figure 9. This Clean FFT of a 97kHz Input Shows Remarkable
Performance for an ADC Sampling at the 500kHz Rate
10
9
VCC = 2.7V
fSMPL = 250kHz
VCC = 5V
fSMPL = 500kHz
8
ENOBs
7
6
5
4
3
2
1
0
1
10
100
FREQUENCY (kHz)
1000
1197/99 G07
Figure 10. Dynamic Accuracy is Maintained
Up to an Input Frequency of 200kHz for the
LTC1197 and 50kHz for the LTC1197L
20
LTC1197/LTC1197L
LTC1199/LTC1199L
U
TYPICAL APPLICATIO S
MICROPROCESSOR INTERFACES
Motorola SPI (MC68HC05C4, MC68HC11)
The LTC1197/LTC1197L/LTC1199/LTC1199L can interface directly (without external hardware to most popular
microprocessor (MPU) synchronous serial formats (see
Table 1). If an MPU without a dedicated serial port is used,
then three or four of the MPU’s parallel port lines can be
programmed to form the serial link. Included here is one
serial interface example and one example showing a
parallel port programmed to form the serial interface.
The MC68HC05C4 has been chosen as an example of an
MPU with a dedicated serial port. This MPU transfers data
MSB-first and in 8-bit increments. With two 8-bit transfers, the A/D result is read into the MPU. The first 8-bit
transfer sends the DIN word to the LTC1199 and clocks the
two ADC MSBs (B9 and B8) into the MPU. The second 8bit transfer clocks the next 8 bits, B7 through B0, of the
ADC into the MPU.
ANDing the first MPU received byte with 03Hex clears the
six MSBs. Notice how the position of the start bit in the DIN
word is used to position the A/D result so that it is rightjustified in two memory locations.
Table 1. Microprocessor with Hardware Serial Interfaces
Compatible with the LTC1197/LTC1197L/LTC1199/LTC1199L
PART NUMBER
TYPE OF INTERFACE
Motorola
MC6805S2,S3
MC68HC11
MC68HC05
SPI
SPI
SPI
RCA
CDP68HC05
SPI
Hitachi
HD6301
HD6303
HD6305
HD63701
HD63705
HD64180
SCI Synchronous
SCI Synchronous
SCI Synchronous
SCI Synchronous
SCI Synchronous
CSI/O
National Semiconductor
COP400 Family
COP800 Family
NSC8050U
HPC16000 Family
MICROWIRETM
MICROWIRE/PLUSTM
MICROWIRE/PLUS
MICROWIRE/PLUS
Texas Instruments
TMS7000 Family
TMS320 Family
Serial Port
Serial Port
Microchip Technology
PIC16C60 Family
PIC16C70 Family
SPI, SCI Synchronous
SPI, SCI Synchronous
MICROWIRE and MICROWIRE/PLUS are trademarks of
National Semiconductor Corp.
21
LTC1197/LTC1197L
LTC1199/LTC1199L
U
TYPICAL APPLICATIO S
Data Exchange Between LTC1199 and MC68HC05C4
START
BIT
BYTE 1
MPU TRANSMIT
WORD
SGL/ ODD/
DIFF SIGN
1
BYTE 2 (DUMMY)
X
X
X
X
X
X
X
DUMMY
X
X
X
X
X
X = DON‘T CARE
CS
START
DUMMY
SGL/ ODD/
DIFF SIGN
DIN
DON‘T CARE
CLK
DOUT
B9
MPU RECEIVED
WORD
?
?
?
?
0
0
B8
B9
B7
B6
B7
B8
B5
B6
1ST TRANSFER
Hardware and Software Interface to Motorola MC68HC05C4
C0
CS
CLK
ANALOG
INPUTS
LTC1199
DIN
DOUT
0
0
0
0
0
0
B9
B8
LOCATION A + 1
B7
B6
B5
B4
B3
B2
B1
B0
BYTE 1
BCLRn
LDA
STA
1197/99 TA05
STA
AND
STA
TST
BPL
BSETn
LDA
STA
LSB
22
START
LDA
LOCATION A
BYTE 2
B4
MNEMONIC
MOSI
MSB
B5
LABEL
TST
BPL
DOUT from LTC1199 Stored in MC68HC05C4
B3
B2
B1
B3
2ND TRANSFER
SCK
MC68HC05C4
MISO
1197/99 TA04
B4
B2
B0
B1
B0
1197/99 TA03
COMMENTS
Bit 0 Port C goes low (CS goes low)
Load LTC1199 DIN word into ACC
Load LTC1199 DIN word into SPI from ACC
Transfer begins
Test status of SPIF
Loop to previous instruction if not done
with transfer
Load contents of SPI data register
into ACC (DOUT MSBs)
Start next SPI cycle
Clear 6 MSBs of the first DOUT word
Store in memory location A (MSBs)
Test status of SPIF
Loop to previous instruction if not done
with transfer
Set B0 of Port C (CS goes high)
Load contents of SPI data register into
ACC. (DOUT LSBs)
Store in memory location A + 1 (LSBs)
LTC1197/LTC1197L
LTC1199/LTC1199L
U
TYPICAL APPLICATIO S
Interfacing to the Parallel Port of the
Intel 8051 Family
LABEL
The Intel 8051 has been chosen to demonstrate the
interface between the LTC1199 and parallel port microprocessors. Normally, the CS, CLK and DIN signals would
be generated on three port lines and the DOUT signal read
on a fourth port line. This works very well. However, we
will demonstrate here an interface with the DIN and DOUT
of the LTC1199 tied together as described in the
SERIAL INTERFACE section. This saves one wire.
LOOP 1
LOOP
The 8051 first sends the start bit and MUX address to the
LTC1199 over the data line connected to P1.2. Then P1.2
is reconfigured as an input (by writing to it a one) and
the 8051 reads back the 8-bit A/D result over the same
data line.
ANALOG
INPUTS
LTC1199
CS
CLK
DOUT
DIN
P1.4
P1.3
P1.2
8051
MUX ADDRESS
A/D RESULT
1197/99 TA06
MNEMONIC
OPERAND
COMMENTS
MOV
SETB
CLR
MOV
RLC
CLR
MOV
SETB
DJNZ
MOV
CLR
MOV
MOV
RLC
SETB
CLR
DJNZ
MOV
MOV
SETB
CLR
CLR
RLC
A, #FFH
P1.4
P1.4
R4, #04
A
P1.3
P1.2, C
P1.3
R4, LOOP 1
P1, #04
P1.3
R4, #0AH
C, P1.2
A
P1.3
P1.3
R4, LOOP
R2, A
C, P1.2
P1.3
P1.3
A
A
MOV
RRC
RRC
MOV
SETB
C, P1.2
A
A
R3, A
P1.4
DIN word for LTC1199
Make sure CS is high
CS goes low
Load counter
Rotate DIN bit into Carry
CLK goes low
Output DIN bit into Carry
CLK goes high
Next bit
Bit 2 becomes an input
CLK goes low
Load counter
Read data bit into Carry
Rotate data bit into ACC
CLK goes high
CLK goes low
Next bit
Store MSBs in R2
Read data bit into Carry
CLK goes high
CLK goes low
Clear ACC
Rotate data bit from Carry to
ACC
Read data bit into Carry
Rotate right into ACC
Rotate right into ACC
Store LSBs in R3
CS goes high
DOUT from LTC1199 Stored in 8051 RAM
MSB
R2
B9
R3
B1
B8
B7
B6
B5
B4
B3
B2
0
0
0
0
0
0
LSB
B0
1197/99 TA07
CS
1
2
START
SGL/
DIFF
3
4
CLK
DATA (DIN/DOUT)
ODD/ DUMMY
SIGN
B9
B8
B7
8051 P1.2 OUTPUTS DATA
TO LTC1199
8051 P1.2 RECONFIGURED
AS AN INPUT AFTER THE 4TH RISING
CLK AND BEFORE THE 4TH FALLING CLK
B6
B5
B4
LTC1199 SENDS A/D RESULT
BACK TO 8051 P1.2
B3
B2
B1
B0
1197/99 TA08
LTC1199 TAKES CONTROL OF DATA LINE
ON 4TH FALLING CLK
23
LTC1197/LTC1197L
LTC1199/LTC1199L
U
TYPICAL APPLICATIO S
A “Quick Look” Circuit for the LTC1197
Users can get a quick look at the function and timing of
the LTC1197 by using the following simple circuit (Figure
11). VREF is tied to VCC. VIN is applied to the +IN input and
the – IN input is tied to the ground. CS is driven at 1/16
the clock rate by the 74HC161 and DOUT outputs the data.
The output data from the DOUT pin can be viewed on an
5V
1µF
+
10k
VCC
CS
VIN
oscilloscope that is set up to trigger on the falling edge
of CS (Figure 12). Note that after the LSB is clocked out,
the LTC1197 clocks out zeros until CS goes high. Also
note that with the resistor divider on DOUT the output
goes midway between VCC and ground when in the high
impedance mode.
CLK
LTC1197
DOUT
– IN
+ IN
GND
VREF
5V
CLR
VCC
CLK
RC
A
QA
B
QB
74HC161
C
QC
D
QD
P
T
GND
LOAD
10k
CLK IN 7.2MHz MAX
DOUT CLK CS
TO OSCILLOSCOPE
1197/99 F11
Figure 11. “Quick Look” Circuit for the LTC1197
CS
CLK
DOUT
HIGH
IMPEDANCE
2 NULL
BITS
MSB
(B9)
LSB
(B0)
FILL
ZEROES
VERTICAL: 5V/DIV
HORIZONTAL: 10µs/DIV
Figure 12. Scope Photo of the LTC1197 “Quick Look” Circuit
Waveforms Showing A/D Output 1001001001 (249HEX)
24
LTC1197/LTC1197L
LTC1199/LTC1199L
U
TYPICAL APPLICATIO S
Resistive Touchscreen Interface
Figure 13 shows the LTC1199 in a 4-wire resistive touchscreen application. Transistor pairs Q1-Q3, Q2-Q4 apply
5V and ground to the X axis and Y axis, respectively. The
LTC1199, with its 2-channel multiplexer, digitizes the
voltage generated by each axis and transmits the conversion results to the system’s processor through a serial
interface. RC combinations R1C1, R2C2 and R3C3 form
lowpass filters that attenuate noise from possible sources
such as the processor clock, switching power supplies
and bus signals. The 74HC14 inverter is used to detect
screen contact both during a conversion sequence and to
trigger its start. Using the single channel LTC1197, 5-wire
resistive touchscreens are as easily accommodated.
5V
R6
4.7k
R7
100k
Q2
2N2907
C5
1000pF
Y+
–
C6
1000pF
X
R9
100k
Q1
2N2907
R8
4.7k
C3
10µF
C4
1000pF
Q3
2N2222A
R3
10Ω
R7
100k
R6
4.7k
R1
100Ω
LTC1199
C1
1µF
1
CS
VCC
CH0
CLK
CH1
DOUT
GND
DIN
2
3
R10
4.7k
Y–
X+
74HC14
R11
100k
Q4
2N2222A
C7
1000pF
R12
100k
R2
100Ω
+
C2
1µF
4
8
7
6
5
TOUCH SENSE
CHIP SELECT
SERIAL CLK
DATA IN
DATA OUT
1197/99 F13
Figure 13. The LTC1199 Digitizes Resistive Touchscreen X and Y Axis Voltages. The ADC’s Auto Shutdown Feature
Helps Maximize Battery Life in Portable Touchscreen Equipment
25
LTC1197/LTC1197L
LTC1199/LTC1199L
U
TYPICAL APPLICATIO S
Battery Current Monitor
The LTC1197L/LTC1199L are ideal for 3V systems. Figure 14 shows a 2.7V to 4V battery current monitor that
draws only 45µA at 3V from the battery it monitors,
sampling at a 1Hz rate. To minimize supply current, the
microprocessor uses the LTC1152 SHDN pin to turn on
the op amp prior to making a measurement and then turn
it off after the measurement has been made. The battery
current is sensed with the 0.005Ω resistor and amplified
by the LTC1152. The LTC1197L digitizes the amplifier
output and sends it to the microprocessor in serial
format. After each sample the LTC1197L automatically
powers down. The LT1004 provides the full-scale reference for the ADC. The circuit’s 45µA supply current is
dominated by the reference and the op amp. The circuit
can be located near the battery and data transmitted
serially to the microprocessor.
500pF
+
2.7V
TO 4V
L
O
A
D
1µF
240k
56k
LTC1197L
2k
0.005Ω
2A FULL
SCALE
–
SHDN
LTC1152
1
100Ω
+
2
3
4
1µF
CS
VCC
+IN
CLK
– IN
DOUT
GND
VREF
0.1µF
TO µP
8
7
6
5
LT1004-1.2
Figure 14. This 0A to 2A Battery Current Monitor Draws Only 45µA from a 3V Battery
26
LTC1197/LTC1197L
LTC1199/LTC1199L
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters), unless otherwise noted.
MS8 Package
8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)
0.118 ± 0.004*
(3.00 ± 0.102)
8
7 6
5
0.118 ± 0.004**
(3.00 ± 0.102)
0.193 ± 0.006
(4.90 ± 0.15)
1
2 3
4
0.043
(1.10)
MAX
0.007
(0.18)
0.034
(0.86)
REF
0° – 6° TYP
0.021 ± 0.006
(0.53 ± 0.015)
SEATING
PLANE
0.009 – 0.015
(0.22 – 0.38)
0.005 ± 0.002
(0.13 ± 0.05)
0.0256
(0.65)
BSC
MSOP (MS8) 1100
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
8
7
6
5
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
1
0.010 – 0.020
× 45°
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
0.053 – 0.069
(1.346 – 1.752)
0°– 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.014 – 0.019
(0.355 – 0.483)
TYP
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
2
3
4
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
BSC
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
SO8 1298
27
LTC1197/LTC1197L
LTC1199/LTC1199L
RELATED PARTS
PART NUMBER
SAMPLE RATE
POWER DISSIPATION
DESCRIPTION
8-Bit, Pin Compatible Serial Output ADCs
LTC1096/LTC1096L
33kHz/15kHz
0.5mW*
1-Channel, Unipolar Operation with Reference Input, 5V/3V
LTC1098/LTC1098L
33kHz/15kHz
0.6mW*
2-Channel, Unipolar Operation, 5V/3V
LTC1196
1MHz/383kHz
20mW
1-Channel, Unipolar Operation with Reference Input, 5V/3V
LTC1198
750kHz/287kHz
20mW*
2-Channel, Unipolar Operation, 5V/3V
10-Bit Serial I/O ADCs
LTC1090
25kHz
5mW
LTC1091
30kHz
7.5mW
8-Channel, Bipolar or Unipolar Operation, 5V
LTC1092
35kHz
5mW
2-Channel, Unipolar Operation with Reference Input, 5V
LTC1093
25kHz
5mW
6-Channel, Bipolar or Unipolar Operation, 5V
LTC1094
25kHz
5mW
8-Channel, Bipolar or Unipolar Operation, 5V
LTC1283
15kHz
0.5mW
8-Channel, Bipolar or Unipolar Operation, 3V
LTC1285/LTC1288
7.5kHz/6.6kHz
0.4mW/0.6mW*
1-Channel with Reference (LTC1285), 2-Channel (LTC1288), 3V
LTC1286/LTC1298
12.5kHz/11.1kHz
1.3mW/1.7mW*
1-Channel with Reference (LTC1286), 2-Channel (LTC1298), 5V
LTC1287
30kHz
3mW
1-Channel, Unipolar Operation, 3V
LTC1289
33kHz
3mW
8-Channel, Bipolar or Unipolar Operation, 3V
LTC1290
50kHz
30mW
8-Channel, Bipolar or Unipolar Operation, 5V
LTC1291
54kHz
30mW
2-Channel, Unipolar Operation, 5V
LTC1292
60kHz
30mW
1-Channel, Unipolar Operation, 5V
LTC1293
46kHz
30mW
6-Channel, Bipolar or Unipolar Operation, 5V
LTC1294
46kHz
30mW
8-Channel, Bipolar or Unipolar Operation, 5V
LTC1296
46kHz
30mW
8-Channel, Bipolar or Unipolar Operation, 5V
1-Channel, Unipolar Operation, 5V
2-Channel, Unipolar Operation, 5V
12-Bit Serial I/O ADCs
LTC1297
50kHz
30mW
LTC1400
400kHz
75mW**
20kHz/12.5kHz
1.6mW/0.5mW*
20kHz/12.5kHz
1.6mW/0.5mW*
LTC1594/LTC1594L
LTC1598/LTC1598L
PART NUMBER
1-Channel, Bipolar or Unipolar Operation, Internal Reference, 5V
4-Channel, Unipolar Operation, 5V/3V
8-Channel, Unipolar Operation, 5V/3V
DESCRIPTION
COMMENTS
LT1004
Micropower Voltage Reference
0.3% Max, 20ppm/°C Typ, 10µA Max
LT1019
Precision Bandgap Reference
0.05% Max, 5ppm/°C Max
LT1236
Precision Low Noise Reference
0.05% Max, 5ppm/°C Max, SO Package
LT1460-2.5
Micropower Precision Series Reference
0.075% Max, 10ppm/°C Max, 130µA Max, SO Package
LT1634
Micropower Precision Reference
0.05% Max, 25ppm/°C Max, 7µA Max, MSOP Package
Low Power References
*These devices have auto shutdown which reduces power dissipation
linearly as sample rate is reduced from fSMPL(MAX).
**Has nap and sleep shutdown modes.
28
Linear Technology Corporation
11979fa LT/LCG 0301 2K REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
 LINEAR TECHNOLOGY CORPORATION 1997