IRFR110, IRFU110, SiHFR110, SiHFU110 Vishay Siliconix FEATURES PRODUCT SUMMARY VDS (V) • Dynamic dV/dt Rating 100 RDS(on) (Ω) VGS = 10 V Available • Repetitive Avalanche Rated 0.54 Qg (Max.) (nC) 8.3 • Surface Mount (IRFR110/SiHFR110) Qgs (nC) 2.3 • Straight Lead (IRFU110/SiHFU110) Qgd (nC) 3.8 • Available in Tape and Reel Configuration Single COMPLIANT • Fast Switching D DPAK (TO-252) RoHS* • Ease of Paralleling • Lead (Pb)-free Available IPAK (TO-251) DESCRIPTION G Third generation Power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The DPAK is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRFU/SiHFU series) is for through-hole mounting applications. Power dissipation levels up to 1.5 W are possible in typical surcace mount applications. S N-Channel MOSFET ORDERING INFORMATION Package Lead (Pb)-free SnPb DPAK (TO-252) DPAK (TO-252) DPAK (TO-252) DPAK (TO-252) IPAK (TO-251) IRFR110PbF IRFR110TRLPbFa IRFR110TRPbFa IRFR110TRRPbFa IRFU110PbF SiHFR110-E3 SiHFR110TL-E3a SiHFR110T-E3a SiHFR110TR-E3a SiHFU110-E3 IRFR110 IRFR110TRLa IRFR110TRa - IRFU110 SiHFR110 SiHFR110TLa SiHFR110Ta - SiHFU110 Note a. See device orientation. ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS 100 Gate-Source Voltage VGS ± 20 Continuous Drain Current Pulsed Drain VGS at 10 V TC = 25 °C TC = 100 °C Currenta ID IDM UNIT V 4.3 2.7 A 17 Linear Derating Factor 0.20 Linear Derating Factor (PCB Mount)e 0.020 W/°C Single Pulse Avalanche Energyb EAS 100 Repetitive Avalanche Currenta IAR 4.3 A Repetitive Avalanche Energya EAR 2.5 mJ Maximum Power Dissipation TC = 25 °C Maximum Power Dissipation (PCB Mount)e TA = 25 °C Peak Diode Recovery dV/dtc PD dV/dt 25 2.5 5.5 mJ W V/ns www.kersemi.com 1 IRFR110, IRFU110, SiHFR110, SiHFU110 ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted PARAMETER Operating Junction and Storage Temperature Range SYMBOL LIMIT TJ, Tstg - 55 to + 150 UNIT °C 260d Soldering Recommendations (Peak Temperature) for 10 s Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. VDD = 25 V, starting TJ = 25 °C, L = 8.1 mH, RG = 25 Ω, IAS = 4.3 A (see fig. 12). c. ISD ≤ 5.6 A, dI/dt ≤ 75 A/µs, VDD ≤ VDS, TJ ≤ 150 °C. d. 1.6 mm from case. e. When mounted on 1” square PCB (FR-4 or G-10 material). THERMAL RESISTANCE RATINGS SYMBOL TYP. MAX. Maximum Junction-to-Ambient PARAMETER RthJA - 110 Maximum Junction-to-Ambient (PCB Mount)a RthJA - 50 Maximum Junction-to-Case (Drain) RthJC - 5.0 UNIT °C/W Note a. When mounted on 1” square PCB (FR-4 or G-10 material). SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient VDS VGS = 0 V, ID = 250 µA 100 - - V ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.13 - V/°C VGS(th) VDS = VGS, ID = 250 µA 2.0 - 4.0 V Gate-Source Leakage IGSS VGS = ± 20 V - - ± 100 nA Zero Gate Voltage Drain Current IDSS VDS = 100 V, VGS = 0 V - - 25 VDS = 80 V, VGS = 0 V, TJ = 125 °C - - 250 Gate-Source Threshold Voltage Drain-Source On-State Resistance Forward Transconductance RDS(on) gfs ID = 2.6 Ab VGS = 10 V VDS = 50 V, ID = 2.6 A µA - - 0.54 Ω 1.6 - - S - 180 - - 80 - - 15 - - - 8.3 Dynamic Input Capacitance Ciss Output Capacitance Coss VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs - - 2.3 Gate-Drain Charge Qgd - - 3.8 Turn-On Delay Time td(on) - 6.9 - tr - 16 - - 15 - - 9.4 - - 4.5 - - 7.5 - Rise Time Turn-Off Delay Time Fall Time td(off) ID = 5.6 A, VDS = 80 V, see fig. 6 and 13b VDD = 50 V, ID = 5.6 A, RG = 24 Ω, RD = 8.4 Ω, see fig. 10b tf Internal Drain Inductance LD Internal Source Inductance LS www.kersemi.com 2 VGS = 10 V Between lead, 6 mm (0.25") from package and center of die contact D pF nC ns nH G S IRFR110, IRFU110, SiHFR110, SiHFU110 SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. - - 4.3 - - 17 - - 2.5 UNIT Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Currenta ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode D A G S TJ = 25 °C, IS = 4.3 A, VGS = 0 Vb TJ = 25 °C, IF = 5.6 A, dI/dt = 100 A/µsb V - 100 200 ns - 0.44 0.88 µC Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %. TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted Fig. 1 - Typical Output Characteristics, TC = 25 °C Fig. 2 -Typical Output Characteristics, TC = 150 °C Fig. 3 - Typical Transfer Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature www.kersemi.com 3 IRFR110, IRFU110, SiHFR110, SiHFU110 Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage www.kersemi.com 4 Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 8 - Maximum Safe Operating Area IRFR110, IRFU110, SiHFR110, SiHFU110 RD VDS VGS D.U.T. RG + - VDD 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Fig. 10a - Switching Time Test Circuit VDS 90 % 10 % VGS Fig. 9 - Maximum Drain Current vs. Case Temperature td(on) td(off) tf tr Fig. 10b - Switching Time Waveforms Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case VDS L Vary tp to obtain required IAS VDS tp VDD D.U.T. RG + - IAS V DD A VDS 10 V tp 0.01 Ω IAS Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms www.kersemi.com 5 IRFR110, IRFU110, SiHFR110, SiHFU110 Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ QG 10 V 12 V 0.2 µF 0.3 µF QGS QGD + D.U.T. VG - VDS VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform www.kersemi.com 6 Fig. 13b - Gate Charge Test Circuit IRFR110, IRFU110, SiHFR110, SiHFU110 Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - + • dV/dt controlled by R G • ISD controlled by duty factor "D" • D.U.T. - device under test RG Driver gate drive P.W. Period D= + - VDD P.W. Period VGS = 10 V* D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Body diode VDD forward drop Inductor current Ripple ≤ 5 % ISD * VGS = 5 V for logic level devices and 3 V drive devices Fig. 14 -For N-Channel www.kersemi.com 7