AUIRLR3636
D-Pak
AUIRLR3636
Features
l
l
l
l
l
l
l
Advanced Process Technology
Ultra Low On-Resistance
175°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
Lead-Free, RoHS Compliant
Automotive Qualified *
Description
Specifically designed for Automotive applications, thi
MOSFET utilizes the latest processing techniques to
achieve extremely low on-resistance per silicon area. Additional
features of this design are a 175°C junction operating
temperature, fast switching speed and improved repetitive
avalanche rating . These features combine to make this design
an extremely efficient and reliable device for use in Automotive
applications and a wide variety of other applications.
D
G
S
VDSS
RDS(on) typ.
max.
ID (Silicon Limited)
ID (Package Limited)
60V
5.4m:
6.8m:
99A
50A
c
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only; and
functional operation of the device at these or any other condition beyond those indicated in the specifications is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. The thermal resistance and power dissipation ratings are measured under
board mounted and still air conditions. Ambient temperature (TA) is 25°C, unless otherwise specified.
Symbol
ID @ TC = 25°C
ID @ TC = 100°C
ID @ TC = 25°C
IDM
PD @TC = 25°C
VGS
EAS
IAR
EAR
Parameter
Max.
99
70
50
396
143
0.95
±16
170
d
Pulsed Drain Current
Maximum Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy (Thermally Limited)
Avalanche Current
Repetitive Avalanche Energy
d
f
e
d
A
W
See Fig.14, 15, 22a, 22b
22
Peak Diode Recovery
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds (1.6mm from case)
dv/dt
TJ
TSTG
Units
c
c
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Package Limited)
W/°C
V
mJ
A
mJ
V/ns
-55 to + 175
°C
300
Thermal Resistance
Symbol
RθJC
RθJA
RθJA
2014-8-24
k
Parameter
Junction-to-Case
Junction-to-Ambient (PCB Mount)
Junction-to-Ambient
j
1
Typ.
Max.
Units
–––
–––
–––
1.05
50
110
°C/W
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AUIRLR3636
Static Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
V(BR)DSS
Drain-to-Source Breakdown Voltage
ΔV(BR)DSS/ΔTJ Breakdown Voltage Temp. Coefficient
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
gfs
RG(int)
IDSS
Gate Threshold Voltage
Forward Transconductance
Internal Gate Resistance
Drain-to-Source Leakage Current
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
60
–––
–––
–––
1.0
31
–––
–––
–––
–––
–––
–––
0.07
5.4
6.6
–––
–––
0.6
–––
–––
–––
–––
Conditions
–––
V VGS = 0V, ID = 250μA
––– V/°C Reference to 25°C, ID = 5mA
6.8
VGS = 10V, ID = 50A
mΩ
VGS = 4.5V, ID = 50A
8.3
2.5
V VDS = VGS, ID = 100μA
–––
S VDS = 25V, ID = 50A
–––
Ω
20
VDS = 60V, VGS = 0V
μA
250
VDS = 60V, VGS = 0V, TJ = 125°C
VGS = 16V
100
nA
VGS = -16V
-100
d
g
g
Dynamic Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Symbol
Qg
Qgs
Qgd
Qsync
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss eff. (ER)
Coss eff. (TR)
Parameter
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Min. Typ. Max. Units
i
h
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
33
11
15
18
45
216
43
69
3779
332
163
437
636
49
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Conditions
ID = 50A
VDS = 30V
nC
VGS = 4.5V
ID = 50A, VDS =0V, VGS = 4.5V
VDD = 39V
ID = 50A
ns
RG = 7.5 Ω
VGS = 4.5V
VGS = 0V
VDS = 50V
pF ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 48V ,See Fig.11
VGS = 0V, VDS = 0V to 48V
g
g
i
h
Diode Characteristics
Symbol
IS
Parameter
Continuous Source Current
VSD
trr
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Qrr
Reverse Recovery Charge
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
ISM
d
Notes:
Calcuted continuous current based on maximum allowable junction
temperature Bond wire current limit is 50A. Note that current
limitation arising from heating of the device leds may occur with
some lead mounting arrangements.
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.136 mH
RG = 25Ω, IAS = 50A, VGS =10V. Part not recommended for use
above this value .
ISD ≤ 50A, di/dt ≤ 1109 A/μs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
2014-8-24
Min. Typ. Max. Units
–––
–––
–––
–––
99
c
396
Conditions
MOSFET symbol
A
showing the
integral reverse
D
G
p-n junction diode.
TJ = 25°C, IS = 50A, VGS = 0V
TJ = 25°C
VR = 51V,
TJ = 125°C
IF = 50A
di/dt = 100A/μs
TJ = 25°C
S
g
––– –––
1.3
V
–––
27
–––
ns
–––
32
–––
–––
31
–––
nC
TJ = 125°C
–––
43
–––
–––
2.1
–––
A TJ = 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
g
Pulse width ≤ 400μs; duty cycle ≤ 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
When mounted on 1" square PCB (FR-4 or G-10 Material). For
recommended footprint and soldering techniquea refer to applocation
note # AN- 994 echniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C.
2
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AUIRLR3636
Qualification Information
†
Automotive
(per AEC-Q101)
Qualification Level
Moisture Sensitivity Level
Machine Model
ESD
Human Body Model
Charged Device
Model
††
Comments: This part number(s) passed Automotive qualification.
IR’s Industrial and Consumer qualification level is granted by
extension of the higher Automotive level.
D-PAK
MSL1
Class M4 (+/- 600V)
AEC-Q101-002
†††
Class H1C (+/- 2000V)
AEC-Q101-001
Class C5 (+/- 2000V)
AEC-Q101-005
RoHS Compliant
†††
†††
Yes
Qualification standards can be found at International Rectifiers web site: http//www.irf.com/
Exceptions (if any) to AEC-Q101 requirements are noted in the qualification report.
Highest passing voltage.
2014-8-24
3
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AUIRLR3636
1000
1000
100
BOTTOM
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
15V
10V
4.5V
4.0V
3.5V
3.3V
3.0V
2.7V
10
2.7V
1
100
≤60μs PULSE WIDTH
Tj = 25°C
1
10
2.7V
10
≤60μs PULSE WIDTH
Tj = 175°C
1
0.1
0.1
BOTTOM
0.1
100
10
100
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
1000
2.5
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (A)
1
V DS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
100
T J = 175°C
T J = 25°C
10
1
VDS = 25V
≤60μs PULSE WIDTH
0.1
ID = 50A
VGS = 10V
2.0
1.5
1.0
0.5
1
2
3
4
5
6
7
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
100000
5.0
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
VGS, Gate-to-Source Voltage (V)
10000
Ciss
1000
ID= 50A
4.5
C oss = C ds + C gd
C, Capacitance (pF)
VGS
15V
10V
4.5V
4.0V
3.5V
3.3V
3.0V
2.7V
Coss
Crss
VDS= 48V
VDS= 30V
VDS= 12V
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
100
1
10
0
100
10
15
20
25
30
35
40
QG, Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
2014-8-24
5
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
4
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AUIRLR3636
1000
1000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED BY R
DS(on)
T J = 175°C
100
T J = 25°C
10
1
100μsec
100
LIMITED BY PACKAGE
10
1msec
10msec
1
VGS = 0V
0.1
0.1
0.1
0.4
0.7
1
1.3
1.6
0.1
1.9
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
110
Limited By Package
ID, Drain Current (A)
90
80
70
60
50
40
30
20
10
0
25
50
75
100
125
150
175
100
80
Id = 5mA
75
70
65
60
55
50
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Temperature ( °C )
T C , Case Temperature (°C)
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Drain-to-Source Breakdown Voltage
0.8
EAS , Single Pulse Avalanche Energy (mJ)
800
0.6
Energy (μJ)
10
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
100
1
VDS, Drain-to-Source Voltage (V)
VSD, Source-to-Drain Voltage (V)
0.4
0.2
0.0
ID
5.69A
10.64A
BOTTOM 50A
700
TOP
600
500
400
300
200
100
0
0
5 10 15 20 25 30 35 40 45 50 55 60 65
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
VDS, Drain-to-Source Voltage (V)
Fig 11. Typical COSS Stored Energy
2014-8-24
DC
Tc = 25°C
Tj = 175°C
Single Pulse
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
5
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AUIRLR3636
Thermal Response ( Z thJC ) °C/W
10
1
D = 0.50
0.20
0.10
0.05
0.02
0.01
0.1
τJ
0.01
1E-005
τJ
τ1
R2
R2
R3
R3
R4
R4
τC
τ
τ1
τ2
τ3
τ2
Ci= τi/Ri
Ci i/Ri
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
R1
R1
0.0001
τ3
τ4
τ4
Ri (°C/W)
τi (sec)
0.02028
0.000011
0.29406
0.000158
0.49179
0.001393
0.24336
0.00725
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Avalanche Current (A)
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔTj = 150°C and
Tstart =25°C (Single Pulse)
100
0.01
0.05
10
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
EAR , Avalanche Energy (mJ)
200
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 50A
150
100
50
0
25
50
75
100
125
150
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
175
Starting T J , Junction Temperature (°C)
Fig 15. Maximum Avalanche Energy vs. Temperature
2014-8-24
6
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AUIRLR3636
14
IF = 20A
V R = 51V
12
2.5
TJ = 25°C
TJ = 125°C
10
2.0
IRRM (A)
VGS(th) , Gate threshold Voltage (V)
3.0
1.5
ID = 100μA
ID = 250μA
ID = 1.0mA
1.0
8
6
4
ID = 1.0A
0.5
2
0.0
0
-75 -50 -25
0
25 50 75 100 125 150 175
0
200
T J , Temperature ( °C )
600
800
1000
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage vs. Temperature
350
16
IF = 30A
V R = 51V
14
TJ = 25°C
TJ = 125°C
250
QRR (A)
10
IF = 20A
V R = 51V
300
TJ = 25°C
TJ = 125°C
12
IRRM (A)
400
diF /dt (A/μs)
8
6
200
150
100
4
50
2
0
0
0
200
400
600
800
0
1000
200
400
600
800
1000
diF /dt (A/μs)
diF /dt (A/μs)
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
350
IF = 30A
V R = 51V
300
TJ = 25°C
TJ = 125°C
QRR (A)
250
200
150
100
50
0
0
200
400
600
800
1000
diF /dt (A/μs)
Fig. 20 - Typical Stored Charge vs. dif/dt
2014-8-24
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AUIRLR3636
Driver Gate Drive
D.U.T
-
-
-
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D=
Period
P.W.
+
+
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor
Current
Inductor Curent
-
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V(BR)DSS
15V
DRIVER
L
VDS
tp
D.U.T
RG
VGS
20V
+
V
- DD
IAS
A
0.01Ω
tp
I AS
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
RD
VDS
VDS
90%
VGS
D.U.T.
RG
+
- VDD
V10V
GS
10%
VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
td(on)
Fig 23a. Switching Time Test Circuit
tr
t d(off)
Fig 23b. Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.T.
Vds
Vgs
50KΩ
12V
tf
.2μF
.3μF
D.U.T.
+
V
- DS
Vgs(th)
VGS
3mA
IG
ID
Qgs1 Qgs2
Current Sampling Resistors
Fig 24a. Gate Charge Test Circuit
2014-8-24
Qgd
Qgodr
Fig 24b. Gate Charge Waveform
8
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AUIRLR3636
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
Part Number
AULR3636
YWWA
Logo
XX
or
Date Code
Y= Year
WW= Work Week
A= Automotive, LeadFree
XX
Lot Code
2014-8-24
9
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AUIRLR3636
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRR
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
TRL
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
2014-8-24
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AUIRLR3636
Ordering Information
Base part number
AUIRLR3636
2014-8-24
Package Type
Dpak
Standard Pack
Form
Tube
Tape and Reel
Tape and Reel Left
Tape and Reel Right
11
Complete Part Number
Quantity
75
2000
3000
3000
AUIRLR3636
AUIRLR3636TR
AUIRLR3636TRL
AUIRLR3636TRR
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