LINER LTC2122 Dual 14-bit 170msps adc with jesd204b serial output Datasheet

LTC2122
Dual 14-Bit 170Msps ADC
with JESD204B Serial Outputs
FEATURES
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DESCRIPTION
6.0Gbps JESD204B Interface
Only One Output Lane Required for Both ADCs
(FS < = 150Msps)
70dBFS SNR
90dBFS SFDR
Low Power: 751mW Total
Single 1.8V Supply
Easy to Drive 1.5VP-P Input Range
1.25GHz Full Power Bandwidth S/H
Optional Clock Divide by Two
Optional Clock Duty Cycle Stabilizer
Low Power Sleep and Nap Modes
Serial SPI Port for Configuration
48-Lead (7mm × 7mm) QFN Package
APPLICATIONS
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Communications
Cellular Base Stations
Software Defined Radios
Medical Imaging
High Definition Video
Test and Measurement Instrumentation
The LTC®2122 is a 2-channel simultaneous sampling
170Msps 14-bit A/D converter with serial JESD204B
outputs. It is designed for digitizing high frequency,
wide dynamic range signals. It is perfect for demanding
communications applications with AC performance that
includes 70dBFS SNR and 90dBFS spurious free dynamic
range (SFDR). The 1.25GHz input bandwidth allows the
ADC to under-sample high frequencies.
The JESD204B serial interface simplifies the PCB design by
minimizing the number of data lines required. At 170Msps,
only two 3.4Gbps output lanes are required. For sample
rates up to 150Msps, both ADCs may share the same
output lane at up to 6.0Gbps.
The DEVCLK+ and DEVCLK– inputs can be driven differentially with sine wave, PECL, or LVDS signals. An optional
clock divide-by-two circuit or clock duty cycle stabilizer
maintains high performance at full speed for a wide range
of clock duty cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
64k Point 2-Tone FFT,
fIN = 71MHz and 69MHz,
–7dBFS, 170Msps
OVDD
1.2V TO 1.9V
LTC2122
50Ω
CLOCK
14-BIT ADC
JESD204B
LOGIC
CLOCK
÷ 2 OR ÷ 1
0
SERIALIZER
3.4Gbps
–20
PLL
OVDD
1.2V TO 1.9V
(170MHz OR
340MHz)
ANALOG
INPUT
JESD204B
FPGA OR ASIC
50Ω
14-BIT ADC
JESD204B
LOGIC
SERIALIZER
AMPLITUDE (dBFS)
ANALOG
INPUT
50Ω
–40
–60
–80
–100
50Ω
–120
3.4Gbps
0
10
20
30
40
50
60
70
80
FREQUENCY (MHz)
2122 TA01a
2122 TA01
2122fa
For more information www.linear.com/LTC2122
1
LTC2122
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
48
47
46
45
44
43
42
41
40
39
38
37
VDD
GND
CS
SCK
SDI
SDO
OF +
OF –
GND
GND
VDD
VDD
TOP VIEW
VDD 1
GND 2
AINA+ 3
AINA– 4
SENSE 5
VREF 6
VCM 7
GND 8
AINB– 9
AINB+ 10
GND 11
VDD 12
36
35
34
33
32
31
30
29
28
27
26
25
49
GND
OVDD
OVDD
DNC
DNC
CMLOUT_A0+
CMLOUT_A0–
CMLOUT_B0+
CMLOUT_B0–
DNC
DNC
OVDD
OVDD
VDD 13
GND 14
DEVCLK– 15
DEVCLK+ 16
GND 17
SYSREF+ 18
SYSREF – 19
GND 20
SYNC~+ 21
SYNC~ – 22
VDD 23
VDD 24
Supply Voltages
VDD, OVDD....................................................... 0.3V to 2V
Analog Input Voltage
AINA/B+, AINA/B –........................ –0.3V to (VDD + 0.2V)
SENSE (Note 3)............................. –0.3V to (VDD + 0.2V)
Digital Input Voltage
DEVCLK+, DEVCLK–, SYSREF+, SYSREF –,
SYNC~+, SYNC~ – (Note 3)........ –0.3V to (VDD + 0.3V)
CS, SDI, SCK (Note 4) ........................... –0.3V to 3.9V
SDO (Note 4) ............................................. –0.3V to 3.9V
Digital Output Voltage................... –0.3V to (VDD + 0.3V)
Operating Ambient Temperature Range
LTC2122C................................................. 0°C to 70°C
LTC2122I .............................................–40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
UK PACKAGE
48-LEAD (7mm × 7mm) PLASTIC QFN
TJMAX = 150°C, θJA = 28°C/W
EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2122CUK#PBF
LTC2122CUK#TRPBF
LTC2122UK
48-Lead (7mm × 7mm) Plastic QFN
0°C to 70°C
LTC2122IUK#PBF
LTC2122IUK#TRPBF
LTC2122UK
48-Lead (7mm × 7mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2
2122fa
For more information www.linear.com/LTC2122
LTC2122
CONVERTER CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
MIN
Resolution (No Missing Codes)
l
14
TYP
MAX
UNITS
Bits
Integral Linearity Error
Differential Analog Input (Note 6)
l
–5.1
±1.2
5.1
LSB
Differential Linearity Error
Differential Analog Input
l
–0.9
±0.35
0.9
LSB
Offset Error
(Note 7)
l
–13
±5
13
mV
Gain Error
Internal Reference
External Reference
l
–4.0
±1.5
±1
2.2
%FS
%FS
Offset Drift
Full-Scale Drift
Internal Reference
External Reference
Transition Noise
±20
µV/ºC
±30
±10
ppm/ºC
ppm/ºC
1.82
LSBRMS
ANALOG INPUT
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VIN
Analog Input Range (AIN+ – AIN–)
1.7V < VDD < 1.9V
l
VIN(CM)
Analog Input Common Mode (AIN+ + AIN–)/2
Differential Analog Input (Note 8)
l
VCM – 20mV
VCM
VCM + 20mV
VSENSE
External Voltage Reference Applied to SENSE External Reference Mode
l
1.2
1.250
1.3
V
IIN1
Analog Input Leakage Current
0 < AIN+, AIN– < VDD, No Clock
l
–1
1
µA
IIN2
SENSE Input Leakage Current
1.2V < SENSE < 1.3V
l
–1
1
µA
1.5
tAP
Sample-and-Hold Acquisition Delay Time
1
tJITTER
Sample-and-Hold Acquisition Delay Jitter
0.15
CMRR
Analog Input Common Mode Rejection Ratio
VP-P
V
ns
psRMS
75
BW–3dB Full-Power Bandwidth
dB
1250
MHz
DYNAMIC ACCURACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
SNR
Signal-to-Noise Ratio
15MHz Input
70MHz Input
140MHz Input
SFDR
Spurious Free Dynamic Range 2nd or 3rd
Harmonic
15MHz Input
70MHz Input
140MHz Input
Spurious Free Dynamic Range 4th Harmonic
or Higher
S/(N+D)
Signal-to-Noise Plus Distortion Ratio
Crosstalk Crosstalk Between Channels
15MHz Input
70MHz Input
140MHz Input
15MHz Input
70MHz Input
140MHz Input
Up to 250MHz Input
l
l
l
l
MIN
TYP
67.7
70
69.8
69.1
MAX
UNITS
dBFS
dBFS
dBFS
76
90
85
80
dBFS
dBFS
dBFS
83
95
95
85
dBFS
dBFS
dBFS
67.3
69.9
69.4
68.5
dBFS
dBFS
dBFS
–90
dB
2122fa
For more information www.linear.com/LTC2122
3
LTC2122
INTERNAL REFERENCE CHARACTERISTICS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
VCM Output Voltage
IOUT = 0
MIN
TYP
MAX
0.435 •
VDD – 18mV
0.435 •
VDD
0.435 •
VDD + 18mV
VCM Output Temperature Drift
UNITS
±37
VCM Output Resistance
–1mA < IOUT < 1mA
VREF Output Voltage
IOUT = 0
ppm/°C
4
1.225
Ω
1.250
VREF Output Temperature Drift
1.275
V
±30
VREF Output Resistance
–400µA < IOUT < 1mA
VREF Line Regulation
1.7V < VDD < 1.9V
V
ppm/°C
7
Ω
0.6
mV/V
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
1.85
1.8
1.9
1.9
V
V
1.9
1.9
V
V
417
459
mA
12
13.8
mA
751
826
mW
VDD
Analog Supply Voltage
Single-Lane Operation
Two-Lane Operation
l
l
1.8
1.7
OVDD
Output Supply Voltage
CML Current = 16mA, Directly Terminated (Note 8)
CML Current = 16mA, AC Terminated
l
l
1.2
1.4
IVDD
Analog Supply Current
IOVDD
Output Supply Current Per Lane
CML Current = 12mA
l
PDISS
Power Dissipation
VDD = 1.8V, Excluding OVDD Power
l
PSLEEP
Sleep Mode Power
2
mW
PNAP
Nap Mode Power
433
mW
l
11
DIGITAL INPUTS AND OUTPUTS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
CLOCK INPUTS (DEVCLK+, DEVCLK–)
VID
Differential Input Voltage
(Note 8)
l
0.2
VICM
Common Mode Input Voltage
Internally Set
Externally Set (Note 8)
l
1.1
RIN
Input Resistance
CIN
Input Capacitance
(See Figure 2)
V
1.2
1.5
V
V
10
kΩ
2
pF
Differential Digital Inputs (SYNC~+, SYNC~–, SYSREF+, SYSREF–)
VID
Differential Input Voltage
(Note 8)
VICM
Common Mode Input Voltage
Internally Set
Externally Set (Note 8)
l
l
0.2
1.1
V
1.2
1.5
V
V
RIN
Input Resistance
6.7
kΩ
CIN
Input Capacitance
2
pF
4
2122fa
For more information www.linear.com/LTC2122
LTC2122
DIGITAL INPUTS AND OUTPUTS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (CS, SDI, SCK)
VIH
High Level Input Voltage
VDD = 1.8V
l
VIL
Low Level Input Voltage
VDD = 1.8V
l
IIN
Input Current
VIN = 0V to 3.6V
l
CIN
Input Capacitance
(Note 8)
1.3
V
–10
0.6
V
10
µA
3
pF
SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO Is Used)
ROL
Logic Low Output Resistance to GND
VDD = 1.8V, SDO = 0V
IOH
Logic High Output Leakage Current
SDO = 0V to 3.6V
COUT
Output Capacitance
(Note 8)
200
l
–10
Ω
10
4
µA
pF
LVDS OUTPUTS (OF+, OF–)
VOD
Differential Output Voltage
VOS
Common Mode Output Voltage
100Ω Differential Load
l
247
350
454
l
1.125
1.25
1.375
mV
V
CML Outputs
VDIFF
CML Differential Output Voltage
Output Current Set to 10mA
Output Current Set to 12mA
Output Current Set to 14mA
Output Current Set to 16mA
500
600
700
800
VOH
Output High Level
Directly-Coupled 50Ω to OVDD
Directly-Coupled 100Ω Differential
AC-Coupled
OVDD
OVDD-1/4 VDIFF
OVDD-1/4 VDIFF
V
V
V
VOL
Output Low Level
Directly-Coupled 50Ω to OVDD
Directly-Coupled 100Ω Differential
AC-Coupled
OVDD-1/2 VDIFF
OVDD-3/4 VDIFF
OVDD-3/4 VDIFF
V
V
V
VOCM
Output Common Mode Level
Directly-Coupled 50Ω to OVDD
Directly-Coupled 100Ω Differential
AC-Coupled
OVDD-1/4 VDIFF
OVDD-1/2 VDIFF
OVDD-1/2 VDIFF
V
V
V
ROUT
Output Resistance
Single-Ended
Differential
l
80
50
100
mVppd
mVppd
mVppd
mVppd
Ω
Ω
120
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
fS, 1/tS
Sampling Frequency
(Note 9)
l
MIN
50
TYP
MAX
UNITS
170
MHz
tL
1× CLK Low Time (Note 8)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
2.79
1.5
2.94
2.94
10
10
ns
ns
tH
1× CLK High Time (Note 8)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
2.79
1.5
2.94
2.94
10
10
ns
ns
tDCK
DEVCLK Period
2X_CLK SPI Register = 0
2X_CLK SPI Register = 1
l
l
5.88
2.94
20
10
ns
ns
Write Mode
Readback Mode CSDO = 20pF, RPULLUP = 2k
l
l
40
250
ns
ns
SPI Port Timing (Note 8)
tSCK
SCK Period
tCSS
CS to SCK Set-Up Time
l
5
ns
tCSH
SCK to CS Hold Time
l
5
ns
tDS
SDI Set-Up Time
l
5
ns
2122fa
For more information www.linear.com/LTC2122
5
LTC2122
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
tDH
SDI Hold Time
tDO
SCK Falling to SDO Valid
CONDITIONS
MIN
l
Readback Mode CSDO = 20pF, RPULLUP = 2K
l
TYP
MAX
5
UNITS
ns
125
ns
1000
1000
ps
ps
0.3
0.35
UI
UI
JESD204B Timing (Note 8)
tBIT, UI
High Speed Serial Bit Period
1 Lane Mode (2 ADC to One Lane)
2 Lane Mode (1 Lane Per ADC)
l
l
tJIT
Total Jitter of CML Outputs (P-P)
> 3.125Gbps Per Lane (BER = 1E-15, Note 8)
< = 3.125Gbps Per Lane (BER = 1E-12, Note 8)
l
l
tSU_SYN
SYNC~ to CLK Set-Up Time
(Note 8)
l
0.6
tH_SYN
DEVCLK to SYNC~ Hold Time
(Note 8)
l
0.6
tSU_SYS
SYSREF to DEVCLK Set-Up Time
(Note 8)
l
0.2
tH_SYS
DEVCLK to SYSREF Hold Time
(Note 8)
l
0.32
LATP1
Pipeline Latency, Single-Lane Mode
(Note 10)
l
10.5
10.5
tS
LATP2
Pipeline Latency, 2-Lane Mode
(Note 10)
l
13.5
13.5
tS
tDS
Delay from DEVCLK to Serial Data Out
(Note 8)
l
0.6
tS
LATSC1
Latency from SYNC~ Assertion to COMMA
Out, Single Lane Mode
(Note 10)
l
7
7
tS
LATSC2
Latency from SYNC~ Assertion to COMMA
Out, 2-Lane Mode
(Note 10)
l
10
10
tS
LATSL1
Latency from SYNC~ De-assertion to LAS
Out, Single-Lane Mode
(Note 10, 11)
l
3
3
tS
LATSL2
Latency from SYNC~ De-assertion to LAS
Out, 2-Lane Mode
(Note 10, 11)
l
6
6
tS
LATOF
Overflow Latency
(Note 10)
l
6
6
tS
tD_OF1X
Analog Delay of OF with 1X_CLK
(Note 8)
l
1.4
1.7
2.0
ns
tD_OF2X
Analog Delay of OF with 2X_CLK
(Note 8)
l
1.6
1.9
2.2
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above VDD
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
Note 5: VDD = 1.8V, fSAMPLE = 170MHz, differential DEVCLK+/DEVCLK– =
2VP-P sine wave, input range = 1.5VP-P with differential drive, unless
otherwise noted.
6
167
294
ns
ns
(tDCK – 0.32)
ns
ns
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7: Offset error is the offset voltage measured from –0.5LSB when the
output code flickers between 01 1111 1111 1111 and 10 0000 0000 0000.
Note 8: Guaranteed by design, not subject to test.
Note 9: Recommended operating conditions.
Note 10: When the “2×_CLK” SPI register bit is set, the DEVCLK
frequency is 2× the sampling frequency. When the “2×_CLK” bit is not
set, the DEVCLK frequency is equal to the sampling frequency. Latency is
measured in units of sampling periods (tS), where tS is the inverse of the
sampling frequency.
Note 11: When in subclass 0, the Lane Alignment Sequence (LAS) latency
measurement begins at the start of the frame following the detection
of SYNC~ de-assertion. When in subclasses 1 or 2 this LAS latency
measurement begins at the start of the first multiframe following the
detection of SYNC~ de-assertion.
2122fa
For more information www.linear.com/LTC2122
LTC2122
TYPICAL PERFORMANCE CHARACTERISTICS
Differential Nonlinearity (DNL)
1.00
1.5
0.75
1.0
0.50
0.5
0.0
–0.5
–0.25
–1.5
–0.75
4096
8192
12288
–1.00
16384
20000
0.00
–0.50
0
25000
0.25
–1.0
–2.0
5000
0
4096
8192
12288
0
8192
16384
64k Point FFT, fIN = 140.0MHz,
–1dBFS, 170Msps
0
–20
–20
–20
–80
–100
AMPLITUDE (dBFS)
0
AMPLITUDE (dBFS)
0
–60
–40
–60
–80
–100
0
20
40
60
–120
80
–40
–60
–80
–100
0
20
FREQUENCY (MHz)
40
60
–120
80
–20
–100
AMPLITUDE (dBFS)
–20
AMPLITUDE (dBFS)
–20
–80
–40
–60
–80
40
60
80
FREQUENCY (MHz)
–120
0
20
40
60
80
–60
–80
–120
0
20
40
60
80
FREQUENCY (MHz)
FREQUENCY (MHz)
2122 G07
–40
–100
–100
20
80
64k Point FFT, fIN = 383.1MHz,
–1dBFS, 170Msps
0
–60
60
2122 G06
64k Point FFT, fIN = 223.1MHz,
–1dBFS, 170Msps
–40
40
FREQUENCY (MHz)
0
0
20
2122 G05
0
–120
0
FREQUENCY (MHz)
2122 G04
64k Point FFT, fIN = 185.1MHz,
–1dBFS, 170Msps
8207
2122 G03
64k Point FFT, fIN = 69.8MHz,
–1dBFS, 170Msps
–40
8198 8201 8204
OUTPUT CODE
2122 G02
64k Point FFT, fIN = 15.0MHz,
–1dBFS, 170Msps
–120
8195
OUTPUT CODE
2122 G01
AMPLITUDE (dBFS)
15000
10000
OUTPUT CODE
AMPLITUDE (dBFS)
AC Grounded Input Histogram
30000
COUNT
DNL ERROR (LSB)
INL ERROR (LSB)
Integral Nonlinearity (INL)
2.0
2122 G08
2122 G09
2122fa
For more information www.linear.com/LTC2122
7
LTC2122
TYPICAL PERFORMANCE CHARACTERISTICS
64k Point FFT, fIN = 567.0MHz,
–1dBFS, 170Msps
64k Point FFT, fIN = 907.0MHz
–1dBFS, 170Msps
0
0
–20
–20
–20
–40
–60
–80
–100
–120
AMPLITUDE (dBFS)
0
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
64k Point FFT, fIN = 421.1MHz,
–1dBFS, 170Msps
–40
–60
–80
–100
0
20
40
60
–120
80
0
20
40
60
SFDR vs Input Level, fIN = 70MHz,
1.5V Range, 170Msps
SNR vs Input Level, fIN = 70MHz,
1.5V Range, 170Msps
70
–100
dBFS
90
SNR (dBc AND dBFS)
–80
80
70
60
dBc
50
40
30
20
50
60
70
0
–80 –70 –60 –50 –40 –30 –20 –10
80
FREQUENCY (MHz)
20
0
–70
0
70
420
65
400
80
65
400
600
800
1000
INPUT FREQUENCY (MHz)
IVDD (mA)
85
70
60
55
380
–30
–20
340
45
320
40
0
200
400
600
–10
0
800
1000
2 LANE
1 LANE
360
50
300
40
60
80
100
120
140
160
180
SAMPLE RATE (Msps)
INPUT FREQUENCY (MHz)
2122 G16
–40
IVDD vs Sample Rate,
fIN = 15MHz, –1dBFS
440
75
–50
2122 G15
75
200
–60
INPUT LEVEL (dBFS)
90
0
dBc
30
SNR vs Input Frequency,
–1dBFS, 1.5V Range, 170Msps
SNR (dBFS)
SFDR (dBFS)
40
2122 G14
SFDR vs Input Frequency,
–1dBFS, 1.5V Range, 170Msps
8
50
INPUT LEVEL (dBFS)
2122 G13
60
dBFS
60
10
10
40
80
80
100
SFDR (dBc AND dBFS)
AMPLITUDE (dBFS)
–20
–60
60
2122 G12
110
–40
40
FREQUENCY (MHz)
120
30
20
2122 G11
0
20
0
FREQUENCY (MHz)
64k Point 2-Tone FFT, fIN = 71MHz
and 69MHz, –7dBFS, 170Msps
10
–80
–120
80
2122 G10
0
–60
–100
FREQUENCY (MHz)
–120
–40
2122 G17
2122 G18
2122fa
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LTC2122
TYPICAL PERFORMANCE CHARACTERISTICS
CMLOUT Bathtub Curve, 3.4Gbps
CMLOUT Eye Diagram, 3.4Gbps
1E-01
1E-05
100mV/DIV
BIT ERROR RATE (BER)
1E-03
1E-07
1E-09
1E-11
1E-13
1E-15
0.0
0.2
0.4
0.6
0.8
1.0
49.0ps/DIV
2122 G20
UNIT INTERVAL (UI)
2122 G19
CMLOUT Eye Diagram,
6.0Gbps Single Lane
CMLOUT Bathtub Curve, 6.0Gbps
1E-01
100mV/DIV
1E-05
1E-07
1E-09
1E-11
1E-13
1E-15
0.0
0.2
0.4
0.6
0.8
1.0
27.8ps/DIV
2122 G22
UNIT INTERVAL (UI)
2122 G21
CMLOUT Eye Diagram, 6.0Gbps,
Single Lane, 8in (20cm) FR4
100mV/DIV
BIT ERROR RATE (BER)
1E-03
27.8ps/DIV
2122 G23
2122fa
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9
LTC2122
PIN FUNCTIONS
VDD (Pins 1, 12, 13, 23, 24, 37, 38, 48): 1.8V Power
Supply. Bypass to ground with 0.1µF ceramic capacitors.
Adjacent pins can share bypass capacitor.
In subclass 2 a low to high transition of SYNC~ is sampled
on the rising edge of DEVCLK to reset the internal dividers
and set up deterministic latency.
GND (Pins 2, 8, 11, 14, 17, 20, 39, 40, 47, Exposed Pad
Pin 49): Device Power Ground. The exposed pad must be
soldered to the PCB ground.
OVDD (Pins 25, 26, 35, 36): 1.2V to 1.9V Output Driver
Supply. Bypass each pair to ground with 0.1μF ceramic
capacitors.
AINA+/AINA– (Pins 3, 4): Analog Input Pair for Channel A.
CMLOUT_B0–/CMLOUT_B0+ (Pins 29, 30): Current Mode
Logic Output Pair for Channel B in two lane mode. Must
be terminated with a 50Ω resistor to OVDD, a differential
100Ω resistor to the complementary output, or AC coupled
to another termination voltage.
SENSE (Pin 5): Reference Programming Pin. Connecting
SENSE to VDD selects the internal reference and a ±0.75V
input range. An external reference between 1.2V and 1.3V
applied to SENSE selects an input range of ±0.6 × VSENSE.
VREF (Pin 6): Reference Voltage Output. Bypass to ground
with a 2.2μF ceramic capacitor. Nominally 1.25V.
VCM (Pin 7): Common Mode Bias Output. Nominally equal
to 0.435 • VDD. VCM should be used to bias the common
mode of the analog inputs. Bypass to ground with a 0.1μF
ceramic capacitor.
CMLOUT_A0–/CMLOUT_A0+ (Pins 31, 32): Current Mode
Logic Output Pair for Channel A in two lane mode or for
both Channel A and Channel B in one lane mode. Must
be terminated with a 50Ω resistor to OVDD, a differential
100Ω resistor to the complementary output, or AC coupled
to another termination voltage.
INB
DEVCLK–/DEVCLK+ (Pins 15, 16): Device Clock Input Pair.
OF–/OF+ (Pins 41, 42): Over/Underflow LVDS Digital
Output. OF is high when an overflow or underflow has
occurred. The overflows for channel A and channel B are
multiplexed together and transmitted at twice the sample
frequency (OF = OF+ – OF–).
DEVCLK may optionally be divided by two. In subclass 1
a low to high transition of the SYSREF signal will initialize
the divide-by-two circuit on the rising edge of DEVCLK. In
Subclass 2 a low to high transition of the SYNC~ signal
will initialize the divide-by-two circuit on the rising edge
of DEVCLK.
SDO (Pin 43): Serial Interface Data Output. SDO is the
optional serial interface data output. Data on SDO is read
back from the mode control registers and can be latched
on the falling edge of SCK. SDO is an open-drain N-channel
MOSFET output that requires an external 2k pull-up resistor from 1.8V to 3.3V. If readback from the mode control
registers is not needed, the pull-up resistor is not necessary and SDO can be left unconnected.
–/A
AINB
+ (Pins 9, 10): Analog Input Pair for Channel B.
The sample clock is derived from this clock signal. In
divide-by-one mode, the analog signal is sampled on the
falling edge of DEVCLK (DEVCLK = DEVCLK+ – DEVCLK–).
SYSREF+/SYSREF– (Pins 18, 19): A JESD204B Subclass
1 Input Signal Pair. A low to high transition of SYSREF is
sampled on the rising edge of DEVCLK to reset the internal dividers and set up deterministic latency (SYSREF =
SYSREF+ – SYSREF–).
SYNC~+/SYNC~– (Pins 21, 22): A JESD204B Synchronization Input Signal Pair. Used to establish initial Code-Group
synchronization for all three subclasses. A low level of
the SYNC~ signal causes the LTC2122 to output K28.5
commas (SYNC~ = SYNC~+ – SYNC~–).
10
SDI (Pin 44): Serial Interface Data Input. SDI is the serial
interface data input. Data on SDI is clocked into the mode
control registers on the rising edge of SCK. SDI can be
driven with 1.8V to 3.3V logic.
SCK (Pin 45): Serial Interface Clock Input. SCK is the
serial interface clock input. SCK can be driven with 1.8V
to 3.3V logic.
CS (Pin 46): Serial Interface Chip Select Input. When CS is
low, SCK is enabled for shifting data on SDI into the mode
control registers. CS can be driven with 1.8V to 3.3V logic.
2122fa
For more information www.linear.com/LTC2122
LTC2122
BLOCK DIAGRAM
CS
SCK
SDI
SDO
SENSE
VREF
VCM
SPI
CONTROL
1.25V
REFERENCE
TEST
PATTERNS
ANALOG
INPUT A
ADC A
DATA
MAPPING
ANALOG
INPUT B
ADC B
DATA
MAPPING
DEVCLK
CLK
REC
PLL AND
CLK DIVIDERS
LANE ALIGN
SEQUENCE
SCRAMBLER
1+x14+x15
SCRAMBLER
1+x14+x15
LANE ALIGN
SEQUENCE
8B/10B
ENCODER
3.4Gbps/6.0Gbps
SERIALIZER
CML
DRIVER
ALIGNMENT
MONITORS
8B/10B
ENCODER
ALIGNMENT
MONITORS
CH. A, LANE 0,
3.4Gbps,
1 LANE/ADC
OR BOTH ADCs
AT 6.0Gbps
CH. B, LANE 1,
3.4Gbps,
1 LANE/ADC
3.4Gbps
SERIALIZER
CML
DRIVER
SYSREF
DECODE
SYSREF
SYSREF
REC
SYNC
DECODE
SYNC~
SYNC
REC
2122 BD01
Figure 1. Functional Block Diagram
2122fa
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11
LTC2122
TIMING DIAGRAM
tAP
ANALOG N–1
INPUT
N+14
N+13
N+1
N
tCONV
DEVCLK
tL
tH
tDS
LATP2
tBIT
CMLOUT_A0
N-14
N-13
N-1
N
N-14
N-13
N-1
N
CMLOUT_B0
2122 TD01
Two-Lane Timing (One Lane Per ADC), fDEVCLK = fS
ANALOG
INPUT
tAP
N–1
N+11
N+1
N
tCONV
DEVCLK
tL
tH
LATP1
tBIT
tDS
CMLOUT_A0
CH A
N-11
CH B
N-11
CH A
N
CH B
N
2122 TD02
One-Lane Timing (Two ADCs On One Lane), fDEVCLK = fS
12
2122fa
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LTC2122
TIMING DIAGRAM
tAP
ANALOG N–1
INPUT
N+6
N
N+7
N+5
N+1
DEVCLK
(1X_CLK)
LATOF
OF
CH A
N-7
CH B
N-7
CH A
N-6
CH B
N-6
tD_OF1X
CH A
N-5
CH A
N
CH B
N
CH A
N+1
CH B
N+1
2122 TD03
Over Flow (OF) Timing, 1X_CLK Mode
tAP
ANALOG N–1
INPUT
N+6
N+7
N+5
N+1
N
DEVCLK
(2X_CLK)
LATOF
OF
CH A
N-7
CH B
N-7
CH A
N-6
CH B
N-6
tD_OF2X
CH A
N-5
CH A
N
CH B
N
CH A
N+1
CH B
N+1
2122 TD04
Over-Flow (OF) Timing 2X_CLK Mode
DEVCLK
tH_SYS
SYSREF
tSU_SYS
2122 TD03
SYSREF Timing (Subclass 1)
DEVCLK
tH_SYN
SYNC~
2122 TD04
tSU_SYN
SYNC~ Rising Edge Clock Reset Timing (Subclass 2)
NOTE: DEVCLK = DEVCLK+ – DEVCLK–,
SYSREF = SYSREF+ – SYSREF–,
SYNC~ = SYNC~+ – SYNC~–,
2122fa
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13
LTC2122
SPI TIMING
tCSS
tCSH
CS
tSCK
SCK
X
X
tDH
tDS
SDI
SDO
X
R/W
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
X
HIGH IMPEDANCE
2122 ST01
SPI Timing, Write Mode
CS
SCK
X
SDI
X
SDO
X
RW
HIGH IMPEDANCE
A6
A5
A4
A3
A2
A1
A0
X
X
X
X
X
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
tDO
X
HIGH IMPEDANCE
2122 ST02
SPI Timing, Read Mode
14
2122fa
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LTC2122
DEFINITIONS
ADC PERFORMANCE TERMS
defined as the ratio of the RMS value of either input tone
to the RMS value of the largest 3rd order IMD product.
Aperture Delay Time
The time it takes for the input signal to be held by the
sample-and-hold circuit after the rising edge of DEVCLK+
is equal to the falling edge of DEVCLK– on the sampling
edge of DEVCLK.
Aperture Delay Jitter
The variation in the aperture delay time from conversion
to conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNRJITTER = –20log (2π • fIN • tJITTER)
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N+D)] is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band limited to frequencies above DC to below half the sampling
frequency.
Crosstalk
Crosstalk is the coupling from one channel (being driven
by a full-scale signal) onto the other channel (being driven
by a –1dBFS signal).
Signal-to-Noise Ratio
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused
by the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function
can create distortion products at the sum and difference
frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.
For example, the 3rd order IMD terms include (2fa + fb),
(fa + 2fb), (2fa – fb) and (fa – 2fb). The 3rd order IMD is
The signal-to-noise (SNR) is the ratio between the RMS
amplitude of the fundamental input frequency and the RMS
amplitude of all other frequency components, except the
first five harmonics.
Spurious Free Dynamic Range (SFDR)
The ratio of the RMS input signal amplitude to the RMS
value of the peak spurious spectral component expressed
in dBc. SFDR may also be calculated relative to full scale
and expressed in dBFS.
2122fa
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15
LTC2122
DEFINITIONS
SERIAL INTERFACE TERMS
Comma
8B/10B Encoding
A special 8B/10B code-group containing the binary sequence “0011111” or “1100000”. Commas are used for
frame alignment and synchronization because a comma
sequence cannot be generated by any combination of
normal code-groups (unless a bit error occurs). There are
three special code-groups that contain a comma, K28.1,
K28.5, and K28.7.
A data encoding standard that encodes an 8-bit octet into
a 10-bit code-group (IEEE Std 802.3-2002 part 3, clause
36.2). The resulting code-group is ideal for serial transmission for two fundamental reasons: 1) The receiver does not
require a high speed clock to capture the data because the
code-groups are run-length limited to ensure a sufficient
number of transitions for PLL-based clock recovery 2)
AC coupling is permitted because the code-groups are
DC balanced (see Running Disparity).
For brevity, each of these three special code-groups are
often called a comma, but in the strictest sense it is the first
7 bits of these code-groups that are designated a comma.
A table of the 256 possible input octets with the resulting
10-bit code-groups is documented in IEEE Std 802.3-2002
part 3 Table 36-1. A name associated with each of the 256
data code-groups is formatted “Dx.y”, with x ranging from
0 to 31 and y ranging from 0 to 7. Additionally, Table 36-2
of the standard defines a set of 12 special code-groups
used as non-data characters (such as commas) with the
naming format of “Kx.y”.
A specially conditioned signal that may be AC coupled with
minimal degradation to the signal. DC balance is achieved
when the average number of 1’s and 0’s are equal, eliminating the undesirable effects of DC wander on the receive
side of the coupling capacitor. When 8B/10B coding is
used, DC balance is achieved by following disparity rules
(see Running Disparity).
Current Mode Logic (CML)
De-Scrambler
A circuit technique used to implement differential high
speed logic. CML employs differential pairs (usually ntype) to steer current into resistive loads. It is possible
to implement any logic function using CML. The output
swing and offset is dependent on the bias current, the
load resistance, and termination resistance.
This product family uses CML drivers to transmit high
speed serial data to the outside world. The output driver
bias current is typically programmable from 10mA to 16mA,
generating a signal swing of approximately 250mVP-P
(500mVppd) to 400mVP-P (800mVppd) across the combined internal and external termination resistance of 25Ω
(50Ω source//50Ω termination) on each output (mVppd
stands for mVP-P differential).
Code-Group
The 10-bit output from an 8B/10B encoder or the 10-bit
input to the 8B/10B decoder.
16
DC Balanced Signal
A logic block that restores scrambled data to its prescrambled state. A self aligning de-scrambler is based on
the same pseudo random bit sequence as the scrambler,
so it requires no alignment signals. In this product family the scrambler is based on the 1+x14+x15 polynomial,
and the self aligning process results in an initial loss of
15 bits, or one ADC sample.
Deterministic Latency
A predictable and repeatable delay from the input to the
output of the system. JESD204B subclasses1 and 2 employ technologies that support a predictable and repeatable
pipeline delay through the system.
Frame
The LTC2122 frame consists of two complete code-groups
per lane, and constitutes one complete ADC sample per
lane.
2122fa
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LTC2122
DEFINITIONS
Frame Alignment Monitoring (FAM)
Octet
After initial frame synchronization has been established,
frame alignment monitoring enables the receiver to verify
that code-group alignment is maintained without the loss
of data. This is done by substituting a K28.7 comma for the
last code-group of the frame when certain conditions are
met. The receiver uses this comma as a position marker
within the frame for alignment verification. After decoding
the data, the receiver replaces the K28.7 comma with the
original data.
The 8-bit input to an 8B/10B encoder, or the 8-bit output
from an 8B/10B decoder.
Initial Frame Synchronization
The process of communicating frame boundary information to the receiver for alignment purposes. The receiver
asserts the SYNC~ signal causing the ADC to transmit
K28.5 commas to the receiver. The receiver deasserts the
SYNC~ signal, and the ADC ceases transmission of commas according to the rules of the particular sub-class and
mode of operation. The point of termination of commas
in the data stream marks the frame boundary.
Lane Alignment Monitoring (LAM)
In JESD204B, lane alignment is attained and monitored
through the use of the 8B/10B K28.3 special characters.
These characters are conditionally embedded in the data
stream at the end of the multiframe. The receiver uses this
character as a position marker within the multiframe for
lane alignment verification. After decoding the data, the
receiver replaces the K28.3 character with the original data.
Local Multiframe Clock (LMFC)
An internal clock within each device of a JESD204B system
that marks the multiframe boundary.
Multiframe
A group of frames intended to be of long duration compared to lane mismatches in multiple lane systems. In
JESD204B the maximum Multiframe length is 32 frames.
There is no external multiframe clock in a JESD204B system, so the signal marking the multiframe boundaries is
referred to as the local multiframe clock (LMFC).
Run-Length Limited (RLL)
Data that has been encoded for the purpose of limiting
the number of consecutive 1’s or 0’s in a data stream.
This process guarantees that there will be an adequate
number of transitions in the serial data for the receiver to
lock onto with a phase-locked loop and recover the high
speed clock.
Running Disparity
In order to maintain DC balance most 8B/10B code-groups
have two output possibilities for each input octet. The running disparity is calculated to determine which of the two
code-groups should be transmitted to maintain DC balance.
The disparity of a code-group is analyzed in two segments
called sub-blocks. Sub-block1 consists of the first six bits
of a code-group and sub-block2 consists of the last four
bits of a code-group. When a sub-block is more heavily
weighted with 1’s the running disparity is positive, and when
it is more heavily weighted with 0’s the running disparity
is negative. When the number of 1’s and 0’s are equal in
a sub-block, the running disparity remains unchanged.
The polarity of the current running disparity determines
which code-group should be transmitted to maintain DC
balance. For a complete description of disparity rules, refer
to IEEE Std 802.3-2002 part 3, Clause 36.2.4.4.
Pseudo Random Bit Sequence (PRBS)
A data sequence having a random nature over a finite interval. The most commonly used PRBS test patterns may be
described by a polynomial in the form of 1+xm+xn and have
a random nature for the length of up to 2n-1 bits, where n
indicates the order of the PRBS polynomial and m plays
a role in maximizing the length of the random sequence.
Scrambler
A logic block that applies a pseudo random bit sequence
to the input octets to minimize the tonal content of the
high speed serial bit stream.
2122fa
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17
LTC2122
APPLICATIONS INFORMATION
CONVERTER OPERATION
INPUT DRIVE CIRCUITS
The LTC2122 is a two-channel, 14-bit 170Msps A/D
converter with JESD204B high speed serial outputs. The
analog inputs must be driven differentially. The DEVCLK
inputs should be driven differentially for optimal performance. The high speed serial interface is capable of data
rates of up to 6.0Gbps per lane. The overflow/underflow
indicators are available as part of the high speed serial
data, and optionally as low-latency double data rate LVDS
outputs. A SPI port provides programmability of multiple
user options.
Input Filtering
ANALOG INPUT
The analog inputs are differential CMOS sample-and hold
circuits (Figure 2). The inputs must be driven differentially
around a common mode voltage set by the VCM output
pin, which is nominally 0.8V. For the 1.5V input range,
the inputs should swing from VCM – 0.375V to VCM +
0.375V. There should be 180° phase difference between
the inputs. The two channels are simultaneously sampled
by a shared clock circuit.
If possible, there should be an RC lowpass filter right at
the analog inputs. This lowpass filter isolates the drive
circuitry from the A/D sample-and-hold switching, and also
limits wide band noise from the drive circuitry. Figure 3
shows an example of an input RC filter. The RC component values should be chosen based on the application’s
specific input frequency.
Transformer-Coupled Circuits
Figure 3 shows the analog input being driven by an RF
transformer with the common mode supplied through a
pair of resistors via the VCM pin. At higher input frequencies
a transmission line balun transformer (Figures 4 and 5)
has better balance, resulting in lower A/D distortion.
10Ω
VCM
0.1µF
0.1µF
4.7Ω
IN
LTC2122
LTC2122
AIN+
25Ω
VDD
RON
20Ω
+
2pF
AIN
10pF
0.1µF
4.7Ω
25Ω
AIN–
2pF
VDD
T1: MACOM ETC1-1T
RON
20Ω
AIN–
2pF
Figure 3. Analog Input Circuit Using a Transformer.
Recommended for Input Frequencies from 5MHz to 70MHz
2pF
VDD
1.2V
2122 F03
÷1
OR
÷2
10Ω
VCM
0.1µF
0.1µF
10k
10k
IN
DEVCLK+
AIN+
45Ω
DEVCLK–
0.1µF
0.1µF
2122 F02
Figure 2. Equivalent Input Circuit for a Single Channel
18
LTC2122
4.7Ω
100Ω
45Ω
T1: MABA
T2: WBC1-1L
007159-000000
4.7Ω
AIN–
2122 F04
Figure 4. Recommended Front-End Circuit for
Input Frequencies from 15MHz to 150MHz
2122fa
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LTC2122
APPLICATIONS INFORMATION
Amplifier Circuits
VCM
0.1µF
10Ω
0.1µF
LTC2122
4.7Ω
IN
45Ω
AIN+
100Ω
0.1µF
45Ω
0.1µF
4.7Ω
AIN–
T1: MABA
007159-000000
2122 F05
Figure 5. Recommended Front-End Circuit for
Input Frequencies from 150MHz to 900MHz
50Ω
50Ω
Reference
VCM
0.1µF
LTC2122
3pF
0.1µF
4.7Ω
INPUT
0.1µF
4.7Ω
AIN–
3pF
2122 F06
Figure 6. Front-End Circuit Using a
High Speed Differential Amplifier
VREF
5Ω
The LTC2122 has an internal 1.25V voltage reference. For
a 1.5V input range with internal reference, connect SENSE
to VDD. For a 1.5V input range with an external reference,
apply a 1.25V reference voltage to SENSE (Figure 7).
Device Clock (DEVCLK) Input
AIN+
3pF
Figure 6 shows the analog input being driven by a high
speed differential amplifier. The output of the amplifier is
AC coupled to the A/D so the amplifier’s output common
mode voltage can be optimally set to minimize distortion.
At very high frequencies an RF gain block will often have
lower distortion than a differential amplifier. If the gain
block is single-ended, then a transformer circuit (Figures 3
through 5) should convert the signal to differential before
driving the A/D. The A/D cannot be driven single-ended.
LTC2122
1.25V
The DEVCLK is used to derive the ADC sample clock, so
the signal quality of the DEVCLK inputs strongly affects
the A/D noise performance. The DEVCLK inputs should
be treated as analog signals. Do not route them next to
digital traces on the circuit board. The DEVCLK inputs are
internally biased to 1.2V through 10k equivalent resistance
(Figure 8).
LTC2122
2.2µF
VDD
1.2V
SCALER/
BUFFER
SENSE
ADC
REFERENCE
10k
10k
DEVCLK+
SENSE
DETECTOR
2122 F07
DEVCLK–
Figure 7. Reference Circuit
2122 F08
Figure 8. Equivalent DEVCLK Input Circuit
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19
LTC2122
APPLICATIONS INFORMATION
If the common mode of the driver is within 1.1V to 1.5V, it
is possible to drive the DEVCLK inputs directly. Otherwise
a transformer or coupling capacitors are needed (Figures
9 and 10). The maximum (peak) voltage of the input signal
should never exceed VDD +0.1V or go below –0.1V.
The ADC sample clock is derived from DEVCLK. For good
performance the sample clock should have a 50% (±5%)
duty cycle. There are two programmable options provided
in the LTC2122 that will ensure a 50% duty cycle sample
clock:
1) An optional DEVCLK divide-by-two circuit is provided
in the clock path to convert a 2X harmonic DEVCLK to
a 50% duty cycle sample clock. The 2X_CLK option is
enabled via SPI register 2, bit 2.
2) If a 2X clock is not available, the clock Duty Cycle
Stabilizer (DCS) circuit may be enabled. When enabled,
the DEVCLK duty cycle can vary from 30% to 70% and
the duty cycle stabilizer will maintain a constant 50%
internal duty cycle. The duty cycle stabilizer is enabled
via SPI register 2, bit 0. If the 2X_CLK option is selected
in the SPI register the Duty Cycle Stabilizer is disabled
regardless of the state of the DCS_en bit.
For applications where the sample rate needs to be changed
quickly and a 2X clock is not available, both the 2X_CLK
and the clock duty cycle stabilizer may be disabled. In this
case, care should be taken to make the DEVCLK a 50%
(±5%) duty cycle.
Overflow Detection
An overflow (OF) is detected when the analog inputs
are either over-ranged or under-ranged. There are two
mechanisms for reporting an OF event:
1) The OF bit is transmitted as part of the serial bit stream
following the LSB of the ADC data.
2) There is a separate LVDS output pair dedicated to early
indication of an OF event. The LVDS OF indicator has a
latency of 6 sample clock cycles. Both ADC OF signals
are multiplexed to one output pair at double data rate.
The Channel A OF signal is active on the first half of
the internal sample clock and the Channel B OF signal
is active on the second half of the cycle.
The LVDS OF indicator is output at standard LVDS levels:
3.5mA output current and a 1.25V output common mode
voltage. An external 100Ω differential termination resistor
is required to function properly. The termination resistor should be located as close as possible to the LVDS
receiver. If used, this LVDS output pair is enabled via SPI
register 2, bit 1.
DATA FORMAT
Table 1 shows the relationship between the analog input
voltage, the digital data output bits and the overflow bit.
The output data format is offset binary.
LTC2122
VDD
1.2V
10k
0.1µF
10k
50Ω
0.1µF
0.1µF
100Ω
50Ω
T1: MACOM
ETC1-1-13
2122 F09
Figure 9. Sinusoidal DEVCLK Drive
20
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LTC2122
APPLICATIONS INFORMATION
LTC2122
interface stay active, allowing faster wake-up. While in nap
mode the data at the output of the each ADC is forced to
zero. The SPI and the serial test patterns are fully functional in nap mode, so any test pattern may be selected
through the SPI. Recovering from nap mode requires at
least 100 clock cycles.
VDD
1.2V
0.1µF
PECL OR
LVDS INPUT
10k
10k
DEVCLK+
JESD204B Overview
100Ω
0.1µF
DEVCLK–
2122 F10
Figure 10. AC Coupled DEVCLK Drive
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–(1.5V RANGE)
OF
D13-D0
(OFFSET BINARY)
>0.75V
+0.75V
+0.749908V
1
0
0
11 1111 1111 1111
11 1111 1111 1111
11 1111 1111 1110
+0.0000915V
+0.000000V
–0.0000915V
–0.0001831V
0
0
0
0
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1110
–0.7499084V
–0.75V
< –0.75V
0
0
1
00 0000 0000 0001
00 0000 0000 0000
00 0000 0000 0000
Power Down Modes
The power down modes are controlled through register 1 of
the SPI interface. The two ADC channels may be powered
down separately, simultaneously, or the entire device may
be placed in sleep mode to conserve power. The “PDA”
and “PDB” SPI register bits are used to power down each
ADC channel individually while keeping the internal clock
and reference circuits active. “SLEEP” powers down the
entire device, resulting in < 5mW power consumption.
The amount of time required to recover from sleep mode
depends on the size of the bypass capacitor on VREF. For the
suggested value of 2.2µF, the A/D will stabilize after 0.1ms
+ 2500 • tp where tp is the period of the sampling clock.
Nap Mode
In "NAP” mode both ADC cores are powered down while
the internal clock circuits, reference circuits, and serial
JESD204B is a JEDEC standard that defines a high speed
serial interface for data converters. The advantages of
serialization include the simplification of printed circuit
board (PCB) layout through the reduction of traces on
the PCB. JESD204B solves several problems associated
with serial data transmission, such as the identification
of the start of a sample and the proper alignment of data
arriving on multiple lanes.
JESD204B devices encode the parallel data using industry
standard 8B/10B code-groups (IEEE 802.3-2002, section 3).
There is an overhead requirement of 2 bits for every 8
encoded bits (8 bits are encoded to 10 bits), but encoding
the ADC data prior to serialization provides certain benefits
which make the transmitted data more suitable for serial
transmission: These benefits include DC balance (for AC
coupling), and Run-Length Limiting (providing a sufficient
number of transitions for the receiver to extract the clock
from the data with a Phase-Locked Loop).
Figures 11 and 12 illustrate the transformation of ADC
sampled data into 10-bit code-groups prior to transmission.
The code-groups are formed into frames and multiframes.
For the LTC2122, there are two possible lane configurations:
1) One lane mode (both ADCs multiplexed to one lane) at
up to 6.0Gbps per lane (up to 150Msps).
2) Two lane mode (one lane per ADC) operating at up to
3.4Gbps per lane.
SYNC~ Signal
In addition to the high speed serial lanes, JESD204B
requires the use of a SYNC~ (active low) signal. The
SYNC~ signal originates from the receiver and serves as
a request to the LTC2122 that synchronization is required
(JESD204B 4.9).
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21
22
BIT
1
BIT
0
BIT
2
F
BIT
4
E
BIT
5
F
BIT
5
BIT
4
BIT
3
BIT
5
I
BIT
6
F
BIT
7
G
BIT
2
C
OCTET 0
E
D
C
BIT
2
D
BIT
9
BIT
3
E
BIT
4
BIT
10
FINAL OCTET 0
BIT
11
8B/10B CODE GROUP 0
BIT
3
D
BIT
6
BIT
7
C
G
H
BIT
12
BIT 0 OF CODE GROUP 0 IS TRANSMITTED FIRST
B
A
G
BIT
6
H
BIT
7
BIT
13
MSB
B
A
BIT
9
J
BIT
0
A
BIT
0
BIT
6
BIT
5
H
G
BIT
0
BIT
3
BIT
1
B
BIT
6
BIT
7
A
G
BIT
6
H
BIT
7
BIT
4
F
BIT
2
C
BIT
5
F
BIT
5
E
D
BIT
4
BIT
3
BIT
0
BIT
4
E
BIT
5
I
BIT
2
C
OF
BIT
B
BIT
6
F
BIT
1
B
BIT
1
Ø
8B/10B CODE GROUP 1
BIT
3
D
C
BIT
2
LSB
BIT
3
OCTET 1
E
D
BIT
4
BIT
1
FINAL OCTET 1
BIT
2
For more information www.linear.com/LTC2122
A
BIT
7
G
BIT
0
A
BIT
0
BIT
8
H
BIT
9
J
ONE FRAME
8B/10B
ENCODER
BIT
0
A
JESD204B PROCESSING
(SCRAMBLING, SUBSTITUTIONS, ETC.)
OCTET
MAPPING
BIT
1
B
H
BIT
2
C
BIT
7
H
BIT
7
G
BIT
3
D
BIT
6
G
BIT
6
BIT
12
F
BIT
4
E
BIT
5
F
BIT
5
E
D
BIT
3
BIT
4
BIT
3
OCTET 2
E
D
BIT
4
BIT
10
BIT
9
BIT
5
I
BIT
6
F
FINAL OCTET 2
BIT
11
8B/10B CODE GROUP 2
BIT
13
MSB
C
BIT
7
G
BIT
2
C
BIT
2
B
BIT
8
H
BIT
1
B
BIT
1
BIT
7
A
BIT
9
J
BIT
0
A
BIT
0
BIT
6
BIT
5
H
BIT
0
A
BIT
7
H
BIT
7
BIT
4
G
BIT
1
B
BIT
6
G
BIT
6
BIT
3
ADC CHANNEL B OUTPUT WORD
BIT
8
Figure 11. Word Formation of the Single Lane in One-Lane Mode
SERIAL OUT FOR CHANNEL A AND B (LANE 0)
BIT
8
H
BIT
1
B
BIT
1
BIT
7
ADC CHANNEL A OUTPUT WORD
BIT
8
F
BIT
2
C
BIT
5
F
BIT
5
E
D
BIT
4
BIT
3
BIT
0
D
E
BIT
4
C
I
BIT
2
OF
BIT
B
BIT
6
F
BIT
1
B
BIT
1
Ø
8B/10B CODE GROUP 3
BIT
3
C
BIT
2
BIT
5
LSB
BIT
3
OCTET 3
E
D
BIT
4
BIT
1
FINAL OCTET 3
BIT
2
A
BIT
7
G
BIT
0
A
BIT
0
H
BIT
8
J
2122 F11
BIT
9
LTC2122
APPLICATIONS INFORMATION
2122fa
LTC2122
APPLICATIONS INFORMATION
ADC CHANNEL A OUTPUT WORD
MSB
BIT
13
BIT
12
BIT
11
BIT
10
BIT
9
BIT
8
BIT
7
BIT
6
BIT
5
BIT
4
LSB
BIT
3
BIT
2
BIT
1
BIT
0
OF
BIT
Ø
OCTET
MAPPING
H
G
F
E
D
C
B
A
H
G
F
E
D
C
B
A
BIT
7
BIT
6
BIT
5
BIT
4
BIT
3
BIT
2
BIT
1
BIT
0
BIT
7
BIT
6
BIT
5
BIT
4
BIT
3
BIT
2
BIT
1
BIT
0
H
G
B
A
H
G
B
A
BIT
7
BIT
6
BIT
1
BIT
0
BIT
7
BIT
6
BIT
1
BIT
0
CHANNEL A, OCTET 0
F
E
D
C
BIT
5
BIT
4
BIT
3
BIT
2
CHANNEL A, OCTET 1
F
E
D
C
BIT
5
CHANNEL A, FINAL OCTET 0
BIT
4
BIT
3
BIT
2
JESD204B PROCESSING
(SCRAMBLING, SUBSTITUTIONS, ETC.)
CHANNEL A, FINAL OCTET 1
8B/10B
ENCODER
A
B
C
D
E
I
F
G
H
J
A
B
C
D
E
I
F
G
H
J
BIT
0
BIT
1
BIT
2
BIT
3
BIT
4
BIT
5
BIT
6
BIT
7
BIT
8
BIT
9
BIT
0
BIT
1
BIT
2
BIT
3
BIT
4
BIT
5
BIT
6
BIT
7
BIT
8
BIT
9
CHANNEL A, 8B/10B CODE GROUP 0
(MOST SIGNIFICANT WORD)
CHANNEL A, 8B/10B CODE GROUP 1
(LEAST SIGNIFICANT WORD)
ONE FRAME
BIT 0 OF CODE GROUP 0 IS TRANSMITTED FIRST
SERIAL OUT FOR CHANNEL A (LANE 0)
ADC CHANNEL B OUTPUT WORD
MSB
BIT
13
BIT
12
BIT
11
BIT
10
BIT
9
BIT
8
BIT
7
BIT
6
BIT
5
BIT
4
LSB
BIT
3
BIT
2
BIT
1
BIT
0
OF
BIT
Ø
OCTET
MAPPING
H
G
F
E
D
C
B
A
H
G
F
E
D
C
B
A
BIT
7
BIT
6
BIT
5
BIT
4
BIT
3
BIT
2
BIT
1
BIT
0
BIT
7
BIT
6
BIT
5
BIT
4
BIT
3
BIT
2
BIT
1
BIT
0
H
G
B
A
H
G
B
A
BIT
7
BIT
6
BIT
1
BIT
0
BIT
7
BIT
6
BIT
1
BIT
0
CHANNEL B, OCTET 0
F
E
D
C
BIT
5
BIT
4
BIT
3
BIT
2
CHANNEL B, FINAL OCTET 0
CHANNEL B, OCTET 1
F
E
D
C
BIT
5
BIT
4
BIT
3
BIT
2
JESD204B PROCESSING
(SCRAMBLING, SUBSTITUTIONS, ETC.)
CHANNEL B, FINAL OCTET 1
8B/10B
ENCODER
A
B
C
D
E
I
F
G
H
J
A
B
C
D
E
I
F
G
H
J
BIT
0
BIT
1
BIT
2
BIT
3
BIT
4
BIT
5
BIT
6
BIT
7
BIT
8
BIT
9
BIT
0
BIT
1
BIT
2
BIT
3
BIT
4
BIT
5
BIT
6
BIT
7
BIT
8
BIT
9
CHANNEL B, 8B/10B CODE GROUP 0
(MOST SIGNIFICANT WORD)
CHANNEL B, 8B/10B CODE GROUP 1
(LEAST SIGNIFICANT WORD)
ONE FRAME
BIT 0 OF CODE GROUP 0 IS TRANSMITTED FIRST
2122 F12
SERIAL OUT FOR CHANNEL B (LANE 1)
Figure 12. Word Formation of Each Lane in Two-Lane Mode
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23
LTC2122
APPLICATIONS INFORMATION
Table 2. JESD204B Link Configuration Parameters
JESD204B LINK
CONFIGURATION
PARAMETER
LTC2122 DEVICE
VALUE FOR SINGLE
LANE MODE
ENCODING
DID<7:0>
SPI Programmable
SPI Programmable
Binary Value
ADJCNT<3:0>
NA, 0000
NA, 0000
Binary Value
BID<3:0>
SPI Programmable
SPI Programmable
Binary Value
ADJDIR
NA, 0
NA, 0
Binary Value
PHADJ
NA, 0
NA, 0
Binary Value
LID–1<4:0>
CMLOUT_A0
CMLOUT_B0
0_0000
NA
0_0000
0_0001
SCR<0>
SPI Programmable
SPI Programmable
Binary Value Minus 1
Binary Value
L –1<4:0>
0_0000
0_0001
Binary Value Minus 1
F–1<7:0>
0000_0011
0000_0001
Binary Value Minus 1
K–1<4:0>
SPI Programmable
SPI Programmable
Binary Value Minus 1
M–1<7:0>
0000_0001
0000_0001
Binary Value Minus 1
CS<1:0>
01
01
Binary Value
N–1<4:0>
0_1101
0_1101
Binary Value Minus 1
SUBCLASSV<2:0>
SPI Programmable
SPI Programmable
Binary Value
N’–1<4:0>
0_1111
0_1111
Binary Value Minus 1
JESDV<2:0>
001
001
Binary Value
S–1<4:0>
0_0000
0_0000
Binary Value Minus 1
HD
0
0
Binary Value
CF<4:0>
0_0000
0_0000
Binary Value
FCHK<7:0>
Sum of all fields mod
256
Sum of all fields mod
256
Binary Value
JESD204B Link Configuration Parameters
There are 20 link configuration parameters used by
JESD204B to describe the operation of the link (JESD204B
8.3, Table 20). The receiver must match the parameters
of the LTC2122 in order for error free communication to
take place. Table 2 summarizes the link parameters of
the LTC2122.
JESD204B Subclasses
There are 3 subclasses of operation for JESD204B. These
subclasses provide different levels of deterministic latency
through the communication link. Below is a simple overview
of the three subclasses:
24
LTC2122 DEVICE
VALUE FOR ONE LANE
PER ADC MODE
Subclass 0: No deterministic latency support is provided.
There is no support for resetting and aligning critical clocks
between the LTC2122 and the receiver. The LTC2122 is
compliant with this subclass.
Subclass 1: Deterministic latency is obtained through the
addition of a SYSREF signal. The SYSREF signal provides
precise timing information for aligning critical clocks in
the LTC2122 and in the receiver. The low to high transition
of SYSREF is sampled by the rising edge of DEVCLK, so
the DEVCLK and SYSREF signals should originate from
close proximity to each other and delays between these
signals should closely match (Figure 13). The LTC2122
is compliant with this subclass.
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As an added subclass 1 protection, the LTC2122 provides an optional Alert mode. Depending on the SYSREF
generation circuit, there could be an erroneous or short
pulse generated as the first SYSREF pulse. To avoid the
possibility of alignment errors due to a compromised first
pulse, an optional Alert mode may be enabled in the SPI.
While in Alert mode, the LTC2122 will ignore the first
SYSREF pulse, and reset critical clocks with the second
pulse. The first pulse, therefore, serves to arm the system,
and the second pulse resets the clocks. After a programmable number of multiframes without a second SYSREF
pulse, the system is disarmed until the next SYSREF pulse
is received. Figure 14 illustrates the state machine of the
Subclass 1 Alert mode.
Subclass 2: Deterministic latency support is obtained by
sampling the low to high transition of the SYNC~ signal
with the rising edge of DEVCLK. Upon detection of the
SYNC~ low to high transition, the critical clocks are realigned. The LTC2122 is compatible with this subclass,
but the detection resolution is always determined by the
ADC DEVCLK frequency.
LTC2122
3.4Gbps LANE
3.4Gbps LANE
SYNC~
MATCHED
DELAYS
SYSREF 1
DEVICE CLOCK 1
SYSREF 2
DEVICE CLOCK 2
MATCHED
DELAYS
CLK GEN
SYSREF 3
DEVICE CLOCK 3
FPGA or
JESD204B
ASIC
MATCHED
DELAYS
LTC2122
3.4Gbps LANE
3.4Gbps LANE
2122 F013
NOTE: INTERNAL CLOCKS ARE RESET BY SYSREF ON THE RISING EDGE OF THE DEVICE CLOCK.
FOR DETERMINISTIC LATENCY, EACH SYSREF/DEVICE CLOCK PAIR SHOULD HAVE MATCHED
DELAYS, AND SHOULD SATISFY SETUP AND HOLD REQUIREMENTS, tSU_SYN AND tH_SYS.
Figure 13. JESD204B Subclass 1 Configuration
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25
LTC2122
APPLICATIONS INFORMATION
RESET
SAMPLE SYSREF
NO SYSREF
RECEIVED
WAIT
ALIGN MULTIFRAME BOUNDRY TO SYSREF;
COUNT MULTIFRAMES;
SAMPLE SYSREF;
RESET COUNT WHEN SYSREF RECEIVED;
SYSREF RECEIVED
COUNT MULTIFRAMES;
SAMPLE SYSREF;
MULTIFRAME
COUNT > R
MULTIFRAME
COUNT > R
ALERT
ALIGN
MULTIFRAME
COUNT ≤ R
SYSREF RECEIVED AND
MULTIFRAME COUNT ≤ R
NO SYSREF
RECEIVED
2122 F14
Figure 14. Alert Mode of Subclass 1
Code-Group Synchronization
(JESD204B 5.3.3.1)
Subclass 0:
In order for each receiver to properly align to the received
serial data, each ADC transmitter must communicate
the location of the start of a code-group and the start of
a frame to its receiver. When multiple ADC devices are
transmitting on multiple lanes, this alignment must take
place on all lanes simultaneously in order for the receivers
to determine the relationship between lanes. A receiver
initiates synchronization by asserting its SYNC~ signal.
When multiple receivers are present, the SYNC~ signals
of all receivers may be logically ORed to provide synchronization requests to all ADC devices simultaneously. The
following synchronization process may be initiated by the
receivers at any time:
• The receiver issues a request for synchronization by
asserting the SYNC~ signal (active low).
• The ADC device will detect the SYNC~ assertion on the
fifth rising edge of its Local Frame Clock (LFC). At the
beginning of the frame following detection, each ADC
transmitter will broadcast a continuous stream of K28.5
symbols in place of data.
• After the receiver has successfully received at least four
consecutive K28.5 symbols, it will deassert the SYNC~
signal.
26
• The ADC device will detect the deassertion of the SYNC~
signal on the rising edge of its device clock, and continue to transmit K28.5 symbols on each lane until the
beginning of the frame following detection.
• If the Initial Lane Alignment Sequence (ILAS) is not
disabled, the ADC device will reset its multiframe start
marker and transmit an ILAS followed by encoded ADC
data. The ILAS will be four multiframes in length.
• If the ILAS is disabled, the ADC device will begin transmitting encoded ADC data on each lane.
Subclass 1:
• The ADC device will detect the deassertion of the SYNC~
signal on the rising edge of its device clock, and continue to transmit K28.5 symbols on each lane until the
beginning of the next multiframe.
• If the ILAS is not disabled, the ADC device will transmit
an ILAS at the beginning of the multiframe. The ILAS
is immediately followed by encoded ADC data.
• If the ILAS is disabled the ADC device will begin transmitting encoded ADC data on each lane at the beginning
of the multiframe boundary.
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Subclass 2:
• Unique to this subclass, the SYNC~ signal must be
deasserted by the receiver on its multiframe boundary. The ADC device will detect the deassertion of the
SYNC~ signal on the rising edge of its device clock (for
minimum latency error the ADC device clock frequency
must be greater than or equal to the receiver device
clock frequency).
• The ADC’s Local Frame Clock (LFC) and Local Multiframe
Clock (LMFC) are reset on the detected edge.
• After resetting the internal clocks, the ADC device will
continue to transmit K28.5 symbols on each lane for
one multiframe (at least 5 frames + 9 octets) to enable
the receiver to re-sync to the new clock positions. The
ADC device will then cease K28.5 transmission at the
next multiframe start.
• If the ILAS is enabled, the ADC device will transmit an
ILAS followed by encoded ADC data.
• If the ILAS is not enabled the ADC device will transmit
encoded ADC data on each lane.
The start of a code-group will coincide with the start of
each K28.5 symbol.
The start of a frame will coincide with the first non-K28.5
symbol after the SYNC~ signal has been deasserted.
Initial Lane Alignment Sequence Transmission
(JESD204B 5.3.3.5)
When the lane alignment sequence is not disabled via
the SPI, the sequence illustrated in the Lane Alignment
Sequence Tables will be transmitted immediately after
code-group synchronization is complete. The lane alignment sequence consists of four complete multiframes. The
minimum number of octets in a multiframe is ultimately
controlled by the configuration contents of the 2nd multiframe in the lane alignment sequence.
The lane alignment sequence is constructed as follows:
• Each multiframe in the sequence will begin with a K28.0
control character, and will end with a K28.3 symbol.
• An 8-bit lane alignment counter is used to generate the
octet data for the lane alignment sequence. The counter
is reset by the code-group synchronization process. The
counter is clocked by an octet clock (character clock).
• The octet of the lane alignment counter is always
transmitted during the lane alignment sequence unless a control character or configuration octet is being
transmitted.
• The second multiframe contains the configuration data.
The configuration data begins on the 3rd octet of the
multiframe, and is preceded by a K28.4 symbol.
• The lane alignment sequence may not be scrambled
(the Scramble option in the SPI register is ignored).
Note that the K28.3 symbol is the lane alignment symbol,
and may be used by the receivers to align the multiframe
boundary pointers in all the lanes in the link.
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LTC2122
APPLICATIONS INFORMATION
Lane Alignment Sequence Tables for Two Lane Mode (One Lane per ADC), 1st Multiframe
Table 3a. Minimum Multiframe Length (K=9), 1st Multiframe
FRAME
DESCRIPTION
0
Start of Subsequence
1
2
3
4
5
6
7
8
DATA
OCTET
(HEX)
DATA
OCTET
(HEX)
8B/10B
SYMBOL
FRAME
DESCRIPTION
K28.0
0
Start of Subsequence
Octet Counter
01
D1.0
Octet Counter
02
D2.0
Octet Counter
03
D3.0
Octet Counter
04
D4.0
Octet Counter
05
D5.0
Octet Counter
06
D6.0
Octet Counter
07
D7.0
Octet Counter
08
D8.0
Octet Counter
09
D9.0
Octet Counter
0A
D10.0
Octet Counter
0B
D11.0
Octet Counter
0C
D12.0
Octet Counter
0D
D13.0
Octet Counter
0E
D14.0
Octet Counter
0F
D15.0
Octet Counter
10
D16.0
Lane Alignment Symbol
Table 3b. Maximum Multiframe Length (K=32), 1st Multiframe
1
2
3
4
5
6
7
8
K28.3
01
D1.0
Octet Counter
02
D2.0
Octet Counter
03
D3.0
Octet Counter
04
D4.0
Octet Counter
05
D5.0
Octet Counter
06
D6.0
Octet Counter
07
D7.0
Octet Counter
08
D8.0
Octet Counter
09
D9.0
Octet Counter
0A
D10.0
Octet Counter
0B
D11.0
Octet Counter
0C
D12.0
Octet Counter
0D
D13.0
Octet Counter
0E
D14.0
Octet Counter
0F
D15.0
Octet Counter
10
D16.0
Octet Counter
11
D17.0
…
…
…
Octet Counter
32
D18.1
Octet Counter
33
D19.1
Octet Counter
34
D20.1
Octet Counter
35
D21.1
Octet Counter
36
D22.1
Octet Counter
37
D23.1
28
Octet Counter
38
D24.1
Octet Counter
39
D25.1
29
Octet Counter
3A
D26.1
Octet Counter
3B
D27.1
Octet Counter
3C
D28.1
Octet Counter
3D
D29.1
Octet Counter
3E
D30.1
26
27
30
31
Lane Alignment Symbol
28
K28.0
Octet Counter
…
25
8B/10B
SYMBOL
K28.3
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Lane Alignment Sequence Tables for Two Lane Mode (One Lane per ADC), 2nd Multiframe
Table 3c. Minimum Multiframe Length (K=9), 2nd Multiframe
DATA
OCTET
(HEX)
FRAME
DESCRIPTION
0
Start of Subsequence
K28.0
Start of Link Configuration
K28.4
DESCRIPTION
0
Start of Subsequence
K28.0
Start of Link Configuration
K28.4
DID[7:0]
*00
D0.0
{ADJCNT[3:0], BID[3:0]}
*00
D0.0
2
{0, ADJDIR, PHADJ, LID[4:0]}
00
D0.0
{SCR, 00, L–1[4:0]}
*01
D1.0
3
F–1 [7:0]
01
D1.0
{000, K–1[4:0]}
*08
D8.0
M–1 [7:0]
01
D1.0
{CS[1:0]], 0, [N–1 [4:0]}
4D
D13.2
4
5
6
7
8
{SUBCLASSV[2:0], N’–1[4:0]}
0F
D15.0
{JESDV[2:0], S–1 [4:0]}
20
D0.1
{HD[0], 00, CF[4:0]}
00
D0.0
Reserved
00
D0.0
Reserved
00
D0.0
FCHK[7:0]
29
D9.1
Octet Counter
22
D2.1
Lane Alignment Symbol
DATA
OCTET
(HEX)
8B/10B
SYMBOL
FRAME
1
Table 3d. Maximum Multiframe Length (K=32), 2nd Multiframe
1
DID[7:0]
*00
D0.0
{ADJCNT[3:0], BID[3:0]}
*00
D0.0
2
{0, ADJDIR, PHADJ, LID[4:0]}
*00
D0.0
{SCR[0], 00, L–1[4:0]}
*01
D1.0
3
F–1 [7:0]
01
D1.0
{000, K–1[4:0]}
*1F
D8.0
M–1 [7:0]
01
D1.0
{CS[1:0]], 0, [N–1 [4:0]}
4D
D13.2
4
5
6
7
8
K28.3
{SUBCLASSV[2:0], N’–1[4:0]}
0F
D15.0
{JESDV[2:0], S–1 [4:0]}
20
D0.1
{HD[0], 00, CF[4:0]}
00
D0.0
Reserved
00
D0.0
Reserved
00
D0.0
FCHK[7:0]
40
D0.2
Octet Counter
50
D16.2
Octet Counter
51
D17.2
Field Descriptions: DID=Device ID, BID=Bank ID, LID=Lane
ID, SCR=Scrambling enabled, L=Lanes per device, F=Octets
per frame, K=Frames per multiframe, M=Converters per
device, CS=Control bits per sample, N=Converter Resolution, N’=Total bits per sample, S=Samples per converter
per frame, HD=High density format, CF=Control words per
frame per link, FCHK=Checksum of all fields (mod 256)
…
Configuration Field Defaults: DID=0, BID=0, LID=0,
SCR=0, L=2, F=2, K=9 or 32, M=2, CS=1, N=14, SUBCLASSV=0, N’=16, S=1, HD=0, CF=0
…
25
…
…
X–1 Indicates that field X is affected by -1 encoding
{} Indicates concatenation
* Indicates a field directly programmable through the SPI
8B/10B
SYMBOL
Octet Counter
72
D18.3
Octet Counter
73
D19.3
Octet Counter
74
D20.3
Octet Counter
75
D21.3
Octet Counter
76
D22.3
Octet Counter
77
D23.3
28
Octet Counter
78
D24.3
Octet Counter
79
D25.3
29
Octet Counter
7A
D26.3
Octet Counter
7B
D27.3
Octet Counter
7C
D28.3
Octet Counter
7D
D29.3
Octet Counter
7E
D30.3
26
27
30
31
Lane Alignment Symbol
K28.3
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Lane Alignment Sequence Tables for Two Lane Mode (One Lane per ADC), 3rd Multiframe
Table 3e. Minimum Multiframe Length (K=9), 3rd Multiframe
FRAME
DESCRIPTION
0
Start of Subsequence
1
2
3
4
5
6
7
8
DATA
OCTET
(HEX)
DATA
OCTET
(HEX)
8B/10B
SYMBOL
FRAME
DESCRIPTION
K28.0
0
Start of Subsequence
Octet Counter
25
D5.1
Octet Counter
26
D6.1
Octet Counter
27
D7.1
Octet Counter
28
D8.1
Octet Counter
29
D9.1
Octet Counter
2A
D10.1
Octet Counter
2B
D11.1
Octet Counter
2C
D12.1
Octet Counter
2D
D13.1
Octet Counter
2E
D14.1
Octet Counter
2F
D15.1
Octet Counter
30
D16.1
Octet Counter
31
D17.1
Octet Counter
32
D18.1
Octet Counter
33
D19.1
Octet Counter
34
D20.1
Lane Alignment Symbol
Table 3f. Maximum Multiframe Length (K=32), 3rd Multiframe
1
2
3
4
5
6
7
8
K28.3
81
D1.4
Octet Counter
82
D2.4
Octet Counter
83
D3.4
Octet Counter
84
D4.4
Octet Counter
85
D5.4
Octet Counter
86
D6.4
Octet Counter
87
D7.4
Octet Counter
88
D8.4
Octet Counter
89
D9.4
Octet Counter
8A
D10.4
Octet Counter
8B
D11.4
Octet Counter
8C
D12.4
Octet Counter
8D
D13.4
Octet Counter
8E
D14.4
Octet Counter
8F
D15.4
Octet Counter
90
D16.4
Octet Counter
91
D17.4
…
…
…
Octet Counter
B2
D18.5
Octet Counter
B3
D19.5
Octet Counter
B4
D20.5
Octet Counter
B5
D21.5
Octet Counter
B6
D22.5
Octet Counter
B7
D23.5
28
Octet Counter
B8
D24.5
Octet Counter
B9
D25.5
29
Octet Counter
BA
D26.5
Octet Counter
BB
D27.5
Octet Counter
BC
D28.5
Octet Counter
BD
D29.5
Octet Counter
BE
D30.5
26
27
30
31
Lane Alignment Symbol
30
K28.0
Octet Counter
…
25
8B/10B
SYMBOL
K28.3
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Lane Alignment Sequence Tables for Two Lane Mode (One Lane per ADC), 4th Multiframe
Table 3g. Minimum Multiframe Length (K=9), 4th Multiframe
FRAME
DESCRIPTION
0
Start of Subsequence
1
2
3
4
5
6
7
8
DATA
OCTET
(HEX)
DATA
OCTET
(HEX)
8B/10B
SYMBOL
FRAME
DESCRIPTION
K28.0
0
Start of Subsequence
Octet Counter
37
D23.1
Octet Counter
38
D24.1
Octet Counter
39
D25.1
Octet Counter
3A
D26.1
Octet Counter
3B
D27.1
Octet Counter
3C
D28.1
Octet Counter
3D
D29.1
Octet Counter
3E
D30.1
Octet Counter
3F
D31.1
Octet Counter
40
D0.2
Octet Counter
41
D1.2
Octet Counter
42
D2.2
Octet Counter
43
D3.2
Octet Counter
44
D4.2
Octet Counter
45
D5.2
Octet Counter
46
D6.2
Lane Alignment Symbol
Table 3h. Maximum Multiframe Length (K=32), 4th Multiframe
1
2
3
4
5
6
7
8
K28.3
C1
D1.6
Octet Counter
C2
D2.6
Octet Counter
C3
D3.6
Octet Counter
C4
D4.6
Octet Counter
C5
D5.6
Octet Counter
C6
D6.6
Octet Counter
C7
D7.6
Octet Counter
C8
D8.6
Octet Counter
C9
D9.6
Octet Counter
CA
D10.6
Octet Counter
CB
D11.6
Octet Counter
CC
D12.6
Octet Counter
CD
D13.6
Octet Counter
CE
D14.6
Octet Counter
CF
D15.6
Octet Counter
D0
D16.6
Octet Counter
D1
D17.6
29
30
31
…
28
…
27
…
26
K28.0
Octet Counter
…
25
8B/10B
SYMBOL
Octet Counter
F2
D18.7
Octet Counter
F3
D19.7
Octet Counter
F4
D20.7
Octet Counter
F5
D21.7
Octet Counter
F6
D22.7
Octet Counter
F7
D23.7
Octet Counter
F8
D24.7
Octet Counter
F9
D25.7
Octet Counter
FA
D26.7
Octet Counter
FB
D27.7
Octet Counter
FC
D28.7
Octet Counter
FD
D29.7
Octet Counter
FE
D30.7
Lane Alignment Symbol
K28.3
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JESD204B Modes of Operation
To avoid spectral interference from the serial data output,
a SPI enabled data scrambler is added between the ADC
data and the 8B/10B encoder to randomize the spectrum
of the serial link. The polynomial used for the scrambler
is 1+x14+x15, which is a pseudorandom pattern repeating
itself every 215–1.
• If the data in the last code-group of the current frame
equals the data in the last code-group of the previous
frame, the converter will replace the last code-group
with the control character K28.7 before serialization.
However, if a K28.7 symbol was already transmitted
in the previous frame, the actual code-group will be
transmitted. If lane alignment monitoring is enabled and
it is the last code-group of a multiframe, a K28.3 will
be transmitted in place of the K28.7, even if a control
character was transmitted in the previous frame.
The scrambled data is converted into two valid 8B/10B
code-groups. The 8B/10B code-groups are then serialized
and transmitted.
• Upon receiving a K28.7 symbol, the receiver is required
to replace it with the data decoded at the same position
of the previous frame.
The receiver is required to deserialize the data, decode
the code-groups into octets, and descramble them back
to the original octets using the self-aligning descrambler
described in JESD204B 5.2.
FAM mode 2 is implemented when scrambling is enabled
as follows:
Scramble Mode
(JESD204B 5.2, Annex D)
Frame Alignment Monitoring (FAM)
(JESD204B 5.3.3.4, 7.3)
A frame contains more than one octet or code-group, so it
is necessary to periodically verify that the frame alignment
of the receiver is correct.
When frame alignment monitoring is not disabled via the
SPI, the receiver may verify frame alignment without the
loss of data. To accomplish this, predetermined data in
the last code-group of the frame is substituted with the
control character, K28.7. The receiver is required to detect
the K28.7 character and replace it with the original data.
In this way, the last octet or code-group may be verified.
There are two possible frame alignment monitoring modes.
FAM mode 1 is implemented when scrambling is not
enabled as follows:
32
• If the data in the last code-group of the current frame
equals D28.7, the converter will replace this data with
the K28.7 control character. If lane alignment monitoring
is enabled and it is the last code-group of a multiframe,
a K28.3 will be transmitted in place of the K28.7.
• Upon receiving a K28.7 symbol, the receiver is required
to replace it with D28.7.
With FAM enabled the receiver is required to search for
the presence of K28.7 symbols in the data stream. If two
successive K28.7 symbols are detected at the same position other than the assumed end of frame, the receiver will
realign its frame boundary to the new position.
Lane Alignment Monitoring (LAM)
(JESD204B 5.3.3.6, 7.5)
When multiple lanes are present in a link, it is useful to
periodically monitor the continued alignment of each lane.
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Lane alignment symbols are inserted into the transmitted
data on a substitution basis to enable the receiver to verify
lane alignment without the loss of data. In this mode, predetermined data in the last code-group of a multiframe is
substituted with the control character K28.3. The receiver
is required to detect the K28.3 character and replace it
with the original data. In this way, the last code-group of
a multiframe may be marked and used for lane alignment.
There are two possible lane alignment monitoring modes.
Pattern 3: Periodic D21.5
Pattern 3 produces the maximum possible frequency for
the high speed interface (a “1010” pattern).
Pattern 4: PRBS15
LAM mode 1 is implemented when scrambling is not
enabled as follows:
Pattern 4 is a Pseudo Random Bit Sequence based on the
polynomial 1+x14+x15 (the same polynomial used by the
scrambler described in JESD204B 5.2). When this pattern
is selected, the scrambler is internally forced on and the
ADC data is forced to zero. The length of the sequence is
215–1 prior to 8B/10B encoding.
• If it is the last code-group of a multiframe and the data
equals the data in the last code-group of the previous
frame, the converter will replace the current code-group
with the control character K28.3.
When Frame and Lane Alignment Monitoring are not
disabled, substitution of data will take place as described
in the Frame Alignment Monitoring and Lane Alignment
sections of this data sheet.
• Upon receiving a K28.3 symbol, the receiver is required
to replace it with the data decoded at the same position
of the previous frame.
Pattern 5: Repeated Lane Alignment Sequence
LAM mode 2 is implemented when scrambling is enabled
as follows:
• If it is the last code-group of a multiframe and the data
of code-group equals D28.3, the converter will replace
this data with the K28.3 control character.
• Upon receiving a K28.3 symbol, the receiver is required
to replace it with D28.3.
Simple and Complex Periodic Test Patterns
Seven test patterns are a provided to the user for evaluation and system debug.
Pattern 1: Periodic K28.5
Pattern 1 contains both disparities of the K28.5 Comma,
and is 20 bits long. The K28.5 pattern contains a unique
combination of maximum and minimum run-lengths,
making this pattern useful in quickly observing the effects
of Inter Symbol Interference (ISI).
Pattern 2: Periodic K28.7
Pattern 2 produces a square wave of the minimum possible frequency for the high speed serial interface (a
“1111100000” pattern).
Pattern 5 is the continuous transmission of the lane alignment sequence as described in JESD204B 5.3.3.8.2. In
this mode, the following occurs:
Case 1 - SYNC~ is active before entering this state
• Code-group synchronization is performed (K28.5 commas are transmitted in whole frames until SYNC~ is
deasserted).
• The lane alignment sequence is transmitted repeatedly
according to tables 3a to 3h.
Case 2 - SYNC~ is not active before entering this state
• At least one multiframe of K28.5 commas are transmitted.
• The lane alignment sequence is transmitted repeatedly
according to tables 3a to 3h.
If scrambling is enabled, the test samples will not be
scrambled.
This test sequence is sensitive to a synchronization request
from the receiver. If the SYNC~ signal is asserted at any
time during test sample transmission, the lane alignment
sequence pointer will be reset, and Case 1 will be repeated.
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Pattern 6: Test Sample Sequence
Pattern 6 is a set of test samples defined in JESD204B
5.1.6.3. The transmission of these test samples over the
link provides a way to verify that the data mapping of the
ADC matches the receiver. To place the ADC in the test
sample transmission mode, the corresponding bit must
be set in the periodic test pattern SPI register. Once this
bit is set, the following occurs:
Case 1 - SYNC~ is active before entering this state
• Code-group synchronization is performed (K28.5 commas are transmitted in whole frames until SYNC~ is
deasserted).
• The lane alignment sequence is transmitted (if enabled)
according to tables 3a to 3h.
• The test samples are repeatedly transmitted according
to tables 4a to 4b.
Case 2 - SYNC~ is not active before entering this state
• Four K28.5 commas are transmitted.
• The lane alignment sequence is transmitted (if enabled)
according to tables 3a to 3h.
• The test samples are repeatedly transmitted according
to tables 4a to 4b.
If scrambling is enabled, the test samples will be scrambled,
but the lane alignment sequence will not be scrambled.
This test sequence is sensitive to a synchronization request
from the receiver. If the SYNC~ signal is asserted at any
time during test sample transmission, the test sample
sequence pointer will be reset, and Case 1 will be repeated.
Table 4a. Pattern 6 Test Sample Data Description for Single Lane (L=1), 4 Octets per Frame (F=4),1 Sample/Converter/Frame Period (S=1)
Test Sample Sequence
ADC 0 (Channel A)
ADC 1 (Channel B)
Lane 0 Octets
Frame 0 (CID+1)
0000_0000
0000_0110
0000_0000
0000_1000
Frame 1 (SID+1)
0000_0000
0000_0100
0000_0000
0000_0110
Frame i, 2≤i≤K
(MSB set to 1)
1000_0000
0000_0000
1000_0000
0000_0000
Table 4b. Pattern 6 Test Sample Data Description for 1 Lane/ADC (L=2), 2 Octets per Frame (F=2), 1 Sample/Converter/Frame Period (S=1)
Test Sample Sequence
ADC 0 (Channel A)
ADC 1 (Channel B)
Lane 0 Octets
Lane 2 Octets
Frame 0 (CID+1)
0000_0000
0000_0110
0000_0000
0000_1000
Frame 1 (SID+1)
0000_0000
0000_0100
0000_0000
0000_0100
Frame 2
1000_0000
0000_0000
1000_0000
0000_0010
Frame 3
1000_0000
0000_0000
1000_0000
0000_0000
Frame i, 2≤i≤K
(MSB set to 1)
1000_0000
0000_0000
1000_0000
0000_0000
Note: CID = Converter ID, SID=Sample ID, K=Frames in Multiframe, 1 indicates the Control-Bit Position (overflow bit)
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Pattern 7: Modified RPAT
Serial Programming
JESD204B clauses 4.4.1, 4.5.1, and 4.6.1 require that one
of two possible patterns be supported by the transmitter
for jitter compliance testing. The modified RPAT pattern
is one of these two patterns, and consists of 12 specific
code-groups repeated continuously (a description of the
modified RPAT sequence may be found in IEEE Std. 802.32008 Annex 48A).
The CS, SCK, SDI and SDO pins make up the Serial Peripheral Interface (SPI) that programs the A/D control
registers. Data is written to a register with a 16-bit serial
word. Data can also be read back from a register to verify
its contents. Serial data transfer starts when CS is taken
low. The data on the SDI pin is latched at the first sixteen
rising edges of SCK. Any SCK rising edges after the first
sixteen are ignored. The data transfer ends when CS is
taken high again. The first bit of the 16-bit input word is
the R/W bit. The next seven bits are the address of the
register (A6:A0). The final eight bits are the register data
(D7:D0). If the R/W bit is low, the serial data (D7:D0) will
be written to the register set by the address bits (A6:A0).
If the R/W bit is high, data in the register set by the address bits (A6:A0) will be read back on the SDO pin (see
the Timing Diagrams). During a readback command the
register is not updated and data on SDI is ignored. The
SDO pin is an open-drain output that pulls to ground with
a 200Ω impedance. If register data is read back through
SDO, an external 2k pull-up resistor is required. If serial
data is only written and readback is not needed, then SDO
can be left floating and no pull-up resistor is needed.
Table 6 shows a map of the mode control registers.
This RPAT pattern must begin with positive disparity. To
gracefully force positive disparity, a ten character preamble
is transmitted. The first nine characters will be the D5.6
code-group. The D5.6 preserves the previous disparity. If
the disparity of these nine symbols is positive, the tenth
preamble character will also be a D5.6 symbol. If the
disparity is negative a reversal is forced by transmitting a
D16.2 code-group as the tenth preamble character.
Table 5. Modified RPAT Test Pattern
OCTET VALUE
(HEX)
DISPARITY
D30.5
BE
+
D23.6
D7
–
D3.1
23
+
D7.2
47
+
D11.3
6B
+
D15.4
8F
+
Soft Reset
D19.5
B3
+
D20.0
14
+
D30.2
5E
–
D27.7
FB
+
D21.1
35
+
D25.2
59
+
The mode control registers should be programmed as soon
as possible after the power supplies turn on and are stable.
A global reset of all SPI registers to the default values may
be performed by writing a 1 to Bit D7 of Address 0. After
the reset is complete, Bit D7 is automatically set back to
zero. This register is write-only.
CODE-GROUP NAME
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Table 6. SPI Register Memory Map
SPI REGISTER DESCRIPTION
ADDRESS
D7
Reset
Soft Reset
0
Power Down
1
ADC CNTL
2
Device ID
3
Bank ID
4
Lanes (–1)
5
Frames/Multiframe (–1)
6
JESD204B Modes
7
JESD204B Subclass Modes
8
Periodic Test Patterns
9
D6
D5
D4
D3
D2
D1
D0
SLEEP
NAP
PDB
PDA
2X_CLK
OF_en
DCS_en
DID[7:0]
BID[3:0]
L–1[2:0]
K–1 [4:0]
LAS_dis
R–1[2:0] (Alert Length)
LAM_dis
FAM_dis
Alert
TX_SYNC
Reserved
RST_dis
SCR_en
SUBCLASS[2:0]
PAT[2:0]
Normal Data
0
0
0
K28.5 (SYNC Comma)
0
0
1
K28.7 (…1111100000…)
0
1
0
D21.5 (…10101010…)
0
1
1
PRBS15 (1+x14+x15)
1
0
0
Lane Alignment Sequence
1
0
1
Test Samples Sequence
1
1
0
Modified RPAT pattern
1
1
1
CML Output Magnitude
10
CML BIAS[1:0]
10mA (250mV)
0
0
12mA (300mV)
0
1
14mA (350mV)
1
0
16mA (400mV)
1
1
Note: X–1 indicates that field X is affected by –1 encoding
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Register A0: Reset Register (Address 00h)
D7
D6
D5
D4
Reset
X
X
X
This register is "Write Only”. Readback from this register will be all ones
Bit 7
RESET
D3
X
D2
X
D1
X
D0
X
Software Reset Bit
0 = Reset Disabled
1 = Software Reset. All SPI registers are set to default values. This bit is automatically set back to zero after the reset is complete.
Bits 6-0
Unused Bits
Register A1: Power Down Modes (Address 01h)
D7
X
Bits 7-4
D6
X
Unused Bit
D5
X
Bit 3
SLEEP
0 = Normal Operation
D4
X
D3
Sleep
D2
Nap
D1
PDB
D0
PDA
D3
X
D2
2X_CLK
D1
OF_en
D0
DCS_en
1 = Power Down Entire ADC
Bit 2
NAP
0 = Normal Operation (Default Setting)
1 = Low Power Keep-Alive Mode for Both Channels
Bit 1
PDB
0 = Normal Operation (Default Setting)
1 = Power Down Channel B
Bit 0
PDA
0 = Normal Operation (Default Setting)
1 = Power Down Channel A
Register A2: ADC Control (Address 02h)
D7
X
Bits 7-3
D6
X
Unused Bits
D5
X
D4
X
Bit 2
2X_CLK
0 = DEVCLK Frequency is Equal to Sample Frequency (Default Setting)
1 = DEVCLK Frequency is Twice the Sample Frequency
Bit 1
OF_en
0 = LVDS Overflow Output is Disabled (Default Setting)
1 = LVDS Overflow Output is Enabled
Bit 0
DCS_en
0 = Duty Cycle Stabilizer is Disabled (Default Setting)
1 = Duty Cycle Stabilizer is Enabled
Register A3: Device ID (Address 03h)
D7-D0
DID[7:0]
Bits 7-0
DID[7:0]
Device ID. Default value is 00000000
DID is defined in JESD204B 8.3. It is only used during the transmission of an initial lane alignment sequence and does not impact the
configuration or functionality of the ADC
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37
LTC2122
APPLICATIONS INFORMATION
Register A4: Bank ID (Address 04h)
D7
X
D6
X
Bits 7-4
Unused Bits
Bits 3-0
BID[3:0]
D5
X
D4
X
D3-D0
BID[3:0]
Bank ID. Default value is 0000
BID is defined in JEDS204B 8.3. Provided as an extension to the DID word. It is only used during the transmission of an initial lane
alignment sequence, and does not impact the configuration or functionality of the ADC or serial link
Register A5: Number of Lanes –1 (Address 05h)
D7
X
D6
X
Bits 7-3
Unused Bits
Bits 2-0
L –1[2:0]
D5
X
D4
X
D3
X
D2-D0
L–1[2:0]
The value of L configures the device. It is also transmitted in the Lane Alignment Sequence
000 = 1 Lane (Both ADCs multiplexed to one lane at up to 6.0Gbps)
001 = 2 Lanes (One Lane per ADC, Default Setting)
Register A6: Number of Frames Per Multiframe –1 (Address 06h)
D7
X
D6
X
Bits 7-5
Unused Bits
Bits 4-0
K–1[4:0]
D5
X
D4-D0
K–1[4:0]
Frames Per Multiframe minus 1. Default value is 01111 (16 frames per multiframe)
K is defined in JEDS204B 5.3.3.5. For both two and four lane operation, the minimum valid value of K is 9 (K–1 = 01000) and the
maximum valid value is 32 (K–1 = 11111)
Register A7: JESD204B Modes (Address 07h)
D7
X
Bits 7-6
D6
X
Unused Bits
Bit 5
LAS_dis
D5
LAS_dis
D4
LAM_dis
D3
FAM_dis
D2
0
D1
RST_dis
D0
SCR_en
0 = Lane Alignment Sequence Enabled (Default Setting)
1 = Lane Alignment Sequence Disabled
Bit 4
LAM­_dis
0 = Lane Alignment Monitor Enabled (Default Setting)
1 = Lane Alignment Monitor Disabled
Bit 3
FAM_dis
0 = Frame Alignment Monitor Enabled (Default Setting)
1 = Frame Alignment Monitor Disabled
Bit 2
Reserved bit. Set to 0
Bit 1
RST_dis
0 = In Subclass 1, SYSREF Reset of Dividers is Enabled (Default Setting)
In Subclass 2 SYNC~ Reset of Dividers is Enabled (Default Setting)
1 = In Subclass 1, SYSREF Reset of Dividers is Disabled
In Subclass 2 SYNC~ Reset of Dividers is Disabled
Bit 0
SCR_en
0 = Scrambling is Disabled (Default Setting)
1 = Scrambling is Enabled
38
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LTC2122
APPLICATIONS INFORMATION
Register A8: JESD204B Subclass Modes (Address 08h)
D7-D5
R–1[2:0]
R–1 [2:0]
Bits 7-5
D4
D3
D2-D0
Alert
TX_SYNC
SUBCLASSV[2:0]
Subclass 1 Alert mode De-arming Length. Default value is 000 (R = 1). Measured in Multiframe Periods
Alert
Bit 4
Subclass 1 Alert Mode. First Pulse Arms, Second Pulse (and later) are Active
0 = Alert Mode Disabled (Default Setting)
1 = Alert Mode Enabled
TX_SYNC
Bit 3
A Multiframe of K28.5 Commas are Transmitted If Multiframe Position Changes
0 = Transmitter Induced Synchronization Disabled (Default Setting)
1 = Transmitter Induced Synchronization Enabled
SUBCLASSV[2:0]
Bits 2-0
000 = JESD204B Subclass 0 (Default Setting)
001 = JESD204B Subclass 1 (Deterministic Latency Obtained Using SYSYSREF)
010 = JESD204B Subclass 2 (Deterministic Latency Obtained Using SYNC~ Rising Edge)
Register A9: Periodic Test Patterns (Address 09h)
D7
X
D6
X
Bits 7-3
Unused Bits
Bits 2-0
PAT[2:0]
D5
X
D4
X
D3
X
D2-D0
PAT[2:0]
000 = Normal ADC Data
001 = K28.5 Pattern (SYNC Comma)
010 = K28.7 Pattern (…1111100000…)
011 = D21.5 Pattern (…1010101010…)
100 = PRBS15 Pattern (1+x14+x15)
101 = Lane Alignment Sequence
110 = Test Samples Sequence
111 = Modified RPAT Pattern
Register A10: CML Output Magnitude (Address 0Ah)
D7
X
Bits 7-2
D6
X
Unused Bits
D5
X
D4
X
Bits 1-0
CMLBIAS[1:0] Affects All CML Outputs
D3
X
D2
X
D1-D0
CMLBIAS[1:0]
00 = 10mA (250mV)
01 = 12mA (300mV)
10 = 14mA (350mV)
11 = 16mA (400mV)
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39
LTC2122
APPLICATIONS INFORMATION
High Speed CML Output Terminations
The CML outputs must be terminated with the transmission line characteristic impedance for proper functionality.
In general, the transmission line impedance should be
designed to provide either 50Ω single-ended or 100Ω
differential.
The OVDD supply voltage and the termination voltage
determine the common mode output level of the CML
outputs. For proper operation of the CML driver, the output
common mode voltage should be greater than 1V.
The directly-coupled termination mode of Figure 15 is
recommended when the receiver termination voltage is
within the required range. When the CML outputs are
directly-coupled to the 50Ω termination resistors, the
OVDD supply voltage also serves as the receiver termination
voltage, and the output common mode voltage will be in
the range of 125mV to 200mV lower than OVDD (depending on the programmed CML current). In this mode, the
OVDD voltage should be in the range of 1.125V to 1.2V
(minimum), and VDD (maximum).
If the serial receiver’s common mode input requirements
are not compatible with the directly-coupled termination
modes, the DC balanced 8B/10B encoded data will permit
DC blocking capacitors as shown in Figure 17. In this
AC-coupled mode, the termination voltage is determined
by the receiver’s requirements. The coupling capacitors
should be selected appropriately for the intended operating
bit-rate, usually between 1nF to 10nF. In the AC-coupled
mode, the output common mode voltage will be 250mV to
400mV below OVDD, so the OVDD supply voltage should be
in the same range as the directly coupled differential case.
The LTC2122 is fully AC compliant with the JESD204B
specification.
Table 7. Minimum OVDD Voltage
DIRECTLY
COUPLED MIN
OVDD
DIRECTLY COUPLED
DIFFERENTIAL MIN
OVDD
AC COUPLED
MIN OVDD
10mA
1.125V
1.25V
1.25V
12mA
1.15V
1.3V
1.3V
14mA
1.175V
1.35V
1.35V
16mA
1.2V
1.4V
1.4V
CML
CURRENT
The directly-coupled differential termination of Figure 16
may be used when no termination voltage at the receiver
is available as long as the input common mode voltage
is within the required range. In this case, the common
mode voltage will be in the range of 250mv to 400mV
below OVDD. The minimum OVDD should be in the range
of 1.25V to 1.4V (depending on the programmed CML
current). The maximum OVDD is equal to VDD.
40
2122fa
For more information www.linear.com/LTC2122
LTC2122
APPLICATIONS INFORMATION
SERIAL CML DRIVER
OVDD
50Ω
50Ω
CMLOUT+
CMLOUT –
1.2V TO VDD
(16mA BIAS)
ZO
SERIAL CML RECEIVER
50Ω
50Ω
ZO
DATA+
DATA–
SPI PROGRAMMABLE
10mA TO 16mA
GND
2122 F15
Figure 15. CML Termination, Directly Coupled Mode
SERIAL CML DRIVER
OVDD
50Ω
50Ω
CMLOUT +
CMLOUT –
1.4V TO VDD
(16mA BIAS)
SERIAL CML RECEIVER
ZO
ZO
100Ω
DATA+
DATA–
SPI PROGRAMMABLE
10mA TO 16mA
GND
2122 F16
Figure 16. CML Termination, Directly Coupled Differential Mode
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41
LTC2122
APPLICATIONS INFORMATION
SERIAL CML DRIVER
OVDD
50Ω
50Ω
CMLOUT +
CMLOUT –
1.4V TO VDD
(16mA BIAS)
SERIAL CML RECEIVER
VTERM
50Ω
ZO
ZO
DATA+
50Ω
0.01µF
0.01µF
DATA–
SPI PROGRAMMABLE
10mA TO 16mA
GND
2122 F17
Figure 17. CML Termination, AC-Coupled Mode
GROUNDING AND BYPASSING
The LTC2122 requires a printed circuit board with a clean
and unbroken ground plane in the first layer beneath the
ADC. A multilayer board with an internal ground plane is
recommended. Layout for the printed circuit board should
ensure that digital and analog signal lines are separated
as much as possible. In particular, care should be taken
not to run any digital track alongside an analog signal
track or underneath the ADC. High quality ceramic bypass
capacitors should be used at the VDD, OVDD, VCM, VREF
pins. Bypass capacitors must be located as close to the
pins as possible. Size 0402 ceramic capacitors are recommended. The traces connecting the pins and bypass
capacitors must be kept short and should be made as
42
wide as possible. The analog inputs, clock signals, and
digital outputs should not be routed next to each other.
Ground fill and grounded vias should be used as barriers
to isolate these signals from each other.
HEAT TRANSFER
Most of the heat generated by the LTC2122 is transferred
from the die through the bottom-side exposed pad and
package leads onto the printed circuit board. For good
electrical and thermal performance, the exposed pad must
be soldered to a large grounded pad on the PC board. This
pad should be connected to the internal ground planes by
an array of vias.
2122fa
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LTC2122
TYPICAL APPLICATIONS
VDD
R63
4.99Ω
R9
24.9Ω
4
R10
45.3Ω
•
•
T2
C27
MABA-007159-000000
0.1µF
5
1
3
C29
0.1µF
R11
45.3Ω
+
AINA
3
–
AINA
VCM
C26
2.2µF
0503
4
SENSE
0503
AINB–
AINB+
VDD
R64
4.99Ω
R65
4.99Ω
12 V
DD
R67
100Ω
0201
38 37
OVDD
OVDD
DNC
AINA+
AINA–
5
SENSE
6 V
REF
7 V
CM
8
GND
9 A –
INB
10 A +
INB
11
GND
DNC
C20
0.1µF
OVDD
36
35
34
33
*
C44 - C47
1000pF
*
32
31
CMLOUT_A0+
CMLOUT_B0+
30
29
CMLOUT_B0+
DNC
28
27
CMLOUT_B0–
DNC
26
25
13 14 15 16 17 18 19 20 21 22 23 24
VDD
CMLOUT_A0–
CMLOUT_B0–
*
*
OVDD
HIGH-SPEED CMLOUT
TRACES ARE 50Ω
*DO NOT INSTALL
VDD
R15
0Ω
R14
100Ω
DEVCLK–
DEVCLK+
R13
0Ω
R12
0Ω
C21
0.1µF
CMLOUT_A0+
CMLOUT_A0–
LTC2122
OVDD
VDD
VDD
1 V
DD
2
GND
46 45 44 43 42 41 40 39
SDI
SDO
OF+
OF –
GND
GND
R66
100Ω
0201
VDD
C25, 2.2µF
R8
24.9Ω
C28
0.1µF
C11
2.2µF
0603
OF+
OF –
VDD
VDD
VDD
R7
45.3Ω
R18
0Ω
SYNC~+
SYNC~–
C24
0.1µF
VDD
49 48 47
R6
45.3Ω
C23
0.1µF
AINB
R5
1k
GND
3
C19
0.1µF
R62
4.99Ω
1
4
C18
0.1µF
CS
SCK
5
C17
0.1µF
GND
C16
0.1µF
GND
VDD
C15
0.1µF
T1
MABA-007159-000000
•
AINA
C14
0.1µF
•
C22
0.1µF
C13
0.1µF
VDD
GND
DEVCLK–
DEVCLK+
GND
SYSREF+
SYSREF–
C12
0.1µF
CS
SCK
SDI
SDO
R16
0Ω
SYNC~–
SYNC~+
SYSREF–
R17
100Ω
SYSREF+
2122 TA02
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43
LTC2122
TYPICAL APPLICATIONS
Silkscreen Top
44
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LTC2122
TYPICAL APPLICATIONS
Top Side
Inner Layer 2, GND
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45
LTC2122
TYPICAL APPLICATIONS
Inner Layer 3
Inner Layer 4
46
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LTC2122
TYPICAL APPLICATIONS
Top Side
Inner Layer 2, GND
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47
LTC2122
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UK Package
48-Lead Plastic QFN (7mm × 7mm)
(Reference LTC DWG # 05-08-1704 Rev C)
0.70 ±0.05
5.15 ±0.05
5.50 REF
6.10 ±0.05 7.50 ±0.05
(4 SIDES)
5.15 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
7.00 ±0.10
(4 SIDES)
0.75 ±0.05
R = 0.10
TYP
R = 0.115
TYP
47 48
0.40 ±0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
2
PIN 1
CHAMFER
C = 0.35
5.50 REF
(4-SIDES)
5.15 ±0.10
5.15 ±0.10
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
48
(UK48) QFN 0406 REV C
0.25 ±0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
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LTC2122
REVISION HISTORY
REV
DATE
DESCRIPTION
A
11/14
Updated the crosstalk specification
Added tDCK specification
Updated the tSU_SYS and tH_SYS specifications
PAGE NUMBER
3
5
6
2122fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LTC2122
49
LTC2122
TYPICAL APPLICATION
VDD
C23
0.1µF
R7
45.3Ω
R63
4.99Ω
AINA+
R9
24.9Ω
4
AINB
R10
45.3Ω
•
•
T2
C27
MABA-007159-000000
0.1µF
5
1
3
C29
0.1µF
C28
0.1µF
R11
45.3Ω
VCM
C26
2.2µF
0503
4
SENSE
0503
AINB–
+
AINB
VDD
R64
4.99Ω
R65
4.99Ω
3
AINA–
C25, 2.2µF
R8
24.9Ω
1 V
DD
2
GND
46 45 44 43 42 41 40 39
12 V
DD
R67
100Ω
0201
38 37
DNC
36
35
34
33
*
C44 - C47
1000pF
*
32
31
CMLOUT_A0+
+
30
29
CMLOUT_B0+
CMLOUT_B0
CMLOUT_B0–
DNC
DNC
13 14 15 16 17 18 19 20 21 22 23 24
VDD
CMLOUT_A0–
26
25
CMLOUT_B0–
*
28
27
*
OVDD
HIGH-SPEED CMLOUT
TRACES ARE 50Ω
*DO NOT INSTALL
VDD
R15
0Ω
R14
100Ω
DEVCLK–
DEVCLK+
C21
0.1µF
CMLOUT_A0+
CMLOUT_A0–
LTC2122
C20
0.1µF
OVDD
OVDD
OVDD
DNC
AINA+
AINA–
5
SENSE
6 V
REF
7 V
CM
8
GND
9 A –
INB
10 A +
INB
11
GND
OVDD
VDD
VDD
VDD
R66
100Ω
0201
OF+
OF –
VDD
VDD
VDD
C24
0.1µF
R18
0Ω
C11
2.2µF
0603
SYNC~+
SYNC~–
•
3
VDD
49 48 47
R6
45.3Ω
1
4
R5
1k
SDI
SDO
OF+
OF –
GND
GND
5
C19
0.1µF
R62
4.99Ω
T1
MABA-007159-000000
AINA
C18
0.1µF
GND
C17
0.1µF
CS
SCK
C16
0.1µF
GND
C15
0.1µF
GND
VDD
C14
0.1µF
•
C22
0.1µF
C13
0.1µF
VDD
GND
DEVCLK–
DEVCLK+
GND
SYSREF+
SYSREF–
C12
0.1µF
CS
SCK
SDI
SDO
R13
0Ω
R16
0Ω
SYNC~–
SYNC~+
SYSREF–
R17
100Ω
R12
0Ω
SYSREF+
2122 TA11
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Receiver Subsystems
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50 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC2122
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTC2122
2122fa
LT 1114 REV A • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2014