PRELIMINARY Integrated Circuit Systems, Inc. ICS843004-02 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS843004-02 is a 4 output LVPECL Synthesizer optimized to generate clock HiPerClockS™ frequencies for a variety of high performance applications and is a member of the HiPerClocksTM family of high performance clock solutions from ICS. This device can select its input reference clock from either a crystal input or a single-ended clock signal and can be configured to generate a number of different output frequencies via the 3 frequency select pins (F_SEL2:0). The ICS843004-02 uses ICS’ 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter. This ensures that it will easily meet clocking requirements for high-speed communication protocols such as 10 and 12 Gigabit Ethernet, 10 Gigbit Fibre Channel, and SONET. This device is also suitable for next generation serial I/O technologies like serial ATA and SCSI and is conveniently packaged in a small 24-pin TSSOP package. • Four 3.3V LVPECL outputs ICS • Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input • Crystal input range: 14MHz - 37.78MHz • VCO Range: 560MHz - 680MHz • Supports the following applications: SONET, Ethernet, Serial ATA, SCSI and HDTV • RMS phase jitter @ 155.52MHz (12kHz - 20MHz): 0.91ps (typical) Offset Noise Power 100Hz ............... -97.1 dBc/Hz 1kHz .............. -121.6 dBc/Hz 10kHz .............. -124.9 dBc/Hz 100kHz .............. -125.1 dBc/Hz • Full 3.3V supply mode FUNCTION TABLE • 0°C to 70°C ambient operating temperature Inputs F_SEL2 F_SEL1 F_SEL0 M Divider Value N Divider Value 0 0 0 18 3 0 0 1 24 4 0 1 0 24 8 0 1 1 32 1 1 0 0 32 2 1 0 1 32 4 1 1 0 32 8 1 1 1 40 8 PIN ASSIGNMENT nQ1 Q1 VCC o Q0 nQ0 MR nPLL_SEL nc nc VCCA F_SEL0 VCC nPLL_SEL Pulldown N XTAL_IN 0 0 XTAL_OUT TEST_CLK Pulldown nXTAL_SEL Pulldown 24 23 22 21 20 19 18 17 16 15 14 13 nQ2 Q2 VCCO Q3 nQ3 F_SEL2 nXTAL_SEL TEST_CLK VEE XTAL_IN XTAL_OUT F_SEL1 ICS843004-02 BLOCK DIAGRAM OSC 1 2 3 4 5 6 7 8 9 10 11 12 1 ÷1 ÷2 ÷3 ÷4 (default) ÷8 Phase Detector VCO 24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm package body Q0 G Package Top View nQ0 Q1 nQ1 1 Q2 M nQ2 ÷18 ÷24 ÷32 (default) ÷40 Q3 nQ3 MR Pulldown 3 F_SEL0:2 The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 843004AG-02 www.icst.com/products/hiperclocks.html REV. A JULY 20, 2005 1 PRELIMINARY ICS843004-02 Integrated Circuit Systems, Inc. CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 1. PIN DESCRIPTIONS Number Name 1, 2 nQ1, Q1 Output Type Differential output pair. LVPECL interface levels. 3, 22 VCCO Power Output supply pins. 4, 5 Q0, nQ0 Ouput 6 MR Input 7 nPLL_SEL Input 8, 9 nc Unused 10 11, 19 12 VCCA F_SEL0, F_SEL2 VCC Power 13 14, 15 16 F_SEL1 XTAL_OUT, XTAL_IN VEE Input Power 17 TEST_CLK Input 18 nXTAL_SEL Input 20, 21 nQ3, Q3 Output 23, 24 Q2, nQ2 Output Input Power Input Description Differential output pair. LVPECL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx Pulldown to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Selects between the PLL and TEST_CLK as input to the dividers. When Pulldown LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL Bypass). LVCMOS/LVTTL interface levels. No connect. Analog supply pin. Pullup Frequency select pins. LVCMOS/LVTTL interface levels. Core supply pin. Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. Parallel resonant cr ystal interface. XTAL_OUT is the output, XTAL_IN is the input. Negative supply pin. Pulldown LVCMOS/LVTTL clock input. Selects between cr ystal or TEST_CLK inputs as the the PLL Reference Pulldown source. Selects XTAL inputs when LOW. Selects TEST_CLK when HIGH. LVCMOS/LVTTL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. NOTE: Pulldown and Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLDOWN Input Pulldown Resistor 51 kΩ RPULLUP Input Pullup Resistor 51 kΩ 843004AG-02 Test Conditions Minimum www.icst.com/products/hiperclocks.html 2 Typical Maximum Units REV. A JULY 20, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843004-02 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 3. OUTPUT CONFIGURATION AND FREQUENCY RANGE FUNCTION TABLE Inputs M Divider Value N Divider Value VCO (MHz) Output Frequency (MHz) Application 0 1 0 Reference Clock 24.75 24 8 594 74.25 HDTV 1 1 1 14.8351649 40 8 593.4066 74.1758245 HDTV 1 1 1 16 40 8 640 80 SCSI 1 0 1 19.44 32 4 622.08 155.52 SONET 1 1 0 19.44 32 8 622.08 77.76 SONET F_SEL2 F_SEL1 F_SEL0 0 1 1 19.44 32 1 622.08 622.08 SONET 1 0 0 19.44 32 2 622.08 311.04 SONET 0 0 1 25 24 4 600 150 SATA 0 1 0 25 24 8 600 75 SATA 0 0 1 26.5625 24 4 637.5 159.375 10 Gig Fibre Channel 1 0 1 19.53125 32 4 625 156.25 10 Gig Ethernet 0 0 0 31.25 18 3 562.5 187.5 12 Gig Ethernet 843004AG-02 www.icst.com/products/hiperclocks.html 3 REV. A JULY 20, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843004-02 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 70°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V VCCO Output Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 125 mA ICCA Analog Supply Current 12 mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol VIH VIL IIH IIL 843004AG-02 Parameter Input High Voltage nPLL_SEL, nXTAL_SEL, Input F_SEL0:F_SEL2, MR Low Voltage TEST_CLK Input High Current Input Low Current Test Conditions Minimum Typical 2 Maximum VCC + 0.3 Units V -0.3 0.8 V -0.3 1.3 V TEST_CLK, MR, F_SEL1 nPLL_SEL, nXTAL_SEL VCC = VIN = 3.465V 15 0 µA F_SEL0, F_SEL2 VCC = VIN = 3.465V 5 µA TEST_CLK, MR, F_SEL1 nPLL_SEL, nXTAL_SEL, VCC = 3.465V, VIN = 0V -150 µA F_SEL0, F_SEL2 VCC = 3.465V, VIN = 0V -5 µA www.icst.com/products/hiperclocks.html 4 REV. A JULY 20, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843004-02 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Minimum Typical Maximum Units VCCO - 1.4 VCCO - 0.9 V VCCO - 2.0 VCCO - 1.7 V 0.6 1.0 V Maximum Units NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Fundamental Frequency 14 MHz 37.78 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Maximum Units 637.5 MHz 562.5 640 MHz 562.5 580 MHz NOTE: Characterized using an 18pf parallel resonant crystal. TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fOUT Output Frequency f VCO PLL VCO Lock Range tsk(o) Output Skew; NOTE 1 tjit(Ø) RMS Phase Jitter; NOTE 2, 3 tL PLL Lock Time tR / tF Output Rise/Fall Time Test Conditions Minimum Typical 74.17 F_SEL0:F_SEL2 = 0 155.52MHz, 12kHz -20MHz 20% to 80% 15 ps 0.91 ps TBD ms 450 ps odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the output differential cross points. NOTE 2: Phase jitter is dependent on the input source used. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. 843004AG-02 www.icst.com/products/hiperclocks.html 5 % REV. A JULY 20, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843004-02 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION 2V Qx V CC , VCCA, VCCO nQx SCOPE Qx nQy LVPECL Qy nQx VEE t sk(o) -1.3V±0.165V 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW Noise Power Phase Noise Plot Phase Noise Mask 80% 80% VSW I N G f1 Offset Frequency Clock Outputs f2 20% 20% tR tF RMS Jitter = Area Under the Masked Phase Noise Plot RMS PHASE JITTER OUTPUT RISE/FALL TIME nQ0:nQ3 Q0:Q3 t PW t odc = PERIOD t PW x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 843004AG-02 www.icst.com/products/hiperclocks.html 6 REV. A JULY 20, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843004-02 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843004-02 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10µF and a .01µF bypass capacitor should be connected to each VCCA. 3.3V VCC .01µF 10Ω VCCA .01µF 10µF FIGURE 1. POWER SUPPLY FILTERING RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS OUTPUTS: INPUTS: LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. TEST CLK INPUT: For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the TEST_CLK to ground. SELECT PINS: All select pins have internal pull-ups and pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. 843004AG-02 www.icst.com/products/hiperclocks.html 7 REV. A JULY 20, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843004-02 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER CRYSTAL INPUT INTERFACE below were determined using a 26.5625MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error. The ICS843004-02 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 XTAL2 C2 33p X1 18pF Parallel Crystal XTAL1 C1 27p ICS843004-02 Figure 2. CRYSTAL INPUt INTERFACE TERMINATION FOR 3.3V LVPECL OUTPUT The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are 3.3V Zo = 50Ω 125Ω FOUT FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω RTT = 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 3A. LVPECL OUTPUT TERMINATION 843004AG-02 125Ω 84Ω FIGURE 3B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 8 REV. A JULY 20, 2005 PRELIMINARY ICS843004-02 Integrated Circuit Systems, Inc. CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER LAYOUT GUIDELINE Figure 4 shows an example of ICS843004-02 application schematic. In this example, the device is operated at VCC=3.3V. The decoupling capacitor should be located as close as possible to the power pin. Both input options are shown. The device can either be driven using a quartz crystal or a 3.3V LVCMOS signal. For the LVPECL output drivers, only two termination examples are shown in this schematic. Additional termination approaches are shown in the LVPECL Termination Application Note. MR nPLL_SEL VCC VCCA R2 10 3.3V C3 10uF C4 0.01u R3 133 VCCO R5 133 Zo = 50 Ohm F_SEL0 Logic Control Input Examples VDD RU2 Not Install To Logic Input pins RD1 Not Install (U1-3) VCC F_SEL1 XTAL_OUT XTAL_IN VEE TEST_CLK nXTAL_SEL F_SEL2 nQ3 Q3 VCCO Q2 nQ2 To Logic Input pins VCC F_SEL0 VCCA NC NC nPLL_SEL MR nQ0 Q0 VCCO Q1 nQ1 RU1 1K Zo = 50 Ohm RD2 1K (U1-12) - U4 R4 82.5 843004-02 R6 82.5 VCC=3.3V VCCO=3.3V 13 14 15 16 17 18 19 20 21 22 23 24 VDD + VCC Set Logic Input to '0' 12 11 10 9 8 7 6 5 4 3 2 1 Set Logic Input to '1' (U1-22) Zo = 50 Ohm F_SEL1 C1 0.1uF C2 0.1uF + C3 0.1uF Zo = 50 Ohm X1 19.44MHz 18pF C2 33pF VCC VCCO R5 50 R6 50 C1 27pF Q1 Ro ~ 7 Ohm R8 Optional Y-Termination Zo = 50 Ohm R7 50 43 Driv er_LVCMOS nXTAL_SEL F_SEL2 FIGURE 4. ICS843004-02 SCHEMATIC EXAMPLE 843004AG-02 www.icst.com/products/hiperclocks.html 9 REV. A JULY 20, 2005 PRELIMINARY ICS843004-02 Integrated Circuit Systems, Inc. CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 70°C/W 65°C/W 62°C/W TRANSISTOR COUNT The transistor count for ICS843004-02 is: 3467 843004AG-02 www.icst.com/products/hiperclocks.html 10 REV. A JULY 20, 2005 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX FOR ICS843004-02 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 24 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N A Maximum 24 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 7.90 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 843004AG-02 www.icst.com/products/hiperclocks.html 11 REV. A JULY 20, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843004-02 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS843004AG-02 ICS843004A02 24 Lead TSSOP tube 0°C to 70°C ICS843004AG-02T ICS843004A02 24 Lead TSSOP 2500 tape & reel 0°C to 70°C The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843004AG-02 www.icst.com/products/hiperclocks.html 12 REV. A JULY 20, 2005