TI1 ADC161S626CIMME 16-bit, 50 to 250 ksps, differential input, micropower adc Datasheet

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ADC161S626
SNAS468D – SEPTEMBER 2008 – REVISED DECEMBER 2014
ADC161S626 16-Bit, 50 to 250 kSPS, Differential Input, MicroPower ADC
1 Features
3 Description
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The ADC161S626 is a 16-bit successiveapproximation register (SAR) Analog-to-Digital
converter (ADC) with a maximum sampling rate of
250 kSPS. The ADC161S626 has a minimum signal
span accuracy of ±0.003% over the temperate range
of −40°C to +85°C. The converter features a
differential analog input with an excellent commonmode signal rejection ratio of 85 dB, making the
ADC161S626 suitable for noisy environments.
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16-bit Resolution With No Missing Codes
Ensured Performance from 50 to 250 kSPS
±0.003% Signal Span Accuracy
Separate Digital Input/Output Supply
True Differential Input
External Voltage Reference Range of 0.5 V to VA
Zero-Power Track Mode with 0-µsec Wake-up
Delay
Wide Input Common-mode Voltage Range of 0 V
to VA
SPI/QSPI™/MICROWIRE™ Compatible Serial
Interface
Operating Temperature Range of −40°C to +85°C
Small VSSOP-10 Package
Key Specifications
– Conversion Rate 50 to 250 kSPS
– DNL +0.8 / −0.5 LSB
– INL ±0.8 LSB
– Offset Error Temp Drift 2.5 μV/°C
– Gain Error Temp Drift 0.3 ppm/°C
– SNR 93.2 dBc
– THD − 104 dBc
– Power Consumption
– 10 kSPS, 5 V 0.24 mW
– 200 kSPS, 5 V 5.3 mW
– 250 kSPS, 5 V 5.8 mW
– Power-Down, 5 V 10 μW
The ADC161S626 operates with a single analog
supply (VA) and a separate digital input/output (VIO)
supply. VA can range from 4.5 V to 5.5 V and VIO can
range from 2.7 V to 5.5 V. This allows a system
designer to maximize performance and minimize
power consumption by operating the analog portion of
the ADC at a VA of 5 V while interfacing with a 3.3-V
controller. The serial data output is binary 2's
complement and is SPI compatible.
The performance of the ADC161S626 is ensured
over temperature at clock rates of 1 MHz to 5 MHz
and reference voltages of 2.5 V to 5.5 V. The
ADC161S626 is available in a small 10-lead VSSOP
package. The high accuracy, differential input, low
power consumption, and small size make the
ADC161S626 ideal for direct connection to bridge
sensors and transducers in battery operated systems
or remote data acquisition applications.
Device Information(1)
PART NUMBER
ADC161S626
Direct Sensor Interface
I/O Modules
Data Acquisition
Portable Systems
Motor Control
Medical Instruments
Instrumentation and Control Systems
BODY SIZE (NOM)
VSSOP (10)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
2 Applications
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PACKAGE
Typical Application Schematic
Wide Supply
Range
VREF independent
of VA
VA
VIO
VREF
+IN
SAR
ADC
Fully Differential
Input
VIO independent
of VA
CONTROLLER
1
VIO
3-wire SPI
MCU
-IN
GND
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADC161S626
SNAS468D – SEPTEMBER 2008 – REVISED DECEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
3
4
4
4
5
7
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Converter Electrical Characteristics..........................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 15
7.1 Overview ................................................................. 15
7.2 Functional Block Diagram ....................................... 15
7.3 Feature Description................................................. 15
7.4 Device Functional Modes........................................ 18
8
Application and Implementation ........................ 22
8.1 Application Information............................................ 22
8.2 Typical Application .................................................. 22
9
Power Supply Recommendations...................... 24
9.1 Analog and Digital Power Supplies......................... 24
9.2 Voltage Reference .................................................. 24
10 Layout................................................................... 24
10.1 Layout Guidelines ................................................. 24
10.2 Layout Example .................................................... 25
11 Device and Documentation Support ................. 26
11.1
11.2
11.3
11.4
Device Support......................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
27
27
27
12 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
Changes from Revision C (March 2013) to Revision D
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2
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
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5 Pin Configuration and Functions
10 Pins
VSSOP Package
Top View
VREF
1
10
VA
+IN
2
9
VIO
- IN
3 ADC161S626 8
SCLK
GND
4
7
DOUT
GND
5
6
CS
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
1
VREF
I
Voltage Reference
0.5 V < VREF < VA
2
+IN
I
Non-Inverting Input
3
−IN
I
Inverting Input
4
GND
Power
Ground
5
GND
Power
Ground
6
CS
I
Chip Select Bar
7
DOUT
O
Serial Data Output
8
SCLK
I
Serial Clock
9
VIO
Power
Digital Input/Output Power
2.7 V < VREF < 5.5 V
10
VA
Power
Analog Power
4.5 V < VREF < 5.5 V
6 Specifications
6.1 Absolute Maximum Ratings (1) (2) (3)
MIN
MAX
UNIT
Analog Supply Voltage VA
−0.3
6.5
V
Digital I/O Supply Voltage VIO
−0.3
6.5
V
Voltage on Any Analog Input Pin to GND
−0.3
(VA + 0.3)
V
Voltage on Any Digital Input Pin to GND
−0.3
(VIO + 0.3)
V
Input Current at Any Pin (4)
–10
10
mA
Package Input Current (4)
–50
Power Consumption at TA = 25°C
Junction Temperature
−65
Storage temperature, Tstg
(1)
(2)
(3)
(4)
(5)
50
See
mA
(5)
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are measured with respect to GND = 0 V, unless otherwise specified.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
When the input voltage at any pin exceeds the power supplies (that is, VIN < GND or VIN > VA), the current at that pin should be limited
to 10 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an
input current of 10 mA to five.
The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax − TA)/θJA. The values for maximum power dissipation listed above will be reached only when the ADC161S626 is
operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply
polarity is reversed). Such conditions should always be avoided.
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6.2 ESD Ratings
VALUE
V(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2500
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1250
Machine model (MM)
(1)
(2)
UNIT
V
250
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
Operating Temperature Range
−40
85
°C
Supply Voltage, VA
4.5
5.5
V
Supply Voltage, VIO
2.7
5.5
V
Reference Voltage, VREF
0.5
VA
V
0
VA
V
+VREF
V
Analog Input Pins Voltage Range
−VREF
Differential Analog Input Voltage
Input Common-Mode Voltage, VCM
See Figure 44
Digital Input Pins Voltage Range
0
VIO
Clock Frequency
1
5
(1)
UNIT
V
MHz
All voltages are measured with respect to GND = 0V, unless otherwise specified.
6.4 Thermal Information
ADC161S626
THERMAL METRIC (1)
DGS
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
163
RθJC(top)
Junction-to-case (top) thermal resistance
57
RθJB
Junction-to-board thermal resistance
82
ψJT
Junction-to-top characterization parameter
6
ψJB
Junction-to-board characterization parameter
81
(1)
4
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Converter Electrical Characteristics
The following specifications apply for VA = 4.5 V to 5.5 V, VIO = 2.7 V to 5.5 V, and VREF = 2.5 V to 5.5 V for fSCLK = 1 MHz to
4 MHz or VREF = 4.5 V to 5.5 V for fSCLK = 1 MHz to 5 MHz; fIN = 20 kHz, and CL = 25 pF, unless otherwise noted. Maximum
and minimum values apply for TA = TMIN to TMAX; the typical values are tested at TA = 25°C. (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
16
Bits
DNL
Differential Non-Linearity
−1
-0.5/+0.8
+2
LSB
INL
Integral Non-Linearity
−2
±0.8
+2
LSB
−1
−0.1
+1
mV
OE
Offset Error
OEDRIFT
FSE
GE
GEDRIFT
Offset Error Temperature Drift
VREF = 2.5 V
VREF = 5 V
VREF = 2.5 V
VREF = 5 V
−0.4
mV
3.7
µV/°C
2.5
µV/°C
Positive Full-Scale Error
–0.03
−0.003
0.03
%FS
Negative Full-Scale Error
–0.03
−0.002
0.03
%FS
Positive Gain Error
–0.02
−0.002
0.02
%FS
Negative Gain Error
–0.02
−0.0001
0.02
%FS
Gain Error Temperature Drift
0.3
ppm/°C
DYNAMIC CONVERTER CHARACTERISTICS
SINAD
SNR
THD
Signal-to-Noise Plus Distortion Ratio
Signal-to-Noise Ratio
Total Harmonic Distortion
SFDR
Spurious-Free Dynamic Range
ENOB
Effective Number of Bits
FPBW
−3 dB Full Power Bandwidth
VREF = 2.5 V
85
88
dBc
VREF = 4.5 V to 5.5 V
89
93.0
dBc
VREF = 2.5 V
85
88
dBc
VREF = 4.5 V to 5.5 V
89
93.2
dBc
VREF = 2.5 V
−104
dBc
VREF = 4.5 V to 5.5 V
−106
dBc
VREF = 2.5 V
108
dBc
VREF = 4.5 V to 5.5 V
111
dBc
VREF = 2.5 V
13.8
14.3
bits
VREF = 4.5 V to 5.5 V
14.5
15.2
bits
26
MHz
Output at 70.7%FS with FS Differential
Input
ANALOG INPUT CHARACTERISTICS
VIN
Differential Input Range
CS high
IINA
Analog Input Current
CINA
CMRR
Input Capacitance (+IN or −IN)
Common Mode Rejection Ratio
−VREF
+VREF
V
–1
1
µA
VREF = 5 V, VIN = 0 V, fS = 50 kSPS
3.2
nA
VREF = 5 V, VIN = 0 V, fS = 200 kSPS
10.3
nA
In Acquisition Mode
20
pF
In Conversion Mode
4
pF
85
dB
See the Specification Definitions for the
test condition
DIGITAL INPUT CHARACTERISTICS
VIH
Input High Voltage
fIN = 0 Hz
VIL
Input Low Voltage
fIN = 0 Hz
IIND
Digital Input Current
CIND
Input Capacitance
(1)
0.7 x VIO
1.9
1.7
–1
V
0.3 x VIO
V
1
µA
4
pF
Typical values are at TJ = 25°C and represent most likely parametric norms. Test limits are specified to AOQL (Average Outgoing
Quality Level).
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Converter Electrical Characteristics (continued)
The following specifications apply for VA = 4.5 V to 5.5 V, VIO = 2.7 V to 5.5 V, and VREF = 2.5 V to 5.5 V for fSCLK = 1 MHz to
4 MHz or VREF = 4.5 V to 5.5 V for fSCLK = 1 MHz to 5 MHz; fIN = 20 kHz, and CL = 25 pF, unless otherwise noted. Maximum
and minimum values apply for TA = TMIN to TMAX; the typical values are tested at TA = 25°C.(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIO − 0.2
VIO −
0.03
V
VIO −
0.09
V
DIGITAL OUTPUT CHARACTERISTICS
ISOURCE = 200 µA
VOH
Output High Voltage
ISOURCE = 1 mA
VOL
Output Low Voltage
ISOURCE = 200 µA
0.01
ISOURCE = 1 mA
0.07
IOZH, IOZL TRI-STATE Leakage Current
Force 0V or VA
COUT
Force 0V or VA
TRI-STATE Output Capacitance
–1
0.4
V
1
µA
V
4
Output Coding
pF
Binary 2's Complement
POWER SUPPLY CHARACTERISTICS
VA
Analog Supply Voltage Range
VIO
Digital Input/Output Supply Voltage
Range
VREF
Reference Voltage Range
(2)
4.5
5
5.5
V
2.7
3
5.5
V
5
VA
0.5
V
Analog Supply Current, Conversion
Mode
VA = 5 V, fSCLK = 4 MHz, fS = 200 kSPS
1060
VA = 5 V, fSCLK = 5 MHz, fS = 250 kSPS
1160
IVIO
(Conv)
Digital I/O Supply Current, Conversion
Mode
VIO = 3 V, fSCLK = 4 MHz, fS = 200 kSPS
80
µA
VIO = 3 V, fSCLK = 5 MHz, fS = 250 kSPS
100
µA
IVREF
(Conv)
Reference Current, Conversion Mode
IVA
(Conv)
VA = 5 V, fSCLK = 4 MHz, fS = 200 kSPS
80
VA = 5 V, fSCLK = 5 MHz, fS = 250 kSPS
100
IVA (PD)
Analog Supply Current, Power Down
Mode (CS high)
fSCLK = 5 MHz, VA = 5 V
(3)
2
IVIO (PD)
Digital I/O Supply Current, Power Down
Mode (CS high)
fSCLK = 5 MHz, VIO = 3 V
1
fSCLK = 0 Hz, VIO = 3 V (3)
0.3
Reference Current, Power Down Mode
(CS high)
fSCLK = 5 MHz, VREF = 5 V
0.5
(3)
0.5
IVREF
(PD)
PWR
(Conv)
Power Consumption, Conversion Mode
fSCLK = 0 Hz, VA = 5 V
fSCLK = 0 Hz, VREF = 5 V
7
VA = 5 V, fSCLK = 4 MHz, fS = 200 kSPS,
and fIN = 20 kHz,
5.3
VA = 5 V, fSCLK = 5 MHz, fS = 250 kSPS,
and fIN = 20
5.8
(3)
PWR
(PD)
Power Consumption, Power Down Mode fSCLK = 5 MHz, VA = 5.0 V
(CS high)
fSCLK = 0 Hz, VA = 5.0 V (3)
PSRR
Power Supply Rejection Ratio
µA
1340
µA
170
See the Specification Definitions for the
test condition
µA
µA
3
µA
µA
0.5
µA
µA
0.7
µA
mW
6.7
35
10
µA
mW
µW
15
−78
µW
dB
AC ELECTRICAL CHARACTERISTICS
fSCLK
Maximum Clock Frequency
fS
Maximum Sample Rate
tACQ
Acquisition/Track Time
tCONV
Conversion/Hold Time
tAD
Aperture Delay
(2)
(3)
(4)
6
1
5
MHz
50
250
kSPS
(4)
600
ns
17
See the Specification Definitions
6
SCLK
cycles
ns
The value of VIO is independent of the value of VA. For example, VIO could be operating at 5.5 V while VA is operating at 4.5V or VIO
could be operating at 2.7 V while VA is operating at 5.5 V.
This parameter is ensured by design and/or characterization and is not tested in production.
While the maximum sample rate is fSCLK / 20, the actual sample rate may be lower than this by having the CS rate slower than fSCLK /
20.
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6.6 Timing Requirements
The following specifications apply for VA = 4.5 V to 5.5 V, VIO = 2.7 V to 5.5 V, VREF = 2.5 V to 5.5 V, fSCLK = 1Mz to 5MHz,
and CL = 25 pF, unless otherwise noted. Maximum and minimum values apply for TA = TMIN to TMAX; the typical values are
tested at TA = 25°C. (1)
MIN
NOM MAX
UNIT
tCSS
CS Setup Time prior to an SCLK rising edge
8
3
tCSH
CS Hold Time after an SCLK rising edge
8
3
tDH
DOUT Hold Time after an SCLK falling edge
6
11
tDA
DOUT Access Time after an SCLK falling edge
18
41
ns
tDIS
DOUT Disable Time after the rising edge of CS (2)
20
30
ns
tCS
Minimum CS Pulse Width
tEN
DOUT Enable Time after the 2nd falling edge of SCLK
20
70
tCH
SCLK High Time
20
ns
tCL
SCLK Low Time
20
ns
tr
DOUT Rise Time
7
ns
tf
DOUT Fall Time
7
ns
(1)
(2)
ns
ns
20
ns
ns
Typical values are at TJ = 25°C and represent most likely parametric norms. Test limits are specified to AOQL (Average Outgoing
Quality Level).
tDIS is the time for DOUT to change 10% while being loaded by the Timing Test Circuit.
tACQ
tCONV (Power-Up)
(Power-Down)
tCS
CS
1
2
tCH
5
4
3
13
14
15
16
18
17
1
2
SCLK
tCL
tEN
DOUT
0
D15
tDIS
D5
D14
D4
D3
D2
D1
0
D0
Figure 1. ADC161S626 Single Conversion Timing Diagram
2 mA
TO OUTPUT
PIN
IOL
1.6V
CL
25 pF
2 mA
IOH
Figure 2. Timing Test Circuit
0.9 x VIO
DOUT
0.1 x VIO
tr
tf
Figure 3. DOUT Rise and Fall Times
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SCLK
VIL
tDA
0.7 x VIO
DOUT
0.3 x VIO
tDH
Figure 4. DOUT Hold and Access Times
SCLK
1
2
tCSH
tCSS
CS
Figure 5. Valid CS Assertion Times
CS
VIH
90%
90%
DOUT
10%
tDIS
90%
DOUT
10%
10%
Figure 6. Voltage Waveform for tDIS
8
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6.7 Typical Characteristics
VA = VIO = VREF = 5 V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS, TA = +25°C, and fIN = 20 kHz unless otherwise stated.
Figure 7. DNL - 250 kSPS
Figure 8. INL - 250 kSPS
Figure 9. DNL vs. VA
Figure 10. INL vs. VA
Figure 11. DNL vs. VREF
Figure 12. INL vs. VREF
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Typical Characteristics (continued)
VA = VIO = VREF = 5 V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS, TA = +25°C, and fIN = 20 kHz unless otherwise stated.
10
Figure 13. DNL vs. SCLK Frequency
Figure 14. INL vs. SCLK Frequency
Figure 15. DNL vs. Temperature
Figure 16. INL vs. Temperature
Figure 17. SINAD vs. VA
Figure 18. THD vs. VA
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Typical Characteristics (continued)
VA = VIO = VREF = 5 V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS, TA = +25°C, and fIN = 20 kHz unless otherwise stated.
Figure 19. SINAD vs. VREF
Figure 20. THD vs. VREF
Figure 21. SINAD vs. SCLK Frequency
Figure 22. THD vs. SCLK Frequency
Figure 23. SINAD vs. INPUT Frequency
Figure 24. THD vs. INPUT Frequency
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Typical Characteristics (continued)
VA = VIO = VREF = 5 V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS, TA = +25°C, and fIN = 20 kHz unless otherwise stated.
12
Figure 25. SINAD vs. Temperature
Figure 26. THD vs. Temperature
Figure 27. VA Current vs. VA
Figure 28. VA Current vs. SCLK Frequency
Figure 29. VA Current vs. Temperature
Figure 30. VREF Current vs. VREF
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Typical Characteristics (continued)
VA = VIO = VREF = 5 V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS, TA = +25°C, and fIN = 20 kHz unless otherwise stated.
Figure 31. VREF Current vs. SCLK Frequency
Figure 32. VREF Current vs. Temperature
Figure 33. VIO Current vs. VIO
Figure 34. VIO Current vs. SCLK Frequency
Figure 35. VIO Current vs. Temperature
Figure 36. Spectral Response - 250 kSPS
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Typical Characteristics (continued)
VA = VIO = VREF = 5 V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS, TA = +25°C, and fIN = 20 kHz unless otherwise stated.
Figure 37. Analog Input CMRR vs. Frequency
Figure 38. Noise Histogram at Code Center
Figure 39. Noise Histogram at Code Transition
14
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7 Detailed Description
7.1 Overview
The ADC161S626 is a 16-bit, 50 kSPS to 250 kSPS sampling Analog-to-Digital (A/D) converter. The converter
uses a successive approximation register (SAR) architecture based upon capacitive redistribution containing an
inherent sample-and-hold function. The differential nature of the analog inputs is maintained from the internal
sample-and-hold circuits throughout the A/D converter to provide excellent common-mode signal rejection.
The ADC161S626 operates from independent analog and digital supplies. The analog supply (VA) can range
from 4.5 V to 5.5 V and the digital input/output supply (VIO) can range from 2.7 V to 5.5 V. The ADC161S626
utilizes an external reference (VREF), which can be any voltage between 0.5 V and VA. The value of VREF
determines the range of the analog input, while the reference input current (IREF) depends upon the conversion
rate.
The analog input is presented to two input pins: +IN and –IN. Upon initiation of a conversion, the differential input
at these pins is sampled on the internal capacitor array. The inputs are disconnected from the internal circuitry
while a conversion is in progress. The ADC161S626 features a zero-power track mode (ZPTM) where the ADC
is consuming the minimum amount of power (Power-Down Mode) while the internal sampling capacitor array is
tracking the applied analog input voltage. The converter enters ZPTM at the end of each conversion window and
experiences no delay when the ADC enters into Conversion Mode. This feature allows the user an easy means
for optimizing system performance based on the settling capability of the analog source while minimizing power
consumption. ZPTM is exercised by bringing chip select bar (CS) high or when CS is held low after the
conversion is complete (after the 18th falling edge of the serial clock).
The ADC161S626 communicates with other devices via a Serial Peripheral Interface (SPI), a synchronous serial
interface that operates using three pins: chip select bar (CS), serial clock (SCLK), and serial data out (DOUT). The
external SCLK controls data transfer and serves as the conversion clock. The duty cycle of SCLK is essentially
unimportant, provided the minimum clock high and low times are met. The minimum SCLK frequency is set by
internal capacitor leakage. Each conversion requires a minimum of 18 SCLK cycles to complete. If less than 16
bits of conversion data are required, CS can be brought high at any point during the conversion. This procedure
of terminating a conversion prior to completion is commonly referred to as short cycling.
The digital conversion result is clocked out by the SCLK input and is provided serially, most significant bit (MSB)
first, at the DOUT pin. The digital data that is provided at the DOUT pin is that of the conversion currently in
progress and thus there is no pipe line delay or latency.
7.2 Functional Block Diagram
SAR
CONTROL
VREF
SERIAL
INTERFACE
+IN
S/H
CDAC
-IN
COMPARATOR
7.3 Feature Description
7.3.1 Reference Input (VREF)
The externally supplied reference voltage (VREF) sets the analog input range. The ADC161S626 will operate with
VREF in the range of 0.5 V to VA.
Operation with VREF below 2.5V is possible with slightly diminished performance. As VREF is reduced, the range
of acceptable analog input voltages is reduced. Assuming a proper common-mode input voltage (VCM), the
differential peak-to-peak input range is limited to (2 x VREF).
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Feature Description (continued)
Reducing VREF also reduces the size of the least significant bit (LSB). For example, the size of one LSB is equal
to [(2 x VREF) / 2n], which is 152.6 µV where n is 16 bits and VREF is 5V. When the LSB size goes below the noise
floor of the ADC161S626, the noise will span an increasing number of codes and overall performance will suffer.
Dynamic signals will have their SNR degrade; while, D.C. measurements will have their code uncertainty
increase. Since the noise is Gaussian in nature, the effects of this noise can be reduced by averaging the results
of a number of consecutive conversions.
VREF and analog inputs (+IN and -IN) are connected to the capacitor array through a switch matrix when the input
is sampled. Hence, IREF, I+IN, and I-IN are a series of transient spikes that occur at a frequency dependent on the
operating sample rate of the ADC161S626.
IREF changes only slightly with temperature. See the curves, “Reference Current vs. SCLK Frequency” and
“Reference Current vs. Temperature” in the Typical Characteristics section for additional details.
7.3.2 Sample and Hold
The ADC161S626 has a differential input where the effective input voltage that is digitized is (+IN) − (−IN).
7.3.2.1 Input Settling
When the ADC161S626 enters acquisition (tACQ) mode at the end of the conversion window, the internal
sampling capacitor (CSAMPLE) is connected to the ADC input via an internal switch and a series resistor (RSAMPLE),
as shown in Figure 40. Typical values for CSAMPLE and RSAMPLE are 20 pF and 200 ohms respectively. If there is
not a large external capacitor (CEXT) at the analog input of the ADC, a voltage spike will be observed at the input
pins. This is a result of CSAMPLE and CEXT being at different voltage potentials. The magnitude and direction of the
voltage spike depend on the difference between the voltage of CSAMPLE and CEXT. If the voltage at CSAMPLE is
greater than the voltage at CEXT, a positive voltage spike will occur. If the opposite is true, a negative voltage
spike will occur. It is not critical for the performance of the ADC161S626 to filter out the voltage spike. Rather,
ensure that the transient of the spike settles out within tACQ.
REXT+
VIN +-
SW+
+
RSAMPLE+ CSAMPLE+
CEXT
REXT-
SW- RSAMPLE- CSAMPLE-
Figure 40. ADC Input Capacitors
7.3.3 Serial Digital Interface
The ADC161S626 communicates via a synchronous 3-wire serial interface as shown in Figure 1 or re-shown in
Figure 41 for convenience. CS, chip select bar, initiates conversions and frames the serial data transfers. SCLK
(serial clock) controls both the conversion process and the timing of the serial data. DOUT is the serial data output
pin, where a conversion result is sent as a serial data stream, MSB first.
A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. The ADC161S626's DOUT
pin is in a high impedance state when CS is high and for the first clock period after CS is asserted; DOUT is active
for the remainder of time when CS is asserted.
The ADC161S626 samples the differential input upon the assertion of CS. Assertion is defined as bringing the
CS pin to a logic low state. For the first 17 periods of the SCLK following the assertion of CS, the ADC161S626
is converting the analog input voltage. On the 18th falling edge of SCLK, the ADC161S626 enters acquisition
(tACQ) mode. For the next three periods of SCLK, the ADC161S626 is operating in acquisition mode where the
ADC input is tracking the analog input signal applied across +IN and -IN. During acquisition mode, the
ADC161S626 is consuming a minimal amount of power.
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Feature Description (continued)
The ADC161S626 can enter conversion mode (tCONV) under three different conditions. The first condition
involves CS going low (asserted) with SCLK high. In this case, the ADC161S626 enters conversion mode on the
first falling edge of SCLK after CS is asserted. In the second condition, CS goes low with SCLK low. Under this
condition, the ADC161S626 automatically enters conversion mode and the falling edge of CS is seen as the first
falling edge of SCLK. In the third condition, CS and SCLK go low simultaneously and the ADC161S626 enters
conversion mode. While there is no timing restriction with respect to the falling edges of CS and SCLK, there are
minimum setup and hold time requirements for the falling edge of CS with respect to the rising edge of SCLK.
See Figure 5 in the Timing Requirements section for more information.
7.3.3.1 CS Input
The CS (chip select bar) input is active low and is CMOS compatible. The ADC161S626 enters conversion mode
when CS is asserted and the SCLK pin is in a logic low state. When CS is high, the ADC161S626 is always in
acquisition mode and thus consuming the minimum amount of power. Since CS must be asserted to begin a
conversion, the sample rate of the ADC161S626 is equal to the assertion rate of CS.
Proper operation requires that the fall of CS not occur simultaneously with a rising edge of SCLK. If the fall of CS
occurs during the rising edge of SCLK, the data might be clocked out one bit early. Whether or not the data is
clocked out early depends upon how close the CS transition is to the SCLK transition, the device temperature,
and the characteristics of the individual device. To ensure that the MSB is always clocked out at a given time
(the 3rd falling edge of SCLK), it is essential that the fall of CS always meet the timing requirement specified in
the Timing Requirements table.
7.3.3.2 SCLK Input
The SCLK (serial clock) is used as the conversion clock to shift out the conversion result. SCLK is CMOS
compatible. Internal settling time requirements limit the maximum clock frequency while internal capacitor
leakage limits the minimum clock frequency. The ADC161S626 offers ensured performance with the clock rates
indicated in the electrical table.
The ADC161S626 enters acquisition mode on the 18th falling edge of SCLK during a conversion frame.
Assuming that the LSB is clocked into a controller on the 18th rising edge of SCLK, there is a minimum
acquisition time period that must be met before a new conversion frame can begin. Other than the 18th rising
edge of SCLK that was used to latch the LSB into a controller, there is no requirement for the SCLK to transition
during acquisition mode. Therefore, it is acceptable to idle SCLK after the LSB has been latched into the
controller.
7.3.3.3 Data Output
The data output format of the ADC161S626 is two’s complement as shown in Figure 42. This figure indicates the
ideal output code for a given input voltage and does not include the effects of offset, gain error, linearity errors, or
noise. Each data output bit is output on the falling edges of SCLK. DOUT is in a high impedance state for the 1st
falling edge of SCLK while the 2nd SCLK falling edge clocks out a leading zero. The 3rd to 18th SCLK falling
edges clock out the conversion result, MSB first.
While most receiving systems will capture the digital output bits on the rising edges of SCLK, the falling edges of
SCLK may be used to capture the conversion result if the minimum hold time for DOUT is acceptable. See
Figure 4 for DOUT hold (tDH) and access (tDA) times.
DOUT is enabled on the second falling edge of SCLK after the assertion of CS and is disabled on the rising edge
of CS. If CS is raised prior to the 18th falling edge of SCLK, the current conversion is aborted and DOUT will go
into its high impedance state. A new conversion will begin when CS is driven LOW.
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Feature Description (continued)
tACQ
tCONV (Power-Up)
(Power-Down)
tCS
CS
1
2
4
3
tCH
5
13
14
15
16
18
17
1
2
SCLK
tCL
tEN
DOUT
0
D15
tDIS
D5
D14
D4
D3
D2
D0
D1
0
Figure 41. ADC161S626 Single Conversion Timing Diagram
7.4 Device Functional Modes
7.4.1 Differential Input Operation
The transfer curve of the ADC161S626 for a fully differential input signal is shown in Figure 42. A positive full
scale output code (0111 1111 1111 1111b or 7FFFh or 32,767d) will be obtained when (+IN) − (−IN) is greater
than or equal to (VREF − 1 LSB). A negative full scale code (1000 0000 0000 0000b or 8000h or -32,768d) will be
obtained when [(+IN) − (−IN)] is less than or equal to (−VREF + 1 LSB). This ignores gain, offset and linearity
errors, which will affect the exact differential input voltage that will determine any given output code.
0111 1111 1111 1111b
|
-1 LSB
|
0000 0000 0000 0000b
|
+1 LSB
- VREF +1LSB
+VREF - 1LSB
|
|
ADC Output Code
|
1000 0000 0000 0000b
Analog Input
Figure 42. ADC Transfer Curve
Both inputs should be biased at a common mode voltage (VCM), which will be thoroughly discussed in Figure 43
shows the ADC161S626 being driven by a full-scale differential source.
VREF
2
VCM
VCM +
RS
VCM
VREF
2
-
VREF
SRC
+
CS
RS
ADC161S626
-
VREF
2
VCM
VCM +
VCM
-
VREF
2
Figure 43. Differential Input
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Device Functional Modes (continued)
The allowable input common mode voltage (VCM) range depends upon VA and VREF used for the ADC161S626.
The ranges of VCM are depicted in Figure 44 and Figure 46. Note that these figures only apply to a VA of 5V.
Equations for calculating the minimum and maximum VCM for differential and single-ended operations are shown
in Figure 44.
6
COMMON-MODE VOLTAGE (V)
Differential Input
5
VA = 5.0V
3.75
2.5
1.25
0
-1
0.0
2.0 2.5 3.0
1.0
4.0
5.0
VREF (V)
Figure 44. VCM range for Differential Input operation
7.4.2 Single-Ended Input Operation
For single-ended operation, the non-inverting input (+IN) of the ADC161S626 can be driven with a signal that has
a peak-to-peak range that is equal to or less than (2 x VREF). The inverting input (−IN) should be biased at a
stable VCM that is halfway between these maximum and minimum values. In order to utilize the entire dynamic
range of the ADC161S626, VREF is limited to (VA / 2). This allows +IN a maximum swing range of ground to VA.
Figure 45 shows the ADC161S626 being driven by a full-scale single-ended source.
VCM + VREF
VCM
VCM
- VREF
RS
+
VREF
SRC
CS
ADC161S626
-
VCM
Figure 45. Single-Ended Input
6
COMMON-MODE VOLTAGE (V)
Single-Ended Input
5
VA = 5.0V
3.75
2.5
1.25
0
-1
0.0
0.75
1.25
1.75
2.5
VREF (V)
Figure 46. VCM Range for single-Ended Operation
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Device Functional Modes (continued)
Since the design of the ADC161S626 is optimized for a differential input, the performance degrades slightly when
driven with a single-ended input. Linearity characteristics such as INL and DNL typically degrade by 0.1 LSB and
dynamic characteristics such as SINAD typically degrade by 2 dB. Note that single-ended operation should only
be used if the performance degradation (compared with differential operation) is acceptable.
ADC Output Code
0111.1111.1111.1111b
0000.0000.0000.0000b
0
Single-ended Input V+IN
VCM =
VA
2
VA
VREF
216
1000.0000.0000.0000b
Figure 47. Single-Ended Transfer Characteristic
7.4.3 Short Cycling
Short cycling refers to the process of halting a conversion after the last needed bit is outputted. Short cycling can
be used to lower the power consumption in those applications that do not need a full 16-bit resolution, or where
an analog signal is being monitored until some condition occurs. In some circumstances, the conversion could be
terminated after the first few bits. This will lower power consumption in the converter since the ADC161S626
spends more time in acquisition mode and less time in conversion mode.
Short cycling is accomplished by pulling CS high after the last required bit is received from the ADC161S626
output. This is possible because the ADC161S626 places the latest converted data bit on DOUT as it is
generated. If only 10-bits of the conversion result are needed, for example, the conversion can be terminated by
pulling CS high after the 10th bit has been clocked out.
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Device Functional Modes (continued)
7.4.4 Burst Mode Operation
Normal operation of the ADC161S626 requires the SCLK frequency to be 20 times the sample rate and the CS
rate to be the same as the sample rate. However, in order to minimize power consumption in applications
requiring sample rates below 250 kSPS, the ADC161S626 should be run with an SCLK frequency of 5 MHz and
a CS rate as slow as the system requires. When this is accomplished, the ADC161S626 is operating in burst
mode. The ADC161S626 enters into acquisition mode at the end of each conversion, minimizing power
consumption. This causes the converter to spend the longest possible time in acquisition mode. Since power
consumption scales directly with conversion rate, minimizing power consumption requires determining the lowest
conversion rate that will satisfy the requirements of the system.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The following sections outline the design principles of data acquisition system based on the ADC161S626.
8.2 Typical Application
5V
3.3V
10uF
0.1uF
0.1uF
VA
VIO
VDD
100
VREF
1uF
1uF
GPIOa
SCLK
100
100
+IN
ADC161S626
GPIOb
CS
MCU
100
Differential
Source
100
DOUT
33n
GPIOc
-IN
1uF
GND
10k
GND
GND
10k
VCM
Figure 48. Low Cost, Low Power Data Acquisition System
Figure 48 shows a typical connection diagram for the ADC161S626 operating at VA of 5 V. VREF is connected to
a 2.5-V shunt reference, the LM4020-2.5, to define the analog input range of the ADC161S626 independent of
supply variation on the 5-V supply line. The VREF pin should be de-coupled to the ground plane by a 0.1-µF
ceramic capacitor and a tantalum capacitor of 10 µF. It is important that the 0.1-µF capacitor be placed as close
as possible to the VREF pin while the placement of the tantalum capacitor is less critical. It is also recommended
that the VA and VIO pins of the ADC161S626 be de-coupled to ground by a 0.1-µF ceramic capacitor in parallel
with a 10-µF tantalum capacitor.
8.2.1 Design Requirements
A positive supply only data acquisition system capable of digitizing differential signals ranging from –5 V to 5 V
(V+IN – V-IN), BW = 10 kHz, and a throughput of 250 kSPS (FS).
The ADC161S626 has to interface to an MCU whose supply is set at 3.3 V.
8.2.2 Detailed Design Procedure
The signal range requirement forces the design to use 5 V as VREF potential. This, in turn, forces the VA to be no
less than 5 V as well.
The requirement of interfacing to the MCU which is powered by 3.3-V supply, forces the choice of 3.3 V as a VD
supply.
Sampling is in fact a modulation process which may result in aliasing of the input signal, if the input signal is not
adequately band limited. In order to avoid the aliasing the Nyquist criterion has to be met:
F
BWsignal £ s = 125kHz
(1)
2
Therefore it is necessary to place an anti-aliasing filter at the input of the ADC. The filter may be single pole low
pass filter whose pole location has to satisfy:
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Typical Application (continued)
F
1
£ s
2p ´ R ´ C 2
1
R´C ³
p ´ Fs
(2)
(3)
With Fs = 250 kHz, a good choice for the single pole filter is:
R = 100
C = 33 nF
This reduces the input BWsignal = 48 kHz.
The capacitor at the inputs of the device provides not only the filtering of the input signal, but it also absorbs the
charge kick-back from the ADC. The kick-back is the result of the internal switches opening at the end of the
acquisition period.
The common mode level of the ADC inputs has to be set by the external bias source. The VCM bias has to be
isolated from the inputs by a large resistance in order to avoid input signal attenuation.
The VA and VIO sources are already separated in this example, due to the design requirements. This also
benefits the overall performance of the ADC, as the potentially noisy VIO supply does not contaminate the VA. In
the same vain, further consideration could be given to the SPI interface, especially when the master MCU is
capable of producing fast rising edges on the digital bus signals. Inserting small resistances in the digital signal
path may help in reducing the ground bounce, and thus improve the overall noise performance of the system.
8.2.3 Application Curve
Figure 49. Spectral Response
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9 Power Supply Recommendations
9.1 Analog and Digital Power Supplies
Any ADC architecture is sensitive to spikes on the power supply, reference, and ground pins. These spikes may
originate from switching power supplies, digital logic, high power devices, and other sources. Power to the
ADC161S626 should be clean and well bypassed. A 0.1 µF ceramic bypass capacitor and a 1 µF to 10 µF
capacitor should be used to bypass the ADC161S626 supply, with the 0.1 µF capacitor placed as close to the
ADC161S626 package as possible.
Since the ADC161S626 has both the VA and VIO pins, the user has three options on how to connect these pins.
The first option is to tie VA and VIO together and power them with the same power supply. This is the most cost
effective way of powering the ADC161S626 but is also the least ideal. As stated previously, noise from VIO can
couple into VA and adversely affect performance. The other two options involve the user powering VA and VIO
with separate supply voltages. These supply voltages can have the same amplitude or they can be different. VA
can be set to any value between +4.5V and +5.5V; while VIO can be set to any value between +2.7V and +5.5V.
Best performance will typically be achieved with VA operating at 5V and VIO at 3V. Operating VA at 5V offers the
best linearity and dynamic performance when VREF is also set to 5V; while operating VIO at 3V reduces the power
consumption of the digital logic. Operating the digital interface at 3V also has the added benefit of decreasing the
noise created by charging and discharging the capacitance of the digital interface pins.
9.2 Voltage Reference
The reference source must have a low output impedance and needs to be bypassed with a minimum capacitor
value of 0.1 µF. A larger capacitor value of 1 µF to 10 µF placed in parallel with the 0.1 µF is preferred. While the
ADC161S626 draws very little current from the reference on average, there are higher instantaneous current
spikes at the reference.
VREF of the ADC161S626, like all A/D converters, does not reject noise or voltage variations. Keep this in mind if
VREF is derived from the power supply. Any noise and/or ripple from the supply that is not rejected by the external
reference circuitry will appear in the digital results. The use of an active reference source is recommended. The
LM4040 and LM4050 shunt reference families and the LM4120 and LM4140 series reference families are
excellent choices for a reference source.
10 Layout
10.1 Layout Guidelines
Capacitive coupling between the noisy digital circuitry and the sensitive analog circuitry can lead to poor
performance. The solution is to keep the analog circuitry separated from the digital circuitry and the clock line as
short as possible. Digital circuits create substantial supply and ground current transients. The logic noise
generated could have significant impact upon system noise performance. To avoid performance degradation of
the ADC161S626 due to supply noise, avoid using the same supply for the VA and VREF of the ADC161S626 that
is used for digital circuitry on the board.
Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. However, to maximize
accuracy in high resolution systems, avoid crossing analog and digital lines altogether. It is important to keep
clock lines as short as possible and isolated from ALL other lines, including other digital lines. In addition, the
clock line should also be treated as a transmission line and be properly terminated. The analog input should be
isolated from noisy signal traces to avoid coupling of spurious signals into the input. Any external component
(e.g., a filter capacitor) connected between the converter's input pins and ground or to the reference input pin
and ground should be connected to a very clean point in the ground plane.
A single, uniform ground plane and the use of split power planes are recommended. The power planes should be
located within the same board layer. All analog circuitry (input amplifiers, filters, reference components, etc.)
should be placed over the analog power plane. All digital circuitry should be placed over the digital power plane.
Furthermore, the GND pins on the ADC161S626 and all the components in the reference circuitry and input
signal chain that are connected to ground should be connected to the ground plane at a quiet point. Avoid
connecting these points too close to the ground point of a microprocessor, microcontroller, digital signal
processor, or other high power digital device.
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Layout Guidelines (continued)
For best performance, care should be taken with the physical layout of the printed circuit board. This is especially
true with a low VREF or when the conversion rate is high. At high clock rates there is less time for settling, so it is
important that any noise settles out before the conversion begins.
10.2 Layout Example
“Analog”
Supply
To differential
source
VREF
VA
+IN
VIO
-IN
SCLK
GND
DOUT
GND
CS
“Digital”
Supply
VCM
To MCU
VIA to GROUND PLANE
GROUND PLANE
Figure 50. PCB Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Specification Definitions
APERTURE DELAY is the time between the first falling edge of SCLK and the time when the input signal is
sampled for conversion.
COMMON MODE REJECTION RATIO (CMRR) is a measure of how well in-phase signals common to both input
pins are rejected.
To calculate CMRR, the change in output offset is measured while the common mode input
voltage is changed from 2V to 3V.
CMRR = 20 LOG ( Δ Common Input / Δ Output Offset)
(4)
CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input
voltage to a digital word.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB.
DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period.
The specification here refers to the SCLK.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion or SINAD. ENOB is defined as (SINAD − 1.76) / 6.02 and says that the converter is
equivalent to a perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input.
GAIN ERROR is the deviation from the ideal slope of the transfer function. It is the difference between Positive
Full-Scale Error and Negative Full-Scale Error and can be calculated as:
Gain Error = Positive Full-Scale Error − Negative Full-Scale Error
(5)
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from
½ LSB below the first code transition through ½ LSB above the last code transition. The deviation
of any given code from this straight line is measured from the center of that code value.
MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC161S626 is
ensured not to have any missing codes.
NEGATIVE FULL-SCALE ERROR is the difference between the differential input voltage at which the output
code transitions from code 0x8001h to 0x8000h and −VREF + 1 LSB.
NEGATIVE GAIN ERROR is the difference between the negative full-scale error and the offset error.
OFFSET ERROR is the difference between the differential input voltage at which the output code transitions
from code 0x0000h to 0x0001h and 1 LSB.
POSITIVE FULL-SCALE ERROR is the difference between the differential input voltage at which the output
code transitions from code 0xFFFEh to 0xFFFFh and VREF - 1 LSB.
POSITIVE GAIN ERROR is the difference between the positive full-scale error and the offset error.
POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well a change in the analog supply voltage
is rejected. PSRR is calculated from the ratio of the change in offset error for a given change in
supply voltage, expressed in dB. For the ADC161S626, VA is changed from 4.5V to 5.5V.
PSRR = 20 LOG (ΔOutput Offset / ΔVA)
(6)
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) is the ratio, expressed in dB, of the rms value of
the input signal to the rms value of all of the other spectral components below one-half the
sampling frequency, including harmonics but excluding d.c.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms
value of the sum of all other spectral components below one-half the sampling frequency, not
26
Submit Documentation Feedback
Copyright © 2008–2014, Texas Instruments Incorporated
Product Folder Links: ADC161S626
ADC161S626
www.ti.com
SNAS468D – SEPTEMBER 2008 – REVISED DECEMBER 2014
Device Support (continued)
including harmonics or d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal
amplitude to the amplitude of the peak spurious spectral component below one-half the sampling
frequency, where a spurious spectral component is any signal present in the output spectrum that
is not present at the input and may or may not be a harmonic.
THROUGHPUT TIME is the minimum time required between the start of two successive conversion.
TOTAL HARMONIC DISTORTION (THD) is the ratio of the rms total of the first five harmonic components at the
output to the rms level of the input signal frequency as seen at the output, expressed in dB. THD is
calculated as
THD = 20 x log10
Af 2 2 + ... + Af 6 2
Af 12
where
•
•
Af1 is the RMS power of the input frequency at the output
Af2 through Af6 are the RMS power in the first 5 harmonic frequencies.
(7)
11.2 Trademarks
QSPI is a trademark of Motorola.
MICROWIRE is a trademark of National Semiconductor Corp.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2008–2014, Texas Instruments Incorporated
Product Folder Links: ADC161S626
27
PACKAGE OPTION ADDENDUM
www.ti.com
13-Sep-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADC161S626CIMM/NOPB
ACTIVE
VSSOP
DGS
10
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
X98C
ADC161S626CIMME/NOPB
ACTIVE
VSSOP
DGS
10
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
X98C
ADC161S626CIMMX/NOPB
ACTIVE
VSSOP
DGS
10
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
X98C
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
13-Sep-2014
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-May-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ADC161S626CIMM/NOPB VSSOP
DGS
10
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
ADC161S626CIMME/NOP VSSOP
B
DGS
10
250
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
ADC161S626CIMMX/NOP VSSOP
B
DGS
10
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-May-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADC161S626CIMM/NOPB
VSSOP
DGS
10
1000
210.0
185.0
35.0
ADC161S626CIMME/NOP
B
VSSOP
DGS
10
250
210.0
185.0
35.0
ADC161S626CIMMX/NOP
B
VSSOP
DGS
10
3500
367.0
367.0
35.0
Pack Materials-Page 2
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