Siemens HYB3165800AT-50 8m x 8-bit dynamic ram Datasheet

8M x 8-Bit Dynamic RAM
( 4k & 8k Refresh)
HYB 3164800AJ/AT(L) -40/-50/-60
HYB 3165800AJ/AT(L) -40/-50/-60
Advanced Information
•
8 388 608 words by 8-bit organization
•
0 to 70 °C operating temperature
•
Fast Page Mode operation
•
Performance:
-40
-50
-60
tRAC
RAS access time
40
50
60
ns
tCAC
CAS access time
10
13
15
ns
tAA
Access time from address
20
25
30
ns
tRC
Read/write cycle time
75
90
110
ns
tPC
Fast page mode cycle time
30
35
40
ns
•
Single + 3.3 V (± 0.3V) power supply
•
Low power dissipation:
max. 396 mW active ( HYB 3164800AJ/AT(L) -40)
max. 324 mW active ( HYB 3164800AJ/AT(L) -50)
max. 270 mW active ( HYB 3164800AJ/AT(L) -60)
max. 558 mW active ( HYB 3165800AJ/AT(L) -40)
max. 468 mW active ( HYB 3165800AJ/AT(L) -50)
max. 378 mW active ( HYB 3165800AJ/AT(L) -60)
7.2 mW standby (LVTTL)
3.24 mW standby (LVCMOS)
720 µW standby for L-versions
•
Read, write, read-modify-write, CAS-before-RAS refresh (CBR),
RAS-only refresh, hidden refresh and self refresh (L-version only)
8192 refresh cycles/128 ms , 13 R/ 10C addresses (HYB 3164800AJ/AT)
4096 refresh cycles/ 64 ms , 12 R/ 11C addresses (HYB 3165800AJ/AT)
• 256 msec refresh period for L-versions
•
•
Plastic Package:
Semiconductor Group
P-SOJ-32-1
400 mil
P-TSOPII-32-1 400 mil
1
HYB 3164(5)800AJ
HYB 3164(5)800AT(L)
6.97
HYB3164(5)800AJ/AT(L)-40/-50/-60
8M x 8-DRAM
This device is a 64 MBit dynamic RAM organized 8 388 608 by 8 bits. The device is fabricated in an
advanced second generation 64Mbit 0,35 µm CMOS silicon gate process technology. The circuit
and process design allow this device to achieve high performance and low power dissipation. This
DRAM operates with a single 3.3 +/-0.3V power supply and interfaces with either LVTTL or
LVCMOS levels. Multiplexed address inputs permit the HYB 3164(5)800AJ/AT to be packaged in a
400mil wide SOJ-32 or TSOP-32 plastic package. These packages provide high system bit
densities and are compatible with commonly used automatic testing and insertion equipment. The
HYB3164(5)800ATL parts (L-versions) have a very low power „sleep mode“ supported by Self
Refresh
Ordering Information
Type
Ordering
Code
Package
Descriptions
HYB 3164800AJ-40
P-SOJ-32-1
400 mil
DRAM (access time 40 ns)
HYB 3164800AJ-50
P-SOJ-32-1
400 mil
DRAM (access time 50 ns)
HYB 3164800AJ-60
P-SOJ-32-1
400 mil
DRAM (access time 60 ns)
HYB 3164800AT-40
P-TSOPII-32-1
400 mil
DRAM (access time 40 ns)
HYB 3164800AT-50
P-TSOPII-32-1
400 mil
DRAM (access time 50 ns)
HYB 3164800AT-60
P-TSOPII-32-1
400 mil
DRAM (access time 60 ns)
HYB 3165800AJ-40
P-SOJ-32-1
400 mil
DRAM (access time 40 ns)
HYB 3165800AJ-50
P-SOJ-32-1
400 mil
DRAM (access time 50 ns)
HYB 3165800AJ-60
P-SOJ-32-1
400 mil
DRAM (access time 60 ns)
HYB 3165800AT-40
P-TSOPII-32-1
400 mil
DRAM (access time 40 ns)
HYB 3165800AT-50
P-TSOPII-32-1
400 mil
DRAM (access time 50 ns)
HYB 3165800AT-60
P-TSOPII-32-1
400 mil
DRAM (access time 60 ns)
HYB 3164(5)800ATL
P-TSOPII-32-1
400 mil
Low Power DRAMs
Pin Names
A0-A12
Address Inputs for 8k-refresh versions HYB 3164800AJ/AT(L)
A0-A11
Address Inputs for 4k-refresh versions HYB 3165800AJ/AT(L)
RAS
Row Address Strobe
OE
Output Enable
I/O1-I/O8
Data Input/Output
CAS
Column Address Strobe
WE
Read/Write Input
Vcc
Power Supply ( + 3.3V)
Vss
Ground
Semiconductor Group
2
HYB3164(5)800AJ/AT(L)-40/-50/-60
8M x 8-DRAM
P-SOJ-32-1 (400 mil)
P-TSOPII-32-1 (400 mil)
VCC
I/O1
I/O2
I/O3
I/O4
N.C.
VCC
WRITE
RAS
.
A0
A1
A2
A3
A4
A5
VCC
O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
I/O8
I/O7
I/O6
I/O5
VSS
CAS
OE
A12 / N.C. *
A11
A10
A9
A8
A7
A6
VSS
* Pin 24 is A12 for HYB 3164800AJ/AT(L) and N.C. for HYB 3165800AJ/AT(L)
Pin Configuration
Semiconductor Group
3
HYB3164(5)800AJ/AT(L)-40/-50/-60
8M x 8-DRAM
TRUTH TABLE
FUNCTION
RAS
CAS
WE
OE
ROW
ADDR
COL
ADDR
I/O1I/O8
Standby
H
H-X
X
X
X
X
High Impedance
Read
L
L
H
L
ROW
COL
Data Out
Early-Write
L
L
L
X
ROW
COL
Data In
Delayed-Write
L
L
H-L
H
ROW
COL
Data In
Read-Modify-Write
L
L
H-L
L-H
ROW
COL
Data Out, Data In
1st Cycle
L
H-L
H
L
ROW
COL
Data Out
2nd Cycle
L
H-L
H
L
n/a
COL
Data Out
1st Cycle
L
H-L
L
X
ROW
COL
Data In
2nd Cycle
L
H-L
L
X
n/a
COL
Data In
1st Cycle
L
H-L
H-L
L-H
ROW
COL
Data Out, Data In
2st Cycle
L
H-L
H-L
L-H
n/a
COL
Data Out, Data In
L
H
X
X
ROW
n/a
High Impedance
CAS-before-RAS refresh
H-L
L
H
X
X
n/a
High Impedance
Test Mode Entry
H-L
L
L
X
X
n/a
High Impedance
READ
L-H-L
L
H
L
ROW
COL
Data Out
WRITE
L-H-L
L
L
X
ROW
COL
Data In
Fast Page Mode Read
Fast Page Mode Early
Write
Fast Page Mode RMW
RAS only refresh
Hidden Refresh
Semiconductor Group
4
HYB3164(5)800AJ/AT(L)-40/-50/-60
8M x 8-DRAM
I/O1 I/O2
I/O8
WE
CAS
&
.
Data in
Buffer
11
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
No. 2 Clock
Generator
8
Column
Address
Buffer(11)
11
Data out
Buffer
8
Column
Decoder
Refresh
Controller
Sense Amplifier
I/O Gating
Refresh
Counter (12)
2048
x8
12
Row
12
RAS
Address
Buffers(12)
12
Row
Decoder 4096
No. 1 Clock
Generator
Block Diagram for HYB 3165800AJ/AT(L)
Semiconductor Group
OE
5
Memory Array
4096 x 2048 x 8
8
HYB3164(5)800AJ/AT(L)-40/-50/-60
8M x 8-DRAM
I/O1 I/O2
I/O8
WE
CAS
&
.
Data in
Buffer
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
No. 2 Clock
Generator
8
Column
Address
Buffer(10)
10
Data out
Buffer
8
Column
Decoder
Refresh
Controller
Sense Amplifier
I/O Gating
Refresh
Counter (13)
1024
x8
13
Row
13
RAS
Address
Buffers(13)
Row
Decoder 8192
13
No. 1 Clock
Generator
Block Diagram for HYB 3164800AJ/AT(L)
Semiconductor Group
OE
6
Memory Array
8192 x 1024 x 8
8
HYB3164(5)800AJ/AT(L)-40/-50/-60
8M x 8-DRAM
Absolute Maximum Ratings
Operating temperature range..............................................................................................0 to 70 °C
Storage temperature range.........................................................................................– 55 to 150 °C
Input/output voltage..................................................................................-0.5 to min (Vcc+0.5,4.6) V
Power supply voltage....................................................................................................-0.5V to 4.6 V
Power dissipation......................................................................................................................1.0 W
Data out current (short circuit)..................................................................................................50 mA
Note
Stresses above those listed under „Absolute Maximum Ratings“ may cause permanent damage of
the device. Exposure to absolute maximum rating conditions for extended periods may effect device
reliability.
DC Characteristics
TA = 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V
Parameter
Symbol
Limit Values
min.
max.
Unit Note
Input high voltage
VIH
2.0
Vcc+0.3
V
1)
Input low voltage
VIL
– 0.3
0.8
V
1)
Output high voltage (LVTTL)
Output „H“ level voltage (Iout = -2mA)
VOH
2.4
–
V
Output low voltage (LVTTL)
Output „L“level voltage (Iout = +2mA)
VOL
–
0.4
V
Output high voltage (LVCMOS)
Output „H“ level voltage (Iout = -100uA)
VOH
Vcc-0.2 -
V
Ouput low voltage (LVCMOS)
Output „L“ level voltage (Iout = +100uA)
VOL
-
0.2
V
Input leakage current,any input
II(L)
–2
2
µA
IO(L)
–2
2
µA
(0 V < Vin < Vcc , all other pins = 0 V
Output leakage current
(DO is disabled, 0 V < Vout < Vcc )
Semiconductor Group
7
HYB3164(5)800AJ/AT(L)-40/-50/-60
8M x 8-DRAM
DC-Characteristics (cont’d)
TA = 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V
Parameter
Symbol refresh version Unit Note
4k
8k
155
130
105
110
90
75
mA
mA
mA
2) 3) 4)
2
2
mA
–
155
130
105
110
90
75
mA
mA
mA
2) 4)
70
60
50
70
60
50
mA
mA
mA
2) 3) 4)
ICC5
900
900
µA
–
ICC5
200
200
µA
–
155
130
105
155
130
105
mA
mA
mA
2) 4)
400
400
µA
ICC1
Operating Current
-40 ns version
-50 ns version
-60 ns version
(RAS, CAS, address cycling: tRC = tRC min.)
ICC2
Standby Current
(RAS=CAS= Vih)
RAS Only Refresh Current:
-
ICC3
-40 ns version
-50ns version
-60 ns version
(RAS cycling: CAS = VIH: tRC = tRC min.)
ICC4
Fast Page Mode Current:
-40 ns version
-50 ns version
-60 ns version
(RAS = VIL, CAS, address cycling: tPC=tPC min.)
Standby Current
(RAS=CAS= Vcc-0.2V)
Standby Current (L-Version)
(RAS=CAS= Vcc-0.2V)
ICC6
CAS Before RAS Refresh Current
-40 ns version
-50 ns version
-60 ns version
(RAS, CAS cycling: tRC = tRC min.)
Self Refresh Current (L-version only)
ICC7
(CBR cycle with tRAS>TRASSmin, CAS held low,
WE = Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)
Semiconductor Group
8
HYB3164(5)800AJ/AT(L)-40/-50/-60
8M x 8-DRAM
AC64-2F
AC Characteristics (note: 6,7,8)
TA = 0 to 70 °C,VCC = 3.3 ± 0.3V
Parameter
-40
Symbol
-50
-60
Unit Note
min.
max. min.
max. min.
max.
tRC
75
–
–
–
tRAS
40
100k 50
100k 60
100k ns
tCAS
10
100k 13
100k 15
100k ns
tRP
25
–
30
–
40
–
ns
CAS precharge time
tCP
10
–
10
–
10
–
ns
Row address setup time
tASR
0
–
0
–
0
–
ns
Row address hold time
tRAH
5
–
7
–
10
–
ns
Column address setup time
tASC
0
–
0
–
0
–
ns
Column address hold time
tCAH
5
–
7
–
10
–
ns
RAS to CAS delay time
tRCD
15
30
17
37
20
45
ns
RAS to column address delay
tRAD
10
20
12
25
15
30
ns
RAS hold time
tRSH
10
–
13
–
15
–
ns
CAS hold time
tCSH
40
–
50
–
60
–
ns
CAS to RAS precharge time
tCRP
5
–
5
–
5
–
ns
tT
1
30
1
30
1
30
ns
Refresh period for 8k-refresh
tREF
–
128
–
128
–
128
ms
Refresh period for 4k-refresh
tREF
–
64
–
64
–
64
ms
Refresh period for L-versions
tREF
–
256
–
256
–
256
ms
Access time from RAS
tRAC
–
40
–
50
–
60
ns
8, 9
Access time from CAS
tCAC
–
10
–
13
–
15
ns
8, 9
Access time from column address
tAA
–
20
–
25
–
30
ns
8, 10
OE access time
tOEA
–
10
–
13
–
15
ns
8
Column address to RAS lead time tRAL
20
–
25
–
30
–
ns
Read command setup time
tRCS
0
–
0
–
0
–
ns
Read command hold time
tRCH
0
–
0
–
0
–
ns
11
Read command hold time
referenced to RAS
tRRH
0
–
0
–
0
–
ns
11
tCLZ
0
–
0
–
0
–
ns
8
Common Parameters
Random read or write cycle time
RAS pulse width
CAS pulse width
RAS precharge time
Transition time (rise and fall)
90
110
ns
7
Read Cycle
CAS to output in low-Z
Semiconductor Group
9
HYB3164(5)800AJ/AT(L)-40/-50/-60
8M x 8-DRAM
AC64-2F
AC Characteristics (cont’d)(note: 6,7,8)
TA = 0 to 70 °C,VCC = 3.3 ± 0.3V
Parameter
-40
Symbol
-50
-60
min.
max. min.
max. min.
max.
Unit Note
Output buffer turn-off delay
tOFF
–
10
–
13
–
15
ns
12
Output buffer turn-off delay from
OE
tOEZ
–
10
–
13
–
15
ns
12
Data to OE low delay
tDZO
0
–
0
–
0
–
ns
13
CAS high to data delay
tCDD
10
–
13
–
15
–
ns
14
OE high to data delay
tODD
10
–
13
–
15
–
ns
14
Write command hold time
tWCH
5
–
7
–
10
–
ns
Write command pulse width
tWP
5
–
7
–
10
–
ns
Write command setup time
tWCS
0
–
0
–
0
–
ns
Write command to RAS lead time tR WL
10
–
13
–
15
–
ns
Write command to CAS lead time tC WL
10
–
13
–
15
–
ns
Data setup time
tDS
0
–
0
–
0
–
ns
16
Data hold time
tDH
5
–
7
–
10
–
ns
16
CAS delay time from Din
tDZC
0
–
0
–
0
–
ns
13
Read-write cycle time
tR WC
105
–
126
–
150
–
ns
RAS to WE delay time
tR WD
55
–
68
–
80
–
ns
15
CAS to WE delay time
tC WD
25
–
31
–
35
–
ns
15
Column address to WE delay time tAWD
35
–
43
–
50
–
ns
15
OE command hold time
tOEH
5
–
7
–
10
–
ns
Fast page mode cycle time
tPC
30
–
35
–
40
–
ns
Access time from CAS precharge
tCPA
–
25
–
30
–
35
ns
tRAS
40
200k 50
200k 60
200k ns
tRHPC
25
–
–
–
Write Cycle
15
Read-Modify-Write Cycle
Fast Page Mode Cycle
RAS pulse width
CAS precharge to RAS Delay
Semiconductor Group
10
30
35
ns
8
HYB3164(5)800AJ/AT(L)-40/-50/-60
8M x 8-DRAM
AC64-2F
AC Characteristics (cont’d)(note: 6,7,8)
TA = 0 to 70 °C,VCC = 3.3 ± 0.3V
Parameter
-40
Symbol
-50
-60
min.
max. min.
max. min.
max.
Unit Note
Fast Page Mode Read-Modify-Write Cycle
Fast page mode read-write cycle
time
tPR WC
60
–
71
–
80
–
ns
CAS precharge to WE
tCPWD
40
–
48
–
55
–
ns
CAS setup time
tCSR
5
–
5
–
5
–
ns
CAS hold time
tCHR
5
–
5
–
10
–
ns
RAS to CAS precharge time
tRPC
0
–
0
–
0
–
ns
Write to RAS precharge time
tWRP
5
–
5
–
10
–
ns
Write hold time referenced to RAS tWRH
5
–
5
–
10
–
ns
CAS-before-RAS Refresh Cycle
Self Refresh Cycle (L-version only)
RAS pulse width
tRASS
100k –
100k –
100k –
ns
17
RAS precharge time
tRPS
75
–
90
–
110
–
ns
17
CAS hold time
tCHS
-50
–
-50
–
-50
–
ns
17
Write command setup time
tWTS
5
–
5
–
5
–
ns
18
Write command hold time
tWTH
5
–
5
–
5
–
ns
18
Test Mode Cycle
Capacitance
TA = 0 to 70 °C,VCC = 3.3 V ± 0.3 V, f = 1 MHz
Parameter
Symbol
Limit Values
min.
max.
Unit
Input capacitance (A0 to A11,A12)
CI1
–
5
pF
Input capacitance (RAS, CAS, WE, OE)
CI2
–
7
pF
I/O capacitance (I/O1-I/O8)
CIO
–
7
pF
Semiconductor Group
11
HYB3164(5)800AJ/AT(L)-40/-50/-60
8M x 8-DRAM
Notes:
1) All voltages are referenced to VSS.
Vih may overshoot to Vcc + 2.0 V for pulse widths of < 4ns with 3.3V. Vil may undershoot to -2.0V for pulse
width < 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference.
2) ICC1, ICC3, ICC4 and ICC6 and ICC7 depend on cycle rate.
3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.
4) Address can be changed once or less while RAS = Vil.In the case of ICC4 it can be changed once or less
during a fast page mode cycle ( tpc).
5) An initial pause of 100 µs is required after power-up followed by 8 RAS-only-refresh cycles, before proper
device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS
initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume tT = 5 ns.
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are
measured between VIH and VIL.
8) Measured with the specified current load and 100 pF at Voh = 2.0 V and Vol = 0.8 V.
9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a
reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by
tCAC.
10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a
reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by
tAA.
11) Either tRCH or tRRH must be satisfied for a read cycle.
12) tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are
not referenced to output voltage levels.
13) Either tDZC or tDZO must be satisfied.
14) Either tCDD or tODD must be satisfied.
15) tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin
will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD
(min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will
contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition
of the I/O pins (at access time) is indeterminate.
16) These parameters are referenced to CAS leading edge in early write cycles and to WRITE leading edge in
Read-Modify-Write cycles.
17) When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM
operation:
If row addresses are being refresh in an evenly distributed manner over the refresh iterval using CBR refresh
cycles, then only one CBR cycle must be performed immediatly after exit from Self Refresh.
If row addresses are being refresh in any other manner (ROR - Distributed/Burst or CBR-Burst) over the
refresh interval, then a full set of row refreshed must be performed immediately before entry to and immediatey
after exit from Self Refresh.
18) In a Test Mode Read Cycle, the value of trac, taa, tcac and tcpa are delayed by 5 ns from the specified value.
These parameters must be adjusted in Test Mode cycles by adding 5ns to the specified value. Associated
timings must be adjusted by 5 ns.
Semiconductor Group
12
HYB3164(5)800AJ/AT(L)-40/-50/-60
8M x 8-DRAM
tRC
tRAS
V
RAS
IH
VIL
tCSH
CAS
IH
VIL
tRAD
tASR
V
Address
AAA
AAAA
IH AAAA
AAAAAAA
AAA
AAAA
AAA
AAAA
AAAAAAA
AAA
VIL
Row
tRAL
tCAH
tASC
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAAAAAA
AAA
tCRP
tRSH
tCAS
tRCD
V
tRP
tASR
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAA
AAA
Column
tRCH
tRAH
tRCS
tRRH
V
WE
AAAAAAAA
AAAAAAAA
AAAAAA
AAAA
IH AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
VIL
V
OE
I/O
(Inputs)
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAA
tAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAA
A
tOEA
IH AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAA
A
VIL
V
Row
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
tCDD
tDZC
tODD
tDZO
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
IH AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
VIL
AAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
tCAC
tCLZ
V
OH
I/O
(Outputs) V
Hi Z
OL
tOFF
AAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAA
A
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAA
A
AAAA
A
tOEZ
AAAAAA
AA
AAAA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AAAAAA
AA
Valid Data Out
Hi Z
tRAC
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAA
WL1
“H” or “L”
Read Cycle
Semiconductor Group
13
HYB3164(5)800AJ/AT(L)-40/-50/-60
8M x 8-DRAM
tRC
tRAS
tRP
V
IH
RAS
VIL
tCSH
tRCD
V
CAS
IH
VIL
tRAD
tASR
V
Address
IH
VIL
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAAAAAA
AAA
V
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAAAAAA
AAA
OE
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAA
AAA
AAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
.
Row
tCWL
tWCS
t WP
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
A
tWCH
tRWL
V AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
IHAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
VIL AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
tDS
I/O
(Inputs)
tASR
Column
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
IH AAAA
VIL
tCAH
tASC
Row
tCRP
tRAL
tRAH
WE
tRSH
tCAS
tDH
V
IH
Valid Data In
VIL
V
OH
I/O
(Outputs) V
Hi Z
OL
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAAAAAA
AAA
WL2
“H” or “L”
Write Cycle (Early Write)
Semiconductor Group
14
HYB3164(5)800AJ/AT(L)-40/-50/-60
8M x 8-DRAM
tRC
tRAS
V
RAS
IH
VIL
tCSH
tRCD
IH
VIL
tRAD
tASR
tCAH
tASC
V AAAA
AAAA
AAAAAAA
IHAAAA
AAAA
AAAAAAAA
AAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAA
Row
Address V AAAA
AAAAAAAA
AAAAAA
IL AAAAAAAAA
tRAL
Column
tASR
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAA
tCWL
tRAH
V
WE
tCRP
tRSH
tCAS
V
CAS
tRP
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
IH AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
VIL AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
tRWL
tWP
.
Row
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAA
tOEH
V
OE
IH AAAAAAAAAAAAAAAAAAAAAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
VIL AAAA
AAAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAAAAAA
AAAA
AAAA
AAA
tODD
tDS
tOEZ
tDZO
tDZC
I/O
(Inputs)
V
IH AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
VIL
AAAAAAAAAAAAAAAAAA
AAAA
AAAAAAAA
AAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
tCLZ
AAAAA
A
AAAA
AAAA
A
AAAA
A
AAAA
A
AAAA
AAAAA
A
AAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAA
tDH
Valid Data
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAA
AAA
tOEA
V
OH
I/O
(Outputs) V
Hi-Z
OL
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAA
WL3
“H” or “L”
Write Cycle (OE Controlled Write)
Semiconductor Group
Hi-Z
15
HYB3164(5)800AJ/AT(L)-40/-50/-60
8M x 8-DRAM
tRWC
tRAS
tRP
V
IH
RAS
tCSH
VIL
tRSH
tCAS
tRCD
V
tCRP
IH
CAS
VIL
tRAH
tCAH
V
A
AAA
IH AAA
AAAAA
Address
VIL
AAA
AA
AAA
AAA
AAAAA
Row
tASR
tASC
tASR
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AAAAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAA
Column
tCWL
tRWL
tAWD
tRAD
tCWD
tRWD
tWP
V
WE
Row
AAAA
AAAA
AAAA
AAAA
IH AAA
AAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
VIL AAAAAAAAAAAAAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAA
AA
tAA
tRCS
tOEH
tOEA
V
OE
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAA
IH AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
VIL AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAA
tDS
tDZO
tDZC
tDH
V
I/O
(Inputs)
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAA
IH AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAA
AA
AAAA
AAAA
AAAA
AAAA
AAAA
VIL AAAAAAAAAAAAAAAAAAAAAAAA
AAAAAA
AA
AAAA
AAA
AAAA
AAA
AAAA
AAAAAAA
AAA
AAAA
AAAAAAA
AAA
tCLZ
Valid
Data in
AAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAA
AAAAAAA
AAA
tODD
tCAC
tOEZ
V
OH
AAAA
AAAAAA
AA Data
AAAA
AA
AAAA
AA Out
AAAA
AAAAAA
AA
I/O
(Outputs) VOL
tRAC
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAA
AAAA
AAAAAAAA
AAAA
“H” or “L”
WL4
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
16
HYB3164(5)800AJ/AT(L)-40/-50/-60
8M x 8-DRAM
tRP
tRASP
V
IH
RAS
VIL
tRHPC
tRSH
tCAS
tPC
tCAS
tRCD
tCAS
tCP
V
tCRP
IH
CAS
VIL
tCSH
tRAH
tASR
V
Address
tCAH
tASC
AA
AAAA
AA
AAAA
AAAA
IH AAAA
AAAA
AA
AAAA
AA
AAAA
AAAA
Row
AA
AAAA
AA
AAAA
AAAA
VIL AAAA
AAAAA
tRAD
tASC
AAAA
AAAA
AA
AAAA
AAAA
AA
AAAA
AAAA
AA
Column
AAAA
AAAA
AA
AAAA
AAAA
AA
AAAA
AAAA
AAAAAAAAAA
AA
Column
tRCH
WE
IH AAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
VIL
AAAA
A
AAAA
A
AAAA
A
AAAA
A
AAAA
AAAAA
A
AAAA
AAAA
AAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
tAA
tOEA
V
OE
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
IH AAAA
VIL
AAAA
AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
tODD
V
AAAAAAAA
AAAAAAAA
IH AAAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
VIL
AAAAAAAA
AAAAAAAAAAAA
AAAAAAAA
AAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAA
tCAC
tRAC
tCLZ
V
OH
OL
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAA
AAAA
AAAAAAAA
AAAA
AAAA
A
AAAA
A
AAAA
AAAAA
A
AAAA
A
AAAA
AAAAA
A
tOFF
tOEZ
AAAA
A
AAAA
AAAAA
A Valid
AAAA
A
AAAA
A Data Out
AAAA
AAAAA
A
I/O
(Outputs) V
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAA
A
AAAA
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAA
A
tODD
tCAC
tCLZ
tOEZ
AAAA
AA
AAAA
AAAAAA
AA Valid
AAAA
AA
AAAA
AA Data Out
AAAA
AAAAAA
AA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAA
AAAA
tCDD
tDZO
AAA
AA
AAA
AA
AAA
AAAAA
AA
AAA
AA
AAA
AAAAA
AA
tOFF
tDZC
AAAA
AAAA
AAA
AAAA
AAAA
AAA
AAAA
AAAA
AAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAAAAAAAAA
AAA
tRRH
tODD
tCAC
tCLZ
AAAA
AAAA
AAAA
AAAAAA
AA
AAAA
AAAAAAAA
AAAAAA
AA
AAAA
AAAAAAAA
AAAAAA
AA
tOFF
tOEZ
AAAA
AAAAAA
AA Valid
AAAA
AA
AAAA
AA Data Out
AAAA
AAAAAA
AA
“H” or “L”
FPM1
Fast Page Mode Read Cycle
Semiconductor Group
tCPA
tAA
tOEA
tDZO
tDZO
I/O
(Inputs)
AAAA
A
AAAA
A
AAAA
A
AAAA
A
AAAA
AAAAA
A
tOEA
tDZC
tDZC
AAAA
AAAA
AAA
AAAA
AAAA
AAA
AAAA
AAAA
AAA
Row
AAAA
AAAA
AAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAAAAAAAAA
AAA
tRCH
tRCS
tCPA
tAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAA
AAAA
tASR
tASC
AAAA
AAAA
A
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAAA
A Column
AAAA
AAAAAAAA
AAAAA
A
tRCS
tRCS
V
tCAH
tCAH
17
HYB3164(5)800AJ/AT(L)-40/-50/-60
8M x 8-DRAM
tRP
tRAS
V
IH
RAS
VIL
tRSH
tPC
tRCD
V
CAS
tCAS
VIL
tCRP
tRAL
tCAH
tASR
V
IH AAAA
AAAAAA
VIL
AAAA
AA
AAAA
AAAA
AAAAAA
Row
AAAA
AA
AAAA
AAAA
AA
AAAA
AAAA
AAAAAA
tCAH
tASC
tASC
tASC
tASR
tCAH
AAAA
AA
AAAA
AA
AAAA
AAAA
A
AAAAAAAA
AAAA
AA
AAAAAAAA
AAAA
AA
AAAA
AAAA
A
AAAA
AA
AAAA
AA
AAAA
AAAA
A
Column AAAA
Column AAAA
AAAA
AAAA
AA
AAAA
AAAA
AA
AAAA
AAAA
A Column
Column
AAAA
AAAA
AA
AAAA
AAAA
AA
AAAA
AAAA
AAAAAAAAAA
AAAAAAAAAA
AAAAAAAAA
A
tCWL
tRAD
tWCS
tCWL
tWCS
tWCH
V
WE
tCAS
tCAS
IH
tRAH
Address
tCP
AAAAAAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAA
IH AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
VIL AAAAAAAAAAAAAAAAAAA
AAA
tWP
AAAA
AAAA
AAA
AAAA
AAAA
AAA
AAAA
AAAA
AAA
AAAA
AAAA
AAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAAAAAAAAA
AAA
tWCS
tCWL
tRWL
tWCH
tWCH
tWP AAAAAAAAAAAAA tWP AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAAAAAAAAAAA
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAA
AAA
V
OE
IH AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
VIL AAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAA
tDH
tDS
tDS
I/O
(Inputs)
V
IH AAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
VIL
AAAA
AAAAAAAA
AAA
AAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AAA
AAAAAAAAAAAAAAA
Valid
Data In
tDH
tDH
AAAA
AAAA
A
AAAA
AAAA
A
AAAA
AAAA
A
AAAA
AAAA
AAAAAAAAA
A
AAAAAAAAA
Valid
Data In
tDS
AAAA
AAAA
AAA
AAAA
AAAA
AAA
AAAA
AAAA
AAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAAAAAAAAA
AAA
AAAAAAAAAAA
Valid
Data In
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAAAAAAAAAAAAAAAAA
AAA
AAAAAAAAAAAAAAAAAAAAAAA
V
OH
I/O
(Outputs) V
HI-Z
OL
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAAAAAA
AAA
“H” or “L”
FPM2
Fast Page Mode Early Write Cycle
Semiconductor Group
18
19
Data
Out
tDS
tDH
tOEZ
tCAC
tDS
tDH
Data
Out
tOEZ
Data
Out
tDS
AAAA
AA
AAAA
AAAAAA
AA
“H” or “L”
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAAAAA
V
OH
I/O
(Outputs) V
IH
I/O
(Inputs) V IL
tRAC
tDZC
tCLZ
tDZO
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AAAAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
AA
AAAA
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Data In
tODD
tWP
tOEA
tWP
tCWL
tAWD
tCPWD
tCWD
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tRWD
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Fast Page Mode Read-Modify-Write Cycle
Semiconductor Group
AAAA
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HYB3164(5)800AJ/AT(L)-40/-50/-60
8M x 8-DRAM
HYB3164(5)800AJ/AT(L)-40/-50/-60
8M x 8-DRAM
tRC
tRAS
tRP
V
IH
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VIL
tCRP
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OH
I/O
(Outputs) V
HI-Z
OL
AAAA
AAAAAAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAA
AAAA
“H” or “L”
WL9
RAS-Only Refresh Cycle
Semiconductor Group
20
Row
HYB3164(5)800AJ/AT(L)-40/-50/-60
8M x 8-DRAM
tRC
tRP
V
RAS
tRAS
IH
VIL
tRPC
tCSR
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V
CAS
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I/O
(Inputs) V
IL
tODD
V
OH
I/O
(Outputs)VOL
HI-Z
tOFF
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAAAAAA
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AAAAAAAA
AAAA
“H” or “L”
WL10
CAS-Before-RAS Refresh Cycle
Semiconductor Group
21
HYB3164(5)800AJ/AT(L)-40/-50/-60
8M x 8-DRAM
tRC
tRC
RAS
tRP
tRAS
V
tRP
tRAS
IH
VIL
tRSH
tRCD
tCRP
tCHR
V
CAS
IH
tRAD
VIL
tWRP
tASC
tASR
Address
V AAAAAAA
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tCDD
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V
I/O
(Inputs)
IH
VIL
AAAA
AAAA
AAAA
AAAA
AA
AAAA
AAAA
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AAAA
AAAA
AAAA
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tOFF
tCLZ
tOEZ
tRAC
V
AAAA
A
AAAA
A
AAAA
A
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A
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A
OH
I/O
(Outputs) V
OL
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAAAAAA
AAA
Valid Data Out
“H” or “L”
HI-Z
WL11
Hidden Refresh Cycle (Read)
Semiconductor Group
AAAA
AAAA
AAAA
AAAA
A
AAAA
AAAA
AAAA
AAAA
A
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A
22
HYB3164(5)800AJ/AT(L)-40/-50/-60
8M x 8-DRAM
tRC
tRC
tRP
tRAS
V
RAS
IH
tRAS
tRP
VIL
tRCD
tRSH
tCHR
tCRP
V
CAS
IH
VIL
tRAD
tRAH
tASC
tCAH
tASR
Address
V AAAAAAA
IHAAAAAAA
AAAAAAA
Row
AAAAAAA
VIL AAAA
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tDS
I/O
(Input)
tASR
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Valid Data
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OH
I/O
(Output) V
OL
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AAAA
HI-Z
“H” or “L”
WL12
Hidden Refresh Cycle (Early Write)
Semiconductor Group
Row
23
HYB3164(5)800AJ/AT(L)-40/-50/-60
8M x 8-DRAM
tRC
tRP
V
RAS
tRAS
tRP
IH
VIL
tRPC
tCSR
tCP
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V
CAS
tCRP
AAAAAAAA
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VIL
tODD
V
IH
I/O
(Inputs) V
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AAA
HI-Z
tCDD
tOEZ
V AAAAAAAAAAAAAAAAAAAAAAA
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OHAAA
I/O
(Outputs) V
OL
AAA
AAAA
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AAAAAAAA
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AAAA
AAAA
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HI-Z
tOFF
“H” or “L”
WL15
Test Mode Entry Cycle
Semiconductor Group
24
HYB3164(5)800AJ/AT(L)-40/-50/-60
8M x 8-DRAM
tRP
V
RAS
tRASS
tRPS
IH
VIL
tRPC
tCP
V
CAS
tCRP
tCHS
tCSR
AAAA
AAAA
A
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A
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AA
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AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AA
IH
VIL
tCDD
V
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tODD
IH
I/O
(Inputs) V
IL
tOEZ
V
OH
I/O
(Outputs) VOL
HI-Z
tOFF
AAAA
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“H” or “L”
WL13
Self Refresh („Sleep Mode“) L-version only
Semiconductor Group
25
HYB3164(5)800AJ/AT(L)-40/-50/-60
8M x 8-DRAM
Package Outlines
Plastic Package P-SOJ-32-1 (400 mil)
(Small Outline J-lead, SMD)
Plastic Package P-TSOPII-32-1 (400 mil)
(Small Outline J-lead, SMD)
Semiconductor Group
26