Cypress CY2XF24 High performance lvpecl oscillator with frequency margining â i2c control Datasheet

CY2XF24
High Performance LVPECL Oscillator with
Frequency Margining – I2C Control
Features
Functional Description
■
Low jitter crystal oscillator (XO)
■
Less than 1 ps typical root mean square (RMS) phase jitter
■
Differential low-voltage positive emitter coupled logic
(LVPECL) output
The CY2XF24 is a high-performance and high-frequency XO. It
uses a Cypress-proprietary low-noise PLL to synthesize the
frequency from an integrated crystal. The output frequency can
be changed using the I2C bus serial interface, allowing easy
frequency margin testing in applications.
■
Output frequency from 50 MHz to 690 MHz
■
Frequency margining through I2C bus
■
Factory-configured or field-programmable
■
Integrated phase-locked loop (PLL)
■
Pb-free package: 5.0 × 3.2 mm leadless chip carrier (LCC)
■
Supply voltage: 3.3 V or 2.5 V
■
Commercial and industrial temperature ranges
The CY2XF24 is available as a factory-configured device or as
a field-programmable device. Factory-configured devices are
configured for general use (see Standard and Application-Specific Factory Configurations) or they can be customer
specific.
Logic Block Diagram
4
CRYSTAL
OSCILLATOR
LOW-NOISE
PLL
CLK
OUTPUT
DIVIDER
5
CLK#
PROGRAMMABLE
CONFIGURATION
1
SDA
I 2C
INTERFACE
2
SCL
Cypress Semiconductor Corporation
Document Number: 001-53146 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 6, 2011
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CY2XF24
Pinouts
Figure 1. Pin Diagram – 6 Pin Ceramic LCC
SDA 1
SCLK 2
VSS 3
6 VDD
5 CLK#
4 CLK
Table 1. Pin Definitions
Name
I/O Type
1
Pin
SDA
I/O
I2C serial data
2
SCLK
CMOS input
I2C serial clock
CLK, CLK#
LVPECL output
6
VDD
Power
Supply voltage: 2.5 V or 3.3 V
3
VSS
Power
Ground
4, 5
Document Number: 001-53146 Rev. *E
Description
Differential output clock
Page 2 of 17
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CY2XF24
Contents
Standard and Application-Specific
Factory Configurations .................................................... 4
Functional Description ..................................................... 4
Configuration Software .................................................... 4
Programming Description ............................................... 4
Field-Programmable CY2XF24F ................................. 4
Factory-Configured CY2XF24 ..................................... 5
Programming Variables ................................................... 5
Output Frequencies ..................................................... 5
Industrial versus Commercial Device Performance .... 5
Memory Map ...................................................................... 5
Serial Interface Protocol and Timing ........................... 5
Device Address ........................................................... 5
Data Valid .................................................................... 5
Data Frame ................................................................. 5
Acknowledge Pulse ..................................................... 5
Write Operations ............................................................... 6
Writing Individual Bytes ............................................... 6
Writing Multiple Bytes .................................................. 6
Read Operations ............................................................... 6
Current Address Read ................................................. 6
Document Number: 001-53146 Rev. *E
Random Read ............................................................. 6
Sequential Read .......................................................... 6
Absolute Maximum Conditions ....................................... 8
Operating Conditions ....................................................... 8
DC Electrical Characteristics .......................................... 8
AC Electrical Characteristics ........................................... 9
I2C Bus Timing Specifications ...................................... 10
Typical Output Characteristics ..................................... 10
Measurement Definitions ............................................... 12
Termination Circuits ....................................................... 12
Ordering Information ...................................................... 13
Possible Configurations ............................................. 13
Package Drawings and Dimensions ............................. 14
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC Solutions ......................................................... 17
Page 3 of 17
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CY2XF24
Standard and Application-Specific Factory Configurations
Part Number
CY2XF24LXI625T
Output Frequency
Frequency Word
78.125 MHz
156.25 MHz
312.50 MHz
625.00 MHz (default)
0
1
2
3
Functional Description
RMS Phase Jitter (Random)
Offset Range
Jitter (Typical)
1.875 MHz to 20 MHz
1.875 MHz to 20 MHz
1.875 MHz to 20 MHz
1.875 MHz to 20 MHz
0.37 ps
0.31 ps
0.29 ps
0.31 ps
Figure 2. Frequency Words
The CY2XF24 is a PLL-based high-performance clock
generator. It uses an internal crystal oscillator as a reference,
and outputs one differential LVPECL clock. It has an I2C bus
serial interface[1], which is used to change the output frequency.
The CY2XF24 comes configured for four different frequencies.
At power-on, the four configurations are transparently loaded
into an internal volatile memory which, in turn, controls the PLL.
You can switch between the four frequencies through the I2C
bus. You can also configure the CY2XF24 with new output
frequencies by shifting new data into the internal memory.
Frequency margining is a common application for this feature.
One frequency is used for the standard operating mode of the
device, while additional frequencies are available for margin
testing, either during product development or in-system
manufacturing test.
Note that all configuration changes made using I2C are
temporary and are lost when power is removed from the device.
At power-on, the device returns to its original state.
The configuration for a particular frequency is stored in a 6-byte
block of memory, known as a word. The CY2XF24 has four such
words, labeled ‘Frequency Word 0’ through ‘Frequency Word 3’.
An additional register byte contains a 2-bit field, which selects
one of the four frequency words. By writing to this Select Byte,
you can switch back and forth between the four programmed
frequencies. The select byte can be configured to select any of
the four frequency words at power on.
When changing the output frequency, the frequency transition is
not guaranteed to be smooth. There can be frequency
excursions beyond the start frequency and the new frequency.
Glitches and runt pulses are possible, and time must be allowed
for the PLL to relock.
I2
If more than four frequencies are needed, the C Bus can be
used to change any of the four frequency words. When writing
frequency words through I2C, you should not change the
currently selected word. Instead, write one of the three
unselected words before changing the select byte to select that
new word.
Figure 2 shows how the frequency words are arranged and
selected.
Register
Address
10h – 15h
Frequency Word 0
00
16h – 1Bh
Frequency Word 1
01
1Ch – 21h
Frequency Word 2
10
22h – 27h
Frequency Word 3
Control
PLL
11
Sel
40h
Select Byte
Bits [1:0]
Configuration Software
Cypress provides CyClockWizard™ software that enables users
to create data values for shifting into the frequency words. This
software is required because the algorithm is too complicated to
be described here.
The user specifies the output frequency. The software then
calculates the bit stream for up to four frequency words, as
outlined by the register addresses for each word seen in
Figure 2.
Programming Description
The CY2XF24 is a programmable device. Before being used in
an application, it must be programmed with the output
frequencies and other variables described in Programming
Variables on page 5. Two different device types are available,
each with its own programming flow. They are described in the
following section.
Field-Programmable CY2XF24F
Field programmable devices are shipped unprogrammed and
must be programmed before being installed on a printed circuit
board (PCB). Customers use CyClockWizard™ Software to
specify the device configuration and generate a joint electron
devices engineering council (JEDEC - extension .jed)
programming file. Programming of samples and prototype
quantities is available using the CyClockWizard software along
with a CY3675-CLKMAKER1 CyClockMaker Clock Programmer
Kit with a CY3675-LCC6A socket adapter. Cypress’s value
added distribution partners also provide programming services.
Field programmable devices are designated with an ‘F’ in the
part number. They are intended for quick prototyping and
inventory reduction. The software and programmer kit hardware
can be downloaded from www.cypress.com by clicking the
hyperlinks above.
Note
1. The serial interface is I2C Bus compliant, with the following exceptions: SDA input leakage current, SDA input capacitance, SDA and SCLK are clamped
to VDD, setup time, and output hold time.
Document Number: 001-53146 Rev. *E
Page 4 of 17
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CY2XF24
Factory-Configured CY2XF24
For ready-to-use devices, the CY2XF24 is available with no field
programming required. Pre-configured devices (see Standard
and Application-Specific Factory Configurations) are available
for samples or orders, or a request for a custom configuration
can be made. All requests are submitted to the local Cypress
field application engineer (FAE) or sales representative. After the
request is processed, the user receives a new part number,
samples, and datasheet with the programmed values. This part
number is used for additional sample requests and production
orders. The CY2XF24 is one-time programmable (OTP).
Table 3. Frequency Words
Frequency
Word
0
1
2
3
Programming Variables
Output Frequencies
7:2
1:0
The CY2XF24 has an output frequency range of 50 MHz to
690 MHz, but the range is not continuous. The CY2XF24 cannot
generate frequencies in the ranges of 521 MHz to 529 MHz, and
596 MHz to 617 MHz.
Industrial versus Commercial Device Performance
Industrial and commercial devices have different internal
crystals. They have a potentially significant impact on
performance levels for applications requiring the lowest possible
phase noise. CyClockWIzard software allows the user to select
between and view the expected performance of both options.
Table 2. Device Programming Variables
Variable
Word Select
(Select Byte 40h)
00
01
10
11
Table 4. Register 40h: Select Byte
Bits
The CY2XF24 is programmed with up to four independent output
frequencies, which are then selected using the I2C interface. The
device can synthesize frequencies to a resolution of 1 part per
million (ppm), but the actual accuracy of the output frequency is
limited by the accuracy of the integrated reference crystal.
Byte Addresses
(hex)
10h to 15h
16h to 1Bh
1Ch to 21h
22h to 27h
Default
Value
Name
Description
(binary)
000000 Reserved Reserved. Always write this value
UserWord
Selects the Frequency Word to
defined Select
determine the output frequency.
00 selects Word 0; 01 selects
Word 1; 10 selects Word 2; 11
selects Word 3
Serial Interface Protocol and Timing
The CY2XF24 uses pins SDA and SCLK for an I2C bus that
operates up to 100 kbits/sec in read or write mode. The
CY2XF24 is always a slave on this bus, meaning that it never
initiates a bus transaction. The basic write protocol is as follows:
Start Bit; 7-bit Device Address (DA); R/W Bit; Slave Clock
Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit
Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in
MA+2; ACK; etc. until STOP Bit. The basic serial format is illustrated in Figure 4 on page 7.
Device Address
The device address is a 7-bit value. The default serial interface
address is 69H.
Output frequency 0
Output frequency 1
Output frequency 2
Output frequency 3
Temperature range (commercial or industrial)
Memory Map
Five fields can be written through the I2C bus. Four frequency
words define the output frequency. As shown in Table 3, each of
these words is a 6-byte field. When writing to a frequency word,
all six bytes should be written. They may be written either as
individual byte writes, or as a block write. The currently selected
frequency word should not be written to. All four words are
symmetrical, meaning that a 6-byte value that is valid for one
word is also valid for any of the other words, and produce the
same frequency.
The fifth field is the select byte, located at byte address 40h. The
value written into the two least significant bits determines the
active frequency word. The other bits of the byte are reserved
and must be written with the values indicated in the table.
Users should never write to any address other than the 25 bytes
described here.
Document Number: 001-53146 Rev. *E
Data Valid
Data is valid when the clock is HIGH, and may only be transitioned when the clock is LOW as illustrated in Figure 5 on page 7.
Data Frame
Every new data frame is indicated by a start and stop sequence,
as illustrated in Figure 6 on page 7.
START sequence - Start frame is indicated by SDA going LOW
when SCLK is HIGH. Every time a start signal is given, the next
8-bit data must be the device address (seven bits) and a R/W bit,
followed by register address (eight bits) and register data (eight
bits).
STOP sequence - Stop frame is indicated by SDA going HIGH
when SCLK is HIGH. A stop frame frees the bus for writing to
another part on the same bus or writing to another random
register address.
Acknowledge Pulse
During write mode, the CY2XF24 responds with an
Acknowledge (ACK) pulse after every eight bits. This is
accomplished by pulling the SDA line LOW during the N*9th clock
cycle as illustrated in Figure 7 on page 8. (N = the number of
bytes transmitted). After the data packet is sent during read
mode, the master generates the acknowledge.
Page 5 of 17
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CY2XF24
Write Operations
Random Read
Writing Individual Bytes
A valid write operation must have a full 8-bit register address
after the device address word from the master, which is followed
by an acknowledge bit from the slave (SDA = 0/LOW). The next
eight bits must contain the data word intended for storage. After
the data word is received, the slave responds with another
acknowledge bit (SDA = 0/LOW), and the master must end the
write sequence with a STOP condition.
Writing Multiple Bytes
To write more than one byte at a time, the master does not end
the write sequence with a stop condition. Instead, the master can
send multiple contiguous bytes of data to be stored. After each
byte, the slave responds with an acknowledge bit, just like after
the first byte, and accept data until the acknowledge bit is
responded to by the STOP condition. When receiving multiple
bytes, the CY2XF24 internally increments the register address.
Read Operations
Read operations are initiated the same way as write operations
except that the R/W bit of the slave address is set to ‘1’ (HIGH).
There are three basic read operations: current address read,
random read, and sequential read.
Through random read operations, the master may access any
memory location. To perform this type of read operation, first the
word address must be set. This is accomplished by sending the
address to the CY2XF24 as part of a write operation. After the
word address is sent, the master generates a START condition
following the acknowledge. This terminates the write operation
before any data is stored in the address, but not before the
internal address pointer is set. Next the master reissues the
control byte with the R/W byte set to ‘1’. The CY2XF24 then
issues an acknowledge and transmits the 8-bit word. The master
device does not acknowledge the transfer, but does generate a
STOP condition which causes the CY2XF24 to stop transmission.
Sequential Read
Sequential read operations follow the same process as random
reads except that the master issues an acknowledge instead of
a STOP condition after transmission of the first 8-bit data word.
This action results in an incrementing of the internal address
pointer, and subsequently output of the next 8-bit data word. By
continuing to issue acknowledges instead of STOP conditions,
the master may serially read the entire contents of the slave
device memory. When the internal address pointer points to the
FFh register, after the next increment, the pointer points to the
00h register.
Current Address Read
The CY2XF24 has an onboard address counter that retains 1
more than the address of the last word access. If the last word
written or read was word ‘n’, then a current address read
operation would return the value stored in location ‘n+1’. When
the CY2XF24 receives the slave address with the R/W bit set to
a ‘1’, the CY2XF24 issues an acknowledge and transmits the
8-bit word. The master device does not acknowledge the
transfer, but does generate a STOP condition, which causes the
CY2XF24 to stop transmission.
Figure 3. Data Transfer Sequence on the Serial Bus
SCLK
SDA
START
Condition
Address or
Acknowledge
Valid
Document Number: 001-53146 Rev. *E
Data may
be changed
STOP
Condition
Page 6 of 17
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CY2XF24
Figure 4. Data Frame Architecture
SDA Write
Multiple
Contiguous
Registers
1 Bit
Slave
ACK
1 Bit
1 Bit Slave
ACK
R/W = 0
7-bit
Device
Address
8-bit
Register
Address
(XXH)
1 Bit
Slave
ACK
8-bit
Register
Data
(XXH)
1 Bit
Slave
ACK
8-bit
Register
Data
(XXH+1)
1 Bit
Slave
ACK
8-bit
Register
Data
(XXH+2)
1 Bit
Slave
ACK
8-bit
Register
Data
(FFH)
1 Bit
Slave
ACK
1 Bit
Slave
ACK
8-bit
Register
Data
(00H)
Stop Signal
Start Signal
SDA Read
Current
Address
Read Start Signal
SDA Read
Multiple
Contiguous
Registers
1 Bit
Slave
ACK
1 Bit
1 Bit Slave
R/W = 1 ACK
7-bit
Device
Address
1 Bit
Master
ACK
8-bit
Register
Data
Stop Signal
1 Bit
Slave
ACK
1 Bit
1 Bit Slave
R/W = 0 ACK
7-bit
Device
Address
8-bit
Register
Address
(XXH)
1 Bit
Master
ACK
7-bit
Device
Address
+R/W=1
1 Bit
Master
ACK
8-bit
Register
Data
(XXH)
1 Bit
Master
ACK
8-bit
Register
Data
(XXH+1)
1 Bit
Master
ACK
8-bit
Register
Data
(FFH)
1 Bit
Master
ACK
1 Bit
Master
ACK
8-bit
Register
Data
(00H)
Stop Signal
Start Signal
Repeated
Start bit
Figure 5. Data Valid and Data Transition Periods
Data Valid
Transition
to next Bit
SDA
tDH
tSU
CLKHIGH
VIH
SCLK
VIL
CLKLOW
Figure 6. Start and Stop Frame
SDA
START
Document Number: 001-53146 Rev. *E
Transition
to next Bit
SCLK
STOP
Page 7 of 17
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CY2XF24
Figure 7. Frame Format (Device Address, R/W, Register Address, Register Data)
SDA
+
START
DA6
DA5 DA0
+
R/W
ACK
RA7
+
RA6 RA1
RA0
ACK
D7
D6
+
+
D1
D0
ACK
STOP
+
SCLK
Absolute Maximum Conditions
Parameter
Description
Condition
Min
Max
Unit
–0.5
4.4
V
Relative to VSS
–0.5
VDD+0.5
V
Non Operating
–55
135
°C
–40
135
°C
2000
–
V
VDD
Supply voltage
VIN[2]
Input voltage, DC
TS
Temperature, storage
TJ
Temperature, junction
ESDHBM
Electrostatic discharge (ESD) protection
human body model (HBM)
JEDEC STD 22-A114-B
ΘJA[3]
Thermal resistance, junction to ambient
0 m/s airflow
64
°C/W
Operating Conditions
Parameter
VDD
Min
Typ
Max
Unit
3.3-V supply voltage range
Description
3.135
3.3
3.465
V
2.5-V supply voltage range
2.375
2.5
2.625
V
TPU
Power-up time for VDD to reach minimum specified voltage (power ramp is
monotonic)
0.05
–
500
ms
TA
Ambient temperature (commercial)
0
–
70
°C
–40
–
85
°C
Condition
Min
Typ
Max
Unit
VDD = 3.465 V, CLK = 150 MHz, output
terminated
–
–
150
mA
VDD = 2.625 V, CLK = 150 MHz, output
terminated
–
–
145
mA
Ambient temperature (industrial)
DC Electrical Characteristics
Parameter
IDD[4]
Description
Operating supply current
VOH
LVPECL high output voltage
VDD = 3.3 V or 2.5 V, RTERM = 50 Ω to VDD – 1.15
VDD – 2.0 V
–
VDD –
0.75
V
VOL
LVPECL low output voltage
VDD = 3.3 V or 2.5 V, RTERM = 50 Ω to
VDD – 2.0 V
VDD – 2.0
–
VDD –
1.625
V
VOD1
LVPECL output voltage swing
(VOH - VOL)
VDD = 3.3 V or 2.5 V, RTERM = 50 Ω to
VDD – 2.0 V
600
–
1000
mV
VOD2
LVPECL output voltage swing
(VOH - VOL)
VDD = 2.5 V, RTERM = 50 Ω to VDD –
1.5 V
500
–
1000
mV
VOCM
LVPECL output common mode
voltage (VOH + VOL)/2
VDD = 2.5 V, RTERM = 50 Ω to VDD –
1.5 V
1.2
–
–
V
Notes
2. The voltage on any input or IO pin cannot exceed the power pin during power up.
3. Simulated. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers
are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.
4. IDD includes ~24 mA of current that is dissipated externally in the output termination resistors.
Document Number: 001-53146 Rev. *E
Page 8 of 17
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CY2XF24
DC Electrical Characteristics (continued)
Parameter
Description
Condition
Min
Typ
Max
Unit
–
–
0.1*VDD
V
0.7*VDD
–
–
V
–
–
0.3*VDD
V
–
–
115
μA
VOLS
Output low voltage (SDA)
VIH
Input high voltage
VIL
Input low voltage
IIH0
Input high current (SDA)
IIH1
Input high current (SCLK)
Input = VDD
–
–
10
μA
IIL0
Input low current (SDA)
Input = VSS
–50
–
–
μA
IIL1
Input low current (SCLK)
Input = VSS
–20
–
–
μA
CIN0[5]
Input capacitance (SDA)
–
15
–
pF
CIN1[5]
Input capacitance (SCLK)
–
4
–
pF
Min
Typ
Max
Unit
50
–
690
MHz
IOL = 4 mA
Input = VDD
AC Electrical Characteristics[5]
Parameter
Description
Condition
FOUT
Output frequency[6]
FSC
Frequency stability, commercial
devices[7]
TA = 0 °C to 70 °C
–
–
±35
ppm
FSI
Frequency stability, industrial
devices[7]
TA = –40 °C to 85 °C
–
–
±55
ppm
AG
Aging, 10 years
–
–
±15
ppm
TDC
Output duty cycle
F <= 450 MHz, measured at zero
crossing
45
50
55
%
F > 450 MHz, measured at zero
crossing
40
50
60
%
0.2
0.4
1.0
ns
TR, TF
Output rise and fall time
20% and 80% of full output swing
TLOCK
Startup time
Time for CLK to reach valid frequency
measured from the time VDD =
VDD(min)
–
–
10
ms
TLSER
Relock time
Time for CLK to reach valid frequency
from serial bus change to select bits in
register 40h, measured from I2C STOP
–
–
10
ms
TJitter(φ)
RMS phase jitter (random)
FOUT = 106.25 MHz (12 kHz to 20 MHz)
–
1
–
ps
Pre-defined factory configurations[8]
See Note 8
ps
Notes
5. Not 100% tested, guaranteed by design and characterization.
6. This parameter is specified in CyClockMaker software.
7. Frequency stability is the maximum variation in frequency from F0. It includes initial accuracy, plus variation from temperature and supply voltage.
8. Typical phase noise specs for factory programmed devices are listed in the Standard and Application-Specific Factory Configurations table on page 2.
Document Number: 001-53146 Rev. *E
Page 9 of 17
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CY2XF24
I2C Bus Timing Specifications
The I2C Bus Timing Specifications for part CY2XF24 are as follows [5]
Parameter
Description
fSCLK
SCLK frequency
tHD:STA
Start mode time from SDA LOW to SCLK LOW
tLOW
SCLK LOW period
tHIGH
SCLK HIGH period
tSU:DAT
Input data setup (SDA transition to SCLK rising edge)
tHD:DAT
Input data hold (SCLK falling edge to SDA transition)
tHD:DO
Output data hold (SCLK falling edge to SDA transition)
tSR
tSF
tSU:STO
Stop mode time from SCLK HIGH to SDA HIGH
tBUF
Stop mode to Start mode
Min
Max
Unit
–
100
kHz
4
–
μs
4.7
–
μs
4
–
μs
1000
–
ns
0
–
ns
200
–
ns
Rise time of SCLK and SDA
–
300
ns
Fall time of SCLK and SDA
–
300
ns
4
–
μs
4.7
–
μs
Typical Output Characteristics
Figure 8. 2.5-V Supply and Termination to VDD–1.5 V, minimum VDD and maximum TA
0.9
1.40
0.8
0.7
VOCM (V)
Swing (V)
1.35
0.6
1.30
1.25
0.5
1.20
0.4
0
100
200
300
400
Frequency (MHz)
Document Number: 001-53146 Rev. *E
500
600
700
0
100
200
300
400
500
600
700
Frequency (MHz)
Page 10 of 17
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CY2XF24
Figure 9. 2.5-V Supply and Termination to VDD–2 V, minimum VDD and maximum TA
0.9
0.90
0.8
0.7
VOCM (V)
Swing (V)
0.85
0.6
0.80
0.75
0.5
0.4
0.70
0
100
200
300
400
500
600
700
0
100
200
Frequency (MHz)
300
400
500
600
700
Frequency (MHz)
Figure 10. 3.3-V Supply and Termination to VDD–2 V, minimum VDD and maximum TA
0.9
1.60
0.8
0.7
VOCM (V)
Swing (V)
1.55
0.6
1.50
1.45
0.5
0.4
1.40
0
100
200
300
400
Frequency (MHz)
Document Number: 001-53146 Rev. *E
500
600
700
0
100
200
300
400
500
600
700
Frequency (MHz)
Page 11 of 17
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CY2XF24
Measurement Definitions
Figure 11. Output DC Parameters
VA
CLK
VOD
VOCM = (V A + VB)/2
CLK#
VB
Figure 12. Duty Cycle Timing
CLK
TDC =
TPW
TPERIOD
CLK#
TPW
TPERIOD
Figure 13. Output Rise and Fall Time
CLK#
CLK
80%
80%
20%
20%
TR
TF
Termination Circuits
Figure 14. LVPECL Termination
VDD - 2V
(VDD = 3.3V)
50Ω
50Ω
50Ω
50Ω
50Ω
CLK#
Document Number: 001-53146 Rev. *E
CLK
BUF
BUF
CLK
VDD - 2V or VDD - 1.5V
(VDD = 2.5V)
50Ω
50Ω
50Ω
CLK#
Page 12 of 17
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CY2XF24
Ordering Information
Part Number
Configuration
Package Description
Product Flow
Pb-free
CY2XF24FLXCT
CY2XF24FLXIT
[9]
CY2XF24LXI625T
Field-programmable
6-pin ceramic LCC surface mount device
(SMD) - tape and reel
Commercial, 0°C to 70°C
Field-programmable
6-pin ceramic LCC SMD - tape and reel
Industrial, –40°C to 85°C
Field-programmable
6-pin ceramic LCC SMD - tape and reel
Industrial, –40°C to 85°C
Some product offerings are factory-programmed customer-specific devices with customized part numbers. The Possible
Configurations table shows the available device types, but not complete part numbers. Contact your local Cypress FAE or sales
representative for more information.
Possible Configurations
Part Number[10]
Configuration
Package Description
Product Flow
Pb-free
CY2XF24LXCxxxT
Factory-configured
6-pin ceramic LCC SMD - tape and reel
Commercial, 0°C to 70°C
CY2XF24LXIxxxT
Factory-configured
6-pin ceramic LCC SMD - tape and reel
Industrial, –40°C to 85°C
Ordering Code Definitions
CY 2XF24 F LX C/I XXX T
Tape and Reel
Custom part configuration code
C = Commercial
I = Industrial
6-pin LCC package
Field programmable device
Base part number
Company ID : CY = Cypress
Notes
9. Device configuration details are described in the Standard and Application-Specific Factory Configurations table on page 2.
10. “xxx” indicates factory programmed parts based on customer specific configuration. For more details, contact your local Cypress FAE or Sales Representative.
Document Number: 001-53146 Rev. *E
Page 13 of 17
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CY2XF24
Package Drawings and Dimensions
Figure 15. 6-Pin 3.2 × 5.0 mm Ceramic LCC LZ06A
001-10044-*A
.
Document Number: 001-53146 Rev. *E
Page 14 of 17
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CY2XF24
Acronyms
Table 5. Acronyms Used in this Document
Acronym
Description
ESD
electrostatic discharge
FAE
field application engineer
HBM
human body model
JEDEC
joint electron devices engineering council
LCC
leadless chip carrier
LVDS
Low-voltage differential signaling
OE
output enable
PCB
printed circuit board
PLL
phase-locked loop
RMS
root mean square
XO
crystal oscillator
Document Conventions
Units of Measure
Symbol
Unit of Measure
°C
degree Celsius
µs
micro seconds
µA
micro Amperes
mA
milli Amperes
mm
milli meter
ms
milli seconds
mV
milli Volts
kHz
kilo Hertz
MHz
Mega Hertz
ns
nano seconds
pF
pico Farad
ps
pico seconds
ppm
parts per million
V
Volts
W
Watts
%
percent
Ω
ohms
Document Number: 001-53146 Rev. *E
Page 15 of 17
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CY2XF24
Document History Page
Document Title: CY2XF24 High Performance LVPECL Oscillator with Frequency Margining – I2C Control
Document Number: 001-53146
Revision
ECN
Orig. of
Change
Submission
Date
**
2704379
KVM/PYRS
05/11/09
*A
2718898
WWZ
06/15/09
Minor ECN to post datasheet to external web
*B
2761926
KVM
09/10/09
Revised maximum output rise and fall times
*C
2896548
KVM
03/19/10
Moved parts with ‘xxx’ into new table, Possible Configurations
Updated package diagram
*D
2973338
CXQ
07/08/10
Added Standard and Application-Specific Factory Configurations table on
page 2.
Added phase jitter specs for pre-defined configurations into the AC Electrical
Specifcations table (note 8 refers users to the new table on page 2 for typical
specs).
Added CY2XF24LXI625T device to the Ordering Information table and added
note 9 to reference the configuration description of the new device.
Changed all references to CyberClocksOnline software to CyClockWizard.
Removed section on phase noise vs jitter SW optimization.
Changed description of Word Select feature from default Word 0 to
user-defined.
*E
3183855
BASH
05/06/11
Updated template as per current Cypress standards.
Added Units table.
Changed status from Preliminary to Final.
Document Number: 001-53146 Rev. *E
Description of Change
New datasheet
Page 16 of 17
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CY2XF24
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
PSoC
Touch Sensing
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
cypress.com/go/touch
USB Controllers
Wireless/RF
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-53146 Rev. *E
Revised May 6, 2011
Page 17 of 17
All products and company names mentioned in this document may be the trademarks of their respective holders.
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