ON NUP2114UCMR6T1G Transient voltage suppressor Datasheet

NUP2114 Series,
SNUP2114UCMR6T1G
Transient Voltage
Suppressors
Low Capacitance ESD Protection for
High Speed Data
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The NUP2114 transient voltage suppressor is designed to protect
high speed data lines from ESD. Ultra−low capacitance and high level
of ESD protection makes this device well suited for use in USB 2.0
applications.
Features
 Low Capacitance 0.8 pF
 S Prefix for Automotive and Other Applications Requiring Unique








Site and Control Change Requirements
AEC−Q101 Qualified and PPAP Capable − SNUP2114
Low Clamping Voltage
Stand Off Voltage: 5 V
Low Leakage
ESD Rating of Class 3B (Exceeding 8 kV) per Human Body model
and Class C (Exceeding 400 V) per Machine Model
Protection for the Following IEC Standards:
IEC 61000−4−2 Level 4 ESD Protection
UL Flammability Rating of 94 V−0
These are Pb−Free Devices
Typical Applications







VP
I/O
I/O
VN
MARKING DIAGRAMS
1
1
PIN CONNECTIONS
VP 1
Symbol
Value
Unit
VN 2
Operating Junction Temperature Range
TJ
−40 to +125
C
NC 3
Storage Temperature Range
Tstg
−55 to +150
C
Lead Solder Temperature −
Maximum (10 Seconds)
TL
260
C
Human Body Model (HBM)
Machine Model (MM)
IEC 61000−4−2 Contact
IEC61000−4−2 Air
ESD
16000
400
8000
15000
V
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
5 I/O
4 I/O
SOT−553
I/O 1
6 I/O
VN 2
5 VP
NC 3
4 NC
TSOP−6
ORDERING INFORMATION
See Application Note AND8308/D for further description of
survivability specs.
March, 2012 − Rev. 1
TSOP−6
P2, P2M = Specific Device Code
M
= Date Code
G
= Pb−Free Package
(*Note: Microdot may be in either location)
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
 Semiconductor Components Industries, LLC, 2012
P2M MG
G
P2MG
G
SOT−553
High Speed Communication Line Protection
USB 2.0 High Speed Data Line and Power Line Protection
Monitors and Flat Panel Displays
MP3
Gigabit Ethernet
Notebook Computers
Digital Video Interface (DVI) and HDMI
Rating
TSOP−6
CASE 318G
SOT−553
CASE 463B
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
1
Publication Order Number:
NUP2114/D
NUP2114 Series, SNUP2114UCMR6T1G
ELECTRICAL CHARACTERISTICS
I
(TA = 25C unless otherwise noted)
IF
Parameter
Symbol
IPP
Maximum Reverse Peak Pulse Current
VC
Clamping Voltage @ IPP
VRWM
IR
VBR
Working Peak Reverse Voltage
Test Current
IF
Forward Current
VF
Forward Voltage @ IF
Ppk
Peak Power Dissipation
V
IR VF
IT
Breakdown Voltage @ IT
IT
C
VC VBR VRWM
Maximum Reverse Leakage Current @ VRWM
IPP
Max. Capacitance @ VR = 0 and f = 1.0 MHz
Uni−Directional TVS
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
ELECTRICAL CHARACTERISTICS (TJ=25C unless otherwise specified)
Parameter
Reverse Working Voltage
Breakdown Voltage
Symbol
VRWM
VBR
Conditions
Min
Typ
(Note 1)
IT = 1 mA, (Note 2)
5.5
Max
Unit
5.0
V
7.5
V
Reverse Leakage Current
IR
VRWM = 5 V
Clamping Voltage
VC
IPP = 5 A (Note 3)
9.0
1.0
V
Clamping Voltage
VC
IPP = 8 A (Note 3)
10
V
Maximum Peak Pulse Current
IPP
8x20 ms Waveform
Junction Capacitance
CJ
VR = 0 V, f = 1 MHz between I/O Pins and GND
Junction Capacitance
CJ
VR = 0 V, f = 1 MHz between I/O Pins
Clamping Voltage
VC
@ IPP = 1 A (Note 4)
Clamping Voltage
VC
Per IEC 61000−4−2 (Note 5)
0.8
mA
12
A
1.0
pF
0.5
pF
12
V
Figures 1 and 2
V
1. TVS devices are normally selected according to the working peak reverse voltage (VRWM), which should be equal or greater than the DC
or continuous peak operating voltage level.
2. VBR is measured at pulse test current IT.
3. Nonrepetitive current pulse (Pin 5 to Pin 2)
4. Surge current waveform per Figure 5.
5. Typical waveform. For test procedure see Figures 3 and 4 and Application Note AND8307/D.
6. Include S-prefix devices where applicable.
Figure 1. ESD Clamping Voltage Screenshot
Positive 8 kV Contact per IEC61000−4−2
Figure 2. ESD Clamping Voltage Screenshot
Negative 8 kV Contact per IEC61000−4−2
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2
NUP2114 Series, SNUP2114UCMR6T1G
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
Ipeak
Level
Test
Voltage
(kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1
2
7.5
4
2
2
4
15
8
4
3
6
22.5
12
6
4
8
30
16
8
100%
90%
I @ 30 ns
I @ 60 ns
10%
tP = 0.7 ns to 1 ns
Figure 3. IEC61000−4−2 Spec
ESD Gun
Oscilloscope
TVS
50 W
Cable
50 W
Figure 4. Diagram of ESD Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
% OF PEAK PULSE CURRENT
100
PEAK VALUE IRSM @ 8 ms
tr
90
PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
80
70
60
HALF VALUE IRSM/2 @ 20 ms
50
40
30
tP
20
10
0
0
20
40
t, TIME (ms)
60
Figure 5. 8 X 20 ms Pulse Waveform
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3
80
NUP2114 Series, SNUP2114UCMR6T1G
Figure 6. 500 MHz Data Pattern
ORDERING INFORMATION
Marking
Package
Shipping†
NUP2114UPXV5T1G
P2
SOT−553
(Pb−Free)
4,000 / Tape & Reel
NUP2114UCMR6T1G
P2M
TSOP−6
(Pb−Free)
3,000 / Tape & Reel
SNUP2114UCMR6T1G
P2M
TSOP−6
(Pb−Free)
3,000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
NUP2114 Series, SNUP2114UCMR6T1G
PACKAGE DIMENSIONS
TSOP−6
CASE 318G−02
ISSUE U
D
H
ÉÉÉ
ÉÉÉ
6
E1
1
NOTE 5
5
2
L2
4
GAUGE
PLANE
E
3
L
b
A1
C
DETAIL Z
e
0.05
M
A
SEATING
PLANE
c
DETAIL Z
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM
LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D
AND E1 ARE DETERMINED AT DATUM H.
5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.
DIM
A
A1
b
c
D
E
E1
e
L
L2
M
MIN
0.90
0.01
0.25
0.10
2.90
2.50
1.30
0.85
0.20
0
MILLIMETERS
NOM
MAX
1.00
1.10
0.06
0.10
0.38
0.50
0.18
0.26
3.00
3.10
2.75
3.00
1.50
1.70
0.95
1.05
0.40
0.60
0.25 BSC
10
−
RECOMMENDED
SOLDERING FOOTPRINT*
6X
0.60
6X
3.20
0.95
0.95
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
5
NUP2114 Series, SNUP2114UCMR6T1G
PACKAGE DIMENSIONS
SOT−553, 6 LEAD
CASE 463B−01
ISSUE B
D
−X−
5
A
4
1
e
2
E
−Y−
3
b
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
L
HE
DIM
A
b
c
D
E
e
L
HE
c
5 PL
0.08 (0.003)
M
X Y
MILLIMETERS
NOM
MAX
0.55
0.60
0.22
0.27
0.13
0.18
1.60
1.70
1.20
1.30
0.50 BSC
0.10
0.20
0.30
1.50
1.60
1.70
MIN
0.50
0.17
0.08
1.50
1.10
INCHES
NOM
0.022
0.009
0.005
0.063
0.047
0.020 BSC
0.008
0.004
0.059
0.063
MIN
0.020
0.007
0.003
0.059
0.043
MAX
0.024
0.011
0.007
0.067
0.051
0.012
0.067
SOLDERING FOOTPRINT*
0.3
0.0118
0.45
0.0177
1.35
0.0531
1.0
0.0394
0.5
0.5
0.0197 0.0197
SCALE 20:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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