Intel GT28F016B3B90 Smart 3 advanced boot block 4-, 8-, 16-, 32-mbit flash memory family Datasheet

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PRELIMINARY
SMART 3 ADVANCED BOOT BLOCK
4-, 8-, 16-, 32-MBIT
FLASH MEMORY FAMILY
28F400B3, 28F800B3, 28F160B3, 28F320B3
28F008B3, 28F016B3, 28F032B3
n
n
n
n
n
n
n
n
Flexible SmartVoltage Technology
 2.7 V–3.6 V Read/Program/Erase
 12 V VPP Fast Production
Programming
n
2.7 V or 1.65 V I/O Option
 Reduces Overall System Power
n
High Performance
 2.7 V–3.6 V: 90 ns Max Access Time
 3.0 V–3.6 V: 80 ns Max Access Time
n
Optimized Block Sizes
 Eight 8-KB Blocks for Data,
Top or Bottom Locations
 Up to Sixty-Three 64-KB Blocks for
Code
Block Locking
 VCC-Level Control through WP#
Low Power Consumption
 10 mA Typical Read Current
Absolute Hardware-Protection
 VPP = GND Option
 VCC Lockout Voltage
n
n
n
n
Flash Data Integrator Software
 Flash Memory Manager
 System Interrupt Manager
 Supports Parameter Storage,
Streaming Data (e.g., Voice)
Automated Program and Block Erase
 Status Registers
Extended Cycling Capability
 Minimum 100,000 Block Erase
Cycles Guaranteed
Automatic Power Savings Feature
 Typical ICCS after Bus Inactivity
Standard Surface Mount Packaging
 48-Ball µBGA* Package
 48-Lead TSOP Package
 40-Lead TSOP Package
Footprint Upgradeable
 Upgrade Path for 4-, 8-, 16-, and 32Mbit Densities
ETOX™ VI (0.25 µ) Flash Technology
Extended Temperature Operation
 –40 °C to +85 °C
The Smart 3 Advanced Boot Block, manufactured on Intel’s latest 0.25 µ technology, represents a featurerich solution at overall lower system cost. Smart 3 flash memory devices incorporate low voltage capability
(2.7 V read, program and erase) with high-speed, low-power operation. Several new features have been
added, including the ability to drive the I/O at 1.65 V, which significantly reduces system active power and
interfaces to 1.65 V controllers. A new blocking scheme enables code and data storage within a single
device. Add to this the Intel-developed Flash Data Integrator (FDI) software, and you have a cost-effective,
monolithic code plus data storage solution. Smart 3 Advanced Boot Block products will be available in 40lead and 48-lead TSOP and 48-ball µBGA* packages. Additional information on this product family can be
obtained by accessing Intel’s WWW page: http://www.intel.com/design/flash.
July 1998
Order Number: 290580-005
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F400B3, 28F800/008B3, 28F160/016B3, 38F320/032B3 may contain design defects or errors known as errata which
may cause the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call 1-800-548-4725
or visit Intel’s Website at http://www.intel.com
COPYRIGHT © INTEL CORPORATION 1996, 1997,1998
*Third-party brands and names are the property of their respective owners
CG-041493
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SMART 3 ADVANCED BOOT BLOCK
CONTENTS
PAGE
1.0 INTRODUCTION .............................................5
1.1 Smart 3 Advanced Boot Block Flash
Memory Enhancements ..............................5
1.2 Product Overview.........................................6
2.0 PRODUCT DESCRIPTION..............................6
2.1 Package Pinouts ..........................................6
2.2 Block Organization .....................................11
2.2.1 Parameter Blocks ................................11
2.2.2 Main Blocks .........................................11
3.0 PRINCIPLES OF OPERATION .....................11
3.1 Bus Operation ............................................12
3.1.1 Read....................................................13
3.1.2 Output Disable.....................................13
3.1.3 Standby ...............................................13
3.1.4 Deep Power-Down / Reset ..................13
3.1.5 Write....................................................13
3.2 Modes of Operation....................................14
3.2.1 Read Array ..........................................14
3.2.2 Read Identifier .....................................15
3.2.3 Read Status Register ..........................16
3.2.4 Program Mode.....................................16
3.2.5 Erase Mode .........................................17
3.3 Block Locking.............................................20
3.3.1 WP# = VIL for Block Locking................20
3.3.2 WP# = VIH for Block Unlocking ............20
3.4 VPP Program and Erase Voltages ..............20
3.4.1 VPP = VIL for Complete Protection .......20
PAGE
3.5 Power Consumption ...................................20
3.5.1 Active Power .......................................21
3.5.2 Automatic Power Savings (APS) .........21
3.5.3 Standby Power ....................................21
3.5.4 Deep Power-Down Mode.....................21
3.6 Power-Up/Down Operation.........................21
3.6.1 RP# Connected to System Reset ........21
3.6.2 VCC, VPP and RP# Transitions .............21
3.7 Power Supply Decoupling ..........................22
4.0 ELECTRICAL SPECIFICATIONS..................23
4.1 Absolute Maximum Ratings ........................23
4.2 Operating Conditions..................................24
4.3 Capacitance ...............................................24
4.4 DC Characteristics .....................................25
4.5 AC Characteristics—Read Operations .......28
4.6 AC Characteristics—Write Operations........30
4.7 Program and Erase Timings .......................31
5.0 RESET OPERATIONS ..................................33
6.0 ORDERING INFORMATION..........................34
7.0 ADDITIONAL INFORMATION .......................36
APPENDIX A: Write State Machine
Current/Next States.....................................37
APPENDIX B: Access Time vs.
Capacitive Load...........................................38
APPENDIX C: Architecture Block Diagram ......39
APPENDIX D: Word-Wide Memory Map
Diagrams......................................................40
APPENDIX E: Byte Wide Memory Map
Diagrams......................................................43
APPENDIX F: Program and Erase Flowcharts .45
PRELIMINARY
3
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SMART 3 ADVANCED BOOT BLOCK
REVISION HISTORY
Number
4
Description
-001
Original version
-002
Section 3.4, VPP Program and Erase Voltages, added
Updated Figure 9: Automated Block Erase Flowchart
Updated Figure 10: Erase Suspend/Resume Flowchart (added program to table)
Updated Figure 16: AC Waveform: Program and Erase Operations (updated notes)
IPPR maximum specification change from ±25 µA to ±50 µA
Program and Erase Suspend Latency specification change
Updated Appendix A: Ordering Information (included 8 M and 4 M information)
Updated Figure, Appendix D: Architecture Block Diagram (Block info. in words not
bytes)
Minor wording changes
-003
Combined byte-wide specification (previously 290605) with this document
Improved speed specification to 80 ns (3.0 V) and 90 ns (2.7 V)
Improved 1.8 V I/O option to minimum 1.65 V (Section 3.4)
Improved several DC characteristics (Section 4.4)
Improved several AC characteristics (Sections 4.5 and 4.6)
Combined 2.7 V and 1.8 V DC characteristics (Section 4.4)
Added 5 V VPP read specification (Section 3.4)
Removed 120 ns and 150 ns speed offerings
Moved Ordering Information from Appendix to Section 6.0; updated information
Moved Additional Information from Appendix to Section 7.0
Updated figure Appendix B, Access Time vs. Capacitive Load
Updated figure Appendix C, Architecture Block Diagram
Moved Program and Erase Flowcharts to Appendix E
Updated Program Flowchart
Updated Program Suspend/Resume Flowchart
Minor text edits throughout.
-004
Added 32-Mbit density
Added 98H as a reserved command (Table 4)
A1–A20 = 0 when in read identifier mode (Section 3.2.2)
Status register clarification for SR3 (Table 7)
VCC and VCCQ absolute maximum specification = 3.7 V (Section 4.1)
Combined IPPW and ICCW into one specification (Section 4.4)
Combined IPPE and ICCE into one specification (Section 4.4)
Max Parameter Block Erase Time (t WHQV2/tEHQV2) reduced to 4 sec (Section 4.7)
Max Main Block Erase Time (t WHQV3/tEHQV3) reduced to 5 sec (Section 4.7)
Erase suspend time @ 12 V (t WHRH2/tEHRH2) changed to 5 µs typical and 20 µs
maximum (Section 4.7)
Ordering Information updated (Section 6.0)
Write State Machine Current/Next States Table updated (Appendix A)
Program Suspend/Resume Flowchart updated (Appendix F)
Erase Suspend/Resume Flowchart updated (Appendix F)
Text clarifications throughout
-005
µBGA package diagrams corrected (Figures 3 and 4)
IPPD test conditions corrected (Section 4.4)
32-Mbit ordering information corrected (Section 6)
µBGA package top side mark information added (Section 6)
PRELIMINARY
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1.0
SMART 3 ADVANCED BOOT BLOCK
INTRODUCTION
1.1
This datasheet contains the specifications for the
Advanced Boot Block flash memory family, which is
optimized for low power, portable systems. This
family of products features 1.65 V–2.5 V or 2.7 V–
3.6 V I/Os and a low VCC/VPP operating range of
2.7 V–3.6 V for read, program, and erase
operations. In addition this family is capable of fast
programming at 12 V. Throughout this document,
the term “2.7 V” refers to the full voltage range
2.7 V–3.6 V (except where noted otherwise) and
“VPP = 12 V” refers to 12 V ±5%. Section 1.0 and
2.0 provide an overview of the flash memory family
including applications, pinouts and pin descriptions.
Section 3.0 describes the memory organization and
operation for these products. Sections 4.0 and 5.0
contain the operating specifications. Finally,
Sections 6.0 and 7.0 provide ordering and other
reference information.
Smart 3 Advanced Boot Block
Flash Memory Enhancements
The Smart 3 Advanced Boot Block flash memory
features
•
Enhanced blocking for easy segmentation of
code and data or additional design flexibility
•
Program Suspend to Read command
•
VCCQ input of 1.65 V–2.5 V on all I/Os. See
Figures 1 through 4 for pinout diagrams and
VCCQ location
•
Maximum program and erase time specification
for improved data storage.
Table 1. Smart 3 Advanced Boot Block Feature Summary
Feature
28F008B3, 28F016B3,
28F032B3(1)
28F400B3(2), 28F800B3,
28F160B3, 28F320B3
Reference
VCC Read Voltage
2.7 V– 3.6 V
Section 4.2, 4.4
VCCQ I/O Voltage
1.65 V–2.5 V or 2.7 V– 3.6 V
Section 4.2, 4.4
2.7 V– 3.6 V or 11.4 V– 12.6 V
Section 4.2, 4.4
VPP Program/Erase Voltage
Bus Width
Speed
Memory Arrangement
Blocking (top or bottom)
Locking
Operating Temperature
8-bit
80 ns, 90 ns, 100 ns, 110 ns
1024 Kbit x 8 (8 Mbit),
2048 Kbit x 8 (16 Mbit),
4096 Kbit x 8 (32 Mbit)
256 Kbit x 16 (4 Mbit),
512 Kbit x 16 (8 Mbit),
1024 Kbit x 16 (16 Mbit)
2048 Kbit x 16 (32 Mbit)
Table 3
Section 4.5
Section 2.2
Eight 8-Kbyte parameter blocks and
Seven 64-Kbyte blocks (4-Mbit) or
Fifteen 64-Kbyte blocks (8-Mbit) or
Thirty-one 64-Kbyte main blocks (16-Mbit)
Sixty-three 64-Kbyte main blocks (32-Mbit)
Section 2.2
Appendix D
WP# locks/unlocks parameter blocks
All other blocks protected using V PP
Section 3.3
Table 8
Extended: –40 °C to +85 °C
Section 4.2, 4.4
100,000 cycles
Section 4.2, 4.4
Program/Erase Cycling
Packages
16 bit
TSOP(1),
40-lead
48-Ball
µBGA* CSP(2)
48-Lead TSOP, 48-Ball
µBGA CSP(2)
Figure 3, Figure 4
NOTES:
1.
4-Mbit and 32-Mbit density not available in 40-lead TSOP.
2.
4-Mbit density not available in µBGA* CSP.
PRELIMINARY
5
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SMART 3 ADVANCED BOOT BLOCK
1.2
Product Overview
Intel provides the most flexible voltage solution in
the flash industry, providing three discrete voltage
supply pins: VCC for read operation, VCCQ for output
swing, and VPP for program and erase operation. All
Smart 3 Advanced Boot Block flash memory
products provide program/erase capability at 2.7 V
or 12 V [for fast production programming] and read
with VCC at 2.7 V. Since many designs read from
the flash memory a large percentage of the time,
2.7 V VCC operation can provide substantial power
savings.
The Smart 3 Advanced Boot Block flash memory
products are available in either x8 or x16 packages
in the following densities: (see Ordering Information
for availability.)
•
4-Mbit (4,194,304-bit) flash memory organized
as 256 Kwords of 16 bits each or 512 Kbytes of
8-bits each
•
8-Mbit (8,388,608-bit) flash memory organized
as 512 Kwords of 16 bits each or 1024 Kbytes
of 8-bits each
•
16-Mbit
(16,777,216-bit)
flash
memory
organized as 1024 Kwords of 16 bits each or
2048 Kbytes of 8-bits each
•
32-Mbit
(33,554,432-bit)
flash
memory
organized as 2048 Kwords of 16 bits each or
4096 Kbytes of 8-bits each
The parameter blocks are located at either the top
(denoted by -T suffix) or the bottom (-B suffix) of the
address map in order to accommodate different
microprocessor protocols for kernel code location.
The upper two (or lower two) parameter blocks can
be locked to provide complete code security for
system initialization code. Locking and unlocking is
controlled by WP# (see Section 3.3 for details).
6
The Command User Interface (CUI) serves as the
interface
between
the
microprocessor
or
microcontroller and the internal operation of the
flash memory. The internal Write State Machine
(WSM) automatically executes the algorithms and
timings necessary for program and erase
operations, including verification, thereby unburdening the microprocessor or microcontroller.
The status register indicates the status of the WSM
by signifying block erase or word program
completion and status.
The Smart 3 Advanced Boot Block flash memory is
also designed with an Automatic Power Savings
(APS) feature which minimizes system current
drain, allowing for very low power designs. This
mode is entered following the completion of a read
cycle (approximately 300 ns later).
The RP# pin provides additional protection against
unwanted command writes that may occur during
system reset and power-up/down sequences due to
invalid system bus conditions (see Section 3.6).
Section 3.0 gives detailed explanation of the
different modes of operation. Complete current and
voltage specifications can be found in the DC
Characteristics section. Refer to AC Characteristics
for read, program and erase performance
specifications.
2.0
PRODUCT DESCRIPTION
This section explains device pin description and
package pinouts.
2.1
Package Pinouts
The Smart 3 Advanced Boot Block flash memory is
available in 40-lead TSOP (x8, Figure 1), 48-lead
TSOP (x16, Figure 2) and 48-ball µBGA packages
(x8 and x16, Figure 3 and Figure 4 respectively). In
all figures, pin changes necessary for density
upgrades have been circled.
PRELIMINARY
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SMART 3 ADVANCED BOOT BLOCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A16
A15
A14
A13
A12
A11
A9
A8
WE#
RP#
VPP
WP#
A18
A7
A6
A5
A4
A3
A2
A1
Advanced Boot Block
40-Lead TSOP
10 mm x 20 mm
TOP VIEW
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A17
GND
A20
A19
A10
DQ7
DQ6
DQ5
DQ4
VCCQ
VCC
NC
DQ3
DQ2
DQ1
DQ0
OE#
GND
CE#
A0
16 M
8M
0580_01
NOTES:
1. 40-Lead TSOP available for 8- and 16-Mbit densities only.
2. Lower densities will have NC on the upper address pins. For example, an 8-Mbit device will have NC on Pin 38.
Figure 1. 40-Lead TSOP Package for x8 Configurations
32 M
16 M
8M
4M
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A15
A14
A13
A12
A11
A10
A9
A8
NC
A20
WE#
RP#
VPP
WP#
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
Advanced Boot Block
48-Lead TSOP
12 mm x 20 mm
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
VCCQ
GND
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
GND
CE#
A0
0580_02
NOTE:
Lower densities will have NC on the upper address pins. For example, an 8-Mbit device will have NC on Pins 9 and 15.
Figure 2. 48-Lead TSOP Package for x16 Configurations
PRELIMINARY
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SMART 3 ADVANCED BOOT BLOCK
1
2
3
4
5
6
7
8
A
A14
A12
A8
VPP
WP#
A20
A7
A4
B
A15
A10
WE#
RP#
A19
A18
A5
A2
C
A16
A13
A9
A21
A6
A3
A1
D
A17
NC
D5
NC
D2
NC
CE#
A0
E
VCCQ
A11
D6
NC
D3
NC
D0
GND
F
GND
D7
NC
D4
VCC
NC
D1
OE#
16M
8M
32M
0580_04
NOTE:
1.
Shaded connections indicate the upgrade address connections. Lower density devices will not have the upper address
solder balls. Routing is not recommended in this area. A20 is the upgrade address for the 16-Mbit device. A21 is the
upgrade address for the 32-Mbit device.
2.
4-Mbit density not available in µBGA* CSP.
Figure 3. x8 48-Ball µBGA* Chip Size Package (Top View, Ball Down)
8
PRELIMINARY
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SMART 3 ADVANCED BOOT BLOCK
1
2
3
4
5
6
7
8
A
A13
A11
A8
VPP
WP#
A19
A7
A4
B
A14
A10
WE#
RP#
A18
A17
A5
A2
C
A15
A12
A9
A20
A6
A3
A1
D
A16
D14
D5
D11
D2
D8
CE#
A0
E
VCCQ
D15
D6
D12
D3
D9
D0
GND
F
GND
D7
D13
D4
VCC
D10
D1
OE#
16M
8M
32M
0580_03
NOTES:
1.
Shaded connections indicate the upgrade address connections. Lower density devices will not have the upper address
solder balls. Routing is not recommended in this area. A19 is the upgrade address for the 16-Mbit device. A20 is the
upgrade address for the 32-Mbit device.
2.
4-Mbit density not available in µBGA* CSP.
Figure 4. x16 48-Ball µBGA* Chip Size Package (Top View, Ball Down)
PRELIMINARY
9
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SMART 3 ADVANCED BOOT BLOCK
The pin descriptions table details the usage of each device pin.
Table 2. Smart 3 Advanced Boot Block Pin Descriptions
Symbol
A0–A21
Type
INPUT
Name and Function
ADDRESS INPUTS for memory addresses. Addresses are internally
latched during a program or erase cycle.
28F008B3: A[0-19], 28F016B3: A[0-20], 28F032B3: A[0-21],
28F800B3: A[0-17], 28F800B3: A[0-18], 28F160B3: A[0-19],
28F320B3: A[0-20]
DQ0–DQ7
INPUT/OUTPUT
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and
WE# cycle during a Program command. Inputs commands to the
Command User Interface when CE# and WE# are active. Data is
internally latched. Outputs array, identifier and status register data. The
data pins float to tri-state when the chip is de-selected or the outputs are
disabled.
DQ8–DQ15
INPUT/OUTPUT
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and
WE# cycle during a Program command. Data is internally latched.
Outputs array and identifier data. The data pins float to tri-state when the
chip is de-selected. Not included on x8 products.
CE#
INPUT
CHIP ENABLE: Activates the internal control logic, input buffers,
decoders and sense amplifiers. CE# is active low. CE# high de-selects
the memory device and reduces power consumption to standby levels.
OE#
INPUT
OUTPUT ENABLE: Enables the device’s outputs through the data
buffers during a read operation. OE# is active low.
WE#
INPUT
WRITE ENABLE: Controls writes to the Command Register and memory
array. WE# is active low. Addresses and data are latched on the rising
edge of the second WE# pulse.
RP#
INPUT
RESET/DEEP POWER-DOWN: Uses two voltage levels (V IL, VIH) to
control reset/deep power-down mode.
When RP# is at logic low, the device is in reset/deep power-down
mode, which drives the outputs to High-Z, resets the Write State
Machine, and minimizes current levels (I CCD).
When RP# is at logic high, the device is in standard operation.
When RP# transitions from logic-low to logic-high, the device resets all
blocks to locked and defaults to the read array mode.
WP#
INPUT
WRITE PROTECT: Provides a method for locking and unlocking the two
lockable parameter blocks.
When WP# is at logic low, the lockable blocks are locked,
preventing program and erase operations to those blocks. If a program
or erase operation is attempted on a locked block, SR.1 and either SR.4
[program] or SR.5 [erase] will be set to indicate the operation failed.
When WP# is at logic high, the lockable blocks are unlocked and
can be programmed or erased.
See Section 3.3 for details on write protection.
10
PRELIMINARY
E
Symbol
VCCQ
SMART 3 ADVANCED BOOT BLOCK
Table 2. Smart 3 Advanced Boot Block Pin Descriptions (Continued)
Type
INPUT
Name and Function
OUTPUT VCC: Enables all outputs to be driven to 1.8 V – 2.5 V while
the VCC is at 2.7 V–3.3 V. If the V CC is regulated to 2.7 V–2.85 V, VCCQ
can be driven at 1.65 V–2.5 V to achieve lowest power operation (see
Section 4.4, DC Characteristics.
This input may be tied directly to V CC (2.7 V–3.6 V).
VCC
DEVICE POWER SUPPLY: 2.7 V–3.6 V
VPP
PROGRAM/ERASE POWER SUPPLY: Supplies power for program
and erase operations. VPP may be the same as V CC (2.7 V–3.6 V) for
single supply voltage operation. For fast programming at manufacturing,
11.4 V–12.6 V may be supplied to V PP. This pin cannot be left floating.
Applying 11.4 V–12.6 V to VPP can only be done for a maximum of 1000
cycles on the main blocks and 2500 cycles on the parameter blocks.
VPP may be connected to 12 V for a total of 80 hours maximum (see
Section 3.4 for details).
VPP < VPPLK protects memory contents against inadvertent or
unintended program and erase commands.
GND
GROUND: For all internal circuitry. All ground inputs must be
connected.
NC
NO CONNECT: Pin may be driven or left floating.
2.2
Block Organization
2.2.2
MAIN BLOCKS
The Smart 3 Advanced Boot Block is an
asymmetrically-blocked architecture that enables
system integration of code and data within a single
flash device. Each block can be erased
independently of the others up to 100,000 times.
For the address locations of each block, see the
memory maps in Appendix D.
After the parameter blocks, the remainder of the
array is divided into equal size main blocks (65,536
bytes / 32,768 words) for data or code storage. The
4-Mbit device contains seven main blocks; 8-Mbit
device contains fifteen main blocks; 16-Mbit flash
has thirty-one main blocks; 32-Mbit has sixty-three
main blocks.
2.2.1
3.0
PARAMETER BLOCKS
The Smart 3 Advanced Boot Block flash memory
architecture includes parameter blocks to facilitate
storage of frequently updated small parameters
(e.g., data that would normally be stored in an
EEPROM). By using software techniques, the wordrewrite functionality of EEPROMs can be emulated.
Each device contains eight parameter blocks of
8-Kbytes/4-Kwords (8192 bytes/4,096 words) each.
PRELIMINARY
PRINCIPLES OF OPERATION
Flash memory combines EEPROM functionality
with in-circuit electrical program and erase
capability. The Smart 3 Advanced Boot Block flash
memory family utilizes a Command User Interface
(CUI) and automated algorithms to simplify program
and erase operations. The CUI allows for 100%
CMOS-level control inputs and fixed power supplies
during erasure and programming.
11
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SMART 3 ADVANCED BOOT BLOCK
When VPP < VPPLK, the device will only execute the
following commands successfully: Read Array,
Read Status Register, Clear Status Register and
Read Identifier. The device provides standard
EEPROM read, standby and output disable
operations. Manufacturer identification and device
identification data can be accessed through the
CUI. All functions associated with altering memory
contents, namely program and erase, are
accessible via the CUI. The internal Write State
Machine (WSM) completely automates program
and erase operations while the CUI signals the start
of an operation and the status register reports
status. The CUI handles the WE# interface to the
data and address latches, as well as system status
requests during WSM operation.
3.1
Bus Operation
Smart 3 Advanced Boot Block flash memory
devices read, program and erase in-system via the
local CPU or microcontroller. All bus cycles to or
from the flash memory conform to standard
microcontroller bus cycles. Four control pins dictate
the data flow in and out of the flash component:
CE#, OE#, WE# and RP#. These bus operations
are summarized in Table 3.
Table 3. Bus Operations(1)
Mode
Read (Array, Status, or
Identifier)
Output Disable
Standby
Note
RP#
CE#
OE#
WE#
DQ0–7
DQ8–15
2–4
VIH
VIL
VIL
VIH
DOUT
DOUT
2
VIH
VIL
VIH
VIH
High Z
High Z
2
VIH
VIH
X
X
High Z
High Z
Reset
2, 7
VIL
X
X
X
High Z
High Z
Write
2, 5–7
VIH
VIL
VIH
VIL
DIN
DIN
NOTES:
1. 8-bit devices use only DQ[0:7], 16-bit devices use DQ[0:15]
2. X must be VIL, VIH for control pins and addresses.
3. See DC Characteristics for VPPLK, VPP1, VPP2, VPP3, VPP4 voltages.
4. Manufacturer and device codes may also be accessed in read identifier mode (A1–A21 = 0). See Table 4.
5. Refer to Table 6 for valid DIN during a write operation.
6. To program or erase the lockable blocks, hold WP# at VIH.
7. RP# must be at GND ± 0.2 V to meet the maximum deep power-down current specified.
12
PRELIMINARY
E
3.1.1
READ
The flash memory has four read modes available:
read array, read identifier, read status and read
query. These modes are accessible independent of
the VPP voltage. The appropriate Read Mode
command must be issued to the CUI to enter the
corresponding mode. Upon initial device power-up
or after exit from reset, the device automatically
defaults to read array mode.
CE# and OE# must be driven active to obtain data
at the outputs. CE# is the device selection control;
when active it enables the flash memory device.
OE# is the data output control and it drives the
selected memory data onto the I/O bus. For all read
modes, WE# and RP# must be at VIH. Figure 7
illustrates a read cycle.
3.1.2
OUTPUT DISABLE
With OE# at a logic-high level (VIH), the device
outputs are disabled. Output pins are placed in a
high-impedance state.
3.1.3
STANDBY
Deselecting the device by bringing CE# to a logichigh level (VIH) places the device in standby mode,
which substantially reduces device power
consumption without any latency for subsequent
read accesses. In standby, outputs are placed in a
high-impedance state independent of OE#. If
deselected during program or erase operation, the
device continues to consume active power until the
program or erase operation is complete.
3.1.4
DEEP POWER-DOWN / RESET
From read mode, RP# at VIL for time tPLPH
deselects the memory, places output drivers in a
high-impedance state, and turns off all internal
circuits. After return from reset, a time tPHQV is
required until the initial read access outputs are
valid. A delay (tPHWL or tPHEL) is required after
return from reset before a write can be initiated.
After this wake-up interval, normal operation is
restored. The CUI resets to read array mode, and
the status register is set to 80H. This case is shown
in Figure 9A.
PRELIMINARY
SMART 3 ADVANCED BOOT BLOCK
If RP# is taken low for time tPLPH during a program
or erase operation, the operation will be aborted
and the memory contents at the aborted location
(for a program) or block (for an erase) are no longer
valid, since the data may be partially erased or
written. The abort process goes through the
following sequence: When RP# goes low, the
device shuts down the operation in progress, a
process which takes time tPLRH to complete. After
this time tPLRH, the part will either reset to read
array mode (if RP# has gone high during tPLRH,
Figure 9B) or enter reset mode (if RP# is still logic
low after tPLRH, Figure 9C). In both cases, after
returning from an aborted operation, the relevant
time tPHQV or tPHWL/tPHEL must be waited before a
read or write operation is initiated, as discussed in
the previous paragraph. However, in this case,
these delays are referenced to the end of tPLRH
rather than when RP# goes high.
As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, processor expects to read from
the flash memory. Automated flash memories
provide status information when read during
program or block erase operations. If a CPU reset
occurs with no flash memory reset, proper CPU
initialization may not occur because the flash
memory may be providing status information
instead of array data. Intel’s Flash memories allow
proper CPU initialization following a system reset
through the use of the RP# input. In this application,
RP# is controlled by the same RESET# signal that
resets the system CPU.
3.1.5
WRITE
A write takes place when both CE# and WE# are
low and OE# is high. Commands are written to the
Command User Interface (CUI) using standard
microprocessor write timings to control flash
operations. The CUI does not occupy an
addressable memory location. The address and
data buses are latched on the rising edge of the
second WE# or CE# pulse, whichever occurs first.
Figure 8 illustrates a program and erase operation.
The available commands are shown in Table 6, and
Appendix A provides detailed information on
moving between the different modes of operation
using CUI commands.
13
SMART 3 ADVANCED BOOT BLOCK
There are two commands that modify array data:
Program (40H) and Erase (20H). Writing either of
these commands to the internal Command User
Interface (CUI) initiates a sequence of internallytimed functions that culminate in the completion of
the requested task (unless that operation is aborted
by either RP# being driven to VIL for tPLRH or an
appropriate suspend command).
3.2.1
3.2
•
Modes of Operation
The flash memory has four read modes and two
write modes. The read modes are read array, read
identifier, read status and read query (see Appendix
C). The write modes are program and block erase.
Three additional modes (erase suspend to program,
erase suspend to read and program suspend to
read) are available only during suspended
operations. These modes are reached using the
commands
summarized
in
Table 4.
A
comprehensive chart showing the state transitions
is in Appendix A.
READ ARRAY
E
When RP# transitions from VIL (reset) to VIH, the
device defaults to read array mode and will respond
to the read control inputs (CE#, address inputs, and
OE#) without any additional CUI commands.
When the device is in read array mode, four control
signals control data output:
WE# must be logic high (VIH)
•
CE# must be logic low (VIL)
•
OE# must be logic low (VIL)
•
RP# must be logic high (VIH)
In addition, the address of the desired location must
be applied to the address pins. If the device is not
in read array mode, as would be the case after a
program or erase operation, the Read Array
command (FFH) must be written to the CUI before
array reads can take place.
Table 4. Command Codes and Descriptions
Code
00,
01,
60,
2F,
C0,
98
Invalid/
Reserved
Description
Unassigned commands that should not be used. Intel reserves the right to
redefine these codes for future functions.
FF
Read Array
Places the device in read array mode, such that array data will be output on the
data pins.
40
Program
Set-Up
This is a two-cycle command. The first cycle prepares the CUI for a program
operation. The second cycle latches addresses and data information and
initiates the WSM to execute the Program algorithm. The flash outputs status
register data when CE# or OE# is toggled. A Read Array command is required
after programming to read array data. See Section 3.2.4.
10
20
14
Device Mode
Alternate
(See 40H/Program Set-Up)
Program Set-Up
Erase
Set-Up
Prepares the CUI for the Erase Confirm command. If the next command is not
an Erase Confirm command, then the CUI will (a) set both SR.4 and SR.5 of the
status register to a “1,” (b) place the device into the read status register mode,
and (c) wait for another command. See Section 3.2.5.
PRELIMINARY
E
SMART 3 ADVANCED BOOT BLOCK
Table 4. Command Codes and Descriptions (Continued)
Code
Device Mode
Description
D0
Erase Confirm
If the previous command was an Erase Set-Up command, then the CUI will
close the address and data latches, and begin erasing the block indicated on the
address pins. During erase, the device will only respond to the Read Status
Register and Erase Suspend commands. The device will output status register
data when CE# or OE# is toggled.
Program / Erase If a program or erase operation was previously suspended, this command will
Resume
resume that operation
B0
Program / Erase Issuing this command will begin to suspend the currently executing
Suspend
program/erase operation. The status register will indicate when the operation
has been successfully suspended by setting either the program suspend (SR.2)
or erase suspend (SR.6) and the WSM status bit (SR.7) to a “1” (ready). The
WSM will continue to idle in the SUSPEND state, regardless of the state of all
input control pins except RP#, which will immediately shut down the WSM and
the remainder of the chip if it is driven to V IL. See Sections 3.2.4.1 and 3.2.5.1.
70
Read Status
Register
This command places the device into read status register mode. Reading the
device will output the contents of the status register, regardless of the address
presented to the device. The device automatically enters this mode after a
program or erase operation has been initiated. See Section 3.2.3.
50
Clear Status
Register
The WSM can set the block lock status (SR.1) , V PP status (SR.3), program
status (SR.4), and erase status (SR.5) bits in the status register to “1,” but it
cannot clear them to “0.” Issuing this command clears those bits to “0.”
90
Read Identifier
Puts the device into the intelligent identifier read mode, so that reading the
device will output the manufacturer and device codes (A 0 = 0 for manufacturer,
A0 = 1 for device, all other address inputs must be 0). See Section 3.2.2.
NOTE: See Appendix A for mode transition information.
3.2.2
READ IDENTIFIER
To read the manufacturer and device codes, the
device must be in read identifier mode, which can
be reached by writing the Read Identifier command
(90H). Once in read identifier mode, A0 = 0 outputs
the manufacturer’s identification code and A0 = 1
outputs the device identifier (see Table 5) Note:
A1—A21 = 0. To return to read array mode, write the
Read Array command (FFH).
Table 5. Read Identifier Table
Device Identifier
Size
Mfr. ID
28F400B3
0089H
8894H
8895H
28F008B3
0089H
D2
D3
8892H
8893H
D0
D1
8890H
8891H
D6
D7
8896
8897
28F800B3
28F016B3
0089H
28F160B3
28F032B3
28F320B3
PRELIMINARY
-T
-B
(Top Boot) (Bot. Boot)
0089H
15
SMART 3 ADVANCED BOOT BLOCK
3.2.3
READ STATUS REGISTER
The device status register indicates when a
program or erase operation is complete and the
success or failure of that operation. To read the
status register issue the Read Status Register
(70H) command to the CUI. This causes all
subsequent read operations to output data from the
status register until another command is written to
the CUI. To return to reading from the array, issue
the Read Array (FFH) command.
The status register bits are output on DQ0–DQ7.
The upper byte, DQ8–DQ15, outputs 00H during a
Read Status Register command.
The contents of the status register are latched on
the falling edge of OE# or CE#. This prevents
possible bus errors which might occur if status
register contents change while being read. CE# or
OE# must be toggled with each subsequent status
read, or the status register will not indicate
completion of a program or erase operation.
When the WSM is active, SR.7 will indicate the
status of the WSM; the remaining bits in the status
register indicate whether or not the WSM was
successful in performing the desired operation (see
Table 7).
3.2.3.1
Clearing the Status Register
The WSM sets status bits 1 through 7 to “1,” and
clears bits 2, 6 and 7 to “0,” but cannot clear status
bits 1 or 3 through 5 to “0.” Because bits 1, 3, 4 and
5 indicate various error conditions, these bits can
only be cleared through the Clear Status Register
(50H) command. By allowing the system software
to control the resetting of these bits, several
operations may be performed (such as cumulatively
programming several addresses or erasing multiple
blocks in sequence) before reading the status
register to determine if an error occurred during that
series. Clear the status register before beginning
another command or sequence. Note, again, that
the Read Array command must be issued before
data can be read from the memory array.
16
3.2.4
PROGRAM MODE
E
Programming is executed using a two-write
sequence. The Program Setup command (40H) is
written to the CUI followed by a second write which
specifies the address and data to be programmed.
The WSM will execute a sequence of internally
timed events to program desired bits of the
addressed location, then Verify the bits are
sufficiently programmed. Programming the memory
results in specific bits within an address location
being changed to a “0.” If the user attempts to
program “1”s, the memory cell contents do not
change and no error occurs.
The status register indicates programming status:
while the program sequence executes, status bit 7
is “0.” The status register can be polled by toggling
either CE# or OE#. While programming, the only
valid commands are Read Status Register,
Program Suspend, and Program Resume.
When programming is complete, the Program
Status bits should be checked. If the programming
operation was unsuccessful, bit SR.4 of the status
register is set to indicate a program failure. If SR.3
is set then VPP was not within acceptable limits, and
the WSM did not execute the program command. If
SR.1 is set, a program operation was attempted on
a locked block and the operation was aborted.
The status register should be cleared before
attempting the next operation. Any CUI instruction
can follow after programming is completed;
however, to prevent inadvertent status register
reads, be sure to reset the CUI to read array mode.
3.2.4.1
Suspending and Resuming
Program
The Program Suspend halts the in-progress
program operation to read data from another
location of memory. Once the programming process
starts, writing the Program Suspend command to
the CUI requests that the WSM suspend the
program sequence (at predetermined points in the
program algorithm). The device continues to output
status register data after the Program Suspend
command is written. Polling status register bits
SR.7 and SR.2 will determine when the program
operation has been suspended (both will be set to
“1”). tWHRH1/tEHRH1 specify the program suspend
latency.
PRELIMINARY
E
A Read Array command can now be written to the
CUI to read data from blocks other than that which
is suspended. The only other valid commands while
program is suspended, are Read Status Register,
Read Identifier, and Program Resume. After the
Program Resume command is written to the flash
memory, the WSM will continue with the program
process and status register bits SR.2 and SR.7 will
automatically be cleared. After the Program
Resume command is written, the device
automatically outputs status register data when
read (see Appendix F for Program Suspend and
Resume Flowchart). VPP must remain at the same
VPP level used for program while in program
suspend mode. RP# must also remain at V IH.
3.2.5
ERASE MODE
To erase a block, write the Erase Set-up and Erase
Confirm commands to the CUI, along with an
address identifying the block to be erased. This
address is latched internally when the Erase
Confirm command is issued. Block erasure results
in all bits within the block being set to “1.” Only one
block can be erased at a time. The WSM will
execute a sequence of internally-timed events to
program all bits within the block to “0,” erase all bits
within the block to “1,” then verify that all bits within
the block are sufficiently erased. While the erase
executes, status bit 7 is a “0.”
When the status register indicates that erasure is
complete, check the erase status bit to verify that
the erase operation was successful. If the erase
operation was unsuccessful, SR.5 of the status
register will be set to a “1,” indicating an erase
failure. If VPP was not within acceptable limits after
the Erase Confirm command was issued, the WSM
will not execute the erase sequence; instead, SR.5
of the status register is set to indicate an erase
error, and SR.3 is set to a “1” to identify that VPP
supply voltage was not within acceptable limits.
PRELIMINARY
SMART 3 ADVANCED BOOT BLOCK
After an erase operation, clear the status register
(50H) before attempting the next operation. Any
CUI instruction can follow after erasure is
completed; however, to prevent inadvertent status
register reads, it is advisable to place the flash in
read array mode after the erase is complete.
3.2.5.1
Suspending and Resuming Erase
Since an erase operation requires on the order of
seconds to complete, an Erase Suspend command
is provided to allow erase-sequence interruption in
order to read data from or program data to another
block in memory. Once the erase sequence is
started, writing the Erase Suspend command to the
CUI requests that the WSM pause the erase
sequence at a predetermined point in the erase
algorithm. The status register will indicate if/when
the erase operation has been suspended.
A Read Array/Program command can now be
written to the CUI in order to read data from/
program data to blocks other than the one currently
suspended.
The
Program
command
can
subsequently be suspended to read yet another
array location. The only valid commands while
erase is suspended are Erase Resume, Program,
Read Array, Read Status Register, or Read
Identifier. During erase suspend mode, the chip can
be placed in a pseudo-standby mode by taking CE#
to VIH. This reduces active current consumption.
Erase Resume continues the erase sequence when
CE# = VIL. As with the end of a standard erase
operation, the status register must be read and
cleared before the next instruction is issued.
17
E
SMART 3 ADVANCED BOOT BLOCK
Table 6. Command Bus Definitions(1, 4)
First Bus Cycle
Command
Notes
Oper
Addr
Data
Write
X
FFH
Write
X
Read Status Register
Write
Clear Status Register
Second Bus Cycle
Oper
Addr
Data
90H
Read
IA
ID
X
70H
Read
X
SRD
Write
X
50H
Write
X
40H / 10H
Write
PA
PD
Block Erase/Confirm
Write
X
20H
Write
BA
D0H
Program/Erase Suspend
Write
X
B0H
Program/Erase Resume
Write
X
D0H
Read Array
Read Identifier
Program
2
3
NOTES:
1.
2.
3.
4.
18
PA: Program Address
PD: Program Data
BA: Block Address
IA: Identifier Address
ID: Identifier Data
SRD: Status Register Data
Bus operations are defined in Table 3.
Following the Intelligent Identifier command, two read operations access manufacturer and device codes. A0 = 0 for
manufacturer code, A0 = 1 for device code. A1—A21 = 0.
Either 40H or 10H command is valid although the standard is 40H.
When writing commands to the device, the upper data bus [DQ 8–DQ15] should be either VIL or VIH, to minimize current
draw.
PRELIMINARY
E
SMART 3 ADVANCED BOOT BLOCK
Table 7. Status Register Bit Definition
WSMS
ESS
ES
PS
VPPS
PSS
BLS
R
7
6
5
4
3
2
1
0
NOTES:
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
Check Write State Machine bit first to determine
word program or block erase completion, before
checking program or erase status bits.
SR.6 = ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase In Progress/Completed
When erase suspend is issued, WSM halts
execution and sets both WSMS and ESS bits to “1.”
ESS bit remains set at “1” until an Erase Resume
command is issued.
SR.5 = ERASE STATUS (ES)
1 = Error In Block Erasure
0 = Successful Block Erase
When this bit is set to “1,” WSM has applied the
max. number of erase pulses to the block and is still
unable to verify successful block erasure.
SR.4 = PROGRAM STATUS (PS)
1 = Error in Word Program
0 = Successful Word Program
When this bit is set to “1,” WSM has attempted but
failed to program a word.
SR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
The VPP status bit does not provide continuous
indication of VPP level. The WSM interrogates VPP
level only after the Program or Erase command
sequences have been entered, and informs the
system if V PP has not been switched on. The VPP is
also checked before the operation is verified by the
WSM. The VPP status bit is not guaranteed to report
accurate feedback between VPPLK max and VPP1 min
or between VPP1 max and VPP4 min.
SR.2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
When program suspend is issued, WSM halts
execution and sets both WSMS and PSS bits to “1.”
PSS bit remains set to “1” until a Program Resume
command is issued.
SR.1 = Block Lock Status
1 = Program/Erase attempted on locked
block; Operation aborted
0 = No operation to locked blocks
If a program or erase operation is attempted to one
of the locked blocks, this bit is set by the WSM. The
operation specified is aborted and the device is
returned to read status mode.
SR.0 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
This bit is reserved for future use and should be
masked out when polling the status register.
PRELIMINARY
19
SMART 3 ADVANCED BOOT BLOCK
3.3
Block Locking
3.4
The Smart 3 Advanced Boot Block flash memory
architecture features
two
hardware-lockable
parameter blocks.
3.3.1
WP# = VIL FOR BLOCK LOCKING
The lockable blocks are locked when WP# = VIL;
any program or erase operation to a locked block
will result in an error, which will be reflected in the
status register. For top configuration, the top two
parameter blocks (blocks #69 and #70, blocks #37
and #38 for the 16-Mbit, blocks #21 and #22 for the
8-Mbit, blocks #13 and #14 for the 4-Mbit) are
lockable. For the bottom configuration, the bottom
two parameter blocks (blocks #0 and #1 for 4-/8-/
16-/32-Mbit) are lockable. Unlocked blocks can be
programmed or erased normally (unless VPP is
below VPPLK).
3.3.2
WP# = VIH FOR BLOCK UNLOCKING
WP# = VIH unlocks all lockable blocks.
These blocks can now be programmed or erased.
Note that RP# does not override WP# locking as in
previous Boot Block devices. WP# controls all block
locking and VPP provides protection against
spurious writes. Table 8 defines the write protection
methods.
Table 8. Write Protection Truth Table for
Advanced Boot Block Flash Memory Family
VPP
WP#
RP#
Write Protection
Provided
X
X
VIL
All Blocks Locked
VIL
X
VIH
All Blocks Locked
≥ VPPLK
VIL
VIH
Lockable Blocks
Locked
≥ VPPLK
VIH
VIH
All Blocks Unlocked
20
E
VPP Program and Erase
Voltages
Intel’s Smart 3 products provide in-system
programming and erase at 2.7 V. For customers
requiring fast programming in their manufacturing
environment, Smart 3 includes an additional lowcost 12 V programming feature.
The 12 V VPP mode enhances programming
performance during the short period of time typically
found in manufacturing processes; however, it is
not intended for extended use. 12 V may be applied
to VPP during program and erase operations for a
maximum of 1000 cycles on the main blocks and
2500 cycles on the parameter blocks. VPP may be
connected to 12 V for a total of 80 hours maximum.
Stressing the device beyond these limits may cause
permanent damage.
During read operations or idle times, VPP may be
tied to a 5 V supply. For program and erase
operations, a 5 V supply is not permitted. The VPP
must be supplied with either 2.7 V–3.6 V or 11.4 V–
12.6 V during program and erase operations.
3.4.1
VPP = VIL FOR COMPLETE
PROTECTION
The VPP programming voltage can be held low for
complete write protection of all blocks in the flash
device. When VPP is below VPPLK, any program or
erase operation will result in a error, prompting the
corresponding status register bit (SR.3) to be set.
3.5
Power Consumption
Intel® Flash devices have a tiered approach to
power savings that can significantly reduce overall
system power consumption. The Automatic Power
Savings (APS) feature reduces power consumption
when the device is selected but idle. If the CE# is
deasserted, the flash enters its standby mode,
where current consumption is even lower. The
combination of these features can minimize
memory power consumption, and therefore, overall
system power consumption.
PRELIMINARY
E
3.5.1
ACTIVE POWER
With CE# at a logic-low level and RP# at a logichigh level, the device is in the active mode. Refer to
the DC Characteristic tables for ICC current values.
Active power is the largest contributor to overall
system power consumption. Minimizing the active
current could have a profound effect on system
power consumption, especially for battery-operated
devices.
3.5.2
AUTOMATIC POWER SAVINGS (APS)
Automatic Power Savings provides low-power
operation during read mode. After data is read from
the memory array and the address lines are
quiescent, APS circuitry places the device in a
mode where typical current is comparable to ICCS.,
The flash stays in this static state with outputs valid
until a new location is read.
3.5.3
STANDBY POWER
With CE# at a logic-high level (VIH) and device in
read mode, the flash memory is in standby mode,
which disables much of the device’s circuitry and
substantially reduces power consumption. Outputs
are placed in a high-impedance state independent
of the status of the OE# signal. If CE# transitions to
a logic-high level during erase or program
operations, the device will continue to perform the
operation and consume corresponding active power
until the operation is completed.
System engineers should analyze the breakdown of
standby time versus active time and quantify the
respective power consumption in each mode for
their specific application. This will provide a more
accurate measure of application-specific power and
energy requirements.
3.5.4
DEEP POWER-DOWN MODE
The deep power-down mode is activated when RP#
= VIL (GND ± 0.2 V). During read modes, RP#
going low de-selects the memory and places the
outputs in a high impedance state. Recovery from
deep power-down requires a minimum time of tPHQV
(see AC Characteristics—Read Operations).
During program or erase modes, RP# transitioning
low will abort the in-progress operation. The
memory contents of the address being programmed
PRELIMINARY
SMART 3 ADVANCED BOOT BLOCK
or the block being erased are no longer valid as the
data integrity has been compromised by the abort.
During deep power-down, all internal circuits are
switched to a low power savings mode (RP#
transitioning to VIL or turning off power to the device
clears the status register).
3.6
Power-Up/Down Operation
The device is protected against accidental block
erasure or programming during power transitions.
Power supply sequencing is not required, since the
device is indifferent as to which power supply, VPP
or VCC, powers-up first.
3.6.1
RP# CONNECTED TO SYSTEM
RESET
The use of RP# during system reset is important
with automated program/erase devices since the
system expects to read from the flash memory
when it comes out of reset. If a CPU reset occurs
without a flash memory reset, proper CPU
initialization will not occur because the flash
memory may be providing status information
instead of array data. Intel recommends connecting
RP# to the system CPU RESET# signal to allow
proper CPU/flash initialization following system
reset.
System designers must guard against spurious
writes when VCC voltages are above VLKO. Since
both WE# and CE# must be low for a command
write, driving either signal to VIH will inhibit writes to
the device. The CUI architecture provides additional
protection since alteration of memory contents can
only occur after successful completion of the twostep command sequences. The device is also
disabled until RP# is brought to VIH, regardless of
the state of its control inputs. By holding the device
in reset (RP# connected to system PowerGood)
during power-up/down, invalid bus conditions during
power-up can be masked, providing yet another
level of memory protection.
3.6.2
VCC, VPP AND RP# TRANSITIONS
The CUI latches commands as issued by system
software and is not altered by VPP or CE#
transitions or WSM actions. Its default state upon
power-up, after exit from reset mode or after VCC
transitions above VLKO (Lockout voltage), is read
array mode.
21
SMART 3 ADVANCED BOOT BLOCK
After any program or block erase operation is
complete (even after VPP transitions down to
VPPLK), the CUI must be reset to read array mode
via the Read Array command if access to the flash
memory array is desired.
3.7
Power Supply Decoupling
Flash memory’s power switching characteristics
require careful device decoupling. System
designers should consider three supply current
issues:
E
Transient current magnitudes depend on the device
outputs’ capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection
will suppress these transient voltage peaks. Each
flash device should have a 0.1 µF ceramic
capacitor connected between each VCC and GND,
and between its VPP and GND. These highfrequency, inherently low-inductance capacitors
should be placed as close as possible to the
package leads.
1. Standby current levels (ICCS)
2. Read current levels (ICCR)
3. Transient peaks produced by falling and rising
edges of CE#.
22
PRELIMINARY
E
4.0
ELECTRICAL SPECIFICATIONS
4.1
Absolute Maximum Ratings*
Extended Operating Temperature
During Read .......................... –40 °C to +85 °C
During Block Erase
and Program.......................... –40 °C to +85 °C
Temperature Under Bias ....... –40 °C to +85 °C
Storage Temperature................. –65 °C to +125 °C
SMART 3 ADVANCED BOOT BLOCK
NOTICE: This datasheet contains preliminary information on
new products in production. Do not finalize a design with
this information. Revised information will be published when
the product is available. Verify with your local Intel Sales
office that you have the latest datasheet before finalizing a
design.
* WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage. These
are stress ratings only. Operation beyond the "Operating
Conditions" is not recommended and extended exposure
beyond the "Operating Conditions" may effect device
reliability.
Voltage on Any Pin
(except VCC, VCCQ and VPP)
with Respect to GND ............. –0.5 V to 3.7 V (1)
VPP Voltage (for Block
Erase and Program)
with Respect to GND ..... –0.5 V to +13.5 V(1,2,4)
VCC and VCCQ Supply Voltage
with Respect to GND ........... –0.2 V to +3.7 V(5)
Output Short Circuit Current.....................100 mA(3)
NOTES:
1. Minimum DC voltage is –0.5 V on input/output pins, with allowable undershoot to –2.0 V for periods < 20 ns. Maximum DC
voltage on input/output pins is VCC + 0.5 V, with allowable overshoot to VCC + 1.5 V for periods < 20 ns.
2. Maximum DC voltage on VPP may overshoot to +14.0 V for periods < 20 ns.
3. Output shorted for no more than one second. No more than one output shorted at a time.
4. VPP Program voltage is normally 2.7 V–3.6 V.
5. Minimum DC voltage is –0.5 V on VCC and VCCQ, with allowable undershoot to –2.0 V for periods < 20 ns. Maximum DC
voltage on VCC and VCCQ pins is VCC + 0.5 V, with allowable overshoot to VCC + 1.5 V for periods < 20 ns.
PRELIMINARY
23
E
SMART 3 ADVANCED BOOT BLOCK
4.2
Operating Conditions
Symbol
Parameter
Min
Max
Units
–40
+85
°C
2.7
3.6
Volts
VCC2
2.7
2.85
VCC3
2.7
3.3
2.7
3.6
VCCQ2
1.65
2.5
VCCQ3
1.8
2.5
2.7
3.6
VPP2
2.7
2.85
VPP3
2.7
3.3
2, 3
11.4
12.6
3
100,000
TA
Operating Temperature
VCC1
VCC Supply Voltage
VCCQ1
Notes
1
I/O Supply Voltage
VPP1
1
Program and Erase Voltage
1
VPP4
Cycling
Block Erase Cycling
Volts
Volts
Cycles
NOTES:
1. VCC1, VCCQ1, and VPP3 must share the same supply when all three are between 2.7 V and 3.6 V.
2. During read operations or idle time, 5 V may be applied to VPP indefinitely. VPP must be at valid levels for program and
erase operations
3. Applying VPP = 11.4 V–12.6 V during a program/erase can only be done for a maximum of 1000 cycles on the main blocks
and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours maximum. See Section 3.4
for details.
4.3
Capacitance
TA = 25 °C, f = 1 MHz
Sym
Parameter
Notes
Typ
Max
Units
Conditions
CIN
Input Capacitance
1
6
8
pF
VIN = 0 V
COUT
Output Capacitance
1
10
12
pF
VOUT = 0 V
NOTE:
1. Sampled, not 100% tested.
24
PRELIMINARY
E
4.4
Sym
SMART 3 ADVANCED BOOT BLOCK
DC Characteristics(1)
Parameter
VCC
2.7 V–3.6 V 2.7 V–2.85 V 2.7 V–3.3 V
VCCQ
2.7 V–3.6 V 1.65 V–2.5 V 1.8 V–2.5 V
Note Typ
Max
Typ
Max
Typ
Max Unit
Test Conditions
ILI
Input Load Current
6
±1
±1
±1
µA
VCC = VCCMax
VCCQ = VCCQMax
VIN = VCCQ or GND
ILO
Output Leakage
Current
6
± 10
± 10
± 10
µA
VCC = VCCMax
VCCQ = VCCQMax
VIN = VCCQ or GND
ICCS
VCC Standby Current
6
18
35
20
50
150
250
µA
VCC = VCCMax
CE# = RP# = VCC
or during Program/
Erase Suspend
ICCD
VCC Power-Down
Current
6
7
20
7
20
7
20
µA
VCC = VCCMax
VCCQ = VCCQMax
VIN = VCCQ or GND
RP# = GND ± 0.2 V
ICCR
VCC Read Current
4,6
10
18
8
15
9
15
mA
VCC = VCCMax
VCCQ = VCCQMax
OE# = VIH , CE# =VIL
f = 5 MHz, I OUT=0mA
Inputs = VIL or VIH
IPPD
VPP Deep PowerDown Current
0.2
5
0.2
5
0.2
5
µA
RP# = GND ± 0.2 V
IPPR
VPP Read Current
ICCW+
IPPW
VCC + VPP Program
Current
VPP ≤ VCC
3
ICCE + VCC + VPP Erase
IPPE
Current
IPPES
IPPWS
VPP Erase Suspend
Current
PRELIMINARY
3,6
3,6
3
2
±15
2
±15
2
±15
µA
VPP ≤ VCC
50
200
50
200
50
200
µA
VPP > VCC
18
55
18
55
18
55
mA
VPP =VPP1, 2, 3
Program in Progress
10
30
10
30
10
30
mA
VPP = VPP4
Program in Progress
20
45
21
45
21
45
mA
VPP = VPP1, 2, 3
Program in Progress
16
45
16
45
16
45
mA
VPP = VPP4
Program in Progress
50
200
50
200
50
200
µA
VPP = VPP1, 2, 3, 4
Program or Erase
Suspend in Progress
25
E
SMART 3 ADVANCED BOOT BLOCK
4.4
Sym
DC Characteristics (Continued)
Parameter
VCC
2.7 V–3.6 V
2.7 V–2.85 V
2.7 V–3.3 V
VCCQ
2.7 V–3.6 V
1.65 V–2.5 V
1.8 V–2.5 V
Min
Max
Min
Max
Min
Max
0.4
–0.2
0.2
–0.2
0.2
Note
VIL
Input Low Voltage
–0.4
VIH
Input High Voltage
VCCQ
–0.4V
VOL
Output Low
Voltage
VOH
Output High
Voltage
VPPLK
VPP Lock-Out
Voltage
2
VPP1
VPP during
2
VPP2
Program and
2
VPP3
Erase Operations
2
VPP4
VCCQ
–0.2V
0.10
VCCQ
–0.1V
2,5
-0.10
-0.10
0.10
1.5
3.6
12.6
V
V
VCCQ
–0.1V
1.5
V
VCC = VCCMin
VCCQ = VCCQMin
IOL = 100 µA
V
VCC = VCCMin
VCCQ = VCCQMin
IOH = –100 µA
V
Complete Write
Protection
V
2.7
11.4
0.10
VCCQ
–0.1V
1.5
2.7
VCCQ
–0.2V
Unit Test Conditions
11.4
2.85
12.6
V
2.7
3.3
V
11.4
12.6
V
VLKO
VCC Prog/Erase
Lock Voltage
1.5
1.5
1.5
V
VLKO2
VCCQ Prog/Erase
Lock Voltage
1.2
1.2
1.2
V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC, TA = +25 °C.
2. Erase and program are inhibited when VPP < VPPLK and not guaranteed outside the valid VPP ranges of VPP1, VPP2, VPP3
and VPP4. For read operations or during idle time, a 5 V supply may be applied to VPP indefinitely. However, VPP must be at
valid levels for program and erase operations.
3. Sampled, not 100% tested.
4. Automatic Power Savings (APS) reduces ICCR to approximately standby levels in static operation.
5. Applying VPP = 11.4 V–12.6 V during program/erase can only be done for a maximum of 1000 cycles on the main blocks
and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours maximum. See Section 3.4
for details. For read operations or during idle time, a 5 V supply may be applied to VPP indefinitely. However, VPP must be
at valid levels for program and erase operations.
6. Since each column lists specifications for a different VCC and VCCQ voltage range combination, the test conditions VCCMax,
VCCQMax, VCCMin, and VCCQMin refer to the maximum or minimum VCC or VCCQ voltage listed at the top of each column.
26
PRELIMINARY
E
SMART 3 ADVANCED BOOT BLOCK
VCCQ
VCCQ
INPUT
TEST POINTS
2
VCCQ
2
OUTPUT
0.0
0580_05
NOTE:
AC test inputs are driven at VCCQ for a logic “1” and 0.0V for a logic “0.” Input timing begins, and output timing ends, at VCCQ/2.
Input rise and fall times (10%–90%) <10 ns. Worst case speed conditions are when VCCQ = VCCQMin.
Figure 5. Input Range and Measurement Points
Test Configuration Component Values for Worst
Case Speed Conditions
VCCQ
Test Configuration
R
1
Device
under
Test
Out
CL (pF)
VCCQ1 Standard Test
50
VCCQ2 Standard Test
50
R1 (Ω) R2 (Ω)
25 K
25 K
16.7 K 16.7 K
NOTE:
CL includes jig capacitance.
CL
R
2
0580_06
NOTE:
See table for component values.
Figure 6. Test Configuration
PRELIMINARY
27
E
SMART 3 ADVANCED BOOT BLOCK
4.5
AC Characteristics —Read Operations(1)
Product
3.0 V–3.6 V
80 ns
100 ns
2.7 V–3.6 V
Parameter
Note
90 ns
Min
Max
#
Sym
R1
tAVAV
Read Cycle Time
R2
tAVQV
Address to
Output Delay
R3
tELQV
CE# to Output
Delay
R4
tGLQV
OE# to Output
Delay
R5
tPHQV
RP# to Output
Delay
R6
tELQX
CE# to Output in
Low Z
3
0
0
0
0
ns
R7
tGLQX
OE# to Output in
Low Z
3
0
0
0
0
ns
R8
tEHQZ
CE# to Output in
High Z
3
25
25
25
25
ns
R9
tGHQZ
OE# to Output in
High Z
3
25
25
25
25
ns
R10
tOH
Output Hold from
Address, CE#, or
OE# Change,
Whichever
Occurs First
3
80
Min
Max
110 ns
90
Min
Max
100
Min
Max
110
Unit
ns
80
90
100
110
ns
2
80
90
100
110
ns
2
30
30
30
30
ns
600
600
600
600
ns
0
0
0
0
ns
NOTES:
1. See AC Waveform: Read Operations.
2. OE# may be delayed up to tELQV–tGLQV after the falling edge of CE# without impact on tELQV.
3. Sampled, but not 100% tested.
28
PRELIMINARY
E
SMART 3 ADVANCED BOOT BLOCK
CE# (E)
Data
Valid
Device and
Address Selection
VIH
ADDRESSES (A)
VIL
Standby
Address Stable
R1
VIH
VIL
R8
VIH
OE# (G)
VIL
R9
VIH
WE# (W)
VIL
VOH
DATA (D/Q)
VOL
RP#(P)
R7
High Z
R10
R3
R6
Valid Output
High Z
R2
VIH
VIL
R4
R5
0580_07
Figure 7. AC Waveform: Read Operations
PRELIMINARY
29
E
SMART 3 ADVANCED BOOT BLOCK
AC Characteristics —Write Operations(1)
4.6
Product
3.0 V – 3.6 V
80
2.7 V – 3.6 V
#
W1
Symbol
tPHWL /
tPHEL
W2
W3
tELWL /
Parameter
Note
RP# High Recovery to WE#
(CE#) Going Low
100
90
110
Min
Min
Min
Min
Unit
600
600
600
600
ns
0
0
0
0
ns
tWLEL
CE# (WE#) Setup to WE#
(CE#) Going Low
tELEH /
WE# (CE#) Pulse Width
4
70
70
70
70
ns
Data Setup to WE# (CE#)
Going High
2
50
50
60
60
ns
Address Setup to WE# (CE#)
Going High
2
70
70
70
70
ns
0
0
0
0
ns
tWLWH
W4
tDVWH /
tDVEH
W5
tAVWH /
tAVEH
W6
tWHEH /
tEHWH
W7
tWHDX /
Data Hold Time from WE#
(CE#) High
2
0
0
0
0
ns
Address Hold Time from WE#
(CE#) High
2
0
0
0
0
ns
tEHAX
tWHWL /
WE# (CE#) Pulse Width High
4
30
30
30
30
ns
VPP Setup to WE# (CE#) Going
High
3
200
200
200
200
ns
tVPEH
tQVVL
VPP Hold from Valid SRD
3
0
0
0
0
ns
tEHDX
W8
W9
CE# (WE#) Hold Time from
WE# (CE#) High
tWHAX /
tEHEL
W10
W11
tVPWH /
NOTES:
1. Read timing characteristics during program suspend and erase suspend are the same as during read-only operations.
2. Refer to command definition table (Table 6) for valid AIN or DIN.
3. Sampled, but not 100% tested.
4. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high
(whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. Similarly, Write pulse width high (tWPH) is defined
from CE# or WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low first). Hence, tWPH =
tWHWL = tEHEL = tWHEL = tEHWL.
30
PRELIMINARY
E
4.7
SMART 3 ADVANCED BOOT BLOCK
Program and Erase Timings
VPP
tBWPB
tBWMB
tWHQV1 / tEHQV1
tWHQV2 / tEHQV2
tWHQV3 / tEHQV3
2.7 V–3.6 V
11.4 V–12.6 V
Notes
Typ(1)
Max
Typ(1)
Max
Units
8-KB Parameter Block
Program Time (Byte)
2, 3
0.16
0.48
0.08
0.24
s
4-KW Parameter Block
Program Time (Word)
2, 3
0.10
0.30
0.03
0.12
s
64-KB Main Block
Program Time (Byte)
2, 3
1.2
3.7
0.6
1.7
s
32-KW Main Block
Program Time(Word)
2, 3
0.8
2.4
0.24
1
s
Byte Program Time
2, 3
17
165
8
185
µs
Word Program Time
2, 3
22
200
8
185
µs
8-KB Parameter Block
Erase Time (Byte)
2, 3
1
4
0.8
4
s
4-KW Parameter Block
Erase Time (Word)
2, 3
0.5
4
0.4
4
s
64-KB Main Block
Erase Time (Byte)
2, 3
1
5
1
5
s
32-KW Main Block
Erase Time (Word)
2, 3
1
5
0.6
5
s
Symbol
Parameter
tWHRH1 / tEHRH1
Program Suspend Latency
5
10
5
10
µs
tWHRH2 / tEHRH2
Erase Suspend Latency
5
20
5
20
µs
NOTES:
1. Typical values measured at nominal voltages and TA = +25 °C.
2. Excludes external system-level overhead.
3. Sampled, not 100% tested.
PRELIMINARY
31
E
SMART 3 ADVANCED BOOT BLOCK
VIH
A
B
C
AIN
ADDRESSES [A]
VIL
VIH
D
E
F
AIN
W8
W5
(Note 1)
CE#(WE#) [E(W)]
VIL
W6
VIH W2
OE# [G]
VIL
W9
(Note 1)
VIH
WE#(CE#) [W(E)]
VIL
W3
W4
VIH
DATA [D/Q]
High Z
VIL
RP# [P]
W7
DIN
DIN
W1
Valid
SRD
DIN
VIH
VIL
VIH
WP#
V
[V]
PP
VIL
W10
W11
VPPH 2
VPPH1
VPPLK
VIL
0580_08
NOTES:
1. CE# must be toggled low when reading Status Register Data. WE# must be inactive (high) when reading Status Register
Data.
A. VCC Power-Up and Standby.
B. Write Program or Erase Setup Command.
C. Write Valid Address and Data (for Program) or Erase Confirm Command.
D. Automated Program or Erase Delay.
E. Read Status Register Data (SRD): reflects completed program/erase operation.
F. Write Read Array Command.
Figure 8. AC Waveform: Program and Erase Operations
32
PRELIMINARY
E
5.0
SMART 3 ADVANCED BOOT BLOCK
RESET OPERATIONS
RP# (P)
VIH
VIL
t PLPH
(A) Reset during Read Mode
t PHQV
t PHWL
t PHEL
Abort
Complete
t PLRH
RP# (P)
VIH
t PHQV
t PHWL
t PHEL
VIL
t PLPH
(B) Reset during Program or Block Erase, t PLPH < t PLRH
Abort Deep
Complete PowerDown
RP# (P)
VIH
V IL
t PLRH
t PHQV
t PHWL
t PHEL
t PLPH
(C) Reset Program or Block Erase, t PLPH > t PLRH
0580_09
Figure 9. AC Waveform: Deep Power-Down/Reset Operation
Reset Specifications
VCC = 2.7 V–3.6 V
Symbol
Parameter
Notes
Min
tPLPH
RP# Low to Reset during Read
(If RP# is tied to VCC, this specification is not applicable)
1,3
100
tPLRH
RP# Low to Reset during Block Erase or Program
2,3
Max
Unit
ns
22
µs
NOTES:
1. If tPLPH is <100 ns the device may still RESET but this is not guaranteed.
2. If RP# is asserted while a block erase or word program operation is not executing, the reset will complete within 100 ns.
3. Sampled, but not 100% tested.
PRELIMINARY
33
SMART 3 ADVANCED BOOT BLOCK
6.0
ORDERING INFORMATION
E
T E2 8 F 1 6 0 B3 T A9 0
Package
TE = 40-Lead/48-Lead TSOP
GT = 48-Ball µBGA* CSP
Product line designator
for all Intel Flash products
Device Density
320 = x16 (32 Mbit)
160 = x16 (16 Mbit)
800 = x16 (8 Mbit)
400 = x 16 (4 Mbit)
Access Speed (ns)
(90, 110)
Lithography
Not Present = 0.4 µm
A = 0.25 µm
T = Top Blocking
B = Bottom Blocking
Product Family
B3 = Smart 3 Advanced Boot Block
VCC = 2.7 V - 3.6 V
VPP = 2.7 V - 3.6 V or 11.4 V - 12.6 V
032 = x 8 (32 Mbit)
016 = x8 (16 Mbit)
008 = x8 (8 Mbit)
34
PRELIMINARY
E
SMART 3 ADVANCED BOOT BLOCK
Ordering Information Valid Combinations
40-Lead TSOP
48-Ball µBGA*
CSP(1)
48-Lead TSOP
Ext. Temp.
GT28F032B3TA95
TE28F320B3TA95
32 M
GT28F032B3BA95
TE28F320B3BA95
GT28F320B3BA95
GT28F032B3TA115
TE28F320B3TA115
GT28F320B3TA115
GT28F032B3BA115
TE28F320B3BA115
GT28F320B3BA115
48-Ball µBGA CSP
GT28F320B3TA95
Ext. Temp.
TE28F016B3TA90(2)
GT28F016B3TA90(2)
TE28F160B3TA90(2)
GT28F160B3TA90(2)
16 M
TE28F016B3BA90(2)
GT28F016B3BA90(2)
TE28F160B3BA90(2)
GT28F160B3BA90(2)
TE28F016B3TA110(2)
GT28F016B3TA110(2)
TE28F160B3TA110(2)
GT28F160B3TA110(2)
TE28F016B3BA110(2)
GT28F016B3BA110(2)
TE28F160B3BA110(2)
GT28F160B3BA110(2)
Ext. Temp.
TE28F008B3TA90(2)
GT28F008B3T90
TE28F800B3TA90(2)
GT28F800B3T90
8M
TE28F008B3BA90(2)
GT28F008B3B90
TE28F800B3BA90(2)
GT28F800B3B90
TE28F008B3TA110(2)
GT28F008B3T110
TE28F800B3TA110(2)
GT28F800B3T110
TE28F008B3BA110(2)
GT28F008B3B110
TE28F800B3BA110(2)
GT28F800B3B110
Ext. Temp
TE28F400B3T110
4M
TE28F400B3B110
NOTES:
1.
The 48-ball µBGA package top side mark reads F160B3 [or F800B3]. This mark is identical for both x8 and x16 products.
All product shipping boxes or trays provide the correct information regarding bus architecture. However, once the devices
are removed from the shipping media, it may be difficult to differentiate based on the top side mark. The device identifier
(accessible through the Device ID command: see Section 3.2.2 for further details) enables x8 and x16 µBGA package
product differentiation.
2.
The second line of the 48-ball µBGA package top side mark specifies assembly codes. For samples only, the first
character signifies either “E” for engineering samples or “S” for silicon daisy chain samples. All other assembly codes
without an “E” or “S” as the first character are production units.
3. Product can be ordered in either 0.25 µm or 0.4 µm material. The “A” before the access speed specifies 0.25 µm material.
4. For new designs, Intel recommends using 0.25 µm Advanced Boot Block devices.
PRELIMINARY
35
E
SMART 3 ADVANCED BOOT BLOCK
7.0
ADDITIONAL INFORMATION (1,2)
Order Number
Document/Tool
210830
1997 Flash Memory Databook
297948
Smart 3 Advanced Boot Block Flash Memory Family Specification Update
297835
28F160B3 Specification Update
Smart 3 Advanced Boot Block Algorithms (‘C’ and assembly)
http://developer.intel.com/design/flcomp
Contact your Intel
Representative
297874
Flash Data Integrator (FDI) Software Developer’s Kit
FDI Interactive: Play with Intel’s Flash Data Integrator on Your PC
NOTE:
1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should
contact their local Intel or distribution sales office.
2. Visit Intel’s World Wide Web home page at http://www.Intel.com or http://developer.intel.com for technical documentation
and tools.
36
PRELIMINARY
E
SMART 3 ADVANCED BOOT BLOCK
APPENDIX A
WRITE STATE MACHINE CURRENT/NEXT STATES
Command Input (and Next State)
Current
State
SR.7
Data
When
Read
Read
Array
(FFH)
Program
Setup
(10/40H)
Erase
Setup
(20H)
Read Array
“1”
Array
Read
Array
Program
Setup
Erase
Setup
Read Status
“1”
Status
Read
Array
Program
Setup
Read
Identifier
“1”
Identifier
Read
Array
Program
Setup
Prog. Setup
“1”
Status
Program
(continue)
“0”
Status
Program
Suspend to
Read Status
“1”
Status
Prog.
Sus. to
Read
Array
Program Suspend
to Read Array
Program
(continue)
Program
Susp. to
Read Array
Program
(continue)
Prog.
Susp. to
Read
Status
Prog.
Sus. to
Read
Array
Prog.
Susp. to
Read
Identifier
Program
Suspend to
Read Array
“1”
Array
Prog.
Susp. to
Read
Array
Program Suspend
to Read Array
Program
(continue)
Program
Susp. to
Read Array
Program
(continue)
Prog.
Susp. to
Read
Status
Prog.
Sus. to
Read
Array
Prog.
Susp. to
Read
Identifier
Prog. Susp.
to Read
Identifier
“1”
Identifier
Prog.
Susp. to
Read
Array
Program Suspend
to Read Array
Program
(continue)
Program
Susp. to
Read Array
Program
(continue)
Prog.
Susp. to
Read
Status
Prog.
Sus. to
Read
Array
Prog.
Susp. to
Read
Identifier
Program
(complete)
“1”
Status
Read
Array
Read
Status
Read
Array
Read
Identifier
Erase Setup
“1”
Status
Erase Cmd.
Error
“1”
Status
Erase
(continue)
“0”
Status
Erase
Suspend to
Status
“1”
Status
Erase
Susp. to
Read
Array
Program
Setup
Erase
Susp. to
Read
Array
Erase
Erase
Susp. to
Read Array
Erase
Erase
Susp. to
Read
Status
Erase
Susp. to
Read
Array
Ers. Susp.
to Read
Identifier
Erase Susp.
to Read
Array
“1”
Array
Erase
Susp. to
Read
Array
Program
Setup
Erase
Susp. to
Read
Array
Erase
Erase
Susp. to
Read Array
Erase
Erase
Susp. to
Read
Status
Erase
Susp. to
Read
Array
Ers. Susp.
to Read
Identifier
Erase Susp.
to Read
Identifier
“1”
Identifier
Erase
Susp. to
Read
Array
Program
Setup
Erase
Susp. to
Read
Array
Erase
Erase
Susp. to
Read Array
Erase
Erase
Susp. to
Read
Status
Erase
Susp. to
Read
Array
Ers. Susp.
to Read
Identifier
Erase
(complete)
“1”
Status
Read
Array
Program
Setup
Erase
Setup
Read
Status
Read
Array
Read
Identifier
PRELIMINARY
Erase
Confirm
(D0H)
Prog/Ers
Suspend
(B0H)
Prog/Ers
Resume
(D0H)
Read
Status
(70H)
Clear
Status
(50H)
Read
Identifier.
(90H)
Read Array
Read
Status
Read
Array
Read
Identifier
Erase
Setup
Read Array
Read
Status
Read
Array
Read
Identifier
Erase
Setup
Read Array
Read
Status
Read
Array
Read
Identifier
Program (Command Input = Data to be Programmed)
Program (continue)
Program
Setup
Erase
Setup
Erase Command Error
Read
Array
Program
Setup
Prog.
Susp. to
Rd. Status
Program (continue)
Read Array
Erase
(continue)
Erase
Cmd. Error
Erase
(continue)
Erase Command Error
Erase
Setup
Read Array
Read
Status
Erase (continue)
Erase Sus.
to Read
Status
Erase (continue)
Read Array
Read
Array
Read
Identifier
37
SMART 3 ADVANCED BOOT BLOCK
APPENDIX B
ACCESS TIME VS. CAPACITIVE LOAD
(tAVQV vs. CL)
E
Access Time vs. Load Capacitance
99
Access Time (ns)
95
91
VCCQ = 2.7V
87
VCCQ = 3.0V
83
79
75
30
40
50
60
70
80
90
100
Load Capacitance (pF)
This chart shows a derating curve for device access time with respect to capacitive load. The value in the
DC Characteristics section of the specification corresponds to C L = 50 pF.
NOTE:
Sampled, but not 100% tested
38
PRELIMINARY
E
SMART 3 ADVANCED BOOT BLOCK
APPENDIX C
ARCHITECTURE BLOCK DIAGRAM
DQ0-DQ15
VCCQ
Power
Reduction
Control
Input Buffer
Identifier
Register
Status
Register
Data
Register
Output
Multiplexer
Output Buffer
I/O Logic
CE#
WE#
OE#
RP#
Command
User
Interface
Data
Comparator
WP#
A0-A19
Y-Decoder
Y-Gating/Sensing
Write State
Machine
Address
Counter
32-KWord
Main Block
X-Decoder
4-KWord
Parameter Block
32-KWord
Main Block
Address
Latch
4-KWord
Parameter Block
Input Buffer
Program/Erase
Voltage Switch
VPP
VCC
GND
0580-C1
PRELIMINARY
39
SMART 3 ADVANCED BOOT BLOCK
APPENDIX D
WORD-WIDE MEMORY MAP DIAGRAMS
E
8-Mbit, 16-Mbit, and 32-Mbit Word-Wide Memory Addressing
Top Boot
Size
(KW)
8M
Bottom Boot
16M
32M
8M
16M
32M
4
7F000-7FFFF
FF000-FFFFF
1FF000-1FFFFF
32
4
7E000-7EFFF
FE000-FEFFF
1FE000-1FEFFF
32
1F0000-1F7FFF
4
7D000-7DFFF
FD000-FDFFF
1FD000-1FDFFF
32
1E8000-1EFFFF
4
7C000-7CFFF
FC000-FCFFF
1FC000-1FCFFF
32
1E0000-1E7FFF
4
7B000-7BFFF
FB000-FBFFF
1FB000-1FBFFF
32
1D8000-1DFFFF
4
7A000-7AFFF
FA000-FAFFF
1FA000-1FAFFF
32
1D0000-1D7FFF
4
79000-79FFF
F9000-F9FFF
1F9000-1F9FFF
32
1C8000-1CFFFF
1F8000-1FFFFF
4
78000-78FFF
F8000-F8FFF
1F8000-1F8FFF
32
1C0000-1C7FFF
32
70000-77FFF
F0000-F7FFF
1F0000-1F7FFF
32
1B8000-1BFFFF
32
68000-6FFFF
E8000-EFFFF
1E8000-1EFFFF
32
1B0000-1B7FFF
32
60000-67FFF
E0000-E7FFF
1E0000-1E7FFF
32
1A8000-1AFFFF
32
58000-5FFFF
D8000-DFFFF
1D8000-1DFFFF
32
1A0000-1A7FFF
32
50000-57FFF
D0000-D7FFF
1D0000-1D7FFF
32
198000-19FFFF
32
48000-4FFFF
C8000-CFFFF
1C8000-1CFFFF
32
190000-197FFF
32
40000-47FFF
C0000-C7FFF
1C0000-1C7FFF
32
188000-18FFFF
32
38000-3FFFF
B8000-BFFFF
1B8000-1BFFFF
32
180000-187FFF
32
30000-37FFF
B0000-B7FFF
1B0000-1B7FFF
32
178000-17FFFF
32
28000-2FFFF
A8000-AFFFF
1A8000-1AFFFF
32
170000-177FFF
32
20000-27FFF
A0000-A7FFF
1A0000-1A7FFF
32
168000-16FFFF
32
18000-1FFFF
98000-9FFFF
198000-19FFFF
32
160000-167FFF
32
10000-17FFF
90000-97FFF
190000-197FFF
32
158000-15FFFF
32
08000-0FFFF
88000-8FFFF
188000-18FFFF
32
150000-157FFF
32
00000-07FFF
80000-87FFF
180000-187FFF
32
148000-14FFFF
32
78000-7FFFF
178000-17FFFF
32
140000-147FFF
32
70000-77FFF
170000-177FFF
32
138000-13FFFF
32
68000-6FFFF
168000-16FFFF
32
130000-137FFF
32
60000-67FFF
160000-167FFF
32
128000-12FFFF
32
58000-5FFFF
158000-15FFFF
32
120000-127FFF
32
50000-57FFF
150000-157FFF
32
118000-11FFFF
32
48000-4FFFF
148000-14FFFF
32
110000-117FFF
32
40000-47FFF
140000-147FFF
32
108000-10FFFF
32
38000-3FFFF
138000-13FFFF
32
32
30000-37FFF
130000-137FFF
32
32
28000-2FFFF
128000-12FFFF
32
F0000-F7FFF
0F0000-0F7FFF
32
20000-27FFF
120000-127FFF
32
E8000-EFFFF
0E8000-0EFFFF
32
18000-1FFFF
118000-11FFFF
32
E0000-E7FFF
0E0000-0E7FFF
32
10000-17FFF
110000-117FFF
32
D8000-DFFFF
0D8000-0DFFFF
32
08000-0FFFF
108000-10FFFF
32
D0000-D7FFF
0D0000-0D7FFF
32
00000-07FFF
100000-107FFF
32
C8000-CFFFF
0C8000-0CFFFF
This column continues on next page
40
Size
(KW)
100000-107FFF
F8000-FFFFF
0F8000-0FFFFF
This column continues on next page
PRELIMINARY
E
SMART 3 ADVANCED BOOT BLOCK
8-Mbit, 16-Mbit, and 32-Mbit Word-Wide Memory Addressing (Continued)
Top Boot
Size
(KW)
8M
32M
Size
(KW)
16M
32M
32
0F8000-0FFFFF
32
0F0000-0F7FFF
32
C0000-C7FFF
0C0000-0C7FFF
32
B8000-BFFFF
32
0B8000-0BFFFF
0E8000-0EFFFF
32
B0000-B7FFF
0B0000-0B7FFF
32
0E0000-0E7FFF
32
A8000-AFFFF
0A8000-0AFFFF
32
0D8000-0DFFFF
32
A0000-A7FFF
0A0000-0A7FFF
32
0D0000-0D7FFF
32
98000-9FFFF
098000-09FFFF
32
0C8000-0CFFFF
32
90000-97FFF
090000-097FFF
32
0C0000-0C7FFF
32
88000-8FFFF
088000-08FFFF
32
0B8000-0BFFFF
32
80000-87FFF
080000-087FFF
32
0B0000-0B7FFF
32
78000-7FFFF
78000-7FFFF
78000-7FFFF
32
0A8000-0AFFFF
32
70000-77FFF
70000-77FFF
70000-77FFF
32
0A0000-0A7FFF
32
68000-6FFFF
68000-6FFFF
68000-6FFFF
32
098000-09FFFF
32
60000-67FFF
60000-67FFF
60000-67FFF
32
090000-097FFF
32
58000-5FFFF
58000-5FFFF
58000-5FFFF
32
088000-08FFFF
32
50000-57FFF
50000-57FFF
50000-57FFF
32
080000-087FFF
32
48000-4FFFF
48000-4FFFF
48000-4FFFF
32
078000-07FFFF
32
40000-47FFF
40000-47FFF
40000-47FFF
32
070000-077FFF
32
38000-3FFFF
38000-3FFFF
38000-3FFFF
32
068000-06FFFF
32
30000-37FFF
30000-37FFF
30000-37FFF
32
060000-067FFF
32
28000-2FFFF
28000-2FFFF
28000-2FFFF
32
058000-05FFFF
32
20000-27FFF
20000-27FFF
20000-27FFF
32
050000-057FFF
32
18000-1FFFF
18000-1FFFF
18000-1FFFF
32
048000-04FFFF
32
10000-17FFF
10000-17FFF
10000-17FFF
32
040000-047FFF
32
08000-0FFFF
08000-0FFFF
08000-0FFFF
32
038000-03FFFF
4
07000-07FFF
07000-07FFF
07000-07FFF
32
030000-037FFF
4
06000-06FFF
06000-06FFF
06000-06FFF
32
028000-02FFFF
4
05000-05FFF
05000-05FFF
05000-05FFF
32
020000-027FFF
4
04000-04FFF
04000-04FFF
04000-04FFF
32
018000-01FFFF
4
03000-03FFF
03000-03FFF
03000-03FFF
32
010000-017FFF
4
02000-02FFF
02000-02FFF
02000-02FFF
32
008000-00FFFF
4
01000-01FFF
01000-01FFF
01000-01FFF
32
000000-007FFF
4
00000-00FFF
00000-00FFF
00000-00FFF
PRELIMINARY
16M
Bottom Boot
8M
41
E
SMART 3 ADVANCED BOOT BLOCK
4-Mbit Word-Wide Memory Addressing
Top Boot
Size
(KW)
42
Bottom Boot
4M
Size
(KW)
4M
4
3F000-3FFFF
32
38000-3FFFF
4
3E000-3EFFF
32
30000-37FFF
4
3D000-3DFFF
32
28000-2FFFF
4
3C000-3CFFF
32
20000-27FFF
4
3B000-3BFFF
32
18000-1FFFF
4
3A000-3AFFF
32
10000-017FFF
4
39000-39FFF
32
08000-0FFFF
4
38000-38FFF
4
07000-07FFF
32
30000-037FFF
4
06000-06FFF
32
28000-2FFFF
4
05000-05FFF
32
20000-2FFFF
4
04000-04FFF
32
18000-1FFFF
4
03000-03FFF
32
10000-017FFF
4
02000-02FFF
32
08000-0FFFF
4
01000-01FFF
32
00000-07FFF
4
00000-00FFF
PRELIMINARY
E
SMART 3 ADVANCED BOOT BLOCK
APPENDIX E
BYTE-WIDE MEMORY MAP DIAGRAMS
Byte-Wide Memory Addressing
Top Boot
Size
(KB)
8M
Bottom Boot
16M
32M
Size
(KB)
8M
16M
32M
8
FE000-FFFFF
1FE000-1FFFFF
3FE000-3FFFFF
64
3F0000-3FFFFF
8
FC000-FDFFF
1FC000-1FDFFF
3FC000-3FDFFF
64
3E0000-3EFFFF
8
FA000-FBFFF
1FA000-1FBFFF
3FA000-3FBFFF
64
3D0000-3DFFFF
8
F8000-F9FFF
1F8000-1F9FFF
3F8000-3F9FFF
64
3C0000-3CFFFF
8
F6000-F7FFF
1F6000-1F7FFF
3F6000-3F7FFF
64
3B0000-3BFFFF
8
F4000-F5FFF
1F4000-1F5FFF
3F4000-3F5FFF
64
3A0000-3AFFFF
8
F2000-F3FFF
1F2000-1F3FFF
3F2000-3F3FFF
64
390000-39FFFF
8
F0000-F1FFF
1F0000-1F1FFF
3F0000-3F1FFF
64
380000-38FFFF
64
E0000-EFFFF
1E0000-1EFFFF
3E0000-3EFFFF
64
370000-37FFFF
64
D0000-DFFFF
1D0000-1DFFFF
3D0000-3DFFFF
64
360000-36FFFF
64
C0000-CFFFF
1C0000-1CFFFF
3C0000-3CFFFF
64
350000-35FFFF
64
B0000-BFFFF
1B0000-1BFFFF
3B0000-3BFFFF
64
340000-34FFFF
64
A0000-AFFFF
1A0000-1AFFFF
3A0000-3AFFFF
64
330000-33FFFF
64
90000-9FFFF
190000-19FFFF
390000-39FFFF
64
320000-32FFFF
64
80000-8FFFF
180000-18FFFF
380000-38FFFF
64
310000-31FFFF
64
70000-7FFFF
170000-17FFFF
370000-37FFFF
64
300000-30FFFF
64
60000-6FFFF
160000-16FFFF
360000-36FFFF
64
2F0000-2FFFFF
64
50000-5FFFF
150000-15FFFF
350000-35FFFF
64
2E0000-2EFFFF
64
40000-4FFFF
140000-14FFFF
340000-34FFFF
64
2D0000-2DFFFF
64
30000-3FFFF
130000-13FFFF
330000-33FFFF
64
2C0000-2CFFFF
64
20000-2FFFF
120000-12FFFF
320000-32FFFF
64
2B0000-2BFFFF
64
10000-1FFFF
110000-11FFFF
310000-31FFFF
64
2A0000-2AFFFF
64
00000-0FFFF
100000-10FFFF
300000-30FFFF
64
290000-29FFFF
64
0F0000-0FFFFF
2F0000-2FFFFF
64
280000-28FFFF
64
0E0000-0EFFFF
2E0000-2EFFFF
64
270000-27FFFF
64
0D0000-0DFFFF
2D0000-2DFFFF
64
260000-26FFFF
64
0C0000-0CFFFF
2C0000-2CFFFF
64
250000-25FFFF
64
0B0000-0BFFFF
2B0000-2BFFFF
64
240000-24FFFF
64
0A0000-0AFFFF
2A0000-2AFFFF
64
230000-23FFFF
64
090000-09FFFF
290000-29FFFF
64
220000-22FFFF
64
080000-08FFFF
280000-28FFFF
64
210000-21FFFF
070000-07FFFF
270000-27FFFF
64
64
060000-06FFFF
260000-26FFFF
64
64
050000-05FFFF
250000-25FFFF
64
1E0000-1EFFFF
1E0000-1EFFFF
64
040000-04FFFF
240000-24FFFF
64
1D0000-1DFFFF
1D0000-1DFFFF
64
030000-03FFFF
230000-23FFFF
64
1C0000-1CFFFF
1C0000-1CFFFF
64
020000-02FFFF
220000-22FFFF
64
1B0000-1BFFFF
1B0000-1BFFFF
64
010000-01FFFF
210000-21FFFF
64
1A0000-1AFFFF
1A0000-1AFFFF
64
000000-00FFFF
200000-20FFFF
64
190000-19FFFF
190000-19FFFF
64
This column continues on next page
PRELIMINARY
200000-20FFFF
1F0000-1FFFFF
1F0000-1FFFFF
This column continues on next page
43
E
SMART 3 ADVANCED BOOT BLOCK
Byte-Wide Memory Addressing (Continued)
Top Boot
Size
(KB)
44
8M
16M
Bottom Boot
32M
Size
(KB)
8M
16M
32M
64
1F0000-1FFFFF
64
180000-18FFFF
180000-18FFFF
64
1E0000-1EFFFF
64
170000-17FFFF
170000-17FFFF
64
1D0000-1DFFFF
64
160000-16FFFF
160000-16FFFF
64
1C0000-1CFFFF
64
150000-15FFFF
150000-15FFFF
64
1B0000-1BFFFF
64
140000-14FFFF
140000-14FFFF
64
1A0000-1AFFFF
64
130000-13FFFF
130000-13FFFF
64
190000-19FFFF
64
120000-12FFFF
120000-12FFFF
64
180000-18FFFF
64
110000-11FFFF
110000-11FFFF
64
170000-17FFFF
64
100000-10FFFF
100000-10FFFF
64
160000-16FFFF
64
0F0000-0FFFFF
0F0000-0FFFFF
64
150000-15FFFF
64
E0000-EFFFF
0E0000-0EFFFF
0E0000-0EFFFF
64
140000-14FFFF
64
D0000-DFFFF
0D0000-0DFFFF
0D0000-0DFFFF
64
130000-13FFFF
64
C0000-CFFFF
0C0000-0CFFFF
0C0000-0CFFFF
64
120000-12FFFF
64
B0000-BFFFF
0B0000-0BFFFF
0B0000-0BFFFF
64
110000-11FFFF
64
A0000-AFFFF
0A0000-0AFFFF
0A0000-0AFFFF
64
100000-10FFFF
64
90000-9FFFF
090000-09FFFF
090000-09FFFF
64
0F0000-0FFFFF
64
80000-8FFFF
080000-08FFFF
080000-08FFFF
64
0E0000-0EFFFF
64
70000-7FFFF
070000-07FFFF
070000-07FFFF
64
0D0000-0DFFFF
64
60000-6FFFF
060000-06FFFF
060000-06FFFF
64
0C0000-0CFFFF
64
50000-5FFFF
050000-05FFFF
050000-05FFFF
64
0B0000-0BFFFF
64
40000-4FFFF
040000-04FFFF
040000-04FFFF
64
0A0000-0AFFFF
64
30000-3FFFF
030000-03FFFF
030000-03FFFF
64
090000-09FFFF
64
20000-2FFFF
020000-02FFFF
020000-02FFFF
64
080000-08FFFF
64
10000-1FFFF
010000-01FFFF
010000-01FFFF
64
070000-07FFFF
8
0E000-0FFFF
00E000-00FFFF
00E000-00FFFF
64
060000-06FFFF
8
0C000-0DFFF
00C000-00DFFF
00C000-00DFFF
64
050000-05FFFF
8
0A000-0BFFF
00A000-00BFFF
00A000-00BFFF
64
040000-04FFFF
8
08000-09FFF
008000-009FFF
008000-009FFF
64
030000-03FFFF
8
06000-07FFF
006000-007FFF
006000-007FFF
64
020000-02FFFF
8
04000-05FFF
004000-005FFF
004000-005FFF
64
010000-01FFFF
8
02000-03FFF
002000-003FFF
002000-003FFF
64
000000-00FFFF
8
00000-01FFF
000000-001FFF
000000-001FFF
F0000-FFFFF
PRELIMINARY
E
SMART 3 ADVANCED BOOT BLOCK
APPENDIX F
PROGRAM AND ERASE FLOWCHARTS
Start
Write 40H
Bus Operation
Command
Write
Program Setup
Write
Program
Program Address/Data
Data = 40H
Data = Data to Program
Addr = Location to Program
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Read
Read Status Register
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Repeat for subsequent programming operations.
No
SR.7 = 1?
Comments
SR Full Status Check can be done after each program or after a sequence of
program operations.
Yes
Write FFH after the last program operation to reset device to read array mode.
Full Status
Check if Desired
Program Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
Bus Operation
1
SR.3 =
0
VPP Range Error
Programming Error
0
1
SR.1 =
Comments
Standby
Check SR.3
1 = VPP Low Detect
Standby
Check SR.4
1 = VPP Program Error
Standby
Check SR.1
1 = Attempted Program to
Locked Block - Program
Aborted
1
SR.4 =
Command
SR.3 MUST be cleared, if set during a program attempt, before further
attempts are allowed by the Write State Machine.
Attempted Program to
Locked Block - Aborted
SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command,
in cases where multiple bytes are programmed before full status is checked.
0
Program Successful
If an error is detected, clear the status register before attempting retry or other
error recovery.
0580_E1
Figure 10. Program Flowchart
PRELIMINARY
45
E
SMART 3 ADVANCED BOOT BLOCK
Start
Bus
Operation
Command
Write
Program
Suspend
Comments
Data = B0H
Addr = X
Write B0H
Write
Read
Write 70H
Read Status
Standby
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Addr = X
Standby
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Read
Read Status Register
0
SR.7 =
1
0
SR.2 =
Program Completed
Check SR.2
1 = Program Suspended
0 = Program Completed
Standby
Write
Read Array
Write
Read
Read Array
Read
Write
Program
Resume
Read array data from block
other than the one being
programmed.
Write
Program
Resume
Data = D0H
Addr = X
1
Write FFH
Data=70H
Addr=X
Data = FFH
Addr = X
Read Array Data
No
Done
Reading
Yes
Write D0H
Write FFH
Program Resumed
Read Array Data
0580_E2
Figure 11. Program Suspend/Resume Flowchart
46
PRELIMINARY
E
SMART 3 ADVANCED BOOT BLOCK
Start
Bus Operation
Write 20H
Write D0H and
Block Address
Command
Write
Erase Setup
Write
Erase Confirm
Data = D0H
Addr = Within Block to Be
Erased
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Read
Read Status Register
Suspend
Erase Loop
0
SR.7 =
No
Suspend Erase
Comments
Data = 20H
Addr = Within Block to Be
Erased
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Yes
Repeat for subsequent block erasures.
Full Status Check can be done after each block erase or after a sequence of
block erasures.
1
Full Status
Check if Desired
Write FFH after the last write operation to reset device to read array mode.
Block Erase Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
Bus Operation
1
SR.3 =
0
1
Command Sequence
Error
0
Check SR.3
1 = VPP Low Detect
Standby
Check SR.4,5
Both 1 = Command Sequence
Error
Standby
Check SR.5
1 = Block Erase Error
Standby
Check SR.1
1 = Attempted Erase of
Locked Block - Erase Aborted
1
SR.5 =
Block Erase Error
Comments
Standby
VPP Range Error
SR.4,5 =
Command
SR. 1 and 3 MUST be cleared, if set during an erase attempt, before further
attempts are allowed by the Write State Machine.
0
1
SR.1 =
0
Attempted Erase of
Locked Block - Aborted
SR.1, 3, 4, 5 are only cleared by the Clear Staus Register Command, in cases
where multiple bytes are erased before full status is checked.
If an error is detected, clear the status register before attempting retry or other
error recovery.
Block Erase
Successful
0580_E3
Figure 12. Block Erase Flowchart
PRELIMINARY
47
E
SMART 3 ADVANCED BOOT BLOCK
Bus
Operation
Start
Write
Command
Comments
Program
Data = B0H
Erase Suspend
Suspend
Addr = X
Write B0H
Write
Read
Write 70H
Data=70H
Addr=X
Read Status
Standby
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Addr = X
Standby
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Read
Read Status Register
0
SR.7 =
1
0
SR.6 =
Erase Completed
Check SR.6
1 = Erase Suspended
0 = Erase Completed
Standby
Write
Read Array
Write
Read
Read Array
Read
Write
Program
Resume
Write
Erase Resume
Data = FFH
Addr = X
Read array data from block
other than the one being
erased.
1
Write FFH
Data = D0H
Addr = X
Read Array Data
No
Done
Reading
Yes
Write D0H
Write FFH
Erase Resumed
Read Array Data
0580_E4
Figure 13. Erase Suspend/Resume Flowchart
48
PRELIMINARY