ICST ICS85211AMI-01T Low skew, 1-to-2 differential-to-hstl fanout buffer Datasheet

ICS85211I-01
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS85211I-01 is a low skew, high performance 1-to-2 Differential-to-HSTL Fanout Buffer
HiPerClockS™
and a member of the HiPerClockS™ family of
High Performance Clock Solutions from ICS.
The CLK, nCLK pair can accept most standard
differential input levels.The ICS85211I-01 is characterized to
operate from a 3.3V power supply. Guaranteed output and
part-to-part skew characteristics make the ICS85211I-01
ideal for those clock distribution applications demanding
well defined performance and repeatability. For optimal
performance, terminate all outputs.
• Two differential HSTL compatible outputs
ICS
• One differential CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, HSTL, SSTL, HCSL
• Maximum output frequency: 700MHz
• Translates any single-ended input signal to HSTL
levels with resistor bias on nCLK input
• Output skew: 30ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Propagation delay: 1ns (maximum)
• Output crossover Voltage: 0.68V to 0.9V
• Output duty cycle: 49% - 51% up to 266.6MHz
• VOH = 1.4V (maximum)
• 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
CLK
nCLK
PIN ASSIGNMENT
Q0
nQ0
Q1
nQ1
Q0
nQ0
Q1
nQ1
1
2
3
4
8
7
6
5
VDD
CLK
nCLK
GND
ICS85211I-01
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
85211AMI-01
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1
REV. A NOVEMBER 1, 2005
ICS85211I-01
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
1, 2
Q0, nQ0
Output
Type
Description
3, 4
Q1, nQ1
Output
Differential output pair. HSTL interface levels.
5
GN D
Power
Power supply ground.
6
nCLK
Input
7
CLK
Input
8
VDD
Power
Differential output pair. HSTL interface levels.
Pullup/
Pulldown
Pulldown
Inver ting differential clock input. VDD/2 default when left floating.
Non-inver ting differential clock input.
Positive supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
Test Conditions
Minimum
Typical
4
Maximum
Units
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
TABLE 3. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
CLK
nCLK
Q0, Q1
nQ0, nQ1
0
0
LOW
HIGH
Input to Output Mode
Polarity
Differential to Differential
Non Inver ting
1
1
HIGH
LOW
Differential to Differential
Non Inver ting
0
Biased; NOTE 1
LOW
HIGH
Single Ended to Differential
Non Inver ting
1
Biased; NOTE 1
HIGH
LOW
Single Ended to Differential
Non Inver ting
Biased; NOTE 1
0
HIGH
LOW
Single Ended to Differential
Inver ting
Biased; NOTE 1
1
LOW
HIGH
Single Ended to Differential
Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
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REV. A NOVEMBER 1, 2005
ICS85211I-01
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VDD
-0.5V to VDD + 0.5 V
Outputs, VDD
-0.5V to VDD + 0.5V
Package Thermal Impedance, θJA
112.7°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V ± 5%, TA = -40°C TO 85°C
Symbol
Parameter
VDD
Power Supply Voltage
Test Conditions
IDD
Power Supply Current
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
22
mA
Maximum
Units
TABLE 4B. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V ± 5%, TA = -40°C TO 85°C
Symbol
Parameter
IIH
Input High Current
IIL
Input Low Current
Test Conditions
Minimum
Typical
nCLK
VDD = VIN = 3.465V
150
µA
CLK
VDD = VIN = 3.465V
150
µA
nCLK
VDD = 3.465V, VIN = 0V
-150
µA
CLK
VDD = 3.465V, VIN = 0V
-5
µA
Peak-to-Peak Input Voltage
0.15
Common Mode Input Voltage;
VCMR
0.5
NOTE 1, 2
NOTE 1: For single ended applications the maximum input voltage for CLK and nCLK is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
1.3
V
VDD - 0.85
V
Maximum
Units
1.0
1.4
V
VPP
TABLE 4C. HSTL DC CHARACTERISTICS, VDD = 3.3V ± 5%, TA = -40°C TO 85°C
Symbol Parameter
VOH
Output High Voltage; NOTE 1
Test Conditions
Minimum
Typical
VOL
Output Low Voltage; NOTE 1
0
0.4
V
VOX
Output Crossover Voltage
0.68
0.9
V
VSWING
Peak-to-Peak Output Voltage Swing
0.6
1.4
V
1.0
NOTE 1: All outputs must be terminated with 50Ω to ground.
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REV. A NOVEMBER 1, 2005
ICS85211I-01
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V ± 5%, TA = -40°C TO 85°C
Symbol
Parameter
fMAX
Output Frequency
tPD
Propagation Delay; NOTE 1
t sk(o)
Output Skew; NOTE 2, 4
t sk(pp)
Par t-to-Par t Skew; NOTE 3, 4
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
Test Conditions
IJ 600MHz
20% to 80%
Minimum
0.7
Typical
Maximum
Units
700
MHz
1.0
ns
30
ps
250
ps
200
500
ps
48
52
%
IJ 266.6MHz
49
51
%
All parameters measured at 600MHz unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The par t does not add jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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REV. A NOVEMBER 1, 2005
ICS85211I-01
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
3.3V±5%
V DD
Qx
V DD
SCOPE
nCLK
HSTL
V
Cross Points
PP
V
CMR
CLK
nQx
GND
GND
0V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
Qx
PART 1
nQx
Qx
Qy
PART 2
nQy
nQy
Qy
tsk(pp)
tsk(o)
OUTPUT SKEW
PART-TO-PART SKEW
nCLK
80%
80%
CLK
VSW I N G
Clock
Outputs
nQ0, nQ1
20%
20%
tF
tR
Q0, Q1
tPD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
nQ0, nQ1
Q0, Q1
t PW
t
odc =
PERIOD
t PW
x 100%
t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV. A NOVEMBER 1, 2005
ICS85211I-01
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
CLK
V_REF
nCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
SCHEMATIC EXAMPLE
Figure 2 shows a schematic example of ICS85211I-01. In this
example, the input is driven by an ICS HiPerClockS HSTL driver.
The decoupling capacitors should be physically located near
the power pin. For ICS85211I-01, the unused outputs
need to be terminated.
Zo = 50 Ohm
1.8V
-
U1
Zo = 50 Ohm
5
6
7
8
Zo = 50 Ohm
nQ1
Q1
nQ0
Q0
VDD=3.3V
LVHSTL
ICS
HiPerClockS
LVHSTL Driv er
GND
nCLK
CLK
VDD
R6
50
R5
50
4
3
2
1
Zo = 50 Ohm
+
R1
50
R2
50
LVHSTL Input
ICS85211-01
C1
0.1u
R3
50
Unused
R4 Output
50 Need To
Be
Terminated
FIGURE 2. ICS85211I-01 HSTL BUFFER SCHEMATIC EXAMPLE
85211AMI-01
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REV. A NOVEMBER 1, 2005
ICS85211I-01
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
RECOMMENDATIONS FOR UNUSED OUTPUT PINS
OUTPUTS:
HSTL OUTPUT
All unused HSTL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
CLOCK INPUT INTERFACE
of the driver components to confirm the driver termination requirement. For example in Figure 3, the input termination applies for
ICS HiPerClockS HSTL drivers. If you are using an HSTL driver
from another vendor, use their termination recommendation.
The CLK /nCLK accepts differential input signals of both VSWING
and VOH to meet the VPP and VCMR input requirements. Figures 3A
to 3D show interface examples for the ICS85211I-01 clock input
driven by most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
R1
50
HiPerClockS
Input
LVPECL
nCLK
R1
50
R2
50
R2
50
R3
50
FIGURE 3A. ICS85211I-01 CLK/NCLK INPUT DRIVEN
HIPERCLOCKS HSTL DRIVER
FIGURE 3B. ICS85211I-01 CLK/NCLK INPUT DRIVEN
3.3V LVPECL DRIVER (INTERFACE 1)
BY
BY
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
LVPECL
Zo = 50 Ohm
C1
Zo = 50 Ohm
C2
R3
125
R4
125
Zo = 50 Ohm
CLK
CLK
Zo = 50 Ohm
nCLK
nCLK
LVPECL
R1
84
HiPerClockS
Input
R5
100-200
R2
84
R6
100-200
R1
84
HiPerClockS
Input
R2
84
R5,R6 locate near the driv er pin.
FIGURE 3C. ICS85211I-01 CLK/NCLK INPUT DRIVEN
3.3V LVPECL DRIVER (INTERFACE 2)
85211AMI-01
FIGURE 3D. ICS85211I-01 CLK/NCLK INPUT DRIVEN
3.3V LVPECL DRIVER WITH AC COUPLE
BY
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REV. A NOVEMBER 1, 2005
ICS85211I-01
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85211I-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85211I-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 22mA = 76.2mW
Power (outputs)MAX = 82.34mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 82.34mW = 164.7mW
Total Power_MAX (3.465V, with all outputs switching) = 76.2mW + 164.7mW = 240.9mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.241W * 103.3°C/W = 110°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA
FOR
8-PIN SOIC, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
153.3°C/W
112.7°C/W
128.5°C/W
103.3°C/W
115.5°C/W
97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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REV. A NOVEMBER 1, 2005
ICS85211I-01
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LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
HSTL output driver circuit and termination are shown in Figure 4.
VDD
Q1
VOUT
RL
50Ω
FIGURE 4. HSTL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (VOH_MAX /R ) * (VDD_MAX - V
L
)
OH_MAX
Pd_L = (VOL_MAX /R ) * (VDD_MAX - VOL_MAX)
L
Pd_H = (1.4V/50Ω) * (3.465V - 1.4V) = 57.82mW
Pd_L = (0.4V/50Ω) * (3.465V - 0.4V) = 24.52mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 82.34mW
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REV. A NOVEMBER 1, 2005
ICS85211I-01
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
153.3°C/W
112.7°C/W
128.5°C/W
103.3°C/W
115.5°C/W
97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85211I-01 is: 411
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REV. A NOVEMBER 1, 2005
ICS85211I-01
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC
TABLE 8. PACKAGE DIMENSIONS
SYMBOL
Millimeters
MINIMUN
N
MAXIMUM
8
A
1.35
1.75
A1
0.10
0.25
B
0.33
0.51
C
0.19
0.25
D
4.80
5.00
E
3.80
4.00
e
1.27 BASIC
H
5.80
6.20
h
0.25
0.50
L
0.40
1.27
α
0°
8°
Reference Document: JEDEC Publication 95, MS-012
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REV. A NOVEMBER 1, 2005
ICS85211I-01
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS85211AMI-01
5211AI01
8 lead SOIC
tube
-40°C to 85°C
ICS85211AMI-01T
5211AI01
8 lead SOIC
2500 tape & reel
-40°C to 85°C
ICS85211AMI-01LF
211AI01L
8 lead "Lead-Free" SOIC
tube
-40°C to 85°C
ICS85211AMI-01LFT
211AI01L
8 lead "Lead-Free" SOIC
2500 tape & reel
-40°C to 85°C
NOTE: Par ts thar are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement
of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional
processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices
or critical medical instruments.
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REV. A NOVEMBER 1, 2005
ICS85211I-01
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
REVISION HISTORY SHEET
Rev
A
Table
Page
1
2
2
2
Throughout data sheet changed LVHSTL to HSTL.
Changed nCLK Type from VDD/2 to Pullup/Pulldown.
Pin Characteristics Table - changed CIN 4pF max. to 4pF typical.
Changed RPULLUP to RPULLUP/RPULLDOWN, Pullup/Pulldown Resistors.
7/16/03
Features section - added Lead Free/RoHS bullet.
Added Recommendations for Unused Output Pins.
Ordering Information Table - added Lead-Free par t number and marking.
11/01/05
T9
1
7
12
A
85211AMI-01
Description of Change
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Date
REV. A NOVEMBER 1, 2005
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