www.fairchildsemi.com FAN8048 2 DC-DC Converter & 4-CH PWM Motor IC Features H-Bridge PWM Driver • 4 Channels direct PWM H-bridge drivers • Digital input and direct PWM output • Internal power switches Descripation The FAN8048 is a monolithic integrated circuit suitable for a 4 channels direct PWM H-bridge driver which incorporates two switch-mode step up-down converter with synchronous rectification provides local microprocessor and servo IC power in portable CD players and portable devices. - ON state resistance : 2.0 Ω (typ.), which value added the upper and the lower switches Synchronous DC-DC Converter • • • • Built-in step up converter (VG converter) Built-in two synchronous step up-down converter Built-in short circuit protection Internal Switches 48-LQFP-0707 - Power Switch : 0.4Ω (typ.) at 500mA -. Synchronous-Rectifier Switch : 0.4Ω (typ.) at 500mA Others • • • • • Built-in power-on reset circuit Built-in battery charge circuit Built-in voltage regulator control circuit Built-in thermal shutdown (TSD) circuit Buit-in channel mute circuit Typical application • Portable CD-MP3 player Ordering Information Device Package Operating Temp. FAN8048 48-LQFP-0707 -30°C ~ +85°C Rev. 1.0.0 ©2004 Fairchild Semiconductor Corporation FAN8048 Pin Assignments LG 48 PGND CH1+ CH147 46 45 CH2+ CH2- PVCC CH3+ 44 43 41 CH4- PGND 40 38 37 39 VG 1 36 CH4F RST 2 35 CH4R OFF 3 34 CH3F ON 4 33 CH3R SPRT 5 32 CH2F SPGND 6 31 CH2R PCT 7 30 CH1 CLK 8 29 MUTE SOFT 9 28 DGND EA1O 10 27 CHGSW EA1- 11 26 CHGCON EA2O 12 25 CHGSEN FAN8048 13 14 15 16 17 18 EA2- VSYS2 USW2 PGND DSW2 VIN 2 42 CH3- CH4+ 19 DSW1 20 21 22 23 PGND USW1 VSYS1 REG 24 DCIN FAN8048 Pin Definitions Pin Number Pin Name I/O Pin Function Description 1 VG - Gate voltage for power MOSFET drive 2 RST O Power-on reset output 3 OFF I System-off signal input 4 ON I System-on signal input 5 SPRT - Short circuit protection delay time setting capacitor 6 SGND - Pre-driver ground 7 PCT - Triangular waveform pin 8 CLK I Clock input 9 SOFT - Soft start time setting capacitor of DC-DC converter 1 and 2 10 EA1O O Error amplifier output of DC-DC Converter1 11 EA1- I Error amplifier inverting input of DC-DC converter1 12 EA2O O Error amplifier output of DC-DC converter2 13 EA2- I Error amplifier inverting input of DC-DC converter2 14 VSYS2 - Output of DC-DC converter2 15 USW2 - DC-DCconvereter2 coil driving pin 1 16 PGND - Power ground 17 DSW2 - DC-DC convereter2 coil driving pin 2 18 VIN - Input voltage of DC-DC coverter 1 and 2 19 DSW1 - DC-DC convereter1 coil driving pin 2 20 PGND - Power ground 21 USW1 - DC-DC convereter1 coil driving pin 1 22 VSYS1 - Output of DC-DC converter1 23 REG O Regulator control output 24 DCIN - Adaptor power supply input pin 25 CHGSEN I Charger current sense Input 26 CHGCON O Charger control output 27 CHGSW I Charger mode switch input 28 DGND - Digital circuit ground 29 MUTE I Channel mute input 30 CH1 I CH1 input pin 31 CH2R I CH2 reverse input pin 32 CH2F I CH2 forward input pin 33 CH3R I CH3 reverse input pin 34 CH3F I CH3 forward input pin 35 CH4R I CH4 reverse input pin 36 CH4F I CH4 forward input pin 37 PGND - Power ground 38 CH4- O Channel 4 negative output 39 CH4+ O Channel 4 positive output 40 CH3- O Channel 3 negative output 41 CH3+ O Channel 3 positive output 42 PVCC - Power supply for H-bridge driver 43 CH2- O Channel 2 negative output 44 CH2+ O Channel 2 positive output 3 FAN8048 Pin Definitions (Continued) 4 Pin Number Pin Name I/O Pin Function Description 45 CH1- O Channel 1 negative output 46 CH1+ O Channel 1 positive output 47 PGND - Power ground 48 LG - VG voltage up coil driving pin FAN8048 Internal Block Diagram LG PGND 48 47 CH1+ CH1- CH2+ CH2- PVCC CH3+ CH3- CH4+ CH4- PGND 45 44 43 42 41 40 39 38 37 46 S1 S3 S2 S4 1 VIN VSYS1 PRE-DRIVER VSYS2 CH4F RST D R V 2 CH3F CH2R VSYS1 3-State Input Control CH2F CH1R 3 ON 4 SPRT 5 SGND 6 PCT 7 CLK 8 SOFT EA1O CH4R CH3R 0.5V OFF S2 S3 S4 S1 VG PVCC H-Bridge 3 H-Bridge 4 H-Bridge 2 PVCC PVCC PVCC H-Bridge 1 SYSTEM OFF SYSTEM Control CH1F 36 CH4F 35 CH4R 34 CH3F 33 CH3R 32 CH2F 31 CH2R 30 CH1 29 MUTE 28 DGND 27 CHGSW 26 CHGCON 25 CHGSEN SYSTEM ON OSC Battery Charger Switch 9 STEP UP/DOWN CONVERTER 2 STEP UP/DOWN CONVERTER 1 Driver & Logic 10 Driver & Logic 0.9V EA1- Regulator & Current Control 11 0.9V EA2O 12 13 EAI2- 14 15 16 VSYS2 USW2 PGND 17 DSW2 18 VIN 19 20 21 22 DSW1 PGND USW1 VSYS1 23 REG 24 DCIN 5 FAN8048 Absolute Maximum Ratings (Ta = 25×C) Parameter Symbol Value Unit PVCC 7 V Predriver supply voltage VG 12 V Primary side input voltage of DC-DC converter VIN 7 V Output voltage of DC-DC converter1 VSYS1 7 V Output voltage of DC-DC converter2 VSYS2 7 V AC adapter supply voltage VDCIN 12 V H-bridge driver output current IO 500 mA Power dissipation PD 1.0 W Operating temperature TOPR -30 ~ +85 °C Stroage temperature TSTG -55 ~ +150 °C H-bridge driver supply voltage Power Dissipation Curve (Air Condition = 0m/S) PD[W] 1.75 1.5 1.25 1 0.75 SOA 0.5 0.25 0 0 25 50 75 100 125 150 Ambient Temperature [℃] Notes: 1. When mounted on 2mm × 114.3mm × 1.6mm PCB (FR-4 glass epoxy material). 2. Refer: EIA/ J SED 51-2 and EIA/ J SED 51-3 JSED51-2 : Integrated circuits thermal test method environmental conditions - Natural convection JSED51-3 : Low effective thermal conductivity test board for leaded surface mount packages 3. Do not exceed PD and SOA(Safe Operating Area). Recommended Operating Conditions (Ta = 25×C) Parameter Symbol Min. Typ. Max. Unit PVCC 1.2 2.4 4.5 V VIN 1.8 2.4 4.5 V Output voltage of DC-DC converter1 VSYS1 2.0 - 3.6 V Output voltage of DC-DC converter2 VSYS2 1.6 - VSYS1 V DCIN 5.0 7.0 10.0 V H-bridge driver supply voltage Power supply of DC-DC converter AC adaptor supply voltage 6 FAN8048 Electrical characteristics (PVCC=VIN=2.4V, VSYS1=VSYS2=2.7V, VG=7.0V, DCIN=0V, CPCT=470pF, Ta=25°C,unless otherwise specifid) Parameter Symbol Conditions IPVCC - Min. Typ. Max. Unit CURRENT PVCC quiescent current VIN operating current - - 3.0 µA IVIN VON = 0V - 1.6 3.0 mA DCIN operating current IDCIN DCIN = 5V - - 1.0 mA VG operating current1 IVG Non driving 4 channels - 1.0 1.5 mA Driving by 4 channels - 1.5 2.0 mA VG operating current2 (Note1) IVG4CH VSYS1 operating current IVSYS1 - 3.0 5.0 mA VSYS2 operating current IVSYS2 - - 1.0 mA IVG=1mA 6.0 7.0 8.0 V VVGST VG=3 → 5V Sweep 3.3 3.9 4.5 V FLG VG=3.5V, VLG=5V 65 100 135 KHz VIN=2.0V, ISYS=100mA 2.58 2.7 2.82 V VIN=2.0V, ISYS=0 to 150mA -30 1.0 30 mV VIN=3.0V, ISYS=100mA 2.58 2.7 2.82 V SYNCHRONOUS DC-DC CONVERTER PART VG CONVERTER PART VG output voltage VG converter start voltage Oscillation frequency VVG STEP UP/DOWN CONVERTER (COMMON)) VSYS voltage at voltage up mode VUP VSYS Load Stability at voltage up mode ∆VUP VSYS voltage at voltage down mode VDOWN VSYS load stability at voltage down mode ∆VDOWN VIN=3.0V, ISYS=0 to 150mA -30 1.0 30 mV VSYS output stability at voltage up/down ∆VUPDW ∆VUPDW=VUP-VDOWN -30 0 30 mV ERROR AMPLIFIER Error amplifier threshold voltage Error amplifier output voltage Error amplifier input current Error amplifier source current Error amplifier sink current VEINTH - 0.86 0.9 0.94 V VEOL - - 0.16 0.2 V -1 0.1 1 µA 150 - - µA 1 - - mA 1.20 1.35 1.45 V IEIN VEI=0.8V IESOURCE VEO=0V, VEI=0V IESINK - VSYS1 OPTION CIRCUIT Error amplifier1 short circuit detection voltage Veos SPRT=L → H SPRT input current1 Isprt1 VEI=0V, VSPRT=0V -9 -6 -4 µA SPRT input current2 Isprt2 OFF=VSPRT=0V -16 -12 -8 µA SPRT threshold voltage Vsprth VPCT=0.3V, VEO=0.4V,VEI=0V, DSW=H → L 0.4 0.5 0.6 V SOFT input current Isoft VSOFT=0V -13 -10 -7 µA SPRT/SOFT discharge reset voltage Vdis VSYS1=1.3 → 1.7V VSPRT, VSOFT=L → H 1.30 1.48 1.62 V Voltage in switching between the starter and normal modes Vstn VSYS1=1.5 →2.0 V,DSW=H → L 1.70 1.84 1.95 V VSYS1=1.5 →2.0 V 100 200 300 mV Vstn hysterisis voltage (Note1) Vsthys 7 FAN8048 Electrical characteristics (Continued) (PVCC=VIN=2.4V, VSYS1=VSYS2=2.7V, VG=7.0V, DCIN=0V, CPCT=470pF, Ta=25°C,unless otherwise specifid) Parameter Symbol Conditions Min. Typ. Max. Unit VSYS2 OPTION CIRCUIT VSYS2 voltage at buck mode operation Load stability of VSYS2 at buck mode operation VBUCK VIN=2.4V, VSYS2=1.8V ISYS2=100mA - 1.8 - V VLS VIN=2.4V, VSYS2=1.8V ISYS2=0 → 100mA -30 0 30 mV OSCILLATOR (PCT) Source current Sink current ISOURCE - 34 42 50 µA ISINK - 11 14 17 µA Oscillation frequency1 FOSC1 No CLK, At self oscillation 45 60 75 KHz Oscillation frequency2 FOSC2 CLK=88.2kHz, At synchronization mode 85.2 88.2 91.2 KHz Maximum duty ratio (Note1) DMAX CLK=88.2kHz 75 % OUTPUT SWITCHES On resistance of upper switch RONSWU Switch A and D, ISYS=500mA - 0.4 0.6 Ω On resistance of lower switch RONSWL Switch B and C, ISYS=500mA - 0.4 0.6 Ω Leakage current of upper switch ILSWU Switch A and D - 0 2 µA Leakage current of lower switch ILSWL Switch B and C - 0 2 µA VRST1 VIN=2.4V, VSYS2=1.0 → 1.8V 1.20 1.35 1.50 V ∆VRST1 VIN=2.4V, VSYS2=1.8 → 1.0V 40 70 100 mV VRST2 VSYS2=2.7V, VIN=1.0 → 1.8V 1.30 1.45 1.60 V ∆VRST2 VSYS2=2.7V, VIN=1.8 → 1.0V 50 80 110 mV VONTH VSYS1=VSYS2=0V - VIN 0.65 VONL VSYS1=VSYS2=0V VIN -1.0 - - V 6 16 26 µA POWER-ON RESET RST threshold voltage1 Hysteresis voltage1 RST threshold voltage2 Hysteresis voltage2 CONTROL INPUT System-on threshold voltage System-on input low level voltage System-on input current System-off threshold voltage System-off input low level voltage System-off input current ION VON=0V VOFFTH - VOFFL - IOFF - V VSYS11.15 V VSYS11.4 - V -85 -70 -55 µA - 2.0 3.0 Ω H-BRIDGE PWM DRIVER PART (CH1) 8 Out on Resistance RON1 Input Resistance RIN1 - - 50 - KΩ High level Input voltage VIH1 - 2.2 - - V Low level Input voltage VIL1 - - - 0.5 V Rising Time (Note1) TRISE1 - - 0.2 - µs Falling Time (Note1) TFALL1 - - 0.2 - µs Minimum Pulse Width (Note1) TMIN1 - - 300 - ns Top + bottom switches FAN8048 Electrical characteristics (Continued) (PVCC=VIN=2.4V, VSYS1=VSYS2=2.7V, VG=7.0V, DCIN=0V, CPCT=470pF, Ta=25°C,unless otherwise specifid) Parameter Symbol Conditions Min. Typ. Max. Unit Out on Resistance RON Top + bottom switches - 2.0 3.0 Ω Input Resistance RIN - - 30 - KΩ High level Input voltage VIH - 2.2 - - V Low level Input voltage VIL - - - 0.5 V Rising Time (Note1) TRISE - - 0.2 - µs Falling Time (Note1) TFALL - - 0.2 - µs Minimum Pulse Width (Note1) TMIN - - 300 - ns Mute input high voltage VMUTEH - 2.2 - - V Mute input low voltage VMUTEL - - - 0.5 V (CH2,3,4) CONTROL INPUT REGULATOR AND CHARGER PART Regulator output voltage VVIN DCIN=6.5V, Ivin1=200mA 3.7 4.0 4.3 V Line regulation of regulator ∆Vdc DCIN=5V → 7V, Ivin1=200mA -50 0 50 mV Load regulation of regulator ∆Vrl Ivin1=0 → 200mA -40 0 10 mV 15 - - mA 400 450 500 mA CHGON Current Ichon - Constant Charge Current Ichg CHGSW-on high voltage VCHGSWH - 2.0 - - V CHGSW-on low voltage VCHGSWL - - - 0.5 V Operating temperature (Note1) TSD - - 150 - °C Thermal hysteresis (Note1) THYS - - 20 - °C Rs=1.1Ω THERMAL SHUT DOWN Notes: 1. Design reference value 9 FAN8048 Application Information 1. System Control and Protection Functions 1-1. System Enable/Disable Function As shown in Figure 1, system enable ON (pin4) should be set low (typically under VIN - 0.65V) only once until OFF (pin3) receives the disable signal (typically under VSYS1 - 0.85V), then all circuits remain in enable status. Also, to prevent malfunction, this function activates when the circuit short condition exists such as over current or circuit shorts, the whole circuit becomes the disable. When the circuit is enabled, to obtain the necessary power (VG) to operate the internal circuits and upper side output power switches of the 4 channels H-bridge driver, the VG converter circuit is activated. Also, to stably operate all circuits, the VG converter keeps other circuits from activating until the output voltage of the VG converter reaches the specific voltage (3.9V). When the output voltage of the VG converter reaches 3.9V, the first DC-DC converter (DC-DC Converter1) activate. And when output voltage of DC-DC converter1(VSYS1) reaches 1.35V, the second converter (DC-DC Converter2) activates in sequence. The circuit activation sequence as stated above and a flow chart are shown in Figure 3 and Figure 4. 1-2. Channel Mute Function When MUTE (pin29) is high (typically above 2.2V), the mute circuit activates, so the all motor driver (4 channels H-bridge driver) outputs are in mute state; on the other hand, when it is low (under 0.5V), mute state is off. 1-3. Thermal Shut Down(TSD) Function This thermal shutdown (TSD) function is designed to protect the chip from being damaged as the chip's internal temperature rises. If the TSD circuit activates, all motor driver (4 channel H-bridge drivers) outputs are in mute state. When the chip's internal temperature reaches 150°C (typical), then the TSD circuit is activated, and when the chip temperature falls to 130°C or below, the TSD circuit is deactivated and the output drivers operate normally. Mute Circuit MUTE 29 125℃ Channel Mute 150℃ TSD Short Circuit Detector VSYS1 6uA 12uA EA1O 10 1.35V OFF SPRT 3 5 System_OFF CSPRT 0.5V VSYS1 22 ON 4 VG 1 Start_up Circuit VSYS1<1.65V System_ON System_ON Bias & Refernece Bias R1 DC-DC Converter Wake-up Singnal R2 Vref1 DC-DC Converter VG Converter Figure 1. Block Diagram of System Control Circuit 10 FAN8048 1-4. Power-On Reset (POR) Function FAN8048 has two DC-DC converters to supply stable power to external circuits and components of the CD player set. Therefore, for these output voltages of DC-DC converters to provide stable power to external circuits and their components, the DC input voltage,VIN, and the output voltages of converter, VSYS1 and VSYS2, monitoring function is required. The DC input voltage, VIN, and the output voltage of converter2 are individually divided by the internal resistors and then compared with the internal 0.5V reference voltage, VREF2, to determine the low voltages condition. This power on reset (POR) circuit is shown in Figure2. VSYS2 14 VIN 18 VSYS1 2 RST Vref2 VSYS1 RST 22 Figure 2. Block Diagram of Power On Reset 1-5. Power Sequence The following graph and flowchart of Figure 3 and Figure 4 show the power sequence of the VG converter and two DC-DC converters (DC-DC converter1 and DC-DC Converter2); herein, VG converter generates power for internal circuits and upper side output power switches of the 4 channels H-bridge driver, and the DC-DC converters supply the external circuits and components. Voltage VG=7.0V 3.9V VSYS1 VRST VSYS2 1.35V Hysteresis t Converter 1 Converter 2 Wake-up Wake-up Reset Signal Figure 3. Plot of Power Sequence 11 FAN8048 Start SYSON SYSOFF VG Converter Wake-up Yes No VG > 3.9V Yes DC-DC Converter 1 Wake-up Yes No VSYS1 > 1.35V Yes Start-up Mode DC-DC Converter 2 Wake-up Yes No VSYS2 > 1.35V Yes Yes VSYS1 > 1.84V No SYSON = LOW No Yes EA1O < 1.35V Time < Tsprt Yes No Normal Mode SYSTEM READY Figure 4. Flow Chart of Power Sequence 12 SYSTEM OFF FAN8048 2. H-Bridge Driver (CH1, CH2, CH3 and CH4 ) 2-1. H-Bridge Driver for Actuators and Sled Motor (CH2, CH3 and CH4) Channel 2, channel 3, and channel 4 have two inputs FWD and RVE and an H-bridge type of output to the forward or reverse Sled motor and the Focus and Tracking actuator as shown in Figure 5. The H-bridge driver operation is as in the following logical truth table below. That is, to forward or reverse, the output is the same as the input, and when the two input signals match, the lower switching devices (switches B and C) are turned-on, Sled motor, Focus and Tracking actuator are in braking state. PVCC VG 32 REV 31 VA Predriver FWD D A VSYS OUT+ VB 44 VC 43 VD OUT- B LOGIC AND PREDRIVER C Figure 5. Block Diagram of H-Bridge driver for CH2, CH3 and CH4 2-2. Logical Truth Table FWD REV OUT+ OUT- Function L L L L Brake L H L H Reverse H L H L Forward H H L L Brake 2-3. H-Bridge driver for spindle motor (CH1) Figure 6 shows spindle motor driver. The circuit consists of 3-states of input (High, Low, and High impedance) to perform forwarding, reversing, and braking of the motor. The detailed operation is shown in logical truth table. VSYS1 50K 70K PVCC VSYS CH1 30 MO2 60K 80K D VA Predriver MO1 50K A VG 40K CH1+ 46 VB VC 45 CH1- VD B LOGIC AND PREDRIVER C OUTPUT STAGE Figure 6. Block Diagram of H-Bridge driver for Spindle motor 2-4. Logical Truth Table INPUT MO1 MO2 CH+ CH- Function H H H H L Forward L L L L H Reverse Z L H L L Brake Note: 1. Z is high impedance input 13 FAN8048 3. DC-DC Converter (VG Converter and Synchronous DC-DC Converter) 3-1. VG Converter (Step up Converter) The VG converter is used to generate necessary power (VG) for upper side output power switches operation of 4 channels Hbridge driver and other internal circuit operations as shown in Figure 7. The output voltage (VG) of VG converter is internally set to 7.0V, and it activates DC-DC Converter 1 when VG converter output voltage reaches 3.9 V. Also VG converter has an oscillator function, which is required for switching operations and to minimize external components. LG D1 LG 48 1 VG DC-DC Converter Wake-up Singnal Vref1 VBAT R1 CG SW R2 Sawtooth FAN8048 SYSTEM_ON ON 4 Clock Figure 7. Set up Converter (VG Converter) 3-2. Synchronous Step-up/Down Converter The FAN8048 provides high efficiency and low noise power for applications such as portable instrumentation. Figure 8 shows the functional block diagram of synchronous step up/down converter. DSW USW 19 21 22 18 VSYS Start Comp 1.79V SPRT 5 Stop Comp VA VA VB VB VC VC VD Power Stage PCT Logic & predriver VD VBAT 7 PCT 0.5V Start & Short Circuit Protection 1.27V VCOM CP VX VZ1 10 Error Amp RC 11 VZ2 0.9V VY R2 0.56V OSC2 9 VSYS VCOM PCT 1.48V CLK 8 Sync. Clock OSC2 FAN8048 DC-DC Converter Figure 8. Block diagram of Step-up/down converter In Figure 8, the output voltage (VSYS) of DC-DC converter is calculated as follows: R1 ) [V ] R2 = 0.9[V ] VSYS = VREF × (1 + where, VREF 14 R1 CC SOFT FAN8048 3-3. Oscillator Oscillator frequency is determined by the charging/discharging current iCG and iDCG of the internal circuit and capacitor (CPCT) connected to PCT (pin7) and ground. To change oscillator frequency, you may change the CPCT capacitor. For example, the external capacitor (CPCT) value can be calculated as follows: t PCT = C PCT × ∆VPCT C PCT × ∆VPCT C PCT × ∆VPCT (iCHG + iDCG ) + = iCG iDCG iCG × iDCG f PCT = C PCT = 1 t PCT = iCG × iDCG C PCT × ∆VPCT × (iCG + iDCG ) iCG × iDCG f PCT × ∆VPCT × (iCG + iDCG ) Where, iCG is charging current, which is 42uA, iDCG is discharging current, which is 14uA, and oscillator peak-peak voltage, ∆VPCT is approximately 300mV. This oscillator is designed to synchronize the frequency of the oscillator itself to the clock pulse frequency separately input to external CLK (pin8). To utilize this function, the oscillator frequency itself should be configured lower than the frequency of the external synchronous signal. 3-4. Error Amplifier The error amplifier of the DC-DC converter is used to amplify the difference between internal reference voltage and output voltage. This amplified voltage generates a square wave pulse corresponding to the difference of triangular waveform-PCT output formed by triangular wave oscillatory circuit of pulse width modulation comparator (PWM comparator), whereby the square wave pulse stabilizes the output voltage by operating the DC-DC converter's switching devices through the operation circuit. The most well-known system stabilization method using an error amplifier is pole-zero compensation. Detailed system design standards and methods will be discussed in a later section of this document. 3-5. Short Circuit Protection Function The short circuit protection is a function to protect circuits from being damaged from various abnormal conditions such as over current or circuit shorts; and on this occasion, when the error amplifier output voltage, EIO1, (pin10) of DC-DC converter1 reaches the specific voltage (typically 1.35V), the internal current source, iSPRT, start charging the external capacitor, CSPRT connected between SPRT(pin5) and ground as shown in Figure 1 and the DC-DC converter circuit will be shutdown. Also, to prevent malfunction, this function activates only when the circuit short condition exists for a certain amount of time. This time setting (TSPRT) is determined according to the capacitance of external capacitor CSPRT, and its formula is as follows: TSPRT = CSPRT × 0.5 [sec] iSPRT Where, iSPRT is charging current, which is 6uA. 3-6. Soft Start This function limits overshoot in the initial operation. This circuit operates when DC-DC converter 1 output voltage rises over a specific voltage (typically 1.48V), thereafter it starts charging the external capacitor CSOFT connected between SOFT (pin9) and Ground. It restricts the error amplifier output voltage caused by sharp-rising capacitor voltage. Soft start time is determined by the following formula: When the output voltage of the conveter, VSYS1, is brought above typically 1.48V, the soft start function is enable and the internal current source is begin to charging the capacitor, CSOFT. A detailed diagram of this fuction is shown in Figure 8. The component CSOFT provide a slow ramping voltage on the SOFT pin to provide a soft start function. The time constant in this case is shown by the next formular. TSOFT = CSOFT × iSOFT = CSOFT ×10uA[sec] where, iSOFT = 10uA 15 FAN8048 3-7. Operation mode of Step-up/down converter Figure 9 shows the connection of the four internal output power switches, external Inductor, and input/output voltage, which are components of the FAN8048 built-in DC-DC converter. As shown in Figure 10, the DC-DC converter determines a switching operation mode (Buck, Buck-Boost and Boost) according to the relationship between control voltage VX and VY and oscillator output voltage VPCT. Also, the DC-DC converter indicates the different operational statuses of output power switch (Output switches, A, B, C, and D) according to operational mode. Herein, control voltage VX is the output voltage of error amplifier, and voltage VY is level shift voltage in VX. VIN DSW 18 USW VSYS 19 21 A 22 D VA VD VB VC B C Figure 9. Simplified Diagram of Output Swiches 75% DMAX_BOOST Switch A ON B OFF PWM CD Swiches Boost Mode DMIN_BOOST Four Switches PWM Buck/Boost Mode DMAX_BUCK Switch D ON C OFF PWM AB Swiches VX > VPCT VX > VY VX ≤ VPCT VY ≤ VPCT VY > VPCT Buck Mode VY > VX 0% Duty Figure 10. Switching control vs. internal control voltages, VX and VY 16 FAN8048 3-8. Buck(Step-down) converter mode (VIN > VSYS) The step-down converter keeps the average output voltage VSYS lower than DC input voltage VIN all the time. Figure 11-a shows a conceptual circuit diagram of the step-down converter in case an electrical load is pure resistance. Herein, all switching devices are supposed to be at ideal conditions and instantaneous output voltage VSYS is dependent on the status of switching devices. That is, the input/output of the step-down converter is obtained by the following formula according to the Volt-Sec balance condition and each waveform is shown in Figure.11-b, where D means duty cycle. In this formula, since duty ratio D is smaller than 1.0, average output voltage VSYS is always displayed in the lower range of the DC input voltage. VSYS = 1 × VIN [V ] D where, D is duty cycle. D= TON TS In practical application circuits, there are several drawbacks as follows: (1) As most practical circuits are not exposed to pure electrical resistance loads, but to inductive loads and because of the stray inductive there is the switch would have dissipate the inductive energy and therefore it may be destroyed. . (2) This is not the case of most application circuit, but when output voltage fluctuates between zero and power voltage VIN, a low pass filter composed of an inductor and capacitor is required to minimize the output voltage ripple. Figure 12 shows the operation waveform of internal control voltage VX and VY and output power switching devices in Stepdown converter mode. When the internal control voltage VY is higher than control voltage VX and triangular waveform VPCT, switch D is always turned-on and switch C is always turned-off in step-down converter mode. The switching operation of switch A is activated by the signal generated by comparison between internal control VX and triangular waveform voltage VPCT. Also, synchronous switch B remains turned-on during synchronous switch B turn-off time. That is, in step-down converter mode, switch A and B always activate in opposite switching operations. The peak-peak ripple voltage (∆VSYS) of output voltage is calculated using the following formula: ∆VSYS = 1 1 ∆I L TS TS VSYS ∆Q × = × (1 − D)TS = × × 2 8C CO CO 2 2 L Where, ∆IL is the inductor current from Figure11 (b) during turn-off (tOFF). ∆I L = VSYS (1 − D)TS L The value of the output capacitor to reduce output voltage ripple is calculated using the following formula. C= TS VSYS 2 × (1 − D)TS 8L ∆VSYS The average value of the inductor current at boundary between continuos and discontinuous conduction mode is 1 DTS I LB = iL , peak = (VIN − VSYS ) 2 2L where, VIN = VSYS [V ] D So to obtain the inductor value using the above formula, the redefined formula is as follows: L= VSYS (1 − D)TS 2 I O ,min 17 FAN8048 A D VA VIN VB VC B C VSYS (a) VL (VIN-VSYS) A 0 VSYS t B (-VIN) iL=IO 0 Ton Toff t Ts (b) Figure 11. Synchronous Step-down Converter VY PCT VX VA VB VC Low High VD Figure 12. Switches operation waveforms during Buck Converter mode 18 R FAN8048 3-9. Buck-Boost (Step-down/up) Converter Mode (VIN = VSYS) As shown in Figure.13-a, the synchronous buck-boost converters take the mixed form of step-up and step-down converters. That is, in case switching devices in the series connection of the two converters activate in the same duty ratio, the input/output relationship during normal conditions can be expressed as follows: Namely, the output voltage VSYS can be higher or lower than DC input voltage VIN according to duty ratio D. VSYS = D VIN [V ] 1− D As shown in Figure 13-b, the current flowing through the inductor is constant in continuous conduction mode. And the input and output voltages relationship formula can be defined as follows, because , the integral of the inductor voltage over one time period to zero. V SYS DT S + ( −V SYS )(1 − D )TS = 0 V SYS D = V IN 1− D Assuming a lossless circuit, input and output power are the same (Pin=Po) and the above formula can be redefined as follows: I SYS 1 − D = I IN D As you can see in Figure 14, when internal control voltage VX and VY remain in the triangular waveform voltage VPCT range, the converter acts as a step-up or step-down converter mode according to DC input voltage VIN and electrical load VSYS and ISYS status. As displayed in Figure13-a, in this operation mode all four switching devices of the output terminal activate upon operational mode step-up or step-down. Figure13-b shows the operational waveform of each section in this activation mode. 19 FAN8048 A D VA VD VB VIN VC B R VSYS C (a) VL (VIN) A 0 VSYS t B (-VSYS) iL=IIN 0 Ton Toff t Ts (b) Figure 13. Synchronous Step-up/down Converter PCT VY VX VA VB VC VD Figure 14. Output switches operation and waveforms at Buck/Boost (Step-up/down) mode 20 FAN8048 3-10. Boost (Step-up) converter mode (VIN < VSYS) The step-up converter keeps the average output voltage VSYS higher than DC input voltage VIN, and its circuit diagram is shown in Figure 15-a. Figure 15-b shows an operational waveform in case inductor current is steady-state. Since in steadystate, the integral of the inductor voltage over one time period to zero, this can be expressed by the following formula: (VIN × t ON ) + ((VIN − VSYS ) × tOFF ) = 0 From the above formula, a redefined formula is as follows after dividing by cycle Ts: VSYS T 1 = S = VIN t OFF 1 − D VSYS = 1 × VIN [V ] 1− D Assuming a lossless circuit, input and output power are the same (Pin=Po) and the above formula can be redefined as follows: VIN I IN = VSYS I O This can be expressed as follows using input/output current and duty ratio: IO = (1 − D) I IN In the boundary condition of continuous mode and discontinuous mode, the inductor's average current is defined as follows: 1 iLB = iL, peak 2 1 VIN = TON 2 L TV = S SYS D(1 − D)2 2L From the above formula, since inductor current and input current are the same (iIN=iL), the average output current at the edge of continuous conduction mode can be redefined as below: I OB = TS × VSYS D(1 − D) 2 2L In a practical synchronous step-up converter, the parasitic elements are due to the loss associated with the inductor, the capacitor and the switches; however, in this formula we assume that all components are at ideal conditions.In the continuous mode, as the output current and peak-peak voltage ripple are considered to be constant, this formula can be redefined as below: ∆VSYS = ∆Q I O DTS VSYS DTS = = C C R C ∆VSYS DTS = VSYS RC Where, R= VSYS [Ω] IO 21 FAN8048 In Figure 16, when control voltage VX is always higher than VY and triangular waveform voltage VPCT, Switch pairs C and D will alternately switching and their circuit is designed to operate as a step-up converter, whose output voltage is always higher than input voltage. Figure 15 shows the operational waveform at the output terminal of each switching device when it acts as a step-up converter. In this operations section, Switch A is always turned-on and switch B is always turned-off. Also, to limit the maximum output voltage in this mode, the maximum duty ratio is limited to about 75%. D A VD VB VIN VC B VSYS R C (a) VL (VIN) A 0 VSYS t B (VIN-VSYS) iL 0 Ton Toff t Ts (b) Figure 15. Synchronous Step-up Converter VX PCT VY VA VB High Low VC VD Figure 16. Output switch operational waveforms in Boost (Step-up) converter mode 22 FAN8048 3.10.1 Effect of Parasitic Elements in Step-up Converter In a practical synchronous step-up converter, the parasitic elements are due to the loss associated with the inductor, the capacitor and the switches; however. Figure 17 qualitatively show the effect of these parasitics on the voltage transfer ratio. Unlike the ideal characteristic, in paractice VSYS/VIN declines as the duty ratio approaches unity. Because of very poor switch utilization at high values of duty ratio, the curves in this range are show as dotted. VSYS VIN Ideal 1 1− D Due to parasitic elements D 0 1 Figure 17. Effect of parasitic elements on voltage conversion ratio 23 FAN8048 3.11 Component of Error Amplifier Compensation Network In this chapter, we would like discuss the method of converter error amplifier design to control voltage mode PWM. In general, a negative feedback control circuit composed of error amplifier using an operational amplifier and comparator is often used to stabilize output voltage in switching mode converters. Controller design standards and methods for a stable system are as follows: (1) To reduce regulation error of the output voltage, the loop gain crossover frequency, fC, should be as high as possible. (2) To obtain stable phase margin, let the slope gain at 0dB be -20dB/dec. That is, have the gain phase at 0dB close to -90°. (3) Set the loop gain crossover frequency, fC be set to 1/5 ~ 1/10 of the switching frequency fS. But in boost converter, due to the RHP zero, fRHPZ, the loop gain frequency, fC, must be designed well below the RHP zero because the boost converter have a right half plane (RHP) zero. ( fC =fRHPZ /10) (4) Set compensation pole, fP1 to cancel the ESR zero fFILTER_ZERO. (fP1= fFILTER_ZERO) (5) Place a high-frequency compensator pole, fP2 to get the maximum attenuation of the switching ripple and high frequency noise the minimum phase lag at fC. (6) Place a two compensator zeroes, fZ1 and fZ2 below fC. Place the fz1 below the power stage natural frequency, fFILTER_POLE to avoid a conditional stability. When setting these two zeroes (fz1 and fz2), converter performance and stability margin should be considered. (7) Select the compensator parameters. (R’s and C’s ) To meet the design standards mentioned above, Figure 18 shows circuits and the characteristics of a typical compensator, which has a controller structure with two zeroes (fz1 and fz2) and poles (fp1 and fp2). First of all to design an error amplifier, natural frequency of system, fFILTER_POLE and ESR zero using an equivalent series resistance of the output capacitor can be obtained by the following formula. Double poles by the output filter are obtained from the following formula: f FILTER _ POLE = 1 [ Hz ] 2π LC O Where, Co is the output capacitor. The ESR zero by the output capacitor, CO and equivalent series resistance of the output capacitor, RESR can be obtained by the following formula. f FILTER _ ZERO = 1 [ Hz ] 2π × RESR × CO where, RESR is the equivalent series resistance of output filter capacitor. Gain VSYS Av2 C3 C2 R1 C1 -20dB/dec = -2slop R2 Vc 11 Note C1>>C3 R1>>R3 Av1 +90o 0.9V Error Amp 0o -90o f1 f2 Figure 18. Error Amplifier Compensation Circuit 24 -20dB/dec = -2slop 20dB/dec = +2slop 10 R3 R4 Phase f3 f4 FAN8048 A troublesome feature in boost converter mode is the right-half plan (RHP) zero, and is given by: 2 f RHPZ VIN = [ Hz ] 2π × I O × L .Most applications demand an improved transient response to allow a smaller output filter capacitor, and to achieve a higher bandwidth, type 3 compensation is required. In Figure 18, pole and zero of the error amplifier are expressed as follows: 1 [ Hz ] 2π × R1× (C1 + C 3) 1 f Z1 = [ Hz ] 2π × R 2 × C1 1 fZ 2 = [ Hz ] 2π × C 2( R1 + R3) 1 f P1 = [ Hz ] 2π × R3 × C 2 1 f P2 = [ Hz ] C1× C 3 2π × R 2 × C1 + C 3 fI = And because it has C1 >> C3 and R1 >> R3 in general, it can be simplified as below: 1 [ Hz ] 2π × R1× C1 1 f Z1 = [ Hz ] 2π × R 2 × C1 1 fZ 2 = [ Hz ] 2π × R1× C 2 1 f P1 = [ Hz ] 2π × R3 × C 2 1 f P2 = [ Hz ] 2π × R 2 × C 3 fI = 25 FAN8048 3-12. Considerations of Input and Output Capacitors in DC-DC converter Input Capacitors The input capacitor is necessary to minimize the peak current drawn from the battery. Typically a several ten times uF tantalum capacitor is recommending. Low equivalent series resistance (ESR) capacitors will help to minimize battery voltage ripple. Output Capacitors Low ESR capacitors should be used at the output of the DC-DC converter to minimize output ripple. The high frequency switching speeds and fast changes in the output capacitor current, mean that the equivalent impedance of the capacitor can contribute greatly to the output ripple. In order to minimize these effects choose an output capacitor with less than 10nH of equivalent series inductance (ESL) and less than 100mW of equivalent series resistance (ESR). Typically these characteristics are met with ceramic capacitor, but may also be met with certain types of tantalum capacitor. For a step change of load, the output filter inductor in Figure 19 acts as a source of constant current during in this load transient, and the change in load current as a transient is supplied by the filter capacitor. Hence, following a load transient, ∆VSYS = − ESR × ∆I SYS 3-13. Layout and Ground Considerations High frequency switching and large peak currents means PCB design for DC-DC converters requires careful consideration. A general rule is to place the DC-DC converter circuitry well away from any sensitive RF or analog components. The layout of the DC-DC converters and its external components are also based on some simple rules to minimize EMI and output voltage ripple. Layout 1. Place all power components, FAN8048, inductor, input capacitor and output capacitor as close together as possible. 2. Keep the output capacitor as close the FAN8048 as possible with very short traces to the VSYS and GND pins. 3. Keep the external feedback loop network as close the FAN8048 as possible with very short traces, but away from the four channels output as far as possible. Grounding 1. Use a star grounding system with separate traces for the power ground and the low power signals such as ON/OFF and MUTE. The star should radiate from where the power supply enters the PCB. 2. On the multilayer boards use components side copper for grounding around the FAN8048 and connect back to a quiet ground plane using vias. iL L iSYS ESR VSYS C Output Filter Figure 19. ESR in the output capacitor 26 R=Load FAN8048 4. Series Voltage Regulator and Battery Charger Function As shown in Figure 20, if the external adaptor supplies high voltage (in general, adaptor voltage used for portable devices is above 4.5V), the series voltage regulator is internally designed to be 4V so as to be suitable for circuit operation; and when necessary, it has the function of battery charging using an external adaptor. 4.1 Non-charging mode (Series Voltage Regulator Function) When battery-charging mode is unnecessary, CHGSW (pin27) input may be LOW. On this occasion, the output voltage VREG (Voltage on pin18) of the series voltage regulator is internally designed to be 4.0V. When DCIN(pin24) is not supplied (when VIN is connected from the batteries), this circuit is need diode(D1) for prevent the VIN (Volatege on pin18) leakage current can not flow in to the IC. The related formula for this is expressed as follows: V REG = ((1 + R1 ) × 0.5) − V Q1, SAT = 4[V ] R2 4.2 Charging mode (Battery Charger function) To charge the battery using an external adaptor, CHGSW ( pin27) input should be HIGH. In charging mode, internal transistor Q1 and external transistor Q3 are turned-on to connect the battery with the external adaptor. On this occasion, charging current, iCHG can be determined by current detection resistance Rs, and charging current is obtained by the following formula: I CHG = 0.5 [ A] RS DCIN 24 REG Q2 23 0.5V D1 Adaptor VIN 18 DC-DC Converter R1 DCIN R2 Q1 CHGSW 27 Charge_ON iCHG Q3 26 CHGCON 25 CHGSEN RS Figure 20. Block Diagram of Regulator and Battery charger 27 FAN8048 5. Precaution 1. Attach a de-coupling capacitor between power supply pins and ground. 2. Check that the following items will not result while this IC is in use, or otherwise the IC will be broken or burned with smoke generated. -. Short-circuiting between output pins -. Short-circuiting between output and ground pins -. Short-circuiting between output and power supply pins -. Reverse insertion of IC The following pins are all output pins. VG(pin1), RST(pin2), EA1O(pin10), EA2O(pin12), VSYS2(pin14), USW2(pin15), DSW2(pin17), DSW1(pin19), USW1(pin21), VSYS1(pin22), REG(pin23), CHGCON(pin26), CH4-(pin38), CH4+(pin39), CH3-(pin40), CH3+(pin41), CH2-(pin43), CH2+(pin44), CH1-(pin45) and CH1+(pin46) The following pins are all ground pins. SGND(pin6), PGND(pin16), PGND(pin20), DGND(pin28), PGND(pin37) and PGND(pin47) The following pins are all power supply pins. VIN(pin18), DCIN(pin24) and PVCC(pin42) Note) This document provides reference information on the use of this IC, which does not, however, guarantee the proper operation of any applications employing this IC. Constantly or values provided in this document are reference values and not guaranteed values. 28 FAN8048 Typical Performance Characteristics Temperature vs Ivin Temperature vs Ivg 3 1.6 2.5 1.4 1.2 Ivg[mA] Ivin[mA] 2 1.5 1 1 0.8 0.6 0.4 0.5 0 -35 0.2 -15 5 25 45 65 0 -35 85 -15 5 Temperature vs Idcin 65 85 45 65 85 45 65 85 Temperature vs Vvg 0.8 9 0.6 8 Vvg [V] Idcin [mA] 45 Temperature [℃] Temperature [℃] 0.4 7 6 0.2 0 -35 25 -15 5 25 45 65 5 -35 85 -15 5 25 Temperature [℃] Temperature [℃] Temperature vs flg Temperature vs fosc 150 80 130 70 flg [KHz] fosc [KHz] 75 65 60 55 50 -35 110 90 70 -15 5 25 Temperature[℃] 45 65 85 50 -35 -15 5 25 Temperature [℃] 29 FAN8048 Typical Performance Characteristics Temperature vs Vdown Temperature vs Vup 2.85 2.8 2.8 2.75 2.75 Vdown [V] Vup[V] 2.85 2.7 Vup1 Vup2 2.65 2.7 Vdown1 Vdown2 2.65 2.6 2.6 2.55 -35 -15 5 25 45 65 2.55 -35 85 -15 Temperature [℃] 5 25 45 65 85 Temperature [℃] DCIN vs VIN(Regulator Output) VIN vs VSYS 4.3 2.9 4.2 VSYS1 VSYS2 4.1 VIN(V) VSYS [V] 2.8 2.7 4 3.9 2.6 3.8 2.5 1.8 2.1 2.4 2.7 3 3.3 VIN [V] 30 3.6 3.9 4.2 4.5 3.7 4.5 5.5 6.5 7.5 DCIN(V) 8.5 9.5 FAN8048 Typical Performance Characteristics (Continued) Output Switches Rdson of DC-DC Converter1 Output Switches Rdson of DC-DC Converter2 0.60 0.60 Rdsw_Upper Rdsw_Low 0.50 0.50 Rusw_Upper Rusw_Low Rdson[Ω] Rdson[Ω] 0.40 0.30 0.20 0.40 0.30 Rdsw_Upper 0.20 Rdsw_Low Rusw_Upper 0.10 0.10 Rusw_Low 0.00 0.00 0 50 100 150 200 250 300 350 400 0 450 50 100 150 1.00 0.90 0.90 0.80 0.80 0.70 0.70 0.60 Rdson[Ω] Rdson[Ω] 1.00 Ron1+_hi 0.50 Ron1+_lo 0.40 0.30 150 200 250 350 400 450 300 350 0.60 0.50 Ron1-_hi 0.40 Ron1-_lo 0.30 0.20 100 300 Output Switches Rdson of Channel 2 Output Switches Rdson of Channel 1 50 250 I_load[mA] I_load[mA] 0 200 400 Ron2+_hi Ron2+_lo Ron2-_hi Ron2-_lo 0.20 450 0 50 100 150 I_load[mA] 200 250 300 350 400 450 I_load[mA] Output Switches Rdson of Channel 4 Output Switches Rdson of Channel 3 1.00 1.00 0.90 0.80 0.80 0.70 0.70 Rdson[Ω] Rdson[Ω] 0.90 0.60 0.50 Ron3+_hi 0.40 Ron3+_lo Ron3-_hi 0.30 100 150 200 250 I_load[mA] 300 350 400 Ron4+_hi Ron4+_lo Ron4-_hi Ron4-_lo 0.30 0.20 50 0.50 0.40 Ron3-_lo 0 0.60 450 0.20 0 50 100 150 200 250 I_load[mA] 300 350 400 450 31 FAN8048 Typical Application Circuits VBATT L1 LG D1 48 47 PGND 46 45 44 43 42 41 40 39 38 37 CH1+ CH1- CH2+ CH2- PVCC CH3+ CH3- CH4+ CH4- PGND 1 VG 2 RST 35 3 OFF 34 4 ON 33 5 SPRT 32 6 SGND 7 PCT 8 CLK 29 9 SOFT 28 10 EA1O 27 11 EA1- 36 CH4F C1 CH4R CH3F CH3R CH2F C2 FAN8048 C3 31 30 CH2R CH1 MUTE DGND C4 CHGSW C5 C6 R9 R1 CHGCON 26 Q2 25 EA2O EAI2- VSYS2 USW2 PGND DSW2 VIN DSW1 14 15 16 17 18 19 13 C7 R2 PGND USW1 VSYS1 REG DCIN 21 22 23 24 20 R3 R7 R5 C9 Q1 C11 R4 C8 L2 D2 VSYS2 VBATT C10 VSYS1 SYSTEM ON SYSTEM OFF RESET CLOCK Servo Amp & Controller 32 R6 L3 DCIN DCGND Tracking F R Focus F R F Sled R Spindle MUTE CHGSW R8 Battery 12 CHGSEN FAN8048 Package Dimensions 48-LQFP-0707 33 FAN8048 DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 1/8/04 0.0m 001 Stock#DSxxxxxxxx 2004 Fairchild Semiconductor Corporation