Intersil ISL83386EIVZ ±15kv esd protected, 3v to 5.5v, 1 microamp, 250kbps, rs-232 transmitters/receivers with separate logic supply Datasheet

ISL83386E
®
Data Sheet
November 19, 2004
±15kV ESD Protected, +3V to +5.5V,
1 Microamp, 250kbps, RS-232
Transmitters/Receivers with Separate
Logic Supply
FN6034.1
Features
• Pb-Free Available (RoHS Compliant)
• VL Pin for Compatibility with Mixed Voltage Systems
The ISL83386E contains 3.0V to 5.5V powered RS-232
transmitters/receivers which meet ElA/TIA-232 and
V.28/V.24 specifications, even at VCC = 3.0V. Targeted
applications are PDAs, Palmtops, and cell phones where the
low operational, and even lower standby, power consumption
is critical. Efficient on-chip charge pumps, coupled with a
manual powerdown function reduces the standby supply
current to a 1µA trickle. Small footprint packaging, and the
use of small, low value capacitors ensure board space
savings as well. Data rates greater than 250kbps are
guaranteed at worst case load conditions.
• ESD Protection for RS-232 I/O Pins to ±15kV (IEC61000)
• Low Power, Pin Compatible Upgrade for MAX3386E and
SP3203E
• Single SHDN Pin Disables Transmitters and Receivers
• Meets EIA/TIA-232 and V.28/V.24 Specifications at 3V
• On-Chip Charge Pumps Require Only Four External
0.1µF Capacitors
• Receiver Hysteresis For Improved Noise Immunity
• Very Low Supply Current . . . . . . . . . . . . . . . . . . . . 300µA
The ISL83386E features a VL pin that adjusts the logic pin
(see Pin Descriptions table) output levels and input
thresholds to values compatible with the VCC powering the
external logic (e.g., a UART).
• Guaranteed Minimum Data Rate . . . . . . . . . . . . . 250kbps
The single pin powerdown function (SHDN = 0) disables all
the receiver and transmitter outputs, while shutting down the
charge pump to minimize supply current drain.
Applications
Table 1 summarizes the features of the ISL83386E, while
Application Note AN9863 summarizes the features of each
device comprising the 3V RS-232 family.
Ordering Information
PART NUMBER
(BRAND)
TEMP.
RANGE (oC)
PACKAGE
PKG. DWG.
#
ISL83386EIV
(83386EIV)
-40 to 85
20 Ld TSSOP
M20.173
ISL83386EIV-T
(83386EIV)
-40 to 85
Tape and Reel
M20.173
ISL83386EIVZ
(83386EIVZ) (Note)
-40 to 85
20 Ld TSSOP
(Pb-free)
M20.173
ISL83386EIVZ-T
(83386EIVZ) (Note)
-40 to 85
Tape and Reel
(Pb-free)
M20.173
• Wide Power Supply Range. . . . . . . . Single +3V to +5.5V
• Low Supply Current in Powerdown State . . . . . . . . . < 1µA
• Any System Requiring RS-232 Communication Ports
- Battery Powered, Hand-Held, and Portable Equipment
- Laptop Computers, Notebooks, Palmtops
- Digital Cameras
- PDA’s and PDA Cradles
- Cellular/Mobile Phones
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination finish,
which are RoHS compliant and compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at Pb-free
peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020C.
TABLE 1. SUMMARY OF FEATURES
PART
NUMBER
ISL83386E
NO. OF NO. OF DATA RATE Rx. ENABLE
Tx.
Rx.
(kbps)
FUNCTION?
3
2
250
1
NO
VL LOGIC
SUPPLY PIN?
YES
MANUAL
AUTOMATIC
POWER- DOWN? POWERDOWN FUNCTION?
YES
NO
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Copyright © Intersil Americas Inc. 2003, 2004. All Rights Reserved
ISL83386E
Pinout
ISL83386E (TSSOP)
TOP VIEW
C1+ 1
20 SHDN
V+
2
19 VCC
C1- 3
18 GND
C2+ 4
17 T1OUT
C2- 5
16 T2OUT
V- 6
15 T3OUT
T1IN 7
14 R1IN
T2IN 8
13 R2IN
T3IN 9
12 VL
11 R1OUT
R2OUT 10
Pin Descriptions
PIN
VCC
FUNCTION
System power supply input (3.0V to 5.5V).
V+
Internally generated positive transmitter supply (+5.5V).
V-
Internally generated negative transmitter supply (-5.5V).
GND
Ground connection.
C1+
External capacitor (voltage doubler) is connected to this lead.
C1-
External capacitor (voltage doubler) is connected to this lead.
C2+
External capacitor (voltage inverter) is connected to this lead.
C2-
External capacitor (voltage inverter) is connected to this lead.
TIN
TTL/CMOS compatible transmitter Inputs. The switching point is a function of the VL voltage.
TOUT
RIN
ROUT
VL
SHDN
±15kV ESD Protected, RS-232 level (nominally ±5.5V) transmitter outputs.
±15kV ESD Protected, RS-232 compatible receiver inputs.
TTL/CMOS level receiver outputs. Swings between GND and VL.
Logic-Level Supply. All TTL/CMOS inputs and outputs are powered by this supply.
Active low TTL/CMOS input to tri-state receiver and transmitter outputs and to shut down the on-board power supply to place device
in low power mode. The switching point is a function of the VL voltage.
2
FN6034.1
November 19, 2004
ISL83386E
Typical Operating Circuit
+3.3V to +5V
C1
0.1µF
C2
0.1µF
T1IN
T2IN
TTL/CMOS
LOGIC LEVELS
T3IN
+
0.1µF
1
+
3
4
+
5
19
C1+
VCC
2
V+
C1C2+
V-
C2-
17
T2
8
C4
0.1µF
T1OUT
16
T2OUT
T3
9
15
T3OUT
R1
R1OUT
6
+
T1
7
+ C3
0.1µF
14
11
RS-232
LEVELS
R1IN
5kΩ
R2
10
13
R2OUT
R2IN
5kΩ
LOGIC VCC
0.1µF
12
+
VL
SHDN
20
VCC
GND
18
3
FN6034.1
November 19, 2004
ISL83386E
Absolute Maximum Ratings
Thermal Information
VCC to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
VL to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -7V
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V
Input Voltages
TIN, SHDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
RIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V
Output Voltages
TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±13.2V
ROUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VL +0.3V)
Short Circuit Duration
TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
20 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . .
140
Moisture Sensitivity (see Technical Brief TB363)
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1
Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(Lead Tips Only)
Operating Conditions
Temperature Range
ISL83386EIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Test Conditions: VCC = 3V to 5.5V, C1 - C4 = 0.1µF, VL = VCC; Unless Otherwise Specified.
Typicals are at TA = 25oC, VCC = VL = 3.3V
Electrical Specifications
PARAMETER
TEST CONDITIONS
TEMP
(oC)
MIN
TYP
MAX
UNITS
DC CHARACTERISTICS
Supply Current, Powerdown
SHDN = GND, All Inputs at VCC or GND
25
-
1
10
µA
Supply Current
All Outputs Unloaded, SHDN = VCC, VCC = 3.15V
25
-
0.3
1
mA
VL = 3.3V or 5V
Full
-
-
0.8
V
VL = 2.5V
Full
-
-
0.6
V
VL = 5V
Full
2.4
-
-
V
VL = 3.3V
Full
2.0
-
-
V
VL = 2.5V
Full
1.4
-
-
V
VL = 1.8V
25
-
0.9
-
V
25
-
0.5
-
V
TIN, SHDN
Full
-
±0.01
±1
µA
Output Leakage Current
VCC = 0V or 3V to 5.5V, SHDN = GND
Full
-
±0.05
±10
µA
Output Voltage Low
IOUT = 1.6mA
Full
-
-
0.4
V
Output Voltage High
IOUT = -1.0mA
Full
VL - 0.6
VL - 0.1
-
V
Full
-25
-
25
V
VL = 5.0V
25
0.8
1.5
-
V
VL = 3.3V
25
0.6
1.2
-
V
VL = 5.0V
25
-
1.8
2.4
V
VL = 3.3V
25
-
1.5
2.4
V
Input Hysteresis
25
-
0.5
-
V
Input Resistance
25
3
5
7
kΩ
LOGIC AND TRANSMITTER INPUTS
Input Logic Threshold Low
TIN, SHDN
Input Logic Threshold High
TIN, SHDN
Transmitter Input Hysteresis
Input Leakage Current
RECEIVER OUTPUTS
RECEIVER INPUTS
Input Voltage Range
Input Threshold Low
Input Threshold High
4
FN6034.1
November 19, 2004
ISL83386E
Test Conditions: VCC = 3V to 5.5V, C1 - C4 = 0.1µF, VL = VCC; Unless Otherwise Specified.
Typicals are at TA = 25oC, VCC = VL = 3.3V (Continued)
Electrical Specifications
PARAMETER
TEST CONDITIONS
TEMP
(oC)
MIN
TYP
MAX
UNITS
TRANSMITTER OUTPUTS
Output Voltage Swing
All Transmitter Outputs Loaded with 3kΩ to Ground
Full
±5.0
±5.4
-
V
Output Resistance
VCC = V+ = V- = 0V, Transmitter Output = ±2V
Full
300
10M
-
Ω
Output Short-Circuit Current
Shorted to GND
Full
-
-
±60
mA
Output Leakage Current
VOUT = ±12V, VCC = 0V or 3V to 5.5V, SHDN = GND
Full
-
-
±25
µA
Maximum Data Rate
RL = 3kΩ, CL = 1000pF, One Transmitter Switching
Full
250
500
-
kbps
Receiver Propagation Delay
Receiver Input to Receiver
Output, CL = 150pF
tPHL
25
-
0.15
-
µs
tPLH
25
-
0.15
-
µs
Receiver Output Enable Time
25
-
200
-
ns
Receiver Output Disable Time
25
-
200
-
ns
TIMING CHARACTERISTICS
Transmitter Output Enable Time
From SHDN Rising Edge to TOUT = ±3.7V
25
-
100
-
µs
Transmitter Skew
tPHL - tPLH (Note 2)
25
-
100
-
ns
Receiver Skew
tPHL - tPLH
25
-
50
-
ns
Transition Region Slew Rate
CL = 150pF to 1000pF
RL = 3kΩ to 7kΩ,
Measured From 3V to -3V or
CL = 150pF to 2500pF
-3V to 3V, VCC = 3.3V
25
6
18
30
V/µs
25
4
13
30
V/µs
Human Body Model
25
-
±15
-
kV
IEC61000-4-2 Air Gap Discharge
25
-
±15
-
kV
IEC61000-4-2 Contact Discharge
25
-
±8
-
kV
ESD PERFORMANCE
RS-232 Pins (TOUT, RIN)
NOTE:
2. Transmitter skew is measured at the transmitter zero crossing points.
Detailed Description
The ISL83386E operates from a single +3V to +5.5V supply,
guarantees a 250kbps minimum data rate, requires only four
small external 0.1µF capacitors, features low power
consumption, and meets all ElA RS-232C and V.28
specifications. The circuit is divided into three sections: The
charge pump, the transmitters, and the receivers.
Charge-Pump
Intersil’s new ISL83386E utilizes regulated on-chip dual
charge pumps as voltage doublers, and voltage inverters to
generate ±5.5V transmitter supplies from a VCC supply as
low as 3.0V. This allows these devices to maintain RS-232
compliant output levels over the ±10% tolerance range of
3.3V powered systems. The efficient on-chip power supplies
require only four small, external 0.1µF capacitors for the
voltage doubler and inverter functions over the full VCC
range; other capacitor combinations can be used as shown
in Table 3. The charge pumps operate discontinuously (i.e.,
they turn off as soon as the V+ and V- supplies are pumped
5
up to the nominal values), resulting in significant power
savings.
Transmitters
The transmitters are proprietary, low dropout, inverting
drivers that translate TTL/CMOS inputs to EIA/TIA-232
output levels. Coupled with the on-chip ±5.5V supplies, these
transmitters deliver true RS-232 levels over a wide range of
single supply system voltages.
All transmitter outputs disable and assume a high
impedance state when the device enters the powerdown
mode (see Table 2). These outputs may be driven to ±12V
when disabled.
All devices guarantee a 250kbps data rate for full load
conditions (3kΩ and 1000pF), VCC ≥ 3.0V, with one
transmitter operating at full speed. Under more typical
conditions of VCC ≥ 3.3V, RL = 3kΩ, and CL = 250pF, one
transmitter easily operates at 1.25Mbps.
The transmitter input threshold is set by the voltage applied
to the VL pin. Transmitter inputs float if left unconnected
FN6034.1
November 19, 2004
ISL83386E
(there are no pull-up resistors), and may cause ICC
increases. Connect unused inputs to GND for the best
performance.
TABLE 2. POWERDOWN TRUTH TABLE
SHDN
PWR
MGT
LOGIC
I/O CHIP
POWER SUPPLY
VL
SHDN TRANSMITTER RECEIVER
INPUT
OUTPUTS
OUTPUTS MODE OF OPERATION
L
High-Z
High-Z
Manual Powerdown
H
Active
Active
Normal Operation
Receivers
VCC
CPU
The ISL83386E contains standard inverting receivers that
convert RS-232 signals to CMOS output levels and accept
inputs up to ±25V while presenting the required 3kΩ to 7kΩ
input impedance (see Figure 1) even if the power is off
(VCC = 0V). The receivers’ Schmitt trigger input stage uses
hysteresis to increase noise immunity and decrease errors
due to slow input signal transitions. Receiver outputs swing
from GND to VL, and tristate in powerdown.
VL
I/O
UART
FIGURE 2. CONNECTIONS FOR MANUAL POWERDOWN
VL Logic Supply Input
RXOUT
RXIN
-25V ≤ VRIN ≤ +25V
ISL83386E
GND ≤ VROUT ≤ VL
5kΩ
GND
FIGURE 1. RECEIVER CONNECTIONS
Low Power Operation
This 3V device requires a nominal supply current of 0.3mA,
even at VCC = 5.5V, during normal operation (not in
powerdown mode). This is considerably less than the 11mA
current required by comparable 5V RS-232 devices, allowing
users to reduce system power simply by replacing the old
style device with the ISL83386E in new designs.
Powerdown Functionality
The already low current requirement drops significantly
when the device enters powerdown mode. In powerdown,
supply current drops to 1µA, because the on-chip charge
pump turns off (V+ collapses to VCC, V- collapses to GND),
and the transmitter and receiver outputs tristate. This micropower mode makes these devices ideal for battery powered
and portable applications.
Software Controlled (Manual) Powerdown
The ISL83386E may be forced into its low power, standby
state via a simple shutdown (SHDN) pin (see Figure 2).
Driving this pin high enables normal operation, while driving
it low forces the IC into its powerdown state. The time
required to exit powerdown, and resume transmission is less
than 100µs. Connect SHDN to VCC if the powerdown
function isn’t needed.
6
Unlike other RS-232 interface devices where the CMOS
outputs swing between 0 and VCC, the ISL83386E features
a separate logic supply input (VL; 1.8V to 5V, regardless of
VCC) that sets VOH for the receiver outputs. Connecting VL
to a host logic supply lower than VCC, prevents the
ISL83386E outputs from forward biasing the input diodes of
a logic device powered by that lower supply. Connecting VL
to a logic supply greater than VCC ensures that the receiver
output levels are compatible even with the CMOS input VIH
of AC, HC, and CD4000 devices. Note that the VL supply
current increases to 100µA with VL = 5V and VCC = 3.3V
(see Figure 11). VL also powers the transmitter and logic
inputs, thereby setting their switching thresholds to levels
compatible with the logic supply. This separate logic supply
pin allows a great deal of flexibility in interfacing to systems
with different logic supplies. If logic translation isn’t required,
connect VL to the ISL83386E VCC.
Capacitor Selection
The ISL83386E charge pumps only require 0.1µF capacitors
for the full operational voltage range. Table 3 lists other
acceptable capacitor values for various supply voltage
ranges. Do not use values smaller than those listed in Table
3. Increasing the capacitor values (by a factor of 2) reduces
ripple on the transmitter outputs and slightly reduces power
consumption.
TABLE 3. REQUIRED CAPACITOR VALUES
VCC
(V)
C1
(µF)
C2, C3, C4
(µF)
3.0 to 3.6
0.1
0.1
4.5 to 5.5
0.047
0.33
3.0 to 5.5
0.22
1
FN6034.1
November 19, 2004
ISL83386E
When using minimum required capacitor values, make sure
that capacitor values do not degrade excessively with
temperature. If in doubt, use capacitors with a larger nominal
value. The capacitor’s equivalent series resistance (ESR)
usually rises at low temperatures and it influences the
amount of ripple on V+ and V-.
VCC
+
0.1µF
+
C1+
VCC
VL
V+
+
C3
C1
C1-
Power Supply Decoupling
ISL83386E
+
In most circumstances a 0.1µF bypass capacitor is
adequate. In applications that are particularly sensitive to
power supply noise, decouple VCC to ground with a
capacitor of the same value as the charge-pump capacitor C1.
Connect the bypass capacitor as close as possible to the IC.
Transmitter Outputs when Exiting
Powerdown
C4
+
C2
C2TIN
TOUT
1000pF
RIN
ROUT
5k
Figure 3 shows the response of two transmitter outputs
when exiting powerdown mode. As they activate, the two
transmitter outputs properly go to opposite RS-232 levels,
with no glitching, ringing, nor undesirable transients. Each
transmitter is loaded with 3kΩ in parallel with 2500pF. Note
that the transmitters enable only when the magnitude of the
supplies exceed approximately 3V.
5V/DIV
V-
C2+
VCC
SHDN
FIGURE 4. TRANSMITTER LOOPBACK TEST CIRCUIT
5V/DIV.
T1IN
SHDN
T1
T1OUT
R1OUT
2V/DIV
VCC = +3.3V
C1 - C4 = 0.1µF
5µs/DIV.
T2
FIGURE 5. LOOPBACK TEST AT 120kbps
VCC = +3.3V
C1 - C4 = 0.1µF
TIME (20µs/DIV.)
FIGURE 3. TRANSMITTER OUTPUTS WHEN EXITING
POWERDOWN
5V/DIV.
T1IN
High Data Rates
The ISL83386E maintains the RS-232 ±5V minimum
transmitter output voltages even at high data rates. Figure 4
details a transmitter loopback test circuit, and Figure 5
illustrates the loopback test result at 120kbps. For this test,
all transmitters were simultaneously driving RS-232 loads in
parallel with 1000pF, at 120kbps. Figure 6 shows the
loopback results for a single transmitter driving 1000pF and
an RS-232 load at 250kbps. The static transmitters were
also loaded with an RS-232 receiver.
T1OUT
R1OUT
VCC = +3.3V
C1 - C4 = 0.1µF
2µs/DIV.
FIGURE 6. LOOPBACK TEST AT 250kbps
7
FN6034.1
November 19, 2004
ISL83386E
Interconnection with 3V and 5V Logic
Standard 3.3V powered RS-232 devices interface well with
3V and 5V powered TTL compatible logic families (e.g., ACT
and HCT), but the logic outputs (e.g., ROUTS) fail to reach
the VIH level of 5V powered CMOS families like HC, AC, and
CD4000. The ISL83386E VL supply pin solves this problem.
By connecting VL to the same supply (1.8V to 5V) powering
the logic device, the ISL83386E logic outputs will swing from
GND to the logic VCC.
±15kV ESD Protection
All pins on the 3V interface devices include ESD protection
structures, but the ISL83386E incorporates advanced
structures which allow the RS-232 pins (transmitter outputs
and receiver inputs) to survive ESD events up to ±15kV. The
RS-232 pins are particularly vulnerable to ESD damage
because they typically connect to an exposed port on the
exterior of the finished product. Simply touching the port
pins, or connecting a cable, can cause an ESD event that
might destroy unprotected ICs. These new ESD structures
protect the device whether or not it is powered up, protect
without allowing any latchup mechanism to activate, and
don’t interfere with RS-232 signals as large as ±25V.
IEC61000-4-2 Testing
The IEC61000 test method applies to finished equipment,
rather than to an individual IC. Therefore, the pins most likely
to suffer an ESD event are those that are exposed to the
outside world (the RS-232 pins in this case), and the IC is
tested in its typical application configuration (power applied)
rather than testing each pin-to-pin combination. The lower
current limiting resistor coupled with the larger charge
storage capacitor yields a test that is much more severe than
the HBM test. The extra ESD protection built into this
device’s RS-232 pins allows the design of equipment
meeting level 4 criteria without the need for additional board
level protection on the RS-232 port.
AIR-GAP DISCHARGE TEST METHOD
For this test method, a charged probe tip moves toward the
IC pin until the voltage arcs to it. The current waveform
delivered to the IC pin depends on approach speed,
humidity, temperature, etc., so it is difficult to obtain
repeatable results. The “E” device RS-232 pins withstand
±15kV air-gap discharges.
CONTACT DISCHARGE TEST METHOD
Human Body Model (HBM) Testing
As the name implies, this test method emulates the ESD
event delivered to an IC during human handling. The tester
delivers the charge through a 1.5kΩ current limiting resistor,
making the test less severe than the IEC61000 test which
utilizes a 330Ω limiting resistor. The HBM method
determines an ICs ability to withstand the ESD transients
typically present during handling and manufacturing. Due to
the random nature of these events, each pin is tested with
Typical Performance Curves
respect to all other pins. The RS-232 pins on “E” family
devices can withstand HBM ESD events to ±15kV.
During the contact discharge test, the probe contacts the
tested pin before the probe tip is energized, thereby
eliminating the variables associated with the air-gap
discharge. The result is a more repeatable and predictable
test, but equipment limits prevent testing devices at voltages
higher than ±8kV. All “E” family devices survive ±8kV contact
discharges on the RS-232 pins.
VCC = 3.3V, TA = 25oC
30
VOUT+
4.0
25
SLEW RATE (V/µs)
TRANSMITTER OUTPUT VOLTAGE (V)
6.0
2.0
1 TRANSMITTER AT 250kbps
OTHER TRANSMITTERS AT 30kbps
0
-2.0
-6.0
0
1000
2000
3000
4000
5000
LOAD CAPACITANCE (pF)
FIGURE 7. TRANSMITTER OUTPUT VOLTAGE vs LOAD
CAPACITANCE
8
+SLEW
15
-SLEW
10
VOUT -
-4.0
20
5
0
1000
2000
3000
4000
5000
LOAD CAPACITANCE (pF)
FIGURE 8. SLEW RATE vs LOAD CAPACITANCE
FN6034.1
November 19, 2004
ISL83386E
Typical Performance Curves
VCC = 3.3V, TA = 25oC (Continued)
45
3.5
40
250kbps
35
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
NO LOAD
ALL OUTPUTS STATIC
3.0
30
120kbps
25
20
20kbps
15
2.5
2.0
1.5
1.0
0.5
10
0
2000
1000
4000
3000
0
2.5
5000
3.0
3.5
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
LOAD CAPACITANCE (pF)
FIGURE 10. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 9. SUPPLY CURRENT vs LOAD CAPACITANCE
WHEN TRANSMITTING DATA
10m
1m
NO LOAD
ALL OUTPUTS STATIC
VCC = 3.3V
100µ
IL (A)
10µ
1µ
100n
10n
1n
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
VL (V)
FIGURE 11. VL SUPPLY CURRENT vs VL VOLTAGE
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP)
GND
TRANSISTOR COUNT
422
PROCESS
Si Gate CMOS
9
FN6034.1
November 19, 2004
ISL83386E
Thin Shrink Small Outline Plastic Packages (TSSOP)
M20.173
N
INDEX
AREA
E
0.25(0.010) M
E1
2
INCHES
GAUGE
PLANE
-B1
20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
B M
SYMBOL
3
L
0.05(0.002)
-A-
0.25
0.010
SEATING PLANE
MIN
MAX
MILLIMETERS
MIN
MAX
NOTES
A
-
0.047
-
1.20
-
A1
0.002
0.006
0.05
0.15
-
A2
0.031
0.051
0.80
1.05
-
b
0.0075
0.0118
0.19
0.30
9
A
D
-C-
α
e
A2
A1
b
c
0.10(0.004)
0.10(0.004) M
C A M
B S
c
0.0035
0.0079
0.09
0.20
-
D
0.252
0.260
6.40
6.60
3
E1
0.169
0.177
4.30
4.50
4
e
0.026 BSC
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
-
E
0.246
0.256
6.25
6.50
-
L
0.0177
0.0295
0.45
0.75
6
8o
0o
N
NOTES:
0.65 BSC
α
20
0o
20
7
8o
Rev. 1 6/98
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
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10
FN6034.1
November 19, 2004
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