This version: Mar. 1999 Semiconductor MSC23CV23268D-xxBS4 2,097,152-word x 32-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE WITH EDO DESCRIPTION The MSC23CV23268D-xxBS4 is a fully decoded, 2,097,152-word x 32-bit CMOS dynamic random access memory module composed of four 16Mb DRAMs (1Mx16) in TSOP packages mounted with eight decoupling capacitors on a 72-pin glass epoxy small outline package. This module supports any application where high density and large capacity of storage memory are required. FEATURES · 2,097,152-word x 32-bit organization · 72-pin Small Outline Dual In-line Memory module MSC23CV23268D-xxBS4 : Gold tab · Single +3.3V supply ± 0.3V tolerance · Input : LVTTL compatible · Output : LVTTL compatible, 3-state · Refresh : 1024cycles/16ms · /CAS before /RAS refresh, hidden refresh, /RAS only refresh capability · Fast page mode with EDO capability PRODUCT FAMILY tRAC tAA tCAC Cycle Time (Min.) MSC23CV23268D-60BS4 60ns 30ns 15ns 104ns 864mW MSC23CV23268D-70BS4 70ns 35ns 20ns 124ns 792mW Access Time (Max.) Family Power Dissipation Operating (Max.) Standby (Max.) 7.2mW Semiconductor MSC23CV23268D MODULE OUTLINE (Unit : mm) MSC23CV23268D-xxBS4 3.80Max. 25.4±0.13 3.18±0.13 3.17Min. 71 1 2.0±0.13 2.62Typ. *1 1.00±0.1 44.45±0.1 59.69±0.2 *1 The common size difference of the board width 19.78mm of its height is specified as ±0.2. The value above 19.78mm is specified as ±0.5. R2.0 1.0±0.1 17.78±0.13 1.8±0.1 0.25 Max. 72 2 3.25Typ. 2-φ1.8 3.03 44.45±0.1 51.66±0.1 R2.0 5.00 0.23 Min. 1.27±0.1 Semiconductor MSC23CV23268D PIN CONFIGURATION Front Side Back Side Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 VSS 37 DQ16 2 DQ0 38 DQ17 3 DQ1 39 VSS 4 DQ2 40 /CAS0 5 DQ3 41 /CAS2 6 DQ4 42 /CAS3 7 DQ5 43 /CAS1 8 DQ6 44 /RAS0 9 DQ7 45 /RAS1 10 VCC 46 NC 11 PD1 47 /WE 12 A0 48 NC 13 A1 49 DQ18 14 A2 50 DQ19 15 A3 51 DQ20 16 A4 52 DQ21 17 A5 53 DQ22 18 A6 54 DQ23 19 A10 55 NC 20 NC 56 DQ24 21 DQ8 57 DQ25 22 DQ9 58 DQ26 23 DQ10 59 DQ27 24 DQ11 60 DQ28 25 DQ12 61 VCC 26 DQ13 62 DQ29 27 DQ14 63 DQ30 28 A7 64 DQ31 29 NC 65 NC 30 VCC 66 PD2 31 A8 67 PD3 32 A9 68 PD4 33 /RAS3 69 PD5 34 /RAS2 70 PD6 35 DQ15 71 PD7 36 NC 72 VSS Presence Detect Pins Pin No. Pin Name -60 -70 11 PD1 NC NC 66 PD2 VSS VSS 67 PD3 VSS VSS 68 PD4 NC NC 69 PD5 NC VSS 70 PD6 NC NC Semiconductor MSC23CV23268D BLOCK DIAGRAM A0-A9 /CAS0 /CAS1 /WE A0-A9 /RAS0 /RAS /LCAS /UCAS /WE /OE VSS A0-A9 /RAS2 /RAS /LCAS /UCAS /WE /OE VSS /CAS2 /CAS3 VCC C1-C8 VSS DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 A0-A9 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 VCC DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 VCC /UCAS DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 A0-A9 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 VCC DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 VCC /RAS /RAS1 /LCAS /WE /OE VSS /RAS /LCAS /UCAS /WE /OE VSS /RAS3 Semiconductor MSC23CV23268D ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Rating Unit VIN, VOUT -0.5 to +4.6 V Voltage on VCC Supply Relative to VSS VCC -0.5 to +4.6 V Short Circuit Output Current IOS 50 mA Power Dissipation PD * 4 W Operating Temperature TOPR 0 to +70 °C Storage Temperature TSTG -40 to +125 °C Voltage on Any Pin Relative to VSS * Ta = 25°C Recommended Operating Conditions ( Ta = 0°C to +70°C ) Parameter Symbol Min. Typ. Max. Unit VCC 3.0 3.3 3.6 V VSS 0 0 0 V Input High Voltage VIH 2.0 - VCC+0.3 V Input Low Voltage VIL -0.3 - 0.8 V Power Supply Voltage Capacitance ( VCC = 3.3V ± 0.3V, Ta = 25°C, f = 1 MHz ) Parameter Symbol Typ. Max. Unit Input Capacitance (A0 - A9) CIN1 - 31 pF Input Capacitance (/WE) CIN2 - 35 pF Input Capacitance (/RAS0- /RAS3) CIN3 - 13 pF Input Capacitance (/CAS0- /CAS3) CIN4 - 20 pF I/O Capacitance (DQ0 - DQ31) CDQ - 20 pF Semiconductor MSC23CV23268D DC Characteristics (VCC = 3.3V ± 0.3V, Ta = 0°C to +70°C ) -60 Parameter Symbol -70 Condition Unit Min. Max. Min. Max. Note Input Leakage Current ILI 0V ≤ VIN ≤ VCC+0.3V; All other pins not under test = 0V -40 40 -40 40 µA Output Leakage Current ILO DQ disable 0V ≤ VOUT ≤ VCC -20 20 -20 20 µA Output High Voltage VOH IOH = -2.0mA 2.4 VCC 2.4 VCC V Output Low Voltage VOL IOL = 2.0mA 0 0.4 0 0.4 V Average Power Supply Current (Operating) ICC1 /RAS, /CAS cycling, tRC = Min. - 240 - 220 mA 1, 2 /RAS, /CAS = VIH - 8 - 8 mA 1 /RAS, /CAS ≥ VCC -0.2V - 2 - 2 mA 1 Power supply current (Standby) ICC2 Average Power Supply Current (/RAS only refresh) ICC3 /RAS cycling, /CAS = VIH, tRC = Min. - 240 - 220 mA 1, 2 Average Power Supply Current (/CAS before /RAS refresh) ICC6 /RAS cycling, /CAS before /RAS - 240 - 220 mA 1, 2 Average Power Supply Current (Fast Page Mode) ICC7 /RAS = VIL, /CAS cycling, tHPC = Min. - 240 - 220 mA 1, 3 Notes: 1. ICC Max. is specified as ICC for output open condition. 2. The address can be changed once or less while /RAS = VIL. 3. The address can be changed once or less while /CAS = VIH. Semiconductor MSC23CV23268D AC Characteristics (1/2) (VCC = 3.3V ± 0.3V, Ta = 0°C to +70°C ) Note: 1, 2, 3 -60 Parameter -70 Symbol Unit Min. Max. Min. Max. Note Random Read or Write Cycle Time tRC 104 - 124 - ns Fast Page Mode Cycle Time tHPC 25 - 30 - ns Access Time from /RAS tRAC - 60 - 70 ns 4, 5, 6 Access Time from /CAS tCAC - 15 - 20 ns 4, 5 Access Time from Column Address tAA - 30 - 35 ns 4, 6 Access Time from /CAS Precharge t CPA - 35 - 40 ns 4 Output Low Impedance Time from /CAS tCLZ 0 - 0 - ns 4 Data Output Hold After /CAS Low tDOH 5 - 5 - ns /CAS to Data Output Buffer Turn-off Delay Time tCEZ 0 15 0 20 ns 7, 8 /RAS to Data Output Buffer Turn-off Delay Time tREZ 0 15 0 20 ns 7, 8 /WE to Data Output Buffer Turn-off Delay Time tWEZ 0 15 0 20 ns 7 Transition Time tT 1 50 1 50 ns 3 Refresh Period tREF - 16 - 16 ms /RAS Precharge Time tRP 40 - 50 - ns /RAS Pulse Width tRAS 60 10K 70 10K ns /RAS Pulse Width (Fast Page Mode with EDO) tRASP 60 100K 70 100K ns /RAS Hold Time tRSH 10 - 13 - ns /CAS Precharge Time (Fast Page Mode with EDO) tCP 10 - 10 - ns /CAS Pulse Width tCAS 10 10K 13 10K ns /CAS Hold Time tCSH 40 - 45 - ns /CAS to /RAS Precharge Time tCRP 5 - 5 - ns /RAS Hold Time from /CAS Precharge tRHCP 35 - 40 - ns /RAS to /CAS Delay Time tRCD 14 45 14 50 ns 5 /RAS to Column Address Delay Time tRAD 12 30 12 35 ns 6 Row Address Set-up Time tASR 0 - 0 - ns Row Address Hold Time tRAH 10 - 10 - ns Column Address Set-up Time tASC 0 - 0 - ns Column Address Hold Time tCAH 10 - 13 - ns Column Address to /RAS Lead Time tRAL 30 - 35 - ns Read Command Set-up Time tRCS 0 - 0 - ns Read Command Hold Time tRCH 0 - 0 - ns 9 Read Command Hold Time referenced to /RAS tRRH 0 - 0 - ns 9 Semiconductor MSC23CV23268D AC Characteristics (2/2) (VCC = 3.3V ± 0.3V, Ta = 0°C to +70°C ) Note: 1, 2, 3 -60 Parameter -70 Symbol Unit Min. Max. Min. Max. Write Command Set-up Time tWCS 0 - 0 - ns Write Command Hold Time tWCH 10 - 13 - ns Write Command Pulse Width tWP 10 - 10 - ns /WE Pulse Width (DQ Disable) tWPE 10 - 10 - ns Write Command to /RAS Lead Time tRWL 10 - 13 - ns Write Command to /CAS Lead Time tCWL 10 - 13 - ns Data-in Set-up Time tDS 0 - 0 - ns Data-in Hold Time tDH 10 - 13 - ns /CAS Active Delay Time from /RAS Precharge tRPC 5 - 5 - ns /RAS to /CAS Set-up Time (/CAS before /RAS) tCSR 5 - 5 - ns /RAS to /CAS Hold Time (/CAS before /RAS) tCHR 10 - 10 - ns Note Semiconductor MSC23CV23268D Notes: 1. A start-up delay of 200µs is required after power-up, followed by a minimum of eight initialization cycles (/RAS only refresh or /CAS before /RAS refresh) before proper device operation is achieved. 2. The AC characteristics assumes tT = 2ns. 3. VIH(Min.) and VIL(Max.) are reference levels for measuring input timing signals. Transition time (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 1TTL loads and 100pF. The output timing reference levels are VOH = 2.0V and VOL = 0.8V. 5. Operation within the tRCD(Max.) limit ensures that tRAC(Max.) can be met. tRCD(Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD(Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD(Max.) limit ensures that tRAC(Max.) can be met. tRAD(Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD(Max.) limit, then the access time is controlled by tAA. 7. tCEZ(Max.), tREZ(Max.) and tWEZ(Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tCEZ and tREZ must be satisfied for open circuit condition. 9. tRCH or tRRH must be satisfied for a read cycle.