ETC2 ISD1964 Single-chip, multiple-message voice record/playback device Datasheet

ISD1900
32
33
34
ISD1900
SINGLE-CHIP, MULTIPLE-MESSAGE
VOICE RECORD/PLAYBACK DEVICE
1
Publication Release Date: Jan 5, 2009
Revision 0.51
ISD1900
TABLE OF CONTENTS
1. GENERAL DESCRIPTION ...............................................................................................................................3
2. FEATURES.......................................................................................................................................................3
2.1.
Address Mode........................................................................................................................................... 3
2.2.
Direct Mode............................................................................................................................................... 4
3. BLOCK DIAGRAM ............................................................................................................................................5
4. PIN CONFIGURATION.....................................................................................................................................6
5. PIN DESCRIPTION ..........................................................................................................................................8
6. FUNCTIONAL DESCRIPTION .......................................................................................................................11
6.1.
Address Mode......................................................................................................................................... 11
6.1.1
Record (REC
¯¯¯¯) Operation................................................................................................................. 12
6.1.2
Edge-triggered Playback (PlayE
¯¯¯¯¯) Operation................................................................................... 14
6.1.3
Level-triggered Playback (¯¯¯¯¯)
PlayL Operation................................................................................... 14
6.1.4
Playback (Supersedes Record) Operation...................................................................................... 15
6.1.5
XCLK Feature .................................................................................................................................. 16
6.2.
Direct Mode............................................................................................................................................. 16
6.3.
Other Operations .................................................................................................................................... 19
6.3.1
Rosc Operation................................................................................................................................ 19
6.3.2
LED Operation ................................................................................................................................. 20
6.3.3
Feed-Through mode Operation....................................................................................................... 20
6.3.4
Power-On Playback Operation........................................................................................................ 20
6.3.5
Automatic Single Message Playback .............................................................................................. 20
6.3.6
Power is interrupted Abruptly .......................................................................................................... 20
7. ABSOLUTE MAXIMUM RATINGS [1]..............................................................................................................21
7.1.
Operating Conditions .............................................................................................................................. 21
8. ELECTRICAL CHARACTERISTICS ..............................................................................................................22
8.1.
DC Parameters ....................................................................................................................................... 22
8.2.
AC Parameters ....................................................................................................................................... 23
9. TYPICAL APPLICATION CIRCUIT ................................................................................................................24
10. PACKAGING...................................................................................................................................................26
10.1.
28-Lead 300-Mil Plastic Small Outline Integrated Circuit (SOIC) ....................................................... 26
11. ORDERING INFORMATION ..........................................................................................................................27
12. VERSION HISTORY.......................................................................................................................................28
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Publication Release Date: Jan 5, 2009
Revision 0.51
ISD1900
1. GENERAL DESCRIPTION
0
Nuvoton’s ISD1900 ChipCorder® Series is a single-chip multiple-message record/playback device with dual
operating modes and wide operating voltage ranging from 2.4V to 5.5V. The sampling frequency can be
selected from 4 to 12 kHz via an external resistor, which also determines the duration. The device is designed
for mostly standalone applications, and of course, it can be manipulated by a microcontroller, if necessary.
The two operating modes are Address Mode and Direct Mode. While in Address Mode, both record and
playback operations are manipulated according to the start address and end address specified through the start
address and end address pins. In Direct Mode, the device can configure the memory up to as many as eight
similar duration messages, pending upon the fixed message configuration settings. With the record or
playback feature being pre-selected, each message can be randomly accessed via its message control pin.
The device has a selectable differential microphone input with AGC feature or single-ended analog input, AnaIn,
under feed-through mode. The audio output is either a differential Class-D PWM direct-drive or a single-ended
voltage output (AUX out), depending on the derivative selected.
2. FEATURES
1
The ISD1900 is a multiple messages record/playback device with two operational modes: Address Mode and
Direct Mode.
•
Supply voltage: 2.4V to 5.5V.
•
External resistor, Rosc, selects sampling frequency and duration.
Sampling Frequency
12 kHz
8 kHz
6.4 kHz
Rosc
53.3 KΩ
80 KΩ
100 KΩ
ISD1916
10.6 sec
16 sec
20 sec
ISD1932
21.3 sec
32 sec
40 sec
ISD1964
42.6 sec
64 sec
80 sec
5.3 kHz
120 KΩ
24 sec
48 sec
96 sec
4 kHz
160 KΩ
32 sec
64 sec
128 sec
•
Mic+/Mic-: differential microphone inputs.
•
AGC: automatic gain control for microphone preamp circuit.
•
FT
¯¯: feed-through the AnaIn signal to the speaker outputs while AnaIn is converted from MIC+.
•
When both FT
¯¯ and recording are active, device will record AnaIn signal into memory with AnaIn signal output
to speaker simultaneously.
•
SP+/SP-: Class-D PWM differential speaker drivers or single-ended voltage output, depending on the
derivative selected.
•
¯¯¯¯:
LED LED is on during recording.
•
Automatically power down after each operation cycle.
•
Playback takes precedence over the recording operation.
y
Temperature option: -40°C to +85°C (Industrial)
y
Packaging: available in SOIC only
2.1. ADDRESS MODE
12
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Publication Release Date: Jan 5, 2009
Revision 0.51
ISD1900
• While in Address Mode, flexible message duration is defined by start address and end address.
• Utilize four start address pins (S0, S1, S2 & S3) and four end address pins (E0, E1, E2 & E3) to specify
the message duration.
• ¯¯¯¯:
REC Level-hold or Edge-trigger (toggle on-off) recording from start to end addresses.
• ¯¯¯¯¯:
PlayE Edge-trigger playback from start to end address and stops at EOM marker, if EOM is prior to
end address. Toggle on-off.
• ¯¯¯¯¯:
PlayL Level-hold playback from start to end address.
playback from start to end address.
Also, if constantly Low, device will loop
2.2. DIRECT MODE
13
• While Direct Mode is active, utilizing the configuration pins, FMC1, FMC2 & FMC3, to define up to eight
similar duration messages for random access.
• The control pins are: M1
¯¯ ~ M8
¯¯ (message activation) and ¯¯/P
R (record or playback selection).
• The record or playback operation is pre-defined by the ¯¯/P
R pin.
• Each message can be randomly accessed via its message control pin (M1
¯¯ ~ M8
¯¯ ) and the desired
operation is facilitated accordingly.
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Revision 0.51
ISD1900
3. BLOCK DIAGRAM
2
Rosc
MIC+ /
AnaIn
MIC- /
NC
Clock Control
PreAmp
Non-Volatile
Multi Level Storage
Array
Antialiasing
Filter
Amp
Automatic
Gain Control
(AGC)
AGC
Smoothing
Filter
SP + /
AUX
Amp
SP - /
NC
Switch
Power Conditioning
Device & Address Control
Address Mode:
Addr
LED FT
XCLK
PlayE PlayL REC S0 S1 S2
Direct Mode:
Drct
LED FT
FMC3
FMC2 FMC1 R/P
S3 E0
E1 E2 E3
VCCA VSSA VCCD VSSD VCCp VSSP1 VSSP2
M1 M2 M3 M4 M5 M6 M7 M8
Figure 3-1 Block Diagram
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Publication Release Date: Jan 5, 2009
Revision 0.51
ISD1900
4. PIN CONFIGURATION
3
VSSD
1
28
VCCD
S0 / M1
2
27
Addr / Drct
S1 / M2
3
26
FT
S2 / M3
4
25
XCLK / FMC3
S3 / M4
5
24
REC / R/P
PlayL / FMC1
6
23
PlayE / FMC2
E0 / M5
7
22
LED
VSSA
8
21
VCCA
E1 / M6
9
20
Rosc
E2 / M7
10
19
Mic-_NC
E3 / M8
11
18
Mic+_AnaIn
VSSP2
12
17
AGC
SP-
13
16
VSSP1
VCCP
14
15
SP+
ISD1900
Figure 4-1 Pin Configuration
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ISD1900
VSSD
1
28
M1
2
27
VCCD
Drct
FT
M2
3
26
FT
25
XCLK
M3
4
25
FMC3
5
24
REC
M4
5
24
R/P
PlayL
6
23
PlayE
FMC1
6
23
FMC2
E0
7
22
LED
M5
7
22
LED
VSSA
8
21
VCCA
VSSA
8
21
VCCA
E1
9
20
Rosc
M6
9
20
Rosc
E2
10
19
Mic-_NC
M7
10
19
Mic-_NC
E3
11
18
Mic+_AnaIn
M8
11
18
Mic+_AnaIn
VSSP2
12
17
AGC
VSSP2
12
17
AGC
SP-
13
16
VSSP1
SP-
13
16
VSSP1
VCCP
14
15
SP+
VCCP
14
15
SP+
VSSD
1
28
S0
2
27
VCCD
Addr
S1
3
26
S2
4
S3
ISD1900
Figure 4-2 Pin Configuration – Address Mode
7
VCC
ISD1900
Figure 4-3 Pin Configuration – Direct Mode
Publication Release Date: Jan 5, 2009
Revision 0.51
ISD1900
5. PIN DESCRIPTION
4
PIN NAME
VSSD
S0/M1
¯¯
PIN #
1
2
I/O
I
I
FUNCTION
Digital Ground: Ground path for digital circuits.
S0[1] : In Address Mode, Start Address Bit 0.
M1
¯¯ : When Direct Mode is active, low active operation on 1st Message.
Internal pull-up & debounce existed.
S1/M2
¯¯
3
I
S1[1] : In Address Mode, Start Address Bit 1.
M2
¯¯ : When Direct Mode is active, low active operation on 2nd Message.
Internal pull-up & debounce existed.
S2/M3
¯¯
4
I
S2[1] : In Address Mode, Start Address Bit 2.
M3
¯¯ : When Direct Mode is active, low active operation on 3rd Message.
Internal pull-up & debounce existed.
S3/M4
¯¯
5
I
S3[1] : In Address Mode, Start Address Bit 3.
M4
¯¯ : When Direct Mode is active, low active operation on 4th Message.
Internal pull-up & debounce existed.
¯¯¯¯¯/FMC1
PlayL
6
I
¯¯¯¯¯:
PlayL In Address Mode, low active input, Level-hold playback start to end
addresses, debounce & internal pull-up existed. Holding ¯¯¯¯¯
PlayL Low
constantly will perform looping playback function from start to end
addresses with insignificant dead time between messages regardless of
sampling frequencies.
FMC1: When Direct Mode is active, FMC1, together with FMC2 & FMC3,
setup various fixed-message configurations.
E0/M5
¯¯
VSSA
E1/M6
¯¯
7
8
9
I
I
I
E0[1] : In Address Mode, End Address Bit 0.
M5
¯¯ : When Direct Mode is active, low active operation on 5th Message.
Internal pull-up & debounce existed.
Analog Ground: Ground path for analog circuits.
E1[1] : In Address Mode, End Address Bit 1.
M6
¯¯ : When Direct Mode is active, low active operation on 6th Message.
Internal pull-up & debounce existed.
E2/M7
¯¯
10
I
E2[1] : In Address Mode, End Address Bit 2.
M7
¯¯ : When Direct Mode is active, low active operation on 7th Message.
Internal pull-up & debounce existed.
E3/M8
¯¯
11
I
VSSP2
SP-
12
13
I
O
VCCP
14
I
E3[1] : In Address Mode, End Address Bit 3.
M8
¯¯ : When Direct Mode is active, low active operation on 8th Message.
Internal pull-up & debounce existed.
Ground: Ground for negative PWM speaker driver.
SP-: Negative signal of the differential Class-D PWM speaker outputs. This
output, together with the SP+, is used to drive an 8Ω speaker directly.
Speaker Power Supply: Power supply for PWM speaker drivers.
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ISD1900
PIN NAME
SP+
PIN #
15
I/O
O
VSSP1
AGC
16
17
I
I
MIC+ / AnaIn
18
I
MIC- / NC
19
I
Rosc
20
I
VCCA
¯¯¯¯
LED
21
22
I
O
¯¯¯¯¯/FMC2
PlayE
23
I
FUNCTION
Depending on the derivative selected, it could be:
SP+: Positive signal of the differential Class-D PWM speaker outputs. This
output, together with the SP-, is used to drive an 8Ω speaker directly.
Or,
AUX out: single-ended voltage output.
Ground: Ground for positive PWM speaker driver.
Automatic Gain Control (AGC): The AGC adjusts the gain of the
preamplifier dynamically to compensate for the wide range of microphone
input levels. The AGC allows the full range of signals to be recorded with
minimal distortion. The AGC is designed to operate with a nominal
capacitor of 4.7 µF connected to this pin.
Connecting this pin to ground (VSSA) provides maximum gain to the
preamplifier circuitry. Conversely, connecting this pin to the power supply
(VCCA) provides minimum gain to the preamplifier circuitry.
MIC+: Non-inverting input of the differential microphone signal.
AnaIn: When FT
¯¯ is selected, the MIC+ input is configured to a single-ended
input with 1Vp-p maximum input amplitude and feed-through to the speaker
outputs.
MIC-: Inverting input of the differential microphone signal. While FT
¯¯ is
enabled, MIC- pin is disabled and must be floated.
Oscillator Resistor: Connect an external resistor from this pin to VSSA to
select the internal sampling frequency.
Analog Power Supply: Power supply for analog circuits.
LED output: During recording, this output is Low. Also, ¯¯¯¯
LED pulses Low
momentarily at the end of playback.
¯¯¯¯¯:
PlayE In Address Mode, low active input, edge-trigger playback from start
to end addresses & toggle on-off. Debounce & internal pull-up existed.
FMC2: When Direct Mode is active, FMC2, together with FMC1 & FMC3,
setup various fixed-message configurations.
¯¯¯¯/
REC ¯¯/P
R
24
I
¯¯¯¯:
REC In Address Mode, level-hold (after 1 sec holding) or edge-trigger
(toggle on-off), low active, recording from start to end addresses. Debounce
& internal pull-up existed.
¯¯/P
R ( When Direct Mode is active):
• When ¯¯/P
R is set to Low, level-hold record operation is selected.
When ¯¯/P
R is set to High, edge-trigger & toggle on-off playback operation is
selected.
¯¯¯¯¯/FMC3
XCLK
25
I
XCLK
External Clock: In Address Mode, low active and level-hold input. As ¯¯¯¯¯
activated, Rosc pin accepts external clock input signal, provided resistor at
Rosc must be removed. Connecting this pin to High enables device running
on internal clock via Rosc resistor. If not used, ¯¯¯¯¯
XCLK must be at high level.
When Direct Mode is active, FMC3, together with FMC1 & FMC2, setup
various fixed-message configurations.
FT
¯¯
26
I
Feed-Through: Low active input, Level-hold, debounce & Internal pull-up
required. When FT
¯¯ is selected, the MIC+ input is configured to a singleended input with 1Vp-p maximum input amplitude and feed-through to the
speaker outputs.
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Publication Release Date: Jan 5, 2009
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ISD1900
PIN NAME
Addr/¯¯¯¯
Drct
PIN #
27
I/O
I
FUNCTION
Level-hold input.
Addr: When set to High, the device operates under Address Mode.
Level-hold input.
¯¯¯¯:
Drct When set to Low, the device operates under Direct Mode. The
device reconfigures its pin definitions to fit various fixed-message
configurations utilizing FMC1 , FMC2 & FMC3 pins as below table.
FMC3
FMC2
FMC1
# of fixed messages
0
0
0
1
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
1
0
1
6
1
1
0
7
1
1
1
8
VCCD
28
I
Digital Power Supply: Power supply for digital circuits.
Notes: [1] : Address bits S0, S1, S2, S3, E0, E1, E2 & E3 are used to access the memory location.
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Publication Release Date: Jan 5, 2009
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ISD1900
6. FUNCTIONAL DESCRIPTION
5
There are two operational modes: Address Mode and Direct Mode.
Addr/¯¯¯¯,
Drct the power must be cycled to enable it.
After a new condition is selected on
6.1. ADDRESS MODE
14
The start address pins (S0, S1, S2 & S3) and end address pins (E0, E1, E2 & E3) are used to access the
memory location and they can divide the memory into a maximum of 16 slots. They are defined as
follows:
S3
S2
S1
S0
Row #
( E3 )
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
( E2 )
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
( E1 )
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
( E0 )
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
8
16
24
32
40
48
56
64
72
80
88
96
104
112
120
S3
S2
S1
S0
Row #
( E3 )
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
( E2 )
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
( E1 )
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
( E0 )
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
16
32
48
64
80
96
112
128
144
160
176
192
208
232
240
11
I1916
Duration [s]
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
12.0
13.0
14.0
15.0
I1932
Duration [s]
0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
18.0
20.0
22.0
24.0
26.0
28.0
30.0
Publication Release Date: Jan 5, 2009
Revision 0.51
ISD1900
S3
S2
S1
S0
Row #
( E3 )
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
( E2 )
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
( E1 )
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
( E0 )
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
32
64
96
128
160
192
224
256
288
320
352
384
416
464
480
I1964
Duration [s]
0
4.0
8.0
12.0
16.0
20.0
24.0
28.0
32.0
36.0
40.0
44.0
48.0
52.0
56.0
60.0
Below is an example:
Given sampling rate set to 6.4 kHz, using the ISD1916 to record four messages: three messages of 2.5 seconds
and one message of 12.5 seconds, then the memory can be assigned as follows:
S3, S2, S1, S0
E3, E2, E1, E0
Message 1 (2.5 seconds)
0
0
0
0
0
0
0
1
Message 2 (2.5 seconds)
0
0
1
0
0
0
1
1
Message 3 (2.5 seconds)
0
1
0
0
0
1
0
1
Message 4 (12.5 seconds)
0
1
1
0
1
1
1
1
6.1.1
21
Record (REC
¯¯¯¯) Operation
• Low active input:
o level-hold for level-trigger or
o falling edge for edge-trigger with debounce required.
• For 8kHz sampling frequency, if ¯¯¯¯
REC is held at Low for a period equal to 1 sec or more, then level
recording is activated. However, if ¯¯¯¯
REC is pulsed Low for less than 1 sec, then edge-trigger
recording is initiated.
• For 6.4kHz sampling frequency, if ¯¯¯¯
REC is held at Low for a period equal to 1.25 sec or more, then level
recording is activated. However, if ¯¯¯¯
REC is pulsed Low for less than 1.25 sec, then edge-trigger
recording is initiated.
• Recording begins from the start address to end address and ¯¯¯¯
LED is on.
• Recording ceases whenever:
ƒ ¯¯¯¯
REC returns to High in level-hold mode or
ƒ a subsequent low-pulse appears while in edge-trigger mode or
ƒ when end address is reached.
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ISD1900
o Then an EOM marker is written at the end of message. And ¯¯¯¯
LED is off.
o Then the device will automatically power down.
• This pin has an internal pull-up device.
• Once ¯¯¯¯
REC is active, input on FT
¯¯, Addr/¯¯¯¯,
Drct S0, S1, S2, S3, E0, E1, E2 or E3 is illegal.
Addr/Drct
<S3:S0>
<E3:E0>
TASet
TAHold
REC
TDeb
LED
TStop1
TErs
Mic+/or AnaIn
End Address
Figure 6-1 Record–Level (REC
¯¯¯¯) function till end address
Addr/Drct
<S3:S0>
<E3:E0>
TAHold
TASet
REC
Start
TDeb
TASet
TAHold
Start
Stop
TSettle1
TDeb
TDeb
LED
TErs
Mic+/or AnaIn
TStop1
TErs
End Address
Figure 6-2 Record–Level (¯¯¯¯
REC ) function with start and stop actions
Addr/Drct
<S3:S0>
<E3:E0>
TAHold
TASet
Start
REC
Start
Stop
TDeb
TDeb
TAHold
TASet
TSettle1
TDeb
LED
Mic+/or AnaIn
TErs
TStop1
TErs
End Address
Figure 6-3 Record–Edge (¯¯¯¯
REC ) function with on-off
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ISD1900
6.1.2
22
Edge-triggered Playback (PlayE
¯¯¯¯¯) Operation
• Low active input, edge-trigger, toggle on-off, debounce required.
• Playback begins from the start address to end address or EOM, whichever occurrs first.
• At the end of message, ¯¯¯¯
LED pulses Low momentarily.
o Then device will automatically power down.
• During playback, a subsequent trigger terminates the playback operation. If EOM marker is not encountered,
then ¯¯¯¯
LED will not pulses Low momentarily.
• This pin has an internal pull-up device.
• Once ¯¯¯¯¯
PlayE is active, input on ¯¯¯¯¯,
PlayL ¯¯¯¯,
REC FT
¯¯, Addr/¯¯¯¯,
Drct S0, S1, S2, S3, E0, E1, E2 or E3 is
banned.
Addr/Drct
<S3:S0>
<E3:E0>
TAHold
TASet
TASet
Start
PlayE
TDeb
Start
Stop
TDeb
TAHold
TSettle2
TEOM
TDeb
LED
End of
Message
Sp+
Sp-
Figure 6-4 Playback–Edge (¯¯¯¯¯
PlayE) function
6.1.3
23
Level-triggered Playback (PlayL
¯¯¯¯¯) Operation
• Low active input, Level-hold, debounce required.
• Once active, playback begins from the start address and stops whenever ¯¯¯¯¯
PlayL returns to High.
When an EOM is encountered, ¯¯¯¯
LED pulses Low momentarily.
o Then device will automatically power down.
• This pin has an internal pull-up device.
• Once ¯¯¯¯¯
PlayL is active, input on ¯¯¯¯¯,
PlayE ¯¯¯¯,
REC FT
¯¯, Addr/¯¯¯¯,
Drct S0, S1, S2, S3, E0, E1, E2 or E3 is
prohibited.
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ISD1900
Addr/Drct
<S3:S0>
<E3:E0>
TASet
TAHold
PlayL
Start
TDeb
TDeb
TASet
Start
Stop
TSettle2
LED
TAHold
TEOM
TDeb
Part of
Message
End of
Message
Sp+
Sp-
Figure 6-5 Playback–Level (¯¯¯¯¯
PlayL ) function
• Holding ¯¯¯¯¯
PlayL Low constantly will perform looping playback function, without power down, from start
address to end address.
Addr/Drct
<S3:S0>
<E3:E0>
TASet
TAHold
PlayL
TDeb
TEOM
TEOM
LED
Sp+
Sp-
Figure 6-6 Looping playback function via ¯¯¯¯¯
PlayL
6.1.4
24
Playback (Supersedes Record) Operation
• Playback takes precedence over the Recording operation.
• If either ¯¯¯¯¯
PlayE or ¯¯¯¯¯
PlayL is activated during a recording cycle, the recording immediately ceases with
an EOM marker attached, and without power down, playback of the just-recorded message performs
accordingly. Then device powers down.
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Addr/Drct
<S3:S0>
<E3:E0>
TAHold
TASet
REC
TEOM
TDeb
LED
TErs
Mic+/or AnaIn
TSettle1 TSettle3
PlayE
TDeb
SP+
SP-
Figure 6-7 An example of Playback supersedes Record
6.1.5
25
XCLK Feature
• When precision sampling frequency is required, external clock mode can be activated by setting ¯¯¯¯¯
XCLK
to Low. Under such condition, the resistor at Rosc pin must be removed and the external clock signal
must be applied to the Rosc pin. These conditions must be satisfied prior to any operations.
• However, when internal clock is used, ¯¯¯¯¯
XCLK must be linked to High.
• The external clock frequencies required for various sampling frequencies are listed in below table.
Sampling Freq [kHz]
12
8
6.4
5.3
4
¯¯¯¯¯
XCLK [MHz]
3.072
2.048
1.638
1.356
1.024
6.2. DIRECT MODE
15
• The Direct Mode is selected by the ¯¯¯¯
Drct pin. Once chosen, the supply voltage must be reset to allow
the device to construct itself to the appropriate configuration by re-defining the function on the related
control pins. Also, the mode change is only allowed while the device is in power down state and is
inhibited when an operation is in progress.
• Once Direct Mode is activated, FMC1, FMC2 & FMC3 are utilized to select various (1 to 8) fixed
message configurations [1]. Pending upon the arrangement on FMC1, FMC2 & FMC3, each divided
message has approximate equal length of duration, which is related to the number of rows assigned as
in tables below.
• The record or playback operation is pre-defined by the ¯¯/P
R pin. Setting this pin to Low allows record
operation while setting it to High enables playback operation.
• Each message can be randomly accessed via its message control pin (M1
¯¯ ~ M8
¯¯ ) and the desired
operations are facilitated accordingly. Non-configured pins are automatically disabled and must be
floated.
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Notes:
[1]
[2]
: Number of fixed message arrangement with respect to FMC1, FMC2 & FMC3.
FMC2
FMC1
# of fixed messages [1]
FMC3
0
0
0
1
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
1
0
1
6
1
1
0
7
1
1
1
8
: Number of memory row arrangement with respect to different number of fixed messages
for ISD1916 (128 Rows). The non-configured Message control pins (Mx) will be disabled.
# of
Msg
M1
M2
M3
M4
M5
M6
M7
M8
128
1
64
64
2
44
42
42
3
32
32
32
32
4
26
26
26
26
24
5
23
21
21
21
21
21
6
20
18
18
18
18
18
18
7
16
16
16
16
16
16
16
16
8
for ISD1932 (256 Rows)
# of
Msg
M1
M2
256
1
128
128
2
86
85
3
64
64
4
52
51
5
43
43
6
37
37
7
32
32
8
for ISD1964 (512 Rows)
# of
Msg
M1
M2
512
1
256
256
2
172
170
3
128
128
4
103
103
5
86
86
6
74
73
7
64
64
8
M3
M4
M5
M6
M7
M8
85
64
51
43
37
32
64
51
43
37
32
51
42
36
32
42
36
32
36
32
32
M3
M4
M5
M6
M7
M8
170
128
102
85
73
64
128
102
85
73
64
102
85
73
64
85
73
64
73
64
64
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[3]
: The durations for various fixed message configurations on I1916 device at 8 kHz
sampling frequency are shown in below table.
# of
Msg
M1
M2
M3
M4
M5
M6
M7
M8
16
1
8
8
2
5.5
5.25
5.25
3
4.0
4.0
4.0
4.0
4
3.25
3.25
3.25
3.25
3.0
5
2.875 2.625 2.625 2.625 2.625 2.625
6
2.50
2.25
2.25
2.25
2.25
2.25
2.25
7
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
8
for ISD1932 (256 Rows)
# of
Msg
M1
M2
32
1
16
16
2
10.62
3
10.75 5
8.0
8.0
4
6.5
6.375
5
5.375 5.375
6
4.625 4.625
7
4.0
4.0
8
for ISD1964 (512 Rows)
# of
Msg
M1
64
1
32
2
21.5
3
16.0
4
12.87
5
5
6
10.75
9.25
7
8.0
8
M2
32
21.25
16.0
12.87
5
10.75
9.125
8.0
M3
M4
M5
10.62
5
8.0
6.375
5.375
4.625
4.0
8.0
6.375
5.375
4.625
4.0
6.375
5.25
4.5
4.0
M3
M4
M5
M6
M7
21.25
16.0
16.0
12.75
10.62
5
9.125
8.0
12.75
10.62
5
9.125
8.0
12.75
10.62
5
9.125
8.0
10.62
5
9.125
8.0
9.125
8.0
18
M6
5.25
4.5
4.0
M7
4.5
4.0
M8
4.0
M8
8.0
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35
Example of four Fixed-Message Configuration:
Addr/Drct
FM3
FM2
FM1
TFSet
R/P
Stop
M1 ~ M4
Start
TSettle1
TDeb
LED
Start
TDeb
TDeb
TStop1
TErs
TErs
Mic+/or AnaIn
End of Duration
Figure 6-8 Record Operation under FMC mode
Addr/Drct
FM3
FM2
FM1
TFSet
R/P
Start
Stop
Start
M1 ~ M4
TEOM
LED
TDeb
TDeb TSettle2
TDeb
End of Message
Sp+
Sp-
Figure 6-9 Playback Operation under FMC mode
6.3. OTHER OPERATIONS
16
6.3.1
26
Rosc Operation
• When the ROSC varies from 53.3 KΩ to 160 KΩ, the sampling frequency changes from 12 to 4 kHz
accordingly.
• When ROSC resistor value is changed during playback, the tone of a recorded message will alter either
faster or slower.
• If the ground side of ROSC resistor is floated or tied to VCC, then the current operation will be freezed.
• The operation will resume when the resistor is connected back to ground.
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6.3.2
27
LED Operation
• ¯¯¯¯
LED turns on during recording. Also, ¯¯¯¯
LED pulses Low at the end of message.
must be sufficiently greater than debounce time.
6.3.3
28
The Low period
Feed-Through mode Operation
• As FT
¯¯ is held Low, the Mic+ pin will be reconfigured as AnaIn input, and the AnaIn signal will be
transmitted to the speaker outputs. Under this mode, Mic- pin is not used (must be floated).
• After FT
¯¯ is enabled, If ¯¯¯¯
REC is triggered, then AnaIn signal will be recorded into memory while the
Feed-Through path remains on.
• If FT
¯¯ is already enabled, activating either ¯¯¯¯¯
PlayE or ¯¯¯¯¯
PlayL will first disable the FT path and then play the
recorded message. Once playback completes, FT path will be resumed.
• During an operation, activating the FT
¯¯ pin is not allowed.
6.3.4
29
Power-On Playback Operation
• If ¯¯¯¯¯
PlayE is kept at Low during power turns on, the device plays message once, then powers down.
• If ¯¯¯¯¯
PlayL is held at Low during power turns on and constantly maintained at Low, the device will play
the message repeatedly, with insignificant dead time between messages regardless of sampling
frequencies. This status will sustain unless power is turned off or ¯¯¯¯¯
PlayL somehow returns to High.
6.3.5
30
Automatic Single Message Playback
• If ¯¯¯¯
LED is connected to ¯¯¯¯¯,
PlayE once ¯¯¯¯¯
PlayE is triggered, the device plays message repeatedly without
power down between the looping playback. However, if ¯¯¯¯¯
PlayE is triggered again during playback,
then playback will stop.
6.3.6
31
Power is interrupted Abruptly
• During the device is in operation, it is strongly recommended that the supply power cannot be
interrupted. Otherwise, it may cause the device to become malfunctioning.
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7. ABSOLUTE MAXIMUM RATINGS [1]
6
ABSOLUTE MAXIMUM RATINGS
CONDITION
VALUE
Junction temperature
150°C
Storage temperature range
-65°C to +150°C
Voltage applied to any pins
(VSS – 0.3V) to (VCC + 0.3V)
Voltage applied to Input pins (current limited to +/-20 mA)
(VSS – 1.0V) to (VCC + 1.0V)
Voltage applied to output pins (current limited to +/-20 mA)
(VSS – 1.0V) to (VCC + 1.0V)
VCC – VSS
-0.3V to +7.0V
[1]
Stresses above those listed may cause permanent damage to the device. Exposure to the absolute
maximum ratings may affect device reliability and performance. Functional operation is not implied at these
conditions.
7.1. OPERATING CONDITIONS
17
OPERATING CONDITIONS
CONDITION
VALUE
Operating temperature range
Operating voltage (VCC)
Ground voltage (VSS)
[1]
VCC = VCCA = VCCD
[2]
VSS = VSSA = VSSD
0°C to +50°C
[1]
+2.4V to +5.5V
[2]
0V
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8. ELECTRICAL CHARACTERISTICS
7
8.1. DC PARAMETERS
18
PARAMETER
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Standby Current
Record Current
Playback Current
Pull-up device for ¯¯¯¯
REC , ¯¯¯¯¯
PlayE ,
¯¯¯¯¯
PlayL , FT
¯¯ & M1
¯¯ ~ M8
¯¯ pins
MIC+ Input Resistance
MIC- Input Resistance
AnaIn Input Resistance
MIC Differential Input
AnaIn Input
Gain from MIC to SP+/-
SYMBOL MIN[2]
VIL
VIH
0.7xVcc
VOL
VOH
0.7xVcc
ISTBY
IREC
IPLAY
RPU1
Gain from AnaIn to SP+/Output Load Impedance
Speaker Output Power
AASP
RSPK
Pout
Speaker Output Voltage
Total Harmonic Distortion
RMICP
RMICN
RANAIN
VIN1
VIN2
AMSP
TYP[1]
MAX[2]
0.3xVcc
0.3xVcc
1
20
20
600
10
30
30
18
18
42
15
300
1
40
6
0
UNITS
V
V
V
V
µA
mA
mA
kΩ
KΩ
KΩ
KΩ
mV
V
dB
CONDITIONS
IOL = 4.0 mA[3]
IOH = -1.6 mA[3]
[4] [5]
VCC = 5.5V [4] [5]
VCC = 5.5V, no load [4] [5]
Peak-to-peak
Peak-to-peak
VIN = 15~300 mVp-p,
AGC = 4.7 µF,
VCC = 2.4V~5.5V
VCC = 2.4V~5.5V
670
313
117
49
dB
Ω
mW
mW
mW
mW
VOUT1
VDD
V
RSPK = 8Ω Speaker,
Typical buzzer
THD
1
%
15 mV p-p 1 kHz sine
wave, Cmessage
weighted
8
Speaker load
VDD = 5.5 V
VDD = 4.4 V
VDD= 3 V
VDD= 2.4 V
1Vp-p,
1 kHz sine
wave at
AnaIn. RSPK
=8Ω
Notes: [1] Typical values @ VCC = 5.5V, TA = 25° and sampling frequency (Fs) at 8 kHz, unless stated.
[2]
Not all specifications are 100 percent tested. All Min/Max limits are guaranteed by Nuvoton via design, electrical testing
and/or characterization.
[3]
LED output during recording.
[4]
VCCA, VCCD and VCCP are connected together. Also, VSSA, VSSD, VSSP1 and VSSP2 are linked together.
[5]
All required control pins must be at appropriate status. External components are biased under a separated power
supply.
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8.2. AC PARAMETERS
19
CHARACTERISTIC [1]
SYMBOL
MIN[2]
Fs
TREC / TPLAY
4
10.6
12
32
UNIT
S
kHz
sec
TREC / TPLAY
21.3
64
sec
[3]
TREC / TPLAY
42.6
128
sec
[3]
Sampling Frequency
Record / Playback
Duration (ISD1916)
Record / Playback
Duration (ISD1932)
Record / Playback
Duration (ISD1964)
Debounce Time
Address Setup Time
Address Hold Time
Erase Time
TDeb
TASet
TAhold
TErs
FMC Setup Time
Record Settle Time
Play Settle Time
TFset
TSettle1
TSettle2
Delay from Record to Play
TSettle3
Record Stop Time
LED Pulse Low Time
TStop1
TEOM
TYP
225k/Fs
30
225k/Fs
1.25MR
N
30
MAX[2]
msec
nsec
msec
msec
32k/Fs
256k/F
s
128k/F
s
30
256k/F
s
nsec
msec
msec
msec
nsec
msec
CONDITIONS
[3]
[3]
[3] [4]
[3] [4]
MRN = message row #
[3] [4]
[3] [4]
[3] [4]
[3] [4]
Notes:
[1]
Conditions are VCC = 5.5V, TA = 25°C and sampling frequency (FS) at 8kHz, unless specified.
[2]
Not all specifications are 100 percent tested. All Min/Max limits are guaranteed by Nuvoton via design, electrical
testing and/or characterization.
[3]
When different FS is applied, the value will change accordingly. Also, stability of internal oscillator may vary as much
as +10% over the operating temperature and voltage ranges.
[4]
k = 1000.
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9. TYPICAL APPLICATION CIRCUIT
8
The following typical application examples on ISD1900 series are for references only. They make no
representation or warranty that such applications shall be suitable for the use specified. It’s customer’s
obligation to verify the design in its own system for the functionalities, voice quality, current consumption,
and etc.
In addition, the below notes apply to the following application examples:
•
The suggested values are for references only. Depending on system requirements, they can be adjusted
for functionalities, voice quality and degree of performance.
It is important to have a separate path for each ground and power back to the related terminals to minimize
the noise. Besides, the power supplies should be decoupled as close to the device as possible.
Also, it is crucial to follow good audio design practices in layout and power supply decoupling. See
recommendations in Application Notes from our websites.
Example #1: Operations via start and end address under Address Mode.
To switches or
address I/Os
VCC
4.7 k Ω∗
4.7μ F*
4.7 k Ω∗
Addr
PLAYE
LED
PLAYL
XCLK
S3
S2
S1
S0
E3
E2
E1
E0
0.1 μ F*
4.7 μ F*
Rosc*
1 KΩ
D1
Vcc
0.1μ F
Gnd
VCCA
VCCD
VCCP
VCCD
VCCD
10 μ F*
VSSD
Mic+_AnaIn
Mic-
VCCA
VCCA
ISD1900
FT
0.1 μ F*
4.7 k Ω∗
REC
0.1μ F
10 μ F*
VSSA
VCCP
VSSP1
VSSP2
AGC
SP+/AUX
Rosc
SP-/NC
24
VCCP
0.1μ F
10 μ F*
10 μ F*
0.1μ F
Speaker
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ISD1900
Example #2: Fixed Message Configuration Operations under Direct Mode.
VCC
1 kΩ
R/P
LED
M1
M2
Drct
FMC3
M3
FMC2
M4
FMC1
VCCD
M5
M6
VCC
M8
ISD1900
FT
4.7 μ F*
Rosc*
36
VCCP
Mic+_AnaIn
0.1 μ F*
4.7 kΩ∗
VCCD
0.1μ F
VSSP1
Mic-
0.1μ F
10 μ F
VCCP
0.1μ F
10 μ F*
10 μ F*
0.1μ F
VSSP2
AGC
Rosc
10 μ F*
VCCA
VCCA
4.7μ F*
0.1 μ F*
Gnd
VCCA
VCCD
VCCP
VSSA
4.7 k Ω∗
Vcc
VSSD
M7
4.7 k Ω∗
D1
SP+/AUX
Speaker
SP-/NC
Good Audio Design Practices
Nuvoton’s ChipCorder are very high-quality single-chip voice recording and playback devices. To ensure the
highest quality voice reproduction, it is important that good audio design practices on layout and power supply
decoupling are followed. See Application Information links below for details.
Good Audio Design Practices
http://www.Nuvoton-usa.com/products/isd_products/chipcorder/applicationinfo/apin11.pdf
Single-Chip Board Layout Diagrams
http://www.Nuvoton-usa.com/products/isd_products/chipcorder/applicationinfo/apin12.pdf
It is strongly recommended that before any design or layout project starts, the designer should contact Nuvoton
Sales Rep for the most update technical information and layout advice.
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10. PACKAGING
9
10.1.
20
28-LEAD 300-MIL PLASTIC SMALL OUTLINE INTEGRATED CIRCUIT (SOIC)
28 27 26 25 24 23 22 21 20 19 18 17 16 15
1
2 3 4 5
6 7 8 9 10 11 12 13 14
A
G
C
B
D
E
H
F
Plastic Small Outline Integrated Circuit (SOIC) Dimensions
INCHES
MILLIMETERS
Min
Nom
Max
Min
Nom
Max
A
0.701
0.706
0.711
17.81
17.93
18.06
B
0.097
0.101
0.104
2.46
2.56
2.64
C
0.292
0.296
0.299
7.42
7.52
7.59
D
0.005
0.009
0.0115
0.127
0.22
0.29
E
0.014
0.016
0.019
0.35
0.41
0.48
0.050
F
1.27
G
0.400
0.406
0.410
10.16
10.31
10.41
H
0.024
0.032
0.040
0.61
0.81
1.02
Note:
Lead coplanarity to be within 0.004 inches.
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11. ORDERING INFORMATION
10
Product Number Descriptor Key
I19 xxxxxxxx
Product Name:
Output Type:
I = ISD
Blank = PWM
01
Product Series:
19 = 1900
Blank = None
R
Duration:
16
: 10.6 – 32 secs
32
: 21.3 – 64 secs
64
: 42.6 – 128 secs
= AUX out
Tape & Reel:
= Tape & Reel
Temperature:
I
= Industrial (-40°C to +85°C)
Package Type:
S
=
Small Outline Integrated Circuit
(SOIC) Package
Lead-Free:
Y
= Lead-Free
When ordering ISD1900 devices, please refer to the above ordering scheme. Contact the local Nuvoton Sales
Representatives for any questions and the availability.
For the latest product information, please contact the Nuvoton Sales/Rep or access
Nuvoton’s worldwide web site at http://www.Nuvoton-usa.com
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12. VERSION HISTORY
11
VERSION
DATE
DESCRIPTION
0
Aug 11, 2007
Initial revision
0.1
Oct 10, 2007
Update block diagram
0.2
Oct 16, 2007
Update description
0.3
July 23, 2008
Generalize for different derivatives.
0.4
Aug 15, 2008
Update timing and application diagrams.
0.41
Aug 21, 2008
Add description of AGC.
0.51
Jan 5, 2009
Rename Norm/Mode
¯¯¯¯ to Addr/¯¯¯¯.
Drct
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Nuvoton products are not designed, intended, authorized or warranted for use as components in systems or equipment
intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation
instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or
sustain life. Furthermore, Nuvoton products are not intended for applications wherein failure of Nuvoton products could
result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur.
Nuvoton customers using or selling these products for use in such applications do so at their own risk and agree to fully
indemnify Nuvoton for any damages resulting from such improper use or sales.
The contents of this document are provided only as a guide for the applications of Nuvoton products. Nuvoton makes no
representation or warranties with respect to the accuracy or completeness of the contents of this publication and
reserves the right to discontinue or make changes to specifications and product descriptions at any time without notice.
No license, whether express or implied, to any intellectual property or other right of Nuvoton or others is granted by this
publication. Except as set forth in Nuvoton's Standard Terms and Conditions of Sale, Nuvoton assumes no liability
whatsoever and disclaims any express or implied warranty of merchantability, fitness for a particular purpose or
infringement of any Intellectual property.
The contents of this document are provided “AS IS”, and Nuvoton assumes no liability whatsoever and disclaims any
express or implied warranty of merchantability, fitness for a particular purpose or infringement of any Intellectual
property. In no event, shall Nuvoton be liable for any damages whatsoever (including, without limitation, damages for
loss of profits, business interruption, loss of information) arising out of the use of or inability to use the contents of this
documents, even if Nuvoton has been advised of the possibility of such damages.
Application examples and alternative uses of any integrated circuit contained in this publication are for illustration only
and Nuvoton makes no representation or warranty that such applications shall be suitable for the use specified.
The 100-year retention and 100K record cycle projections are based upon accelerated reliability tests, as published in
the Nuvoton Reliability Report, and are neither warranted nor guaranteed by Nuvoton. This product incorporates
SuperFlash®.
Information contained in this ISD® ChipCorder® datasheet supersedes all data for the ISD ChipCorder products
published by ISD® prior to August, 1998.
This datasheet and any future addendum to this datasheet is(are) the complete and controlling ISD® ChipCorder®
product specifications. In the event any inconsistencies exist between the information in this and other product
documentation, or in the event that other product documentation contains information in addition to the information in
this, the information contained herein supersedes and governs such other information in its entirety. This datasheet is
subject to change without notice.
Copyright© 2005, Nuvoton Electronics Corporation. All rights reserved. ChipCorder® and ISD® are trademarks of
Nuvoton Electronics Corporation. SuperFlash® is the trademark of Silicon Storage Technology, Inc. All other trademarks
are properties of their respective owners.
Please note that all data and specifications are subject to change without notice.
All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.
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