Mitsubishi MF601G2-02BJXX 2.5 flash drive Datasheet

MITSUBISHI STORAGE CARD
Preliminary
FLASH DRIVES
MF6128M-02BJxx
MF6256M-02BJxx
MF6512M-02BJxx
MF6640M-02BJxx
MF601G2-02BJxx
2.5" Flash Drive
Connector Type
IDE ATA 44-pin
DESCRIPTION
FEATURES
• 2.5”, IDE ATA 44-pin
• Single 5V Supply
• Up to 1.2GB maximum
• Nonvolatile, No Batteries Required
• High reliability based on internal ECC function
• Fast read/write performance
Mitsubishi’s Flash Drives provide large memory
capacities on a device approximately the size of a 2.5”
IDE Type Hard Disk (101.85mm(L) × 69.85mm (W) ×
8.47mm (T)).
Available in 128MB, 256MB, 512MB, 640MB and 1.2GB
capacities.
Read:
5MB/s(max.)
Write: 128MB card = 2.0MB/s(max.)
The others = 3.0MB/s(max.)
• Multiword DMA commands supported.
• 100,000 program/erase cycles
APPLICATIONS
• Computers
• Data Communication
• Office Automation
• Industrial
• Consumer
PRODUCT LIST
Memory capacity
(Bytes)
MF6128M-02AJxx
MF6256M-02AJxx
MF6512M-02AJxx
MF6640M-02AJxx
128,057,344
257,163,264
515,579,904
640,475,136
MF601G2-02AJxx
1,219,534,848
Data Bus
width(bits)
8/16
Memory
Cylinder
Head
Sector
Out line
256Mbit Flash x 4
256Mbit Flash x 8
256Mbit Flash x 16
256Mbit Flash x 20
977
981
999
1241
8
16
16
16
32
32
63
63
2.5"
IDE
256Mbit Flash x 40
2363
16
63
Oct.2000.Rev.0.3
MITSUBISHI
ELECTRIC
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MITSUBISHI STORAGE CARD
Preliminary
MF6XXXX-02BJXX series
FLASH DRIVES
PIN ASSIGNMENT
Pin
Signal
I/O
Pin
Signal
I/O
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
RESET#
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
GND
DMARQ
DIOW#
RIOR#
IORDY
DMACK#
INTRQ
DA1
DA0
CS0#
DASP#
VDD
GND
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
O
I
O
I
I
I
I/O
-
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
GND
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
(keypin)
GND
GND
GND
CSEL
GND
IOCS16#
PDIAG#
DA2
CS1#
GND
VDD
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
O
I/O
I
I
-
Oct.2000. Rev. 0.3
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ELECTRIC
2/18
MITSUBISHI STORAGE CARD
Preliminary
MF6XXXX-02BJXX series
FLASH DRIVES
Master/Slave/Cable Select Configuration
(1) Master(or single) [Default]
If all of pins A, B, C, D are Open, the drive is a Master.
43
1
C A
• • • • • • • • • • • • • • • • • • • • • •
• • • • • • • • • • • •
• • • • • • • • •
• •
• •
44
D B
20
2
(2) Slave
If pins C, D are open and jumper position A-B is used, the drive is a Slave.
43
1
C A
• • • • • • • • • • • • • • • • • • • • • •
• • • • • • • • • • • •
• • • • • • • • •
• •
• •
44
D B
20
2
(3) Cable Select [Default]
If jumper position D-B is used and pins C, A is open, Master/Slave setting is determined by the condition
of CSEL signal from the host.
43
1
C A
• • • • • • • • • • • • • • • • • • • • • •
• • • • • • • • • • • •
• • • • • • • • •
• •
• •
44
D B
20
2
Oct.2000. Rev. 0.3
MITSUBISHI
ELECTRIC
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MITSUBISHI STORAGE CARD
Preliminary
MF6XXXX-02BJXX series
FLASH DRIVES
Signal Description
Signal Name
Address bus[DA2-DA0]
Data bus[D15-D0]
I/O
I
I/O
Pin No.
36, 33, 35
Chip select[CS0#, CS1#]
I
18, 16, 14, 12,
10, 8, 6, 4, 3, 5,
7, 9, 11, 13, 15,
17
37, 38
Drive I/O read[DIOR#]
Drive I/O write[DIOW#]
DMA acknowledge[DMACK#]
I
I
I
25
23
29
DMA request[DMARQ]
O
21
Drive interrupt[INTRQ]
Drive 16-bit I/O[IOCS16#]
O
O
31
32
Drive active/drive1 present[DASP#]
I/O
39
Drive reset[RESET#]
I
1
I/O channel ready[IORDY]
O
27
Passed diagnostics[PDIAG#]
I/O
34
Cable select[CSEL]
I
28
VDD
GND
-
41, 42
2, 19, 22, 24,
26, 30, 40, 43,
44
Description
Signals DA2-DA0 are address bus. DA2 is the MSB
and DA0 is the LSB.
Signals DD15-DD0 are data bus.
CS0# is used to select the Command Block
Registers. CS1# is used to select the Control Block
Registers.
DIOR# is used to read data from the Drive’s I/O space.
DIOW# is used to write data to the Drive’s I/O space.
This signal shall be used by the host in response to
DMARQ to either acknowledge that data has been
accepted, or that data is available.
This signal, used for DMA data transfer between host
and drive, shall be asserted by the drive when it is
ready to transfer data to or from the host.
This signal is active high interrupt request to the host.
This output signal is asserted when the I/O port
address is capable of 16-bit access.
This signal is the DISK Active/Slave Present signal in
the Master/Slave handshake protocol.
This input pin is the active low hardware reset from the
host.
This signal is asserted to delay completion of the
memory or I/O access cycle.
This signal is the Pass Diagnostic signal in the
Master/Slave handshake protocol.
This signal is used to configure this Drive as a Master
or a Slave. When this signal is grounded, this Drive is
configured as a Master. When this signal is Open, this
Drive is configure as a Slave.
5V power.
Ground.
Oct.2000. Rev. 0.3
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4/18
MITSUBISHI STORAGE CARD
Preliminary
MF6XXXX-02BJXX series
FLASH DRIVES
BLOCK DIAGRAM
VDD
GND
Internal VDD
Controller
DA2-DA0
CS0#
CS1#
DIOR#
DIOW#
DMACK#
DMARQ
RESET#
DD15-DD0
INTRQ
IOCS16#
PDIAG#
DASP#
IORDY
CSEL
RESET Circuit
POR#
RES#
64Mbit
AND
256Mbit
AND
Flash
Memory
Flash Memory
(x14)
(x40)
CE#
OE#
WE#
CDE#
SC
I/O7-I/O0
R/B#
XIN
XOUT
Resonator
Oct.2000. Rev. 0.3
MITSUBISHI
ELECTRIC
5/18
MITSUBISHI STORAGE CARD
Preliminary
MF6XXXX-02BJXX series
FLASH DRIVES
IDE ATA Interface
CS1#
1
1
1
1
1
1
1
1
0
0
CS0#
0
0
0
0
0
0
0
0
1
1
DA2-DA0
0h
1h
2h
3h
4h
5h
6h
7h
6h
7h
Register
DIOR#=”L”
Data Register(DD15-DD0)
Error Register(DD7-DD0)
Sector Count Register(DD7-DD0)
Sector Number Register(DD7-DD0)
Cylinder Low Register(DD7-DD0)
Cylinder High Register(DD7-DD0)
Drive Head Register(DD7-DD0)
Status Register(DD7-DD0)
Alt. Status Register(DD7-DD0)
Drive Address Register(DD7-DD0)
DIOW#=“L”
Data Register(DD15-DD0)
Feature Register(DD7-DD0)
Sector Count Register(DD7-DD0)
Sector Number Register(DD7-DD0)
Cylinder Low Register(DD7-DD0)
Cylinder High Register(DD7-DD0)
Drive Head Register(DD7-DD0)
Command Register(DD7-DD0)
Device Control Register(DD7-DD0)
invalid
Oct.2000. Rev. 0.3
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MITSUBISHI STORAGE CARD
Preliminary
MF6XXXX-02BJXX series
FLASH DRIVES
Sector Number Register
ATA Register Specifications
This register is written by the host with the starting sector
number to be used in the subsequent Cylinder-Head-Sector
command. After the command is complete, the host may
read the final sector number from this register. When logical
block addressing is used, this register is written by the host
with bit7 to 0 of the starting logical block number and
contains bit7 to 0 of the final logical block number after the
command is complete.
Data Register
This register is a 16 bit register which is used to transfer data
blocks between the card data buffer and the host. Data may
be transferred by either a series of word accesses to the Data
register or a series of byte accesses to the Data register.
DD15
DD1
4
DD1
3
DD1
2
DD1
1
DD1
0
DD9
DD8
Data Word
Odd Data Byte
DD7
DD6
DD5
DD4
DD3
DD7
DD2
DD1
Field
BBK
UNC
IDNF
ABRT
AMNF
DD4
IDNF
DD3
0
DD2
ABRT
DD1
0
DD0
AMNF
DD7
function
This bit is set when a Bad Block is detected in requested ID
field. Host can not read/write on data area that is marked as
a Bad Block.
This bit is set when Uncorrectable error is occurred at
reading the card.
The requested sector ID is in error or cannot be found.
This bit is set if the command has been aborted because of
the card status condition. (Not ready, Write fault, etc.) or
when an invalid command has been issued.
This bit is set in case of a general error.
DD5
DD4
DD3
DD2
DD1
DD5
DD4
DD3
DD2
DD1
Cylinder Low Byte
Logical Block Number bits A15-A08(LBA Addressing)
DD0
This register is written by the host with the high-order byte
of the starting cylinder address to be used in the subsequent
Cylinder-Head-Sector command. After the command is
complete, the host may read the high-order byte of the final
cylinder number from this register. When logical block
addressing is used, this register is written by the host with
bits 23 to 16 of the starting logical block number and
contains bits23 to 16 of the final logical block number after
the command is complete.
This register is written by the host to provide command
specific information to the drive regarding features of the
drive which the host wish to utilize. The Feature register is a
write only register.
DD6
DD6
Cylinder High Register
Feature Register
DD7
DD0
This register is written by the host with the low-order byte of
the starting cylinder address to be used in the subsequent
Cylinder-Head-Sector command. After the command is
complete, the host may read the low-order byte of the final
cylinder number from this register. When logical block
addressing is used, this register is written by the host with
bits15 to 8 of the starting logical block number and contains
bits15 to 8 of the final logical block number after the
command complete.
This register contains additional information about the
source of an error which has occurred in processing of the
preceding command. This register should be checked by the
host when ERR bit in the Status register is set. The Error
register is a read only register.
DD5
0
DD4
DD3
DD2
DD1
Sector Number
Logical Block Number bits A07-A00(LBA Addressing)
Cylinder Low Register
Error Register
DD6
UNC
DD5
DD0
Data Word
Data Byte
DD7
BBK
DD6
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
Cylinder High Byte
Logical Block Number bits A23-A16(LBA Addressing)
DD0
Feature byte
Sector Count Register
This register is written by the host with the number of
sectors or blocks to be processed in the subsequent
command. After the command is complete, the host may
read this register to obtain the count of sectors left
unprocessed by the command.
DD7
DD6
DD5
DD4
DD3
Sector Count
DD2
DD1
DD0
Oct.2000. Rev. 0.3
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MITSUBISHI STORAGE CARD
Preliminary
MF6XXXX-02BJXX series
FLASH DRIVES
Drive/Head Register
Device Control Register
The Drive/Head register is used to specify the selected drive
of a pair of drives sharing a set of registers.
This register is used to control the card interrupt request and
to issue a soft reset to the card. The Device Control register
is a write only register.
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
X
LBA
X
DRV
HS3
LBA27
HS2
LBA26
HS1
LBA25
HS0
LBA2
4
Field
function
X
LBA
Undefined . “0” or “1”.
This bit is “0” for CHS addressing and “1” for Logical
Block addressing.
This bit is number of the drive which the host has
selected. When DRV is cleared, Drive0 is selected. When
DRV is set, Drive1 is selected. The card is selected to be
Drive0 or to be Drive1 using the “Copy” field of the PC
Card Socket Copy Register.
HS3-0 of the head number in CHS addressing or
LBA27-24 of the Logical Block Number in LBA
addressing.
DRV
HS3-0
LBA27-24
DD6
DD5
DD4
DD3
DD2
DD1
DD0
BSY
DRDY
DWF
DSC
DRQ
CORR
IDX
ERR
CORR
IDX
ERR
DD4
DD3
DD2
DD1
DD0
X
X
1
SRST
nIEN
0
0
function
don’t care.
This bit is set to “1”.
This bit is set to “1” in order to force the card to perform a
Command Block Reset operation. This does not change the
Card Configuration registers as a Hardware Reset does.
The card remains in Reset until this bit is reset to “0”.
This bit is used for enabling IREQ#. When this bit is set to
“0”, IREQ# is enabled. When this bit is set to “1”, IREQ# is
disabled.
This bit is set to “0”.
Drive Address Register
DD7
DWF
DSC
DRQ
DD5
X
nIEN
This register is provided for compatibility with the AT disk
drive interface.
The Status register and the Alternate Status register return
the card status when read by the host. Reading the Status
register clears a pending interrupt request while reading the
Alternate Status register does not. The Status register and the
Alternate Status register are read only registers.
DRDY
DD6
X
Field
X
1
SRST
Status and Alternate Status Registers
Field
BSY
DD7
DD7
DD6
X
nWTG
Field
X
nWTG
nHS3-0
function
This bit is set when the card internal operation is
executing. When this bit is set to “1”, other bits in this
register are invalid.
DRDY indicates whether the card is capable of
performing card operations.
This bit, if set, indicates a write fault has occurred.
This bit is set when the drive seek complete.
This bit is set when the information can be transferred
between the host and Data register.
This bit is set when a correctable data error has been
occurred and the data has been corrected.
This bit is always set to “0”.
This bit is set when the previous command has ended in
some type of error. The error information is set in the
other Status register bits or Error register. This bit is
cleared by the next command.
nDS1
nDS0
DD5
DD4
DD3
nHS3-0
DD2
DD1
DD0
nDS1
nDS0
function
This bit is unknown.
This bit is set to “0” when a Flash write operation is in
progress, otherwise it is set to “1”.
These bits is the negative value of Head Select bits in
Drive/Head register.
This bit is set to “0” when Slave drive is active and selected.
This bit is set to “0” when Master drive is active and selected.
Command Register
The Command register contains the command code being
sent to the device. Command execution begins immediately
after this register is written. The Command register is a write
only register.
DD7
DD6
DD5
DD4
DD3
Command
DD2
DD1
DD0
Oct.2000. Rev. 0.3
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8/18
MITSUBISHI STORAGE CARD
Preliminary
MF6XXXX-02BJXX series
FLASH DRIVES
ATA Command Specifications
This table summarizes the ATA command set with the paragraphs. Following shows the support commands and command codes
which are written in command registers.
Command
Check Power Mode
Execute Drive Diagnostic
Erase Sector(s)
Format Track
Identify Drive
Idle
Idle Immediate
Initialize Drive Parameters
Read Buffer
Read DMA
Read Long Sector
Read Multiple
Read Sector(s)
Read Verify Sector(s)
Recalibrate
Request Sense
Seek
Set Features
Set Multiple mode
Set Sleep Mode
Standby
Standby Immediate
Translate Sector
Wear Level
Write Buffer
Write DMA
Write Long Sector
Write Multiple
Write Multiple without Erase
Write Sector(s)
Write Sector without Erase
Write Verify
FR : Feature Register,
SN : Sector Number Register,
DR Drive bit of Drive/Head Register,
Code
98h, E5h
90h
C0h
50h
ECh
97h, E3h
95h, E1h
91h
E4h
C8h,C9h
22h, 23h
C4h
20h, 21h
40h, 41h
1xh
03h
7xh
EFh
C6h
99h, E6h
96h, E2h
94h, E0h
87h
F5h
E8h
CAh,CBh
32h, 33h
C5h
CDh
30h, 31h
38h
3Ch
FR
SC
SN
CY
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
DR
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
SC : Sector Count Register,
CY : Cylinder Low/High Register,
HD : Head No. of Drive/Head Register,
HD
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
Oct.2000. Rev. 0.3
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9/18
MITSUBISHI STORAGE CARD
Preliminary
MF6XXXX-02BJXX series
FLASH DRIVES
Check Power Mode(98h, E5h)
Read Multiple(C4h)
This command checks the power mode.
This command performs similarly to the Read Sector(s)
command. Interrupt are not generated on each sector, but on
the transfer of a block which contains the number of sectors
defined by a Set Multiple command.
Execute Drive Diagnostic(90h)
This command performs the internal diagnostic tests
implemented by the card.
Read Sector(s)(20h, 21h)
This command transfers data from the card to the host. Data
transfer starts at the sector specified by the Cylinder, Head,
and Sector Number registers, and proceeds for the number
of sectors specified in the Sector Count register.
Erase Sector(s)(C0h)
This command is used to pre-erase and condition data
sectors in advance of a Write without Erase or Write
Multiple without Erase command.
Read Verify Sector(s)(40h, 41h)
This command writes the desired head and cylinder of the
selected drive with a FFh pattern.
This command is identical to the Read Sector(s) command,
except that DRQ is not asserted, and no data is transferred to
the host.
Format Track(50h)
Identify Drive(ECh)
Recalibrate(1xh)
This command enables the host to receive parameter
information from the card. (Refer to the Identify Drive
Information table.)
Although this command is supported for backward
compatibility, it has no actual function. The card will always
return good status at the completion of this command.
Idle(97h, E3h)
Request Sense(03h)
This command causes the card to set BSY, enter the Idle
mode, clear BSY and generate an interrupt. If the sector
count is non-zero, the automatic power down mode is
enabled. If the sector count is zero, the automatic power
down mode is disabled.
This command requests extended error information for the
previous command.
Seek(7xh)
This command is supported for backward compatibility.
Although this command has no actual function, it does
perform a range check of valid track, and posts an IDNF
error if the Head or Cylinder specified are out of bounds.
Idle Immediate(95h, E1h)
This command causes the card to set BSY, enter the idle
mode, clear BSY and generate an interrupt.
Set Features(EFh)
This command is used by the host to establish or select
certain features.
Initialize Drive Parameters(91h)
This command allows the host to alter the number of sectors
per track and the number of heads per cylinder.
Set Multiple Mode(C6h)
This command enables the card to perform Read and Write
Multiple operations and establishes the block count for these
commands. This card supports 1 sector block size.
Read Buffer(E4h)
This command enables the host to read the current contents
of the card’s sector buffer.
Read DMA(C8h,C9h)
Set Sleep Mode(99h, E6h)
This command enables the host to read the sector data by
the Multiword DMA protocol.
This command causes the card to set BSY, enter the Sleep
mode, clear BSY and generate an interrupt.
Read Long Sector(22h, 23h)
This command is similar to the Read Sector(s) command
except the contents of the Sector Count register are ignored
and only one sector is read. The 512 data bytes and 4 ECC
bytes are read into the buffer(with no ECC correction) and
then transferred to the host.
Oct.2000. Rev. 0.3
MITSUBISHI
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10/18
MITSUBISHI STORAGE CARD
Preliminary
MF6XXXX-02BJXX series
FLASH DRIVES
Standby(96h, E2h)
Write Sector(s)(30h, 31h)
This command causes the card to set BSY, enter the
Standby mode, clear BSY and generate an interrupt.
This command transfers data from the host to the card. Data
transfer starts at the sector specified by the Cylinder, Head,
and Sector Number registers, and proceeds for the number
of sectors specified in the Sector Count register.
Standby Immediate(94h, E0h)
This command causes the card to set BSY, enter the
Standby mode, clear BSY and generate an interrupt.
Write Sector without Erase(CDh)
This command is similar to the Write Sector(s) command.
The sectors should be pre-erased with the Erase Sector
command before this command is issued. If the sector is not
pre-erased, Write Sector command operation will occur.
Translate Sector(87h)
This command allows the host to know the number of
times an user sector has been erased and programmed.
This card doesn't support the Hot Count value.
Write Verify(3Ch)
This command is similar to the Write Sector(s) command,
except each sector is verified immediately after being
written.
Wear Leveling(F5h)
Although this command is supported for backward
compatibility, it has no actual function. The card will always
return good status at the completion of this command.
Write Buffer(E8h)
This command enables the host to overwrite contents of the
card’s sector buffer with any data pattern desired. This
command has the same protocol as the Write Sector(s)
command and transfers 512 bytes.
Write DMA(CAh, CBh)
This command enables the host to write sector data by the
Multiword DMA protocol.
Write Long Sector(32h, 33h)
This command is similar to the Write Sector(s) except the
contents of the Sector Count register are ignored and only
one sector is written. The 512 data bytes and 4 ECC bytes
are transferred from the host and then written from the
buffer to the flash.
Write Multiple(C5h)
This command is similar to the Write Sector(s) command.
Interrupts are not presented on each sector, but on the
transfer of a block which contains the number of sectors
defined by Set Multiple command.
Write Multiple without Erase(CDh)
This command is similar to the Write Multiple command.
The sectors should be pre-erased with the Erase Sector
command before this command is issued. If the sector is not
pre-erased, Write Multiple command operation will occur.
Oct.2000. Rev. 0.3
MITSUBISHI
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11/18
MITSUBISHI STORAGE CARD
Preliminary
MF6XXXX-02BJXX series
FLASH DRIVES
Identify Drive Information
Word Address
Data
0
848Ah
1
2
3
4
5
6
7-8
9
10-19
20
21
22
23-26
27-46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69-255
xxxxh
0000h
000xh
0000h
0200h
0020h
xxxxh, xxxxh
0000h
2020h
0001h
0001h
0004h
xxxxh
xxxxh
0001h
0000h
0300h
0000h
0200h
0000h
0003h
xxxxh
xxxxh
xxxxh
xxxxh
xxxxh
010xh
xxxxh
xxxxh
0000h
0007h
0003h
0078h
0078h
00F0h
0078h
0000h
Description
General configuration bit-significant information
15
1
Non-rotating disk drive
14
0
Format speed tolerance gap not required
13
0
Track offset option not available
12
0
Data strobe offset option not available
11
0
Rotational speed tolerance is < 0.5%
10
1
Disk transfer rate > 10Mbs
9
0
10Mbs <= Disk transfer rate > 5Mbs
8
0
Disk transfer rate <= 5Mbs
7
1
Removable cartridge drive
6
0
Not a fixed drive
5
0
Spindle motor control option not implemented
4
0
Head switch time > 15us
3
1
Not MFM encoded
2
0
Not soft sectored
1
1
Hard sectored
0
0
Reserved
Number of Cylinders
Reserved
Number of Heads
Number of unformatted bytes per track
Number of unformatted bytes per sector
Number of sectors per track
Number of sectors per card (word 7 = MSW, word 8 = LSW)
Reserved
Reserved
Buffer type: Single ported, single-sector, w/o read cache
Buffer size, in 512 byte increments
ECC length used on Read and Write Long command
Firmware revision, 8 ASCII characters
Model number, 40 ASCII characters.
Maximum Block Count=1 for Read/write Multiple commands
Cannot perform doubleword I/O
Capabilities
Reserved
PIO timing cycle timing mode 2
Reserved
Words 54-58 are valid(bit0), words 64-70 are valid(bit1).
Number of Current Cylinders
Number of Current Heads
Number of Current Sectors per Track
LSW of the Current Capacity in Sectors
MSW of the Current Capacity in Sectors
Current Setting for Block Count for R/W Multiple commands
LSW of the total number of user addressable LBA mode
MSW of the total number of user addressable LBA mode
Reserved
Multiword DMA mode2 supported
Advanced PIO modes supported
Minimum Multiword DMA transfer cycle time (120ns)
Manufacturer’s recommended Multiword DMA transfer cycle (120ns)
Minimum PIO transfer cycle time with out flow control (240ns)
Minimum PIO transfer cycle time with IORDY (120ns)
Reserved
Oct.2000. Rev. 0.3
MITSUBISHI
ELECTRIC
12/18
MITSUBISHI STORAGE CARD
Preliminary
MF6XXXX-02BJXX series
FLASH DRIVES
ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
Vi
Vo
Pd
T opr
T stg
Parameter
Conditions
Supply voltage
Input voltage
Output voltage
Power dissipation
Operating temperature
Storage temperature
With respect to GND
T a = 25 °C
Ratings
Unit
-0.3~6.2
-0.3~VDD+0.3
-0.3~VDD+0.3
1.2
0~60
-10~80
V
V
V
W
°C
°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VDD(5V)
GND
VIH
VIL
Parameter
Min.
4.5
VDD Supply voltage
System ground
High input voltage
Low input voltage
Limits
Typ.
5.0
0
0.7VDD
0
Max.
5.5
VDD
0.8
Unit
V
V
V
V
DC ELECTRICAL CHARACTERISTICS (Ta=0~60°C, VDD=5V±10%, unless otherwise noted)
Symbol
VOH
Parameter
High output voltage
Test Condition
IOH=4mA(4.5V)
INTRQ,
INPACK#,
DASP#,
PDIAG#
the other
outputs
INTRQ,
INPACK#,
DASP#,
PDIAG#
the other
outputs
IOH=8mA(4.5V)
VOL
Low output voltage
IOL=-4mA(4.5V)
IOL=-8mA(4.5V)
IOZ
ICCR
ICCW
ICCS
ICCD
Output current in off
state
Active supply current
(Read)
Active supply current
(Write)
Standby current
(Auto power down)
Sleep current
(Sleep command)
CS0# = CS1# = VIH
DD15-DD0
Output open
CS0# = CS1# = VDD
DD15-DD0 = GND
Other inputs = VDD or GND
CS0# = CS1# = VDD
DD15-DD0 = GND
Other inputs = VDD or GND
Min.
4.5V
Limits
Typ.
Max.
5.5V
Unit
0.8VDD
-
V
-
0.4
V
-
±10
µA
70
110
mA
100
140
mA
2.0
4.0
mA
500
800
µA
Oct.2000. Rev. 0.3
MITSUBISHI
ELECTRIC
13/18
MITSUBISHI STORAGE CARD
Preliminary
MF6XXXX-02BJXX series
FLASH DRIVES
DC ELECTRICAL CHARACTERISTICS(Continued)
Symbol
IIH
IIL
Parameter
High input current
Low input current
Test Condition
VIN=VDD
VIN=GND
CS0#, CS1#,
DIOR#, DIOW#,
DA2-DA0,
DD15-DD0
RESET#,
DASP#, PDIAG#
CSEL
Min.
4.5V
Limits
Typ.
Max.
5.5V
Unit
-10
+10
µA
-10
+10
-30
-100
-10
-50
µA
CAPACITANCE
Symbol
Parameter
Test Condition
CI
Input capacitance
VI=GND, Vi=25mVrms, f=1 MHZ, Ta=25°C
CO
Output capacitance
VO=GND, Vo=25mVrms, f=1 MHZ, Ta=25°C
Note : These parameters are not 100% tested.
Min.
Limits
Typ.
Max.
45
45
Unit
pF
Oct.2000. Rev. 0.3
MITSUBISHI
ELECTRIC
14/18
MITSUBISHI STORAGE CARD
Preliminary
MF6XXXX-02BJXX series
FLASH DRIVES
AC ELECTRICAL CHARACTERISTICS
PIO READ /WRITE TIMING
Limit
Symbol
Parameter
Min
tsuA(DIOR / DIOW)
thA(DIOR / DIOW)
Address Setup before DIOR# / DIOW# *
Address Hold following DIOR# / DIOW# *
25
10
tw(DIOR / DIOW)
td(DIOR)
DIOR# / DIOW# Width Time
Data Delay after DIOR#
70
Max
Unit
ns
ns
50
ns
ns
th(DIOR)
Data Hold following DIOR#
5
ns
tsu(DIOW)
th(DIOW)
Data Setup before DIOW#
Data Hold after DIOW#
20
10
ns
ns
tdfIOCS16(A)
tdrIOCS16(A)
IOCS16# Delay Falling from Address *
IOCS16# Delay Rising from Address *
35
35
ns
ns
The maximum load on IOCS16# are 1 LSTTL with 50 pF total load.
* “Address” includes DA2-DA0 and CS0#, CS1#.
I/O READ / WRITE TIMING DIAGRAM
DA[2:0]
thA(DIOR/DIOW)
tsuA(DIOR/DIOW)
CS0# / CS1#
tw(DIOR/DIOW)
DIOR# / DIOW#
tdr IOCS16(A)
IOCS16#
READ
D[15:0]
tdf IOCS16(A)
td (DIOR)
th (DIOR)
VALID
tsu(DIOW)
th(DIOW)
WRITE
D[15:0]
Oct.2000. Rev. 0.3
MITSUBISHI
ELECTRIC
15/18
MITSUBISHI STORAGE CARD
Preliminary
MF6XXXX-02BJXX series
FLASH DRIVES
Multiword DMA TIMING
Limit
Symbol
Parameter
Min
Max
Unit
tsuCS(DIOR / DIOW)
thCS(DIOR / DIOW)
CS0#, CS1# Setup before DIOR# / DIOW#
CS0#, CS1# Hold following DIOR# / DIOW#
25
10
ns
ns
tw(DIOR / DIOW)
tnw(DIOR / DIOW)
DIOR# / DIOW# Width Time
DIOR# / DIOW# negate pulse Width Time
70
35
ns
ns
tcycle(DIOR / DIOW)
DIOR# / DIOW# Cycle Time
120
td(DIOR)
th(DIOR)
Data Delay after DIOR#
Data Hold following DIOR#
5
ns
ns
tsu(DIOW)
th(DIOW)
Data Setup before DIOW#
Data Hold after DIOW#
20
10
ns
ns
tsuDMACK(DIOR / DIOW)
DMACK# Setup Time before DIOR# / DIOW#
0
ns
thDMACK(DIOR / DIOW)
tdDMARQ(DIOR / DIOW)
DMACK# Hold Time following DIOR# / DIOW#
DMARQ negate delay time from DIOR# / DIOW#
5
ns
50
35
ns
ns
Multiword DMA TIMING DIAGRAM
tsuCS(DIOR/DIOW)
thCS(DIOR/DIOW)
CS0# / CS1#
tcycle(DIOR/DIOW)
DMARQ
tdDMARQ(DIOR/DIOW)
DMACK#
tsuDMACK(DIOR/DIOW)
tw(DIOR/DIOW)
tnw(DIOR/DIOW)
thDMACK(DIOR/DIOW)
DIOR# / DIOW#
td (DIOR)
READ
D[15:0]
th (DIOR)
VALID
th (DIOW)
WRITE
D[15:0]
tsu(DIOW)
Oct.2000. Rev. 0.3
MITSUBISHI
ELECTRIC
16/18
MITSUBISHI STORAGE CARD
Preliminary
MF6XXXX-02BJXX series
FLASH DRIVES
RECOMMENDED POWER UP/DOWN CONDITIONS (Ta=0~60°C, unless otherwise noted)
Symbol
Parameter
Conditions
Vi(CS)
CS input voltage
tsu(VDD)
tsu(RESET#)
trec(VDD)
tpr
tpf
tw(RESET#)
th(Hi-zRESET#)
ts(Hi-zRESET#)
CS setup time
RESET# setup time
CS recover time
VDD rising time
VDD falling time
RESET# width
Min.
0V≤ VDD <2V
2V≤ VDD <VIH
VIH ≤ VDD
0
VDD-0.1
VIH
20
20
1
0.1
3
10
1
0
10%à90% of VDD
90% of VDDà10%
Limits
Typ.
VDD
Max.
Unit
VDD
VDD+0.1
VDD+0.1
V
V
V
ms
ms
µs
ms
ms
µs
ms
ms
100
300
POWER UP/DOWN TIMING DIAGRAM
tsu(VDD)
tpr
VDD
tsu(RESET#)
VDD @ 90%
tsu (RESET#)
VIH
VDD @ 10%
2V
CS0#, CS1#
th(Hi-z RESET#)
tw(RESET#)
RESET#
Hi-z
tw(RESET#)
VDD
tpf
VDD @ 90%
trec(VDD)
VIH
2V
VDD @ 10%
CS0#, CS1#
ts(Hi-z RESET#)
Hi-z
RESET#
Oct.2000. Rev. 0.3
MITSUBISHI
ELECTRIC
17/18
MITSUBISHI STORAGE CARD
Preliminary
MF6XXXX-02BJXX series
FLASH DRIVES
Keep safty first in your circuit designs!
• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the
possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give
due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use
of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
•These materials are
intended
as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the
circuit
designs!
customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric
Corporation or a third party.
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product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
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other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility
for any damage, liability, or other loss rising from these inaccuracies or errors.
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Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.
•Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in
which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor
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Oct.2000. Rev. 0.3
MITSUBISHI
ELECTRIC
18/18