ICST ICS844003AGILF Femtoclocksâ ¢ crystal-to-lvds frequency synthesizer Datasheet

PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844003I
FEMTOCLOCKS™CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS844003I is a 3 differential output LVDS
Synthesizer designed to generate Ethernet referHiPerClockS™ ence clock frequencies and is a member of the
HiPerClocks™ family of high performance clock
solutions from ICS. Using a 31.25MHz or
26.041666MHz, 18pF parallel resonant crystal, the following
frequencies can be generated based on the settings of 4 frequency select pins (DIV_SEL[A1:A0], DIV_SEL[B1:B0]):
625MHz, 312.5MHz, 156.25MHz, and 125MHz. The 844003I
has 2 output banks, Bank A with 1 differential LVDS output
pair and Bank B with 2 differential LVDS output pairs.
• Three LVDS outputs on two banks, A Bank with one LVDS
pair and B Bank with 2 LVDS output pairs
The two banks have their own dedicated frequency select pins and can be independently set for the frequencies mentioned above. The ICS844003I uses ICS’ 3rd generation low phase noise VCO technology and can achieve
1ps or lower typical rms phase jitter, easily meeting
Ethernet jitter requirements. The ICS844003I is packaged
in a small 24-pin TSSOP package.
• 3.3V output supply mode
ICS
• Using a 31.25MHz or 26.041666MHz crystal, the two
output banks can be independently set for 625MHz,
312.5MHz, 156.25MHz or 125MHz
• Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended input
• VCO range: 560MHz to 700MHz
• RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz):
0.63ps (typical)
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
PIN ASSIGNMENT
DIV_SELB0
VCO_SEL
MR
VDDO_A
QA0
nQA0
CLK_ENB
CLK_ENA
FB_DIV
VDDA
VDD
DIV_SELA0
BLOCK DIAGRAM
24
23
22
21
20
19
18
17
16
15
14
13
DIV_SELB1
VDDO_B
QB0
nQB0
QB1
nQB1
XTAL_SEL
TEST_CLK
XTAL_IN
XTAL_OUT
GND
DIV_SELA1
ICS844003I
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
CLK_ENA Pullup
DIV_SELA[1:0]
VCO_SEL
1
2
3
4
5
6
7
8
9
10
11
12
Pullup
QA0
00
TEST_CLK Pulldown
0
XTAL_IN
OSC
1
0
Phase
Detector
VCO
÷1
01
÷2 (default)
10
11
÷4
÷5
00
01
÷1
÷2
10
÷4 (default)
11
÷5
nQA0
1
560-700MHz
XTAL_OUT
XTAL_SEL Pullup
QB0
FB_DIV
0 = ÷20 (default)
1 = ÷24
FB_DIV Pulldown
nQB0
QB1
nQB1
DIV_SELB[1:0]
MR
Pulldown
CLK_ENB Pullup
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
844003AGI
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REV. B AUGUST 25, 2005
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844003I
FEMTOCLOCKS™CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
1
24
Name
DIV_SELB0
DIV_SELB1
Type
2
VCO_SEL
Input
3
MR
Input
4
VDDO_A
Power
5, 6
QA0, nQA0
Ouput
7
CLK_ENB
Input
Pullup
8
CLK_ENA
Input
Pullup
9
FB_DIV
Input
Pulldown
10
VDDA
Power
11
12
13
14
VDD
DIV_SELA0
DIV_SELA1
GND
Power
15, 16
XTAL_OUT,
XTAL_IN
Input
17
TEST_CLK
Input
18
XTAL_SEL
Input
Input
Input
Power
19, 20
nQB1, QB1
Output
21, 22
nQB0, QB0
Output
Description
Division select pin for Bank B. Default = Low.
Pulldown
LVCMOS/LVTTL interface levels.
VCO select pin. When Low, the PLL is bypassed and the cr ystal reference
or TEST_CLK (depending on XTAL_SEL setting) are passed directly to the
Pullup
output dividers. Has an internal pullup resistor so the PLL is not bypassed
by default. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inver ted outputs nQx
Pulldown to go high. When logic LOW, the internal dividers and the outputs are
enabled. Has an internal pulldown resistor so the power-up default state of
outputs and dividers are enabled. LVCMOS/LVTTL interface levels.
Output supply pin for Bank A outputs.
Differential output pair. LVDS interface levels.
Output enable Bank B. Active High outputs are enable. When logic HIGH,
the output pairs on Bank B are enabled. When logic LOW, the output pairs
are in a high impedance state. Has an internal pullup resistor so the default
power-up state of outputs are enabled. LVCMOS/LVTTL interface levels.
Output enable Bank A. Active High output enable. When logic HIGH,
the output pair in Bank A is enabled. When logic LOW, the output pair is in
a high impedance state. Has an internal pullup resistor so the default
power-up state of output is enabled. LVCMOS/LVTTL interface levels.
Feedback divide select. When Low (default), the feedback divider is set
for ÷20. When HIGH, the feedback divider is set for ÷24.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Core supply pin.
Division select pin for Bank A. Default = HIGH.
Pullup
LVCMOS/LVTTL interface levels.
Power supply ground.
Parallel resonant cr ystal interface. XTAL_OUT is the output, XTAL_IN is the
input. XTAL_IN is also the overdrive pin if you want to overdrive the cr ystal
circuit with a single-ended reference clock.
Single-ended reference clock input. Has an internal pulldown resistor to
Pulldown pull to low state by default. Can leave floating if using the cr ystal interface.
LVCMOS/LVTTL interface levels.
Cr ystal select pin. Selects between the single-ended TEST_CLK or cr ystal
interface. Has an internal pullup resistor so the cr ystal interface is selected
Pullup
by default. LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Power
Output supply pin for Bank B outputs.
23
VDDO_B
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLDOWN
Input Pulldown Resistor
51
kΩ
RPULLUP
Input Pullup Resistor
51
kΩ
844003AGI
Test Conditions
Minimum
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2
Typical
Maximum
Units
REV. B AUGUST 25, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844003I
FEMTOCLOCKS™CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
TABLE 3A. BANK A FREQUENCY TABLE
Inputs
Bank A
Output Divider
M/N
Multiplication
Factor
QA0/nQA0
Output
Frequency
(MHz)
Crystal Frequency
(MHz)
DIV_SELA1
DIV_SELA0
FB_DIV
Feedback
Divider
31.25
0
0
0
20
1
20
625
31.25
0
1
0
20
2
10
312.5
31.25
1
0
0
20
4
5
156.25
31.25
1
1
0
20
5
4
125
26.041666
0
0
1
24
1
24
625
26.041666
0
1
1
24
2
12
312.5
26.041666
1
0
1
24
4
6
156.25
26.041666
1
1
1
24
5
64.8
125
FB_DIV
Feedback
Divider
Bank B
Output Divider
M/N
Multiplication
Factor
QB0/nQB0
Output
Frequency
(MHz)
TABLE 3B. BANK B FREQUENCY TABLE
Inputs
Crystal Frequency
(MHz)
DIV_SELB1
DIV_SELB0
31.25
0
0
0
20
1
20
625
31.25
0
1
0
20
2
10
312.5
31.25
1
0
0
20
4
5
156.25
31.25
1
1
0
20
5
4
125
26.041666
0
0
1
24
1
24
625
26.041666
0
1
1
24
2
12
312.5
26.041666
1
0
1
24
4
6
156.25
26.041666
1
1
1
24
5
4.8
125
844003AGI
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3
REV. B AUGUST 25, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844003I
FEMTOCLOCKS™CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
TABLE 3C. OUTPUT BANK CONFIGURATION SELECT FUNCTION TABLE
Inputs
Inputs
Outputs
Outputs
QA
DIV_SELB1
DIV_SELB0
0
÷1
0
0
÷1
1
÷2
0
1
÷2
1
0
÷4
1
0
÷4
1
1
÷5
1
1
÷5
DIV_SELA1
DIV_SELA0
0
0
QB
TABLE 3D. FEEDBACK DIVIDER CONFIGURATION SELECT FUNCTION TABLE
Inputs
FB_DIV
Feedback Divide
0
÷20
1
÷24
Enabled
Disabled
TEST_CLK
CLK_ENx
nQA0,
nQB0:nQB1
QA0,
QB0:QB1
FIGURE 1. CLK_EN TIMING DIAGRAM
TABLE 3E. CLK_ENA SELECT FUNCTION TABLE
Inputs
CLK_ENA
844003AGI
TABLE 3F. CLK_ENB SELECT FUNCTION TABLE
Outputs
QA0
Inputs
nQA0
CLK_ENB
Outputs
QB0:QB1
nQB0:nQB1
0
LOW
HIGH
0
LOW
HIGH
1
Active
Active
1
Active
Active
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4
REV. B AUGUST 25, 2005
PRELIMINARY
Integrated
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Systems, Inc.
ICS844003I
FEMTOCLOCKS™CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, θJA
70°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO_A = VDDO_B = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
3.135
3.3
3.465
V
VDDA
Analog Supply Voltage
3.135
3.3
3.465
V
VDDO_A, B
Output Supply Voltage
3.135
3.3
3.465
V
IDD
Power Supply Current
99
mA
IDDA
Analog Supply Current
10
mA
IDDO_A, B
Output Supply Current
52
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO_A = VDDO_B = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
IIL
844003AGI
Input
High Current
Input
Low Current
Test Conditions
Minimum
Typical
Maximum
Units
VDD = 3.3V
2
VDD + 0.3
V
VDD = 2.5V
1.7
VDD + 0.3
V
VDD = 3.3V
-0.3
0.8
V
VDD = 2.5V
VDD = VIN = 3.465V
or 2.625V
-0.3
0.7
V
150
µA
5
µA
TEST_CLK, MR, FB_DIV
DIV_SELA1, DIV_SELB0
DIV_SELB1, DIV_SELA0,
VCO_SEL, XTAL_SEL,
CLK_ENA, CLK_ENB
VDD = VIN = 3.465V
or 2.625V
TEST_CLK, MR, FB_DIV
DIV_SELA1, DIV_SELB0
VDD = 3.465V or 2.625V,
VIN = 0V
DIV_SELB1, DIV_SELA0,
VCO_SEL, XTAL_SEL,
CLK_ENA, CLK_ENB
VDD = 3.465V or 2.625V,
VIN = 0V
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5
-5
µA
-150
µA
REV. B AUGUST 25, 2005
PRELIMINARY
Integrated
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Systems, Inc.
ICS844003I
FEMTOCLOCKS™CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
TABLE 4C. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO_A = VDDO_B = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VOD
Differential Output Voltage
Δ VOD
VOD Magnitude Change
VOS
Offset Voltage
Δ VOS
VOS Magnitude Change
Test Conditions
Minimum
Typical
Maximum
Units
40
mV
50
mV
Maximum
Units
350
0
mV
1.4
0
V
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Frequency
Typical
Fundamental
FB_DIV = ÷20
28
35
MHz
FB_DIV = ÷24
23.33
29.16
MHz
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
Maximum
Units
NOTE: Characterized using an 18pF parallel resonant cr ystal.
TABLE 6. AC CHARACTERISTICS, VDD = VDDA = VDDO_A = VDDO_B = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
fOUT
Output Frequency Range
tsk(b)
Bank Skew, NOTE 1
tsk(o)
Output Skew; NOTE 2, 4
tjit(Ø)
t R / tF
RMS Phase Jitter (Random);
NOTE 3
Output Rise/Fall Time
Test Conditions
Minimum
Typical
Output Divider = ÷1
560
700
MHz
Output Divider = ÷2
28 0
35 0
MHz
Output Divider = ÷4
140
175
MHz
Output Divider = ÷5
112
14 0
MHz
3
ps
Outputs @ Same Frequency
15
ps
Outputs @ Different Frequencies
30
ps
625MHz (1.875MHz - 20MHz)
0.55
ps
312.5MHz (1.875MHz - 20MHz)
0.59
ps
156.25MHz (1.875MHz - 20MHz)
0.63
ps
125MHz (1.875MHz - 20MHz)
0.64
ps
20% to 80%
325
ps
odc
Output Duty Cycle
50
NOTE 1: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Please refer to the Phase Noise Plots.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
844003AGI
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6
%
REV. B AUGUST 25, 2005
PRELIMINARY
Integrated
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Systems, Inc.
ICS844003I
FEMTOCLOCKS™CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 156.25MHZ
➤
0
-10
-20
-30
10Gb Ethernet Filter
156.25MHz
RMS Phase Jitter (Random)
1.875Mhz to 20MHz = 0.63ps (typical)
-70
-80
Raw Phase Noise Data
-90
-100
-110
-120
-130
-140
-150
-160
➤
➤
NOISE POWER dBc
Hz
-40
-50
-60
-170
-180
-190
100
1k
Phase Noise Result by adding
10Gb Ethernet Filter to raw data
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
844003AGI
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7
REV. B AUGUST 25, 2005
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Systems, Inc.
ICS844003I
FEMTOCLOCKS™CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
VDD
Noise Power
Phase Noise Plot
SCOPE
Qx
Power Supply
+
Float GND
-
LVDS
Phase Noise Mask
nQx
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
LVDS 3.3V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
nQA0,
nQB0, nQB1
nQx
QA0,
QB0, QB1
Qx
t PW
t
nQy
Qy
odc =
tsk(o)
PERIOD
t PW
x 100%
t PERIOD
OUTPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
nQB0
80%
80%
QB0
VSW I N G
Clock
Outputs
nQB1
20%
20%
tR
tF
QB1
tsk(b)
OUTPUT RISE/FALL TIME
BANK SKEW
VDD
VDD
out
➤
➤
LVDS
100
DC Input
VOD/Δ VOD
out
LVDS
➤
➤
DC Input
➤
out
out
VOS/Δ VOS
➤
DIFFERENTIAL OUTPUT VOLTAGE SETUP
844003AGI
OFFSET VOLTAGE SETUP
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REV. B AUGUST 25, 2005
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ICS844003I
FEMTOCLOCKS™CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS844003I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA, and VDDOx
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VDDA pin. The 10Ω
resistor can also be replaced by a ferrite bead.
3.3V
VDD
.01μF
10 Ω
VDDA
.01μF
10μF
FIGURE 2. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
were determined using a 31.25MHz or 26.041666MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error.
The ICS844003I has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in Figure 3 below
XTAL_OUT
C1
22p
X1
18pF Parallel Crystal
XTAL_IN
C2
22p
ICS844003I
Figure 3. CRYSTAL INPUt INTERFACE
844003AGI
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REV. B AUGUST 25, 2005
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ICS844003I
FEMTOCLOCKS™CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1kΩ
resistor can be tied from XTAL_IN to ground.
LVDS
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, we
recommend that there is no trace attached.
TEST_CLK INPUT:
For applications not requiring the use of the test clock, it can
be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the TEST_CLK to
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
3.3V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100Ω across near
the receiver input.
3.3V
3.3V
LVDS
+
R1
100
-
100 Ohm Differential Transmission Line
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
844003AGI
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10
REV. B AUGUST 25, 2005
PRELIMINARY
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Systems, Inc.
ICS844003I
FEMTOCLOCKS™CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
FOR
24 LEAD TSSOP
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
70°C/W
65°C/W
62°C/W
TRANSISTOR COUNT
The transistor count for ICS844003I is: 3394
844003AGI
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11
REV. B AUGUST 25, 2005
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PACKAGE OUTLINE - G SUFFIX
FOR
ICS844003I
FEMTOCLOCKS™CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
24 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
SYMBOL
Millimeters
Minimum
N
Maximum
24
A
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
7.70
E
E1
7.90
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
844003AGI
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12
REV. B AUGUST 25, 2005
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Systems, Inc.
ICS844003I
FEMTOCLOCKS™CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS844003AGI
ICS844003AGI
24 Lead TSSOP
tube
-40°C to 85°C
ICS844003AGIT
ICS844003AGI
24 Lead
2500 tape & reel
-40°C to 85°C
ICS844003AGILF
TBD
24 Lead "Lead-Free" TSSOP
tube
-40°C to 85°C
ICS844003AGITLF
TBD
24 Lead "Lead-Free" TSSOP
2500 tape & reel
-40°C to 85°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended
without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in
life support devices or critical medical instruments.
844003AGI
www.icst.com/products/hiperclocks.html
13
REV. B AUGUST 25, 2005
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