LINER LT8391 60v 2mhz synchronous 4-switch buck-boost controller with spread spectrum Datasheet

LT8390A
60V 2MHz Synchronous
4-Switch Buck-Boost Controller
with Spread Spectrum
FEATURES
DESCRIPTION
4-Switch Single Inductor Architecture Allows VIN
Above, Below or Equal to VOUT
nn Up to 95% Efficiency at 2MHz
nn Proprietary Peak-Buck Peak-Boost Current Mode
nn Wide V Range: 4V to 60V
IN
nn ±1.5% Output Voltage Accuracy: 1V ≤ V
OUT ≤ 60V
nn ±3% Input or Output Current Accuracy with Monitor
nn Spread Spectrum Frequency Modulation for Low EMI
nn High Side PMOS Load Switch Driver
nn No Top MOSFET Refresh Noise in Buck or Boost
nn Adjustable and Synchronizable: 600kHz to 2MHz
nn V
OUT Disconnected from VIN During Shutdown
nn Available in 28-Lead TSSOP with Exposed Pad and
28-Lead QFN (4mm × 5mm)
The LT®8390A is a synchronous 4-switch buck-boost DC/DC
controller that regulates output voltage, input or output
current from an input voltage above, below, or equal to
the output voltage. The proprietary peak-buck peak-boost
current mode control scheme allows adjustable and synchronizable 600kHz to 2MHz fixed frequency operation, or
internal 25% triangle spread spectrum frequency modulation for low EMI. With a 4V to 60V input voltage range, 0V
to 60V output voltage capability, and seamless low noise
transitions between operation regions, the LT8390A is ideal
for voltage regulator, battery and supercapacitor charger
applications in automotive, industrial, telecom, and even
battery-powered systems.
nn
APPLICATIONS
nn
nn
Automotive, Industrial, Telecom Systems
High Frequency Battery-Powered System
The LT8390A provides input or output current monitor
and power good flag. Fault protection is also provided to
detect output short-circuit condition, during which the
LT8390A retries, latches off, or keeps running.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Analog
Devices, Inc. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
95% Efficient 48W (12V 4A) 2MHz Buck-Boost Voltage Regulator
1µH
5mΩ
22µF
63V
0.1µF
100V
×2
0.1µF
4.7µF
100V
×2
SW1 LSP
BST1
INTVCC
LSN
10mΩ
0.1µF
SW2
BST2
BG1
BG2
0.1µF
16V
×2
VOUT
12V
4A
22µF
16V
×2
22µF
16V
Efficiency vs VIN
100
INTVCC
GND
TG1
VIN
383k
VOUT
1µF
169k
1µF
EN/UVLO
ISP
LOADTG
ISN
TEST
ISMON
ISMON
133k
0.47µF
10Ω
1µF 10Ω
FB
SSFM OFF
SYNC/SPRD
CTRL
100k
90
TG2
LT8390A
INTVCC
INTVCC
4.7µF
LOADEN
VREF
SS
22nF
PGOOD
RT
VC
10k
2.2nF
SSFM ON
100k
PGOOD
110k
10k
EFFICIENCY (%)
VIN
6V TO 28V
CONTINUOUS
4V TO 56V
TRANSIENT
80
70
IOUT = 4A
IOUT = 2A
60
50
CONTINUOUS OPERATION WITH
HIGHEST COMPONENT TEMPERATURE
BELOW 90°C (TA = 25°C)
0
5
10
15 20 25 30
INPUT VOLTAGE (V)
35
40
8390a TA01b
59.0k
2MHz
8390a TA01a
8390afa
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1
LT8390A
ABSOLUTE MAXIMUM RATINGS
(Note 1)
VIN, EN/UVLO, VOUT, ISP, ISN.....................................60V FB, LOADEN, SYNC/SPRD, CTRL, PGOOD....................6V
(ISP-ISN)...........................................................–1V to 1V Operating Junction Temperature Range (Notes 2, 3)
BST1, BST2.................................................................66V
LT8390AE............................................ –40°C to 125°C
LT8390AI............................................. –40°C to 125°C
SW1, SW2, LSP, LSN...................................... –6V to 60V
LT8390AH............................................ –40°C to 150°C
INTVCC, (BST1-SW1), (BST2-SW2)...............................6V
(BST1-LSP), (BST1-LSN)..............................................6V Storage Temperature Range.................... –65°C to 150°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
26 SW2
TG1
4
25 TG2
TG1 1
22 TG2
LSP
5
24 VOUT
LSP 2
21 VOUT
LSN
6
23 LOADTG
LSN 3
20 LOADTG
VIN
7
20 VC
EN/UVLO 6
18 SS
LOADEN 8
VREF 12
17 PGOOD
CTRL 13
16 ISMON
ISP 14
15 SS
9 10 11 12 13 14
15 ISN
FE PACKAGE
28-LEAD PLASTIC TSSOP
θJA = 30°C/W, θJC = 5°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
17 VC
16 FB
TEST 7
PGOOD
19 FB
18 RT
ISMON
TEST 10
LOADEN 11
19 SYNC/SPRD
29
GND
ISN
9
21 RT
INTVCC 5
ISP
EN/UVLO
VIN 4
22 SYNC/SPRD
VREF
8
28 27 26 25 24 23
CTRL
INTVCC
29
GND
SW2
27 BST2
3
BST2
2
SW1
BG2
BST1
BG1
28 BG2
BST1
1
SW1
BG1
UFD PACKAGE
28-LEAD (4mm × 5mm) PLASTIC QFN
θJA = 43°C/W, θJC = 3.4°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
http://www.linear.com/product/LT8390A#orderinfo
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT8390AEFE#PBF
LT8390AEFE#TRPBF
LT8390AFE
28-Lead Plastic TSSOP
–40°C to 125°C
LT8390AIFE#PBF
LT8390AIFE#TRPBF
LT8390AFE
28-Lead Plastic TSSOP
–40°C to 125°C
LT8390AHFE#PBF
LT8390AHFE#TRPBF
LT8390AFE
28-Lead Plastic TSSOP
–40°C to 150°C
LT8390AEUFD#PBF
LT8390AEUFD#TRPBF
8390A
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
LT8390AIUFD#PBF
LT8390AIUFD#TRPBF
8390A
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
LT8390AHUFD#PBF
LT8390AHUFD#TRPBF
8390A
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
2
8390afa
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LT8390A
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, VEN/UVLO = 1.5V unless otherwise noted.
PARAMETER
Supply
VIN Operating Voltage Range
VIN Quiescent Current
VOUT Voltage Range
VOUT Quiescent Current
Linear Regulators
INTVCC Regulation Voltage
INTVCC Load Regulation
INTVCC Line Regulation
INTVCC Current Limit
INTVCC Dropout Voltage (VIN – INTVCC)
INTVCC Undervoltage Lockout Threshold
INTVCC Undervoltage Lockout Hysteresis
VREF Regulation Voltage
VREF Load Regulation
VREF Line Regulation
VREF Current Limit
VREF Undervoltage Lockout Threshold
VREF Undervoltage Lockout Hysteresis
Control Inputs/Outputs
EN/UVLO Shutdown Threshold
EN/UVLO Enable Threshold
EN/UVLO Enable Hysteresis
EN/UVLO Hysteresis Current
CTRL Input Bias Current
CTRL Latch-Off Threshold
CTRL Latch-Off Hysteresis
Load Switch Driver
LOADEN Threshold
LOADEN Hysteresis
Minimum VOUT for LOADTG to be On
LOADTG On Voltage V(VOUT-LOADTG)
LOADTG Off Voltage V(VOUT-LOADTG)
LOADEN to LOADTG Turn On Propagation Delay
LOADEN to LOADTG Turn Off Propagation Delay
LOADTG Turn On Fall Time
LOADTG Turn Off Rise Time
CONDITIONS
MIN
l
4
VEN/UVLO = 0.3V
VEN/UVLO = 1.1V
Not Switching
1
270
2.1
l
VEN/UVLO = 0.3V, VOUT = 12V
VEN/UVLO = 1.1V, VOUT = 12V
Not Switching, VOUT = 12V
0
20
IINTVCC = 20mA
IINTVCC = 0mA to 80mA
IINTVCC = 20mA, VIN = 6V to 60V
VINTVCC = 4.5V
IINTVCC = 20mA, VIN = 4V
Falling
IVREF = 100µA
IVREF = 0mA to 1mA
IVREF = 100µA, VIN = 4V to 60V
VREF = 1.8V
Falling
4.85
110
3.44
l
1.97
2
1.78
l
0.3
1.196
VEN/UVLO = 0.3V
VEN/UVLO = 1.1V
VEN/UVLO = 1.3V
VCTRL = 0.75V, Current Out of Pin
Falling
l
–0.1
2.1
–0.1
0
285
Rising
l
1.3
l
Falling
VLOADEN = 5V
VOUT = 12V
VOUT = 12V
CLOADTG = 3.3nF to VOUT, 50% to 50%
CLOADTG = 3.3nF to VOUT, 50% to 50%
CLOADTG = 3.3nF to VOUT, 10% to 90%
CLOADTG = 3.3nF to VOUT, 90% to 10%
TYP
4.5
–0.1
0.1
0.1
40
5.0
1
1
145
160
3.54
0.24
2.00
0.4
0.1
2.5
1.84
50
MAX
60
2
2.8
60
0.5
0.5
60
5.15
4
4
190
3.64
2.03
1
0.2
3.2
1.90
0.6
1.220
13
0
2.5
0
20
300
25
1.0
1.244
1.4
220
2.4
5
0
90
40
300
10
1.5
0.1
2.9
0.1
50
315
3
5.5
0.1
UNITS
V
µA
µA
mA
V
µA
µA
µA
V
%
%
mA
mV
V
V
V
%
%
mA
V
mV
V
V
mV
µA
µA
µA
nA
mV
mV
V
mV
V
V
V
ns
ns
ns
ns
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3
LT8390A
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, VEN/UVLO = 1.5V unless otherwise noted.
PARAMETER
Error Amplifier
Full Scale Current Regulation V(ISP-ISN)
1/10th Current Regulation V(ISP-ISN)
ISMON Monitor Output VISMON
ISP/ISN Input Common Mode Range
ISP/ISN Low Side to High Side Switchover Voltage
ISP/ISN High Side to Low Side Switchover Voltage
ISP Input Bias Current
ISN Input Bias Current
ISP/ISN Current Regulation Amplifier gm
FB Regulation Voltage
FB Line Regulation
FB Load Regulation
FB Voltage Regulation Amplifier gm
FB Input Bias Current
VC Output Impedance
VC Standby Leakage Current
Current Comparator
Maximum Current Sense Threshold V(LSP-LSN)
LSP Pin Bias Current
LSN Pin Bias Current
Fault
FB Overvoltage Threshold (VFB)
FB Overvoltage Hysteresis
FB Short Threshold (VFB)
FB Short Hysteresis
ISP/ISN Over Current Threshold V(ISP-ISN)
PGOOD Upper Threshold Offset from VFB
PGOOD Lower Threshold Offset from VFB
PGOOD Pull-Down Resistance
SS Hard Pull-Down Resistance
SS Pull-Up Current
SS Pull-Down Current
SS Fault Latch-Off Threshold
SS Fault Reset Threshold
4
CONDITIONS
VCTRL = 2V, VISP = 12V
VCTRL = 2V, VISP = 0V
VCTRL = 0.35V, VISP = 12V
VCTRL = 0.35V, VISP = 0V
V(ISP-ISN) = 100mV, VISP = 12V/0V
V(ISP-ISN) = 10mV, VISP = 12V/0V
V(ISP-ISN) = 0mV, VISP = 12V/0V
l
l
l
l
l
l
l
l
MIN
TYP
MAX
UNITS
97
97
8
8
1.20
0.30
0.20
0
100
100
10
10
1.25
0.35
0.25
103
103
12
12
1.30
0.40
0.30
60
mV
mV
mV
mV
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µs
V
%
%
µS
nA
MΩ
nA
VISP = VISN
VISP = VISN
VLOADEN = 5V, VISP = VISN = 12V
VLOADEN = 5V, VISP = VISN = 0V
VEN/UVLO = 0V, VISP = VISN = 12V or 0V
VLOADEN = 5V, VISP = VISN = 12V
VLOADEN = 5V, VISP = VISN = 0V
VEN/UVLO = 0V, VISP = VISN = 12V or 0V
VC = 1.2V
VIN = 4V to 60V
l
0.985
FB in Regulation, Current Out of Pin
VC = 1.2V, VLOADEN = 0V
–10
1.8
1.7
23
–10
0
23
–10
0
2000
1.00
0.2
0.2
660
10
10
0
1.015
0.5
0.8
40
10
Buck, VFB = 0.8V
Boost, VFB = 0.8V
VLSP = VLSN = 12V
VLSP = VLSN = 12V
l
l
35
40
50
50
60
60
65
60
mV
mV
µA
µA
Rising
l
1.08
35
0.24
35
1.1
50
0.25
50
750
10
–10
100
100
12.5
1.25
1.7
0.2
1.12
65
0.26
65
V
mV
V
mV
mV
%
%
Ω
Ω
µA
µA
V
V
l
Falling
Hysteresis
VISP = 12V
Rising
Falling
VEN/UVLO = 1.1V
VFB = 0.4V, VSS = 0V
VFB = 0.1V, VSS = 2V
l
l
l
l
8
–12
10
1
12
–8
200
200
15
1.5
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LT8390A
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, VEN/UVLO = 1.5V unless otherwise noted.
PARAMETER
Oscillator
RT Pin Voltage
Switching Frequency
SYNC Frequency
SYNC/SPRD Input Bias Current
SYNC/SPRD Threshold Voltage
Highest Spread Spectrum Above Oscillator Frequency
Region Transition
Buck-Boost to Boost (VIN /VOUT)
Boost to Buck-Boost (VIN /VOUT)
Buck to Buck-Boost (VIN /VOUT)
Buck-Boost to Buck (VIN /VOUT)
Peak-Buck to Peak-Boost (VIN /VOUT)
Peak-Boost to Peak-Buck (VIN /VOUT)
NMOS Drivers
TG1, TG2 Gate Driver On-Resistance
Gate Pull-Up
Gate Pull-Down
BG1, BG2 Gate Driver On-Resistance
Gate Pull-Up
Gate Pull-Down
TG1, TG2 Rise Time
TG1, TG2 Fall Time
BG1, BG2 Rise Time
BG1, BG2 Fall Time
TG Off to BG On Delay
BG Off to TG On Delay
TG1 Minimum Duty Cycle in Buck Region
TG1 Maximum Duty Cycle in Buck Region
TG1 Fixed Duty Cycle in Buck-Boost Region
BG2 Fixed Duty Cycle in Buck-Boost Region
BG2 Minimum Duty Cycle in Boost Region
BG2 Maximum Duty Cycle in Boost Region
CONDITIONS
MIN
RT = 100kΩ
VSYNC/SPRD = 0V, RT = 226kΩ
VSYNC/SPRD = 0V, RT = 100kΩ
VSYNC/SPRD = 0V, RT = 59.0kΩ
VSYNC/SPRD = 5V
VSYNC/SPRD = 5V
l
645
1290
1900
600
–0.1
0.4
21
0.73
0.83
1.23
1.31
0.96
1.00
V(BST-SW) = 5V
VINTVCC = 5V
CL = 3.3nF, 10% to 90%
CL = 3.3nF, 90% to 10%
CL = 3.3nF, 10% to 90%
CL = 3.3nF, 90% to 10%
CL = 3.3nF
CL = 3.3nF
Peak-Buck Current Mode
Peak-Buck Current Mode
Peak-Boost Current Mode
Peak-Buck Current Mode
Peak-Boost Current Mode
Peak-Boost Current Mode
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT8390AE is guaranteed to meet performance specifications
from 0°C to 125°C operating junction temperature. Specifications over
the –40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LT8390AI is guaranteed over the –40°C to 125°C operating junction
TYP
MAX
UNITS
23
725
1430
2100
2100
0.1
1.5
25
V
kHz
kHz
kHz
kHz
µA
V
%
0.75
0.85
1.25
1.33
0.98
1.02
0.77
0.87
1.27
1.35
1.00
1.04
1.00
685
1360
2000
0
2.6
1.4
Ω
Ω
3.2
1.2
25
20
25
20
25
25
10
90
80
20
10
90
Ω
Ω
ns
ns
ns
ns
ns
ns
%
%
%
%
%
%
temperature range. The LT8390AH is guaranteed over the –40°C to 150°C
operating junction temperature range. High junction temperatures degrade
operating lifetimes. Operating lifetime is derated at junction temperatures
greater than 125°C.
Note 3: The LT8390A includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 150°C when overtemperature protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability.
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5
LT8390A
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Load Current
(Buck Region)
TA = 25°C, unless otherwise noted.
Efficiency vs Load Current
(Buck-Boost Region)
Efficiency vs Load Current
(Boost Region)
90
90
90
80
80
80
70
60
50
0.5
1
1.5 2 2.5 3
LOAD CURRENT (A)
3.5
60
50
FRONT PAGE APPLICATION
VIN = 24V, VOUT = 12V, fSW = 2MHz
0
70
40
4
0
0.5
1
8390a G01
IL
2A/DIV
VSW2
20V/DIV
IL
2A/DIV
VOUT
500mV/DIV
VOUT
500mV/DIV
8390 G04
200ns/DIV
FRONT PAGE APPLICATION
VIN = 24V, IOUT = 2A
3.0
2.5
10
2.0
IQ (µA)
12
8
1.0
4
0.5
2
3
4
5
LOAD CURRENT (A)
6
7
0
0.5
1
1.5 2 2.5 3
LOAD CURRENT (A)
3.5
4
8390a G03
Switching Waveforms
(Boost Region)
IL
2A/DIV
VOUT
500mV/DIV
200ns/DIV
FRONT PAGE APPLICATION
VIN = 8V, IOUT = 2A
8390 G05
VIN Shutdown Current
2.8
0.0
–50 –25
8390 G06
VIN Quiescent Current
2.6
VIN = 60V
1.5
6
1
FRONT PAGE APPLICATION
VIN = 8V, VOUT = 12V, fSW = 2MHz
VSW1
20V/DIV
VSW2
20V/DIV
200ns/DIV
FRONT PAGE APPLICATION
VIN = 12V, IOUT = 2A
VOUT vs IOUT (CV/CC)
0
40
4
VSW1
20V/DIV
VSW2
20V/DIV
OUTPUT VOLTAGE (V)
3.5
Switching Waveforms
(Buck-Boost Region)
VSW1
20V/DIV
2
60
8390a G02
Switching Waveforms
(Buck Region)
14
1.5 2 2.5 3
LOAD CURRENT (A)
70
50
FRONT PAGE APPLICATION
VIN = 12V, VOUT = 12V, fSW = 2MHz
IQ (mA)
40
EFFICIENCY (%)
100
EFFICIENCY (%)
100
EFFICIENCY (%)
100
VIN = 12V
VIN = 60V
2.4
VIN = 12V
2.2
VIN = 4V
2.0
VIN = 4V
0
25 50 75 100 125 150
TEMPERATURE (°C)
1.8
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
8390a G07
8390a G08
6
8390a G09
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LT8390A
TYPICAL PERFORMANCE CHARACTERISTICS
5.15
INTVCC Voltage vs Temperature
5.15
5.10
5.10
5.05
5.05
TA = 25°C, unless otherwise noted.
INTVCC Voltage vs VIN
4.0
INTVCC UVLO Threshold
3.9
IINTVCC = 0mA
5.00
IINTVCC = 80mA
IINTVCC = 20mA
VINTVCC (V)
VINTVCC (V)
VINTVCC (V )
3.8
5.00
4.95
4.95
4.90
4.90
RISING
3.7
3.6
FALLING
3.5
3.4
4.85
–50 –25
0
4.85
25 50 75 100 125 150
TEMPERATURE (°C)
3.3
0
10
20
30
VIN (V)
40
50
VREF Voltage vs Temperature
2.03
2.03
2.02
2.02
IVREF = 100µA
2.00
1.99
IVREF = 1mA
1.98
1.95
2.01
VREF (V)
VREF (V)
1.99
VREF UVLO Threshold
2.00
VREF (V)
2.04
2.00
RISING
1.85
FALLING
1.80
1.75
1.97
0
1.90
1.98
1.97
1.96
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
8390a G12
VREF Voltage vs VIN
2.04
IVREF = 0mA
0
8390a G11
8390a G10
2.01
3.2
–50 –25
60
1.96
25 50 75 100 125 150
TEMPERATURE (°C)
0
10
20
30
VIN (V)
40
50
1.70
–50 –25
60
0
25 50 75 100 125 150
TEMPERATURE (°C)
8390a G14
8390a G13
EN/UVLO Enable Threshold
8390a G15
EN/UVLO Hysteresis Current
1.240
CTRL Latch-Off Threshold
0.40
3.0
1.235
2.8
1.230
0.35
RISING
RISING
1.220
FALLING
1.215
1.210
2.6
VCTRL (V)
IHYS (µA)
VEN/UVLO (V)
1.225
2.4
0.30
FALLING
0.25
2.2
1.205
1.200
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
2.0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
0.20
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
8390a G18
8390a G16
8390a G17
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LT8390A
TYPICAL PERFORMANCE CHARACTERISTICS
106
125
V(ISP-ISN) (mV)
75
50
25
0
106
104
104
102
102
100
98
96
0
0.25 0.50 0.75 1 1.25 1.50 1.75
VCTRL (V)
94
2
0
10
20
30
VISP (V)
8390a G19
80
1.01
60
0.99
20
0.98
Maximum Current Sense
vs Temperature
VIN = 4V
VIN = 12V
VIN = 60V
0
60
55
50
45
40
35
30
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
1.15
0.35
0
25 50 75 100 125 150
TEMPERATURE (°C)
PGOOD Thresholds
20
15
RISING
RISING
VFB (V)
0.30
FALLING
0.25
0.20
0.15
25 50 75 100 125 150
TEMPERATURE (°C)
BUCK
BOOST
8390a G24
FB Short Threshold
0.40
0
8390a G21
8390a G23
FB Overvoltage Threshold
0.95
25 50 75 100 125 150
TEMPERATURE (°C)
65
0.97
–50 –25
1.20
1.00
0
70
8390a G22
FALLING
ISP = 0V
ISP = 12V
ISP = 60V
94
–50 –25
60
1.00
40
0
0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04
VFB (V)
VFB (V)
50
CURRENT LIMIT (mV)
1.02
VFB (V)
100
V(ISP-ISN) (mV)
1.03
0.90
–50 –25
40
FB Regulation vs Temperature
120
1.05
98
8390a G20
V(ISP-ISN) Regulation vs VFB
1.10
100
96
THRESHOLD OFFSET (%)
V(ISP-ISN) (mV)
100
V(ISP-ISN) Regulation
vs Temperature
V(ISP-ISN) Regulation vs VISP
V(ISP-ISN) (mV)
V(ISP-ISN) Regulation vs VCTRL
TA = 25°C, unless otherwise noted.
0.10
–50 –25
UPPER RISING
10
UPPER FALLING
5
0
–5
LOWER RISING
–10
LOWER FALLING
–15
0
25 50 75 100 125 150
TEMPERATURE (°C)
8390a G25
–20
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
8390a G27
8390a G26
8
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LT8390A
TYPICAL PERFORMANCE CHARACTERISTICS
15.0
12.5
1.00
10.0
0.75
5.0
0.25
2.5
20
40
60
V(ISP-ISN) (mV)
80
100
PULL-UP
7.5
0.50
0
2.5
SWITCHING FREQUENCY (MHz)
1.25
0
Oscillator Frequency
vs Temperature
SS Current vs Temperature
ISS (µA)
VISMON (V)
1.50
ISMON Voltage vs V(ISP-ISN)
TA = 25°C, unless otherwise noted.
0.0
–50 –25
PULL-DOWN
0
25 50 75 100 125 150
TEMPERATURE (°C)
8390a G28
RT = 59.0k
2.0
RT = 100k
1.5
1.0
RT = 226k
0.5
0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
8390a G30
8390a G29
PIN FUNCTIONS
BG1: Buck Side Bottom Gate Drive. Drives the gate of buck
side bottom N-channel MOSFET with a voltage swing from
ground to INTVCC.
BST1: Buck Side Bootstrap Floating Driver Supply. The
BST1 pin has an integrated bootstrap Schottky diode from
the INTVCC pin and requires an external bootstrap capacitor
to the SW1 pin. The BST1 pin swings from a diode voltage
drop below INTVCC to (VIN + INTVCC).
SW1: Buck Side Switch Node. The SW1 pin swings from
a Schottky diode voltage drop below ground up to VIN.
TG1: Buck Side Top Gate Drive. Drives the gate of buck
side top N-channel MOSFET with a voltage swing from
SW1 to BST1.
LSP: Positive Terminal of the Buck Side Inductor Current
Sense Resistor (RSENSE). Ensure accurate current sense
with Kelvin connection.
LSN: Negative Terminal of the Buck Side Inductor Current
Sense Resistor (RSENSE). Ensure accurate current sense
with Kelvin connection.
VIN: Input Supply. The VIN pin must be tied to the power
input to determine the buck, buck-boost, or boost operation
regions. Locally bypass this pin to ground with a minimum
1µF ceramic capacitor.
INTVCC: Internal 5V Linear Regulator Output. The INTVCC
linear regulator is supplied from the VIN pin, and powers the
internal control circuitry and gate drivers. Locally bypass
this pin to ground with a minimum 4.7µF ceramic capacitor.
EN/UVLO: Enable and Undervoltage Lockout. Force the
pin below 0.3V to shut down the part and reduce VIN quiescent current below 2µA. Force the pin above 1.233V for
normal operation. The accurate 1.220V falling threshold
can be used to program an undervoltage lockout (UVLO)
threshold with a resistor divider from VIN to ground. An
accurate 2.5µA pull-down current allows the programming
of VIN UVLO hysteresis. If neither function is used, tie this
pin directly to VIN.
TEST: Factory Test. This pin is used for testing purpose
only and must be directly connected to ground for the
part to operate properly.
LOADEN: Load Switch Enable Input. The LOADEN pin is
used to control the ON/OFF of the high side PMOS load
switch. If the load switch control is not used, tie this pin
to VREF or INTVCC. Forcing the pin low turns off TG1 and
TG2, turns on BG1 and BG2, disconnects the VC pin from
all internal loads, and turns off LOADTG.
VREF: Voltage Reference Output. The VREF pin provides
an accurate 2V reference capable of supplying 1mA
current. Locally bypass this pin to ground with a 0.47µF
ceramic capacitor.
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9
LT8390A
PIN FUNCTIONS
CTRL: Control Input for ISP/ISN Current Sense Threshold.
The CTRL pin is used to program the ISP/ISN current limit:
IIS(MAX) =
Min ( VCTRL − 0.25V,1V )
10 • RIS
The VCTRL can be set by an external voltage reference or
a resistor divider from VREF to ground. For 0.3V ≤ VCTRL
≤ 1.15V, the current sense threshold linearly goes up
from 5mV to 90mV. For VCTRL ≥ 1.35V, the current sense
threshold is constant at 100mV full scale value. For 1.15V
≤ VCTRL ≤ 1.35V, the current sense threshold smoothly
transitions from the linear function of VCTRL to the 100mV
constant value. Tie CTRL to VREF for the 100mV full scale
threshold. Force the pin below 0.3V to stop switching.
ISP: Positive Terminal of the ISP/ISN Current Sense Resistor (RIS). Ensure accurate current sense with Kelvin
connection.
ISN: Negative Terminal of the ISP/ISN Current Sense
Resistor (RIS). Ensure accurate current sense with Kelvin
connection.
ISMON: ISP/ISN Current Sense Monitor Output. The ISMON
pin generates a voltage that is equal to ten times V(ISP-ISN)
plus 0.25V offset voltage. For parallel applications, tie the
master LT8390A ISMON pin to the slave LT8390A CTRL pin.
PGOOD: Power Good Open Drain Output. The PGOOD
pin is pulled low when the FB pin is within ±10% of the
final regulation voltage. To function, the pin requires an
external pull-up resistor.
SS: Soft-Start Timer Setting. The SS pin is used to set
soft-start timer by connecting a capacitor to ground. An
internal 12.5µA pull-up current charging the external SS
capacitor gradually ramps up FB regulation voltage. A
22nF capacitor is recommended on this pin. Any UVLO or
thermal shutdown immediately pulls SS pin to ground and
stops switching. Using a single resistor from SS to VREF,
the LT8390A can be set in three different fault protection
modes during output short-circuit condition: hiccup (no
resistor), latch-off (499kΩ), and keep-running (100kΩ).
See more details in the Application Information section.
FB: Voltage Loop Feedback Input. The FB pin is used for
constant-voltage regulation and output fault protection.
The internal error amplifier with its output VC regulates
VFB to 1.00V through the DC/DC converter. During output
10
short-circuit (VFB < 0.25V) condition, the part gets into one
fault mode per customer setting. During an overvoltage
(VFB > 1.1V) condition, the part turns off all TG1, BG1,
TG2, BG2, and LOADTG.
VC: Error Amplifier Output to Set Inductor Current Comparator Threshold. The VC pin is used to compensate the
control loop with an external RC network. During LOADEN
low state, the VC pin is disconnected from all internal loads
to store its voltage information.
RT: Switching Frequency Setting. Connect a resistor from
this pin to ground to set the internal oscillator frequency
from 600kHz to 2MHz.
SYNC/SPRD: Switching Frequency Synchronization or
Spread Spectrum. Ground this pin for switching at internal oscillator frequency. Apply a clock signal for external
frequency synchronization. Tie to INTVCC for 25% triangle
spread spectrum above internal oscillator frequency.
LOADTG: High Side PMOS Load Switch Top Gate Drive. A
buffered and inverted version of the LOADEN input signal, the
LOADTG pin drives an external high side PMOS load switch
with a voltage swing from the higher voltage of (VOUT-5V)
and 1.2V to VOUT. Leave this pin unconnected if not used.
VOUT: Output Supply. The VOUT pin must be tied to the
power output to determine the buck, buck-boost, or boost
operation regions. The VOUT pin also serves as positive rail
for the LOADTG drive. Locally bypass this pin to ground
with a minimum 1µF ceramic capacitor.
TG2: Boost Side Top Gate Drive. Drives the gate of boost
side top N-Channel MOSFET with a voltage swing from
SW2 to BST2.
SW2: Boost Side Switch Node. The SW2 pin swings from
a Schottky diode voltage drop below ground to VOUT.
BST2: Boost Side Bootstrap Floating Driver Supply. The
BST2 pin has an integrated bootstrap Schottky diode from
the INTVCC pin and requires an external bootstrap capacitor
to the SW2 pin. The BST2 pin swings from a diode voltage
drop below INTVCC to (VOUT + INTVCC).
BG2: Boost Side Bottom Gate Drive. Drives the gate of
boost side bottom N-channel MOSFET with a voltage
swing from ground to INTVCC.
GND (Exposed Pad): Ground. Solder the exposed pad
directly to the ground plane.
For more information www.linear.com/LT8390A
8390afa
LT8390A
BLOCK DIAGRAM
LSN
VIN
INTVCC
LSP
INTVCC
+
5V LDO
–
VREF
+
A1
–
2V REF
BST1
A3
TG1
PEAK_BUCK
SW1
BUCK
LOGIC
INTVCC
LOADON
RT
OSC
SYNC/SPRD
+
–
0.3V
CTRL
ISMON
BG1
VOS
1X
EN/UVLO
1.220V
+
–
FBOV
VIS
VOUT/BST2
VIN/BST1
CHARGE
CONTROL
FB
1.1V
INHIBIT
SWITCH
–
+
BG2
+
–
ISOC
2.5µA
LOADON
VISP-ISN
0.75V
PEAK_BOOST
BOOST
LOGIC
INTVCC
SW2
TG2
+
–
LOADEN
TEST
VOUT
LOADON
+
–
0.25V
FB
SHORT
BST2
VREF
12.5µA
LOADTG
PGOOD
A4
10µA
VOUT –5V
+
–
+
–
1.1V
FAULT
LOGIC
FB
EA2
1.25µA
FB
1V
+
+
FB
CTRL
1.25V
–
LOADON
0.9V
SS
INTVCC
+
EA1 +
–
VC
GND
+
VIS
+
A2=10
–
ISP
ISN
0.25V
8390a BD
8390afa
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11
LT8390A
OPERATION
The LT8390A is a current mode DC/DC controller that
can regulate output voltage, input or output current from
input voltage above, below, or equal to the output voltage.
The LTC proprietary peak-buck peak-boost current mode
control scheme uses a single inductor current sense resistor and provides smooth transition between buck region,
buck-boost region, and boost region. Its operation is best
understood by referring to the Block Diagram.
VIN
VOUT
A
TG1
SW1
RSENSE
D
L
B
BG1
TG2
SW2
C
BG2
8390a F01
Figure 1. Simplified Diagram of the Power Switches
Power Switch Control
Figure 1 shows a simplified diagram of how the four power
switches A, B, C, and D are connected to the inductor L,
the current sense resistor RSENSE, power input VIN, power
output VOUT, and ground. The current sense resistor RSENSE
connected to the LSP and LSN pins provides inductor
current information for both peak current mode control
and reverse current detection in buck region, buck-boost
region, and boost region. Figure 2 shows the current mode
control as a function of VIN/VOUT ratio and Figure 3 shows
the operation region as a function of VIN/VOUT ratio. The
power switches are properly controlled to smoothly transition between modes and regions. Hysteresis is added to
prevent chattering between modes and regions.
There are total four states: (1) peak-buck current mode
control in buck region, (2) peak-buck current mode control in buck-boost region, (3) peak-boost current mode
control in buck-boost region, and (4) peak-boost current
mode control in boost region. The following sections give
detailed description for each state with waveforms, in
which the shoot-through protection dead time between
switches A and B, between switches C and D are ignored
for simplification.
PEAK-BUCK
PEAK-BOOST
0.98 1.00 1.02
VIN/VOUT
8390a F02
Figure 2. Current Mode vs VIN/VOUT Ratio
(1)
BUCK
(3)
(2)
BUCK-BOOST
(2)
BOOST
(4)
0.75
0.85
1.00
VIN/VOUT
1.25
1.33
8390a F03
Figure 3. Operation Region vs VIN/VOUT Ratio
12
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LT8390A
OPERATION
(1) Peak-Buck in Buck Region (VIN >> VOUT)
(2) Peak-Buck in Buck-Boost Region (VIN ~> VOUT)
When VIN is much higher than VOUT, the LT8390A uses
peak-buck current mode control in buck region (Figure
4). Switch C is always off and switch D is always on. At
the beginning of every cycle, switch A is turned on and
the inductor current ramps up. When the inductor current hits the peak buck current threshold commanded by
VC voltage at buck current comparator A3 during (A+D)
phase, switch A is turned off and switch B is turned on
for the rest of the cycle. Switches A and B will alternate,
behaving like a typical synchronous buck regulator.
When VIN is slightly higher than VOUT, the LT8390A uses
peak-buck current mode control in buck-boost region
(Figure 5). Switch C is always turned on for the beginning
20% cycle and switch D is always turned on for the remaining 80% cycle. At the beginning of every cycle, switches
A and C are turned on and the inductor current ramps
up. After 20% cycle, switch C is turned off and switch D
is turned on, and the inductor keeps ramping up. When
the inductor current hits the peak buck current threshold
commanded by VC voltage at buck current comparator A3
during (A+D) phase, switch A is turned off and switch B
is turned on for the rest of the cycle.
A
A
B
B
C
100% OFF
C
D
100% ON
D
20%
80%
IL
IL
A+D
B+D
B+D
A+D
80%
A+D
A+C
A+D
B+D
A+C
B+D
8390a F05
8390a F04
Figure 4. Peak-Buck in Buck Region (VIN >> VOUT)
20%
Figure 5. Peak-Buck in Buck-Boost Region (VIN ~> VOUT)
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13
LT8390A
OPERATION
(3) Peak-Boost in Buck-Boost Region (VIN <~ VOUT)
(4) Peak-Boost in Boost Region (VIN << VOUT)
When VIN is slightly lower than VOUT, the LT8390A uses
peak-boost current mode control in buck-boost region
(Figure 6). Switch A is always turned on for the beginning 80% cycle and switch B is always turned on for the
remaining 20% cycle. At the beginning of every cycle,
switches A and C are turned on and the inductor current
ramps up. When the inductor current hits the peak boost
current threshold commanded by VC voltage at boost
current comparator A4 during (A+C) phase, switch C is
turned off and switch D is turned on for the rest of the
cycle. After 80% cycle, switch A is turned off and switch
B is turned on for the rest of the cycle.
When VIN is much lower than VOUT, the LT8390A uses
peak-boost current mode control in boost region (Figure 7).
Switch A is always on and switch B is always off. At the
beginning of every cycle, switch C is turned on and the
inductor current ramps up. When the inductor current hits
the peak boost current threshold commanded by VC voltage at boost current comparator A4 during (A+C) phase,
switch C is turned off and switch D is turned on for the
rest of the cycle. Switches C and D will alternate, behaving
like a typical synchronous boost regulator.
A
A
100% ON
B
100% OFF
80%
B
80%
20%
20%
C
C
D
D
IL
A+C
A+D
A+C
B+D
A+D
IL
B+D
A+C
A+D
A+C
A+D
8390a F07
8390a F06
Figure 6. Peak-Boost in Buck-Boost Region (VIN <~ VOUT)
14
Figure 7. Peak-Boost in Boost Region (VIN << VOUT)
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LT8390A
OPERATION
Main Control Loop
Internal Charge Path
The LT8390A is a fixed frequency current mode controller. The inductor current is sensed through the inductor
sense resistor between the LSP and LSN pins. The current
sense voltage is gained up by amplifier A1 and added to
a slope compensation ramp signal from the internal oscillator. The summing signal is then fed into the positive
terminals of the buck current comparator A3 and boost
current comparator A4. The negative terminals of A3 and
A4 are controlled by the voltage on the VC pin, which is
the diode-OR of error amplifiers EA1 and EA2.
Each of the two top MOSFET drivers is biased from its
floating bootstrap capacitor, which is normally re-charged
by INTVCC through both the external and internal bootstrap diodes when the top MOSFET is turned off. When
the LT8390A operates exclusively in the buck or boost
regions, one of the top MOSFETs is constantly on. An
internal charge path, from VOUT and BST2 to BST1 or from
VIN and BST1 to BST2, charges the bootstrap capacitor to
4.6V so that the top MOSFET can be kept on.
Depending on the state of the peak-buck peak-boost current mode control, either the buck logic or the boost logic
is controlling the four power switches so that either the
FB voltage is regulated to 1V or the current sense voltage
between the ISP and ISN pins is regulated by the CTRL
pin during normal operation. The gains of EA1 and EA2
have been balanced to ensure smooth transition between
constant-voltage and constant-current operation with the
same compensation network.
Light Load Current Operation
At light load, the LT8390A runs either at full switching frequency discontinuous conduction mode or pulse-skipping
mode, where the switches are held off for multiple cycles
(i.e., skipping pulses) to maintain the regulation and
improve the efficiency. Both the buck and boost reverse
current sense thresholds are set to 1mV (typical) so that
no reverse inductor current is allowed. Such no reverse
inductor current from the output to the input is highly
desired in certain applications.
In the buck region, switch B is turned off whenever the
buck reverse current threshold is triggered during (B+D)
phase. In the boost region, switch D is turned off whenever
the boost reverse current threshold is triggered during
(A+D) phase. In the buck-boost region, switch D is turned
off whenever the boost reverse current threshold is triggered during (A+D) phase, and both switches B and D are
turned off whenever the buck reverse current threshold is
triggered during (B+D) phase.
Shutdown and Power-On-Reset
The LT8390A enters shutdown mode and drains less than
2µA quiescent current when the EN/UVLO pin is below its
shutdown threshold (0.3V minimum). Once the EN/UVLO
pin is above its shutdown threshold (1V maximum), the
LT8390A wakes up startup circuitry, generates bandgap
reference, and powers up the internal INTVCC LDO. The
INTVCC LDO supplies the internal control circuitry and gate
drivers. Now the LT8390A enters undervoltage lockout
(UVLO) mode with a hysteresis current (2.5µA typical)
pulled into the EN/UVLO pin. When the INTVCC pin is
charged above its rising UVLO threshold (3.78V typical), the EN/UVLO pin passes its rising enable threshold
(1.233V typical), and the junction temperature is less than
its thermal shutdown (165°C typical), the LT8390A enters
enable mode, in which the EN/UVLO hysteresis current is
turned off and the voltage reference VREF is being charged
up from ground. From the time of entering enable mode to
the time of VREF passing its rising UVLO threshold (1.89V
typical), the LT8390A is going through a power-on-reset
(POR), waking up the entire internal control circuitry and
settling to the right initial conditions. After the POR, the
LT8390A is ready and waiting for the signals on the CTRL
and LOADEN pins to start switching.
8390afa
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15
LT8390A
OPERATION
Start-Up and Fault Protection
Figure 8 shows the start-up and fault sequence for the
LT8390A. During the POR state, the SS pin is hard pulled
down with a 100Ω to ground. In a pre-biased condition,
the SS pin has to be pulled below 0.2V to enter the INIT
state, where the LT8390A wait 10µs so that the SS pin can
be fully discharged to ground. After the 10µs, the LT8390A
enters the UP/PRE state when the LOADON signal goes
high. The LOADON high signal happens when CTRL pin is
above its rising latch-off thresholds (0.325V typical) and
the LOADEN is high.
During the UP/PRE state, the SS pin is charged up by a
12.5µA pull-up current while the switching is disabled
and the LOADTG is turned off. Once the SS pin is charged
POR = HI or
ISOC = HI
POR
INIT
• SS hard pull down
• Switching disabled
• LOADTG turned off
• No short detection
• SS hard pull down
• Switching disabled
• LOADTG turned off
• No short detection
SS < 0.2V
Wait 10µs and
LOADON = HI
UP/TRY
• SS 12.5µA pull up
• Switching disabled
• LOADTG turned on
• No short detection
UP/PRE
SS > 0.25V
• SS 12.5µA pull up
• Switching disabled
• LOADTG turned off
• No short detection
Wait 10µs
UP/RUN
• SS 12.5µA pull up
• Switching enabled
• LOADTG turned on
• No short detection
OK/RUN
SS > 1.75V
• SS 12.5µA pull up
• Switching enabled
• LOADTG turned on
• Short detection
SS < 0.2V and
LOADON = HI
SHORT
DOWN/STOP
• SS 1.25µA pull down
• Switching disabled
• LOADTG turned on
• No short detection
FAULT/RUN
SS < 1.7V
• SS 1.25µA pull down
• Switching enabled
• LOADTG turned on
• Short detection
8390a F08
Figure 8. Start-Up and Fault Sequence
16
above 0.25V, the LT8390A enters the UP/TRY state, where
the LOADTG is turned on first while the switching is still
disabled. If an excessive current flowing through the
current sense resistor triggers the ISP/ISN over current
(ISOC) signal, it will reset the LT8390A back into the POR
state. After 10µs in the UP/TRY state without triggering
the ISOC signal, the LT8390A enters the UP/RUN state.
During the UP/RUN state, the switching is enabled and
the start-up of the output voltage VOUT is controlled by
the voltage on the SS pin. When the SS pin voltage is less
than 1V, the LT8390A regulates the FB pin voltage to the
SS pin voltage instead of the 1V reference. This allows the
SS pin to be used to program soft-start by connecting an
external capacitor from the SS pin to GND. The internal
12.5µA pull-up current charges up the capacitor, creating
a voltage ramp on the SS pin. As the SS pin voltage rises
linearly from 0.25V to 1V (and beyond), the output voltage
VOUT rises smoothly to its final regulation voltage.
Once the SS pin is charged above 1.75V, the LT8390A
enters the OK/RUN state, where the output short detection is activated. The output short means VFB < 0.25V.
When the output short happens, the LT8390A enters
the FAULT/RUN state, where a 1.25µA pull-down current
slowly discharges the SS pin with the other conditions the
same as the OK/RUN state. Once the SS pin is discharged
below 1.7V, the LT8390A enters the DOWN/STOP state,
where the switching is disabled and the short detection is
deactivated with the previous fault latched. Once the SS
pin is discharged below 0.2V and the LOADON signal is
still high, the LT8390A goes back to the UP/RUN state.
In an output short condition, the LT8390A can be set to
hiccup, latch-off, or keep-running fault protection mode
with a resistor between the SS and VREF pins. Without
any resistor, the LT8390A will hiccup between 0.2V and
1.75V and go around the UP/RUN, OK/RUN, FAULT/RUN,
and DOWN/STOP states until the fault condition is cleared.
With a 499kΩ resistor, the LT8390A will latch off until the
EN/UVLO is toggled. With a 100kΩ resistor, the LT8390A
will keep running regardless of the fault.
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LT8390A
APPLICATIONS INFORMATION
Switching Frequency Selection
The LT8390A uses a constant frequency control scheme
between 600kHz and 2MHz. Selection of the switching
frequency is a tradeoff between efficiency and component
size. Low frequency operation improves efficiency by
reducing MOSFET switching losses, but requires larger
inductor and capacitor values. For high power applications, consider operating at lower frequencies to minimize
MOSFET heating from switching losses. For low power
applications, consider operating at higher frequencies to
minimize the total solution size.
implements a triangle spread spectrum frequency modulation scheme. With the SYNC/SPRD pin tied to INTVCC,
the LT8390A starts to spread its switching frequency 25%
above the internal oscillator frequency. Figure 9 and Figure
10 show the noise spectrum of the front page application
when spread spectrum enabled.
90
SSFM ON WITH EMI FILTER
NOISE FLOOR
CISPER 25 CLASS 5 PEAK LIMITS
80
70
60
EMI (dBµV)
The front page shows a typical LT8390A application circuit.
This Applications Information section serves as a guideline
of selecting external components for typical applications.
The examples and equations in this section assume continuous conduction mode unless otherwise specified.
LW
50
40
MW
CB
20
10
0
–10
0.1
1
FREQUENCY (MHz)
90
80
LW
70
Table 1. Switching Frequency vs RT Value (1% Resistor)
fOSC (MHz)
RT (k)
0.6
267
0.8
191
1.0
147
1.2
118
1.4
97.6
1.6
82.5
1.8
66.5
2.0
59.0
Spread Spectrum Frequency Modulation
Switching regulators can be particularly troublesome for
applications where electromagnetic interference (EMI) is
a concern. To improve the EMI performance, the LT8390A
EMI (dBµV)
60
The switching frequency of the LT8390A can be set by
the internal oscillator. With the SYNC/SPRD pin pulled to
ground, the switching frequency is set by a resistor from
the RT pin to ground. Table 1 shows RT resistor values
for common switching frequencies.
10
8390a F09
Figure 9. Average Conducted EMI
In addition, the specific application also plays an important
role in switching frequency selection. In a noise-sensitive
system, the switching frequency is usually selected to keep
the switching noise out of a sensitive frequency band.
Switching Frequency Setting
SW
30
50
SSFM ON WITH EMI FILTER
NOISE FLOOR
CISPER 25 CLASS 5 PEAK LIMITS
MW
SW
CB
40
30
20
10
0
–10
0.1
1
FREQUENCY (MHz)
10
8390a F10
Figure 10. Peak Conducted EMI
Frequency Synchronization
The LT8390A switching frequency can be synchronized to
an external clock using the SYNC/SPRD pin. Driving the
SYNC/SPRD with a 50% duty cycle waveform is always a
good choice, otherwise maintain the duty cycle between
10% and 90%. Due to the use of a phase-locked loop (PLL)
inside, there is no restriction between the synchronization
frequency and the internal oscillator frequency. The rising
edge of the synchronization clock represents the beginning of a switching cycle, turning on switches A and C,
or switches A and D.
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LT8390A
APPLICATIONS INFORMATION
Inductor Selection
RSENSE Selection and Maximum Output Current
The switching frequency and inductor selection are interrelated in that higher switching frequencies allow the use of
smaller inductor and capacitor values. The inductor value
has a direct effect on ripple current. The highest current
ripple ∆IL% happens in the buck region at VIN(MAX), and the
lowest current ripple ∆IL% happens in the boost region at
VIN(MIN). For any given ripple allowance set by customers,
the minimum inductance can be calculated as:
RSENSE is chosen based on the required output current.
The duty cycle independent maximum current sense
thresholds (50mV in peak-buck and 50mV in peak-boost)
set the maximum inductor peak current in buck region,
buck-boost region, and boost region.
LBUCK >
VOUT • ( VIN(MAX) − VOUT )
f •IOUT(MAX) • ∆IL % • VIN(MAX)
LBOOST >
VIN(MIN)2 • ( VOUT − VIN(MIN) )
f •IOUT(MAX) • ∆IL % • VOUT2
 50mV ∆IL(BOOST)  VIN(MIN)
IOUT(MAX _ BOOST) = 
−
•
2
 RSENSE
 VOUT
where ∆IL(BOOST) is peak-to-peak inductor ripple current
in boost region and can be calculated as:
∆IL(BOOST) =
where:
∆IL % =
∆IL
IL(AVG)
f • L • VOUT
 50mV ∆IL(BUCK) 
IOUT(MAX _ BUCK) = 
−

2
 RSENSE

VIN(MIN) is minimum input voltage
where ∆IL(BUCK) is peak-to-peak inductor ripple current in
buck region and can be calculated as:
VIN(MAX) is maximum input voltage
VOUT is output voltage
IOUT(MAX) is maximum output current
Slope compensation provides stability in constant frequency current mode control by preventing subharmonic
oscillations at certain duty cycles. The minimum inductance
required for stability when duty cycles are larger than 50%
can be calculated as:
10 • VOUT • RSENSE
f
For high efficiency, choose an inductor with low core loss,
such as ferrite. Also, the inductor should have low DC
resistance to reduce the I2R losses, and must be able to
handle the peak inductor current without saturating. To
minimize radiated noise, use a shielded inductor.
18
VIN(MIN) • ( VOUT − VIN(MIN) )
In buck region, the lowest maximum average load current
happens at VIN(MAX) and can be calculated as:
f is switching frequency
L>
In boost region, the lowest maximum average load current
happens at VIN(MIN) and can be calculated as:
∆IL(BUCK) =
VOUT • ( VIN(MAX) − VOUT )
f • L • VIN(MAX)
The maximum current sense RSENSE in boost region is:
RSENSE(BOOST) =
2 • 50mV • VIN(MIN)
2 •IOUT(MAX) • VOUT + ∆IL(BOOST) • VIN(MIN)
The maximum current sense RSENSE in buck region is
RSENSE(BUCK) =
2 • 50mV
2 •IOUT(MAX) + ∆IL(BUCK)
The final RSENSE value should be lower than the calculated
RSENSE in both buck and boost regions. A 20% to 30%
margin is usually recommended. Always choose a low
ESL current sense resistor.
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Power MOSFET Selection
RL is the maximum DCR resistor of inductor at 25°C
The LT8390A requires four external N-channel power MOSFETs, two for the top switches (switches A and D shown
in Figure 1) and two for the bottom switches (switches B
and C shown in Figure 1). Important parameters for the
power MOSFETs are the breakdown voltage VBR(DSS),
threshold voltage VGS(TH), on-resistance RDS(ON), reverse
transfer capacitance CRSS and maximum current IDS(MAX).
To achieve 2MHz operation, the power MOSFET selection
is critical. With typical 25ns shoot-through protection
deadtime, high performance power MOSFETs with low
Qg and low RDS(ON) must be used.
Since the gate drive voltage is set by the 5V INTVCC supply,
logic-level threshold MOSFETs must be used in LT8390A
applications. Switching four MOSFETs at higher frequency
like 2MHz, the substantial gate charge current from INTVCC
can be estimated as:
IINTVCC = f • (QgA +QgB +QgC +QgD)
In order to select the power MOSFETs, the power dissipated by the device must be known. For switch A, the
maximum power dissipation happens in boost region, when
it remains on all the time. Its maximum power dissipation
at maximum output current is given by:
 IOUT(MAX) • VOUT  2
PA(BOOST) = 
 • ρT • RDS(ON)
VIN


where ρT is a normalization factor (unity at 25°C) accounting for the significant variation in on-resistance with
temperature, typically 0.4%/°C as shown in Figure 11. For
a maximum junction temperature of 125°C, using a value
of ρT = 1.5 is reasonable.
Switch B operates in buck region as the synchronous
rectifier. Its power dissipation at maximum output current is given by:
f is the switching frequency
QgA, QgB, QgC, QgD are the total gate charges of MOSFETs
A, B, C, D
Make sure the total required INTVCC current not exceeding the INTVCC current limit in the datasheet. Typically,
MOSFETs with less than 10nC Qg are recommended.
The LT8390A uses the VIN/VOUT ratio to transition between
modes and regions. Bigger IR drop in the power path caused
by improper MOSFET and inductor selection may prevent
the LT8390A from smooth transition. To ensure smooth
transitions between buck, buck-boost, and boost modes
of operation, choose low RDS(ON) MOSFETs and low DCR
inductor to satisfy:
0.025• VOUT
RA,B +RC,D +RSENSE +RL
where:
RA,B is the maximum RDS(ON) of MOSFETs A or B at 25°C
RC,D is the maximum RDS(ON) of MOSFETs C or D at
25°C
PB(BUCK) =
VIN − VOUT
•IOUT(MAX)2 • ρT • RDS(ON)
VIN
Switch C operates in boost region as the control switch.
Its power dissipation at maximum current is given by:
PC(BOOST) =
( VOUT − VIN ) • VOUT •I
VIN
2
• RDS(ON) + k • VOUT3 •
2
OUT(MAX)
IOUT(MAX)
VIN
• ρT
• CRSS • f
2.0
ρT NORMALIZED ON-RESISTANCE (Ω)
where:
IOUT(MAX) ≤
The RDS(ON) and DCR increase at higher junction
temperatures and the process variation have been included
in the calculation above.
1.5
1.0
0.5
0
–50
50
100
0
JUNCTION TEMPERATURE (°C)
150
8390a F11
Figure 11. Normalized RDS(ON) vs Temperature
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19
LT8390A
APPLICATIONS INFORMATION
where CRSS is usually specified by the MOSFET manufacturers. The constant k, which accounts for the loss caused
by reverse recovery current, is inversely proportional to
the gate drive current and has an empirical value of 1.7.
For switch D, the maximum power dissipation happens in
boost region, when its duty cycle is higher than 50%. Its
maximum power dissipation at maximum output current
is given by:
PD(BOOST) =
VOUT
•IOUT(MAX)2 • ρT • RDS(ON)
VIN
For the same output voltage and current, switch A has the
highest power dissipation and switch B has the lowest
power dissipation unless a short occurs at the output.
From a known power dissipated in the power MOSFET, its
junction temperature can be obtained using the following
formula:
TJ = TA + P • RTH(JA)
The junction-to-ambient thermal resistance RTH(JA) includes the junction-to-case thermal resistance RTH(JC)
and the case-to-ambient thermal resistance RTH(CA). This
value of TJ can then be compared to the original, assumed
value used in the iterative calculation process.
Optional Schottky Diode (DB, DD) Selection
The optional Schottky diodes DB (in parallel with switch
B) and DD (in parallel with switch D) conduct during the
dead time between the conduction of the power MOSFET
switches. They are intended to prevent the body diode of
synchronous switches B and D from turning on and storing
charge during the dead time. In particular, DB significantly
reduces reverse recovery current between switch B turnoff and switch A turn-on, and DD significantly reduces
reverse recovery current between switch D turn-off and
switch C turn-on. They improve converter efficiency and
reduce switch voltage stress. In order for the diode to be
effective, the inductance between it and the synchronous
switch must be as small as possible, mandating that these
components be placed adjacently.
20
CIN and COUT Selection
Input and output capacitance is necessary to suppress
voltage ripple caused by discontinuous current moving
in and out the regulator. A parallel combination of capacitors is typically used to achieve high capacitance and low
equivalent series resistance (ESR). Dry tantalum, special
polymer, aluminum electrolytic and ceramic capacitors are
all available in surface mount packages. Capacitors with
low ESR and high ripple current ratings, such as OS-CON
and POSCAP are also available.
Ceramic capacitors should be placed near the regula-tor
input and output to suppress high frequency switching
spikes. Ceramic capacitors, of at least 1µF, should also
be placed from VIN to GND and VOUT to GND as close to
the LT8390A pins as possible. Due to their excellent low
ESR characteristics, ceramic capacitors can significantly
reduce input ripple voltage and help reduce power loss in
the higher ESR bulk capacitors. X5R or X7R dielectrics are
preferred, as these materials retain their capacitance over
wide voltage and temperature ranges. Many ceramic capacitors, particularly 0805 or 0603 case sizes, have greatly
reduced capacitance at the desired operating voltage.
Input Capacitance CIN: Discontinuous input current is
highest in the buck region due to the switch A toggling
on and off. Make sure that the CIN capacitor network has
low enough ESR and is sized to handle the maximum RMS
current. In buck region, the input RMS current is given by:
IRMS ≈ IOUT(MAX) •
VOUT
VIN
•
−1
VIN
VOUT
The formula has a maximum at VIN = 2VOUT, where IRMS
= IOUT(MAX) /2. This simple worst-case condition is commonly used for design because even significant deviations
do not offer much relief.
Output Capacitance COUT: Discontinuous current shifts
from the input to the output in the boost region. Make sure
that the COUT capacitor network is capable of reducing
the output voltage ripple. The effects of ESR and the bulk
capacitance must be considered when choosing the right
capacitor for a given output ripple voltage. The maximum
steady state ripple due to charging and discharging the
bulk capacitance is given by:
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∆VCAP(BOOST) =
IOUT(MAX) • ( VOUT − VIN(MIN) )
COUT • VOUT • f


V
VOUT • 1− OUT 
 VIN(MAX) 
∆VCAP(BUCK) =
8 • L • f2 • COUT
The maximum steady ripple due to the voltage drop across
the ESR is given by:
∆VESR(BOOST) =
VOUT •IOUT(MAX)
VIN(MIN)
• ESR


V
VOUT • 1− OUT 
 VIN(MAX) 
• ESR
∆VESR(BUCK) =
L•f
INTVCC Regulator
An internal P-channel low dropout regulator produces
5V at the INTVCC pin from the VIN supply pin. The INTVCC
powers internal circuitry and gate drivers in the LT8390A.
The INTVCC regulator can supply a peak current of 145mA
and must be bypassed to ground with a minimum of
4.7µF ceramic capacitor. Good local bypass is necessary
to supply the high transient current required by MOSFET
gate drivers.
Higher input voltage applications with large MOSFETs being driven at higher switching frequencies may cause the
maximum junction temperature rating for the LT8390A
to be exceeded. The system supply current is normally
dominated by the gate charge current. Additional external
loading of the INTVCC also needs to be taken into account
for the power dissipation calculation. The total LT8390A
power dissipation in this case is VIN • IINTVCC, and overall
efficiency is lowered. The junction temperature can be
estimated by using the equation:
TJ = TA + PD • θJA
Top Gate MOSFET Driver Supply (CBST1, CBST2)
The top MOSFET drivers, TG1 and TG2, are driven between
their respective SW and BST pin voltages. The boost voltages are biased from floating bootstrap capacitors CBST1
and CBST2, which are normally recharged through both the
external and internal bootstrap diodes when the respective
top MOSFET is turned off. External bootstrap diodes are
recommended because the internal bootstrap diodes are
not always strong enough to refresh top MOSFETs at 2MHz.
Both capacitors are charged to the same voltage as the
INTVCC voltage. The bootstrap capacitors CBST1 and CBST2,
need to store about 100 times the gate charge required by
the top switches A and D. In most applications, a 0.1µF
to 0.47µF, X5R or X7R dielectric capacitor is adequate.
Programming VIN UVLO
A resistor divider from VIN to the EN/UVLO pin implements
VIN undervoltage lockout (UVLO). The EN/UVLO enable
falling threshold is set at 1.220V with 13mV hysteresis. In
addition, the EN/UVLO pin sinks 2.5µA when the voltage
on the pin is below 1.220V. This current provides user
programmable hysteresis based on the value of R1. The
programmable UVLO thresholds are:
R1+R2
+ 2.5µA • R1
R2
R1+R2
VIN(UVLO−) = 1.220V •
R2
VIN(UVLO+) = 1.233V •
Figure 12 shows the implementation of external shut-down
control while still using the UVLO function. The NMOS
grounds the EN/UVLO pin when turned on, and puts the
LT8390A in shutdown with quiescent current less than 2µA.
VIN
R1
EN/UVLO
LT8390A
where θJA (in °C/W) is the package thermal resistance.
To prevent maximum junction temperature from being
exceeded, the input supply current must be checked operating in continuous mode at maximum VIN.
R2
RUN/STOP
CONTROL
(OPTIONAL)
GND
8390a F12
Figure 12. VIN Undervoltage Lockout (UVLO)
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LT8390A
APPLICATIONS INFORMATION
Programming Input or Output Current Limit
The input or output current limit can be programmed by
placing an appropriate value current sense resistor, RIS, in
the input or output power path. The voltage drop across
RIS is (Kelvin) sensed by the ISP and ISN pins. The CTRL
pin should be tied to a voltage higher than 1.35V to get
the full-scale 100mV (typical) threshold across the sense
resistor. The CTRL pin can be used to reduce the current
threshold to zero, although relative accuracy decreases
with the decreasing sense threshold. When the CTRL pin
voltage is between 0.3V and 1.15V, the current limit is:
IIS(MAX) =
VCTRL − 0.25V
10 • RIS
When VCTRL is between 1.15V and 1.35V the current limit
varies with VCTRL, but departs from the equation above
by an increasing amount as VCTRL increases. Ultimately,
when VCTRL is larger than 1.35V, the current limit no
longer varies. The typical V(ISP-ISN) threshold vs VCTRL is
listed in Table 2.
Table 2. V(ISP-ISN) Threshold vs VCTRL
VCTRL (V)
V(ISP-ISN) (mV)
1.15
90
1.20
94.5
1.25
98
1.30
99.5
1.35
100
frequency is expected. If the current sense resistor RIS
is placed between power input and input bulk capacitor
(Figure 13a), or between output bulk capacitor and system
output (Figure 14a), a filter is typically not necessary. If
the RIS is placed between input bulk capacitor and input
decoupling capacitor (Figure 13b), or between output
decoupling capacitor and output bulk capacitor (Figure
14b), a low pass filter formed by RF and CF is recommended to reduce the current ripple and stabilize the
current loop. Since the bias currents of the ISP and ISN
pins are matched, no offset is introduced by RF. If input
or output current limit is not used, the ISP and ISN pins
should be shorted to VIN, VOUT, or ground.
ISMON Current Monitor
The ISMON pin provides a buffered monitor output of the
current flowing through the ISP/ISN current sense resistor,
RIS. The VISMON voltage is calculated as V(ISP-ISN) • 10 +
0.25V. Since the ISMON pin has the same 0.25V offset
as the CTRL pin, the master LT8390A ISMON pin can
be directly tied to the slave LT8390A CTRL pin for equal
current sharing in parallel applications.
RIS
FROM POWER
INPUT
+
ISN
ISP
LT8390A
8390a F13a
When VCTRL is larger than 1.35V, the current threshold
is regulated to:
IIS(MAX) =
100mV
RIS
(13a)
FROM POWER
INPUT
The CTRL pin should not be left open (tie to VREF if not
used). The CTRL pin can also be used in conjunction with
a thermistor to provide overtemperature protection for
the output load, or with a resistor divider to VIN to reduce
output power and switching current when VIN is low.
The presence of a time varying differential voltage ripple
signal across the ISP and ISN pins at the switching
22
TO DRAIN OF
SWITCH A
RIS
+
RF
CF
TO DRAIN OF
SWITCH A
RF
ISN
ISP
LT8390A
8390a F13b
(13b)
Figure 13. Programming Input Current Limit
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FROM DRAIN OF
SWITCH D
RIS
TO SYSTEM
OUTPUT
+
ISN
ISP
LT8390A
Programming Output Voltage and Thresholds
The LT8390A has a voltage feedback pin FB that can be
used to program a constant-voltage output. The output
voltage can be set by selecting the values of R3 and R4
(Figure 15) according to the following equation:
VOUT = 1V •
8390a F14a
(14a)
RIS
FROM DRAIN OF
SWITCH D
RF
CF
RF
+
TO SYSTEM
OUTPUT
R3+R4
R4
In addition, the FB pin also sets output overvoltage
threshold, output power good thresholds, and output
short threshold. For an application with small output
capacitors, the output voltage may overshoot a lot during
VOUT
ISN
ISP
LT8390A
R3
LT8390A
FB
8390a F14b
R4
(14b)
8390a F15
Figure 14. Programming Output Current Limit
Load Switch Control
The LOADEN and LOADTG pins provide high side PMOS
load switch control. The LOADEN pin accepts a logic level
ON/OFF signal and then drives the LOADTG pin to turn on
or off the high side PMOS load switch, thereby connecting or disconnecting the LT8390A power output from the
system output. When the LOADEN pin is forced low, the
LT8390A turns off TG1 and TG2, turns on BG1 and BG2,
disconnects the VC pin from all internal loads, and turns
off LOADTG. The LOADEN pin should not be left open (tie
to INTVCC or VREF if not used).
High Side PMOS Load Switch Selection
A high side PMOS load switch is recommended in some
LT8390A applications requiring load switch control. The
high side PMOS load switch is typically selected for drainsource voltage VDS, gate-source threshold voltage VGS(TH),
and continuous drain current ID. For proper operations,
VDS rating should exceed the output regulation voltage
set by the FB pin, the absolute value of VGS(TH) should
be less than 3V, and ID rating should be above IOUT(MAX).
Figure 15. Feedback Resistor Connection
load transient event. Once the FB pin hits its overvoltage
threshold 1.1V, the LT8390A stops switching by turning
off TG1, BG1, TG2, and BG2, and also turns off LOADTG
to disconnect the output load for protection. The output
overvoltage threshold can be set as:
VOUT(OVP) = 1.1V •
R3+R4
R4
To provide the output short-circuit detection and protection,
the output short falling threshold can be set as:
VOUT(SHORT) = 0.25V •
R3+R4
R4
Power GOOD (PGOOD) Pin
The LT8390A provides an open-drain status pin, PGOOD,
which is pulled low when VFB is within ±10% of the 1.00V
regulation voltage. The PGOOD pin is allowed to be pulled
up by an external resistor to INTVCC or an external voltage
source of up to 6V.
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LT8390A
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Soft-Start and Short-Circuit Protection
As shown in Figure 8 and explained in the Operation section, the SS pin can be used to program the output voltage
soft-start by connecting an external capacitor from the SS
pin to ground. The internal 12.5µA pull-up current charges
up the capacitor, creating a voltage ramp on the SS pin.
As the SS pin voltage rises linearly from 0.25V to 1V (and
beyond), the output voltage rises smoothly into its final
voltage regulation. The soft-start time can be calculated as:
tSS = 1V •
CSS
12.5µA
Make sure the CSS is at least five to ten times larger than the
compensation capacitor on the VC pin for a well-controlled
output voltage soft-start. A 22nF ceramic capacitor is a
good starting point.
The SS pin is also used as a fault timer. Once an output
short-circuit fault is detected, a 1.25µA pull-down current
source is activated. Using a single resistor from the SS pin
to the VREF pin, the LT8390A can be set to three different
fault protection modes: hiccup (no resistor), latch-off
(499k), and keep-running (100k).
With a 100k resistor in keep-running mode, the LT8390A
continues switching normally and regulates the current
into ground. With a 499k resistor in latch-off mode, the
LT8390A stops switching until the EN/UVLO pin is pulled
low and high to restart. With no resistor in hiccup mode,
the LT8390A enters low duty cycle auto-retry operation.
The 1.25µA pull-down current discharges the SS pin to
0.2V and then 12.5µA pull-up current charges the SS
pin up. If the output short-circuit condition has not been
removed when the SS pin reaches 1.75V, the 1.25µA
pull-down current turns on again, initiating a new hiccup
cycle. This will continue until the fault is removed. Once
the output short-circuit condition is removed, the output
will have a smooth short-circuit recovery due to soft-start.
Loop Compensation
The LT8390A uses an internal transconductance error
amplifier, the output of which, VC, compensates the con-
24
trol loop. The external inductor, output capacitor, and the
compensation resistor and capacitor determine the loop
stability.
The inductor and output capacitor are chosen based on
performance, size and cost. The compensation resistor
and capacitor on the VC pin are set to optimize control
loop response and stability. For a typical voltage regulator
application, a 2.2nF compensation capacitor on the VC pin
is adequate, and a series resistor should always be used
to increase the slew rate on the VC pin to maintain tighter
output voltage regulation during fast transients on the
input supply of the converter.
Efficiency Considerations
The power efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Although all dissipative
elements in circuits produce losses, four main sources
account for most of the losses in LT8390A circuits:
1. DC I2R losses. These arise from the resistances of the
MOSFETs, sensing resistor, inductor and PC board
traces and cause the efficiency to drop at high output
currents.
2. Transition loss. This loss arises from the brief amount
of time switch A or switch C spends in the saturated
region during switch node transitions. It depends upon
the input voltage, load current, driver strength and
MOSFET capacitance, among other factors.
3. INTVCC current. This is the sum of the MOSFET driver
and control currents.
4. CIN and COUT loss. The input capacitor has the difficult job of filtering the large RMS input current to the
regulator in buck region. The output capacitor has the
difficult job of filtering the large RMS output current in
boost region. Both CIN and COUT are required to have
low ESR to minimize the AC I2R loss and sufficient
capacitance to prevent the RMS current from causing
additional upstream losses in fuses or batteries.
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5. Other losses. Schottky diode DB and DD are responsible
for conduction losses during dead time and light load
conduction periods. Inductor core loss occurs predominately at light loads. Switch A causes reverse recovery
current loss in buck region, and switch C causes reverse
recovery current loss in boost region.
When making adjustments to improve efficiency, the
input current is the best indicator of changes in efficiency. If you make a change and the input current
decreases, then the efficiency has increased. If there is
no change in the input current, then there is no change
in efficiency.
PC Board Layout Checklist
n
n
n
n
n
The basic PC board layout requires a dedicated ground
plane layer. Also, for high current, a multilayer board
provides heat sinking for power components.
n
n
n
n
n
n
The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.
Place CIN, switch A, switch B and DB in one compact
area. Place COUT, switch C, switch D and DD in one
compact area.
n
n
Use immediate vias to connect the components to the
ground plane. Use several large vias for each power
component.
Use planes for VIN and VOUT to maintain good voltage
filtering and to keep power losses low.
Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. Connect the copper areas to any DC net
(VIN or GND).
Separate the signal and power grounds. All small-signal
components should return to the exposed GND pad
from the bottom, which is then tied to the power GND
close to the sources of switch B and switch C.
n
n
Place switch A and switch C as close to the controller as
possible, keeping the PGND, BG and SW traces short.
Keep the high dV/dT SW1, SW2, BST1, BST2, TG1 and
TG2 nodes away from sensitive small-signal nodes.
The path formed by switch A, switch B, DB and the
CIN capacitor should have short leads and PCB trace
lengths. The path formed by switch C, switch D, DD and
the COUT capacitor also should have short leads and
PCB trace lengths.
The output capacitor (–) terminals should be connected
as close as possible to the (–) terminals of the input
capacitor.
Connect the top driver bootstrap capacitor CBST1 closely
to the BST1 and SW1 pins. Connect the top driver
bootstrap capacitor CBST2 closely to the BST2 and SW2
pins.
Connect the input capacitors CIN and output capacitors
COUT closely to the power MOSFETs. These capacitors
carry the MOSFET AC current.
Route LSP and LSN traces together with minimum
PCB trace spacing. Avoid sense lines pass through
noisy areas, such as switch nodes. The filter capacitor
between LSP and LSN should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connections at the RSENSE resistor. Low ESL sense
resistor is recommended.
Connect the VC pin compensation network close to the
IC, between VC and the signal ground. The capacitor
helps to filter the effects of PCB noise and output voltage ripple voltage from the compensation loop.
Connect the INTVCC bypass capacitor, CINTVCC, close to
the IC, between the INTVCC and the power ground. This
capacitor carries the MOSFET drivers’ current peaks.
8390afa
For more information www.linear.com/LT8390A
25
LT8390A
TYPICAL APPLICATIONS
95% Efficient 48W (12V 4A) 2MHz Buck-Boost Voltage Regulator
VIN
6V TO 28V
CONTINUOUS
4V TO 56V
TRANSIENT
22µF
63V
4.7µF
100V
×2
L1
1µH
R1
5mΩ
M1
0.1µF
0.1µF
100V
×2
SW1 LSP
BST1
LSN
0.1µF
SW2
BST2
0.1µF
16V
×2
D2
D1
INTVCC
M2
R2
10mΩ
M4
BG1
BG2
INTVCC
22µF
16V
×2
22µF
16V
VOUT
12V
4A
M3
GND
TG1
VIN
TG2
LT8390A
VOUT
1µF
383k
169k
1µF
EN/UVLO
ISP
LOADTG
ISN
TEST
ISMON
133k
0.47µF
SSFM OFF
SYNC/SPRD
CTRL
100k
1µF 10
FB
ISMON
INTVCC
INTVCC
4.7µF
LOADEN
VREF
SS
22nF
PGOOD
RT
VC
10k
10
10k
SSFM ON
100k
PGOOD
59.0k
2MHz
110k
L1: WURTH 74437336010 1µH
M1, M2: INFINEON BSZ065NO6LS5
M3, M4: INFINEON BSZ033NE2LS5
D1, D2: NXP BAT46WJ
R1: Susumu KRL3216D-M-R005-F-T5
2.2nF
8390a TA02a
26
8390afa
For more information www.linear.com/LT8390A
LT8390A
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LT8390A#packaging for the most recent package drawings.
FE Package
28-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev L)
Exposed Pad Variation EB
9.60 – 9.80*
(.378 – .386)
4.75
(.187)
4.75
(.187)
28 27 26 2524 23 22 21 20 1918 17 16 15
6.60 ±0.10
4.50 ±0.10
2.74
(.108)
SEE NOTE 4
0.45 ±0.05
EXPOSED
PAD HEAT SINK
ON BOTTOM OF
PACKAGE
6.40
2.74
(.252)
(.108)
BSC
1.05 ±0.10
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.25
REF
1.20
(.047)
MAX
0° – 8°
0.65
(.0256)
BSC
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN MILLIMETERS
(INCHES)
3. DRAWING NOT TO SCALE
1 2 3 4 5 6 7 8 9 10 11 12 13 14
0.195 – 0.30
(.0077 – .0118)
TYP
0.05 – 0.15
(.002 – .006)
FE28 (EB) TSSOP REV L 0117
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
8390afa
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27
LT8390A
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LT8390A#packaging for the most recent package drawings.
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev C)
0.70 ±0.05
4.50 ±0.05
3.10 ±0.05
2.50 REF
2.65 ±0.05
3.65 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
3.50 REF
4.10 ±0.05
5.50 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ±0.10
(2 SIDES)
0.75 ±0.05
R = 0.05
TYP
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
2.50 REF
R = 0.115
TYP
27
28
0.40 ±0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 ±0.10
(2 SIDES)
3.50 REF
3.65 ±0.10
2.65 ±0.10
(UFD28) QFN 0816 REV C
0.200 REF
0.00 – 0.05
0.25 ±0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGHD-3).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
28
8390afa
For more information www.linear.com/LT8390A
LT8390A
REVISION HISTORY
REV
DATE
DESCRIPTION
A
09/17
Added H-Grade Temperature Option
PAGE NUMBER
2, 5
Clarified Block Diagram
11
Clarified Sense Resistors descriptiion in Route LSP and LSN traces bullet
25
8390afa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LT8390A
29
LT8390A
TYPICAL APPLICATION
25W (5V 5A) 2MHz Buck-Boost Voltage Regulator
VIN
4.5V TO 20V
CONTINUOUS
4V TO 56V
TRANSIENT
22µF
63V
0.1µF
0.1µF
100V
×2
L1
0.33µH
R1
5mΩ
M1
SW1 LSP
BST1
LSN
0.1µF
SW2
BST2
INTVCC
M2
0.1µF
10V
×2
D2
D1
4.7µF
100V
×2
R2
10mΩ
M4
BG1
BG2
INTVCC
VOUT
5V
5A
47µF
10V
×2
47µF
10V
M3
GND
TG1
VIN
TG2
LT8390A
VOUT
1µF
383k
169k
1µF
EN/UVLO
ISP
LOADTG
ISN
TEST
ISMON
95.3k
0.47µF
INTVCC
INTVCC
4.7µF
LOADEN
VREF
SS
22nF
PGOOD
RT
VC
11k
40.2k
SSFM OFF
SYNC/SPRD
CTRL
105k
1µF 10Ω
FB
ISMON
10Ω
59k
2MHz
10k
SSFM ON
100k
PGOOD
L1: COILCRAFT XEL4020-331ME 0.33µH
M1, M2: INFINEON BSZ034N04LS
M3, M4: INFINEON BSZ033NE2LS5
D1, D2: NXP BAT46WJ
R1: SUSUMU KRL3216D-M-R005-F-T5
2.2nF
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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60V Synchronous 4-Switch Buck-Boost Controller
with Spread Spectrum
VIN: 4V to 60V, VOUT: 0V to 60V, ±1.5% Voltage Accuracy, ±3% Current
Accuracy, TSSOP-28 and 4mm × 5mm QFN-28
LT8391
60V Synchronous 4-Switch Buck-Boost LED
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VIN: 4V to 60V, VOUT: 0V to 60V, ±1.5% Voltage Accuracy, ±3% Current
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LT8391A
60V Synchronous 2MHz 4-Switch Buck-Boost LED
Controller with Spread Spectrum
VIN: 4V to 60V, VOUT: 0V to 60V, ±1.5% Voltage Accuracy, ±3% Current
Accuracy, TSSOP-28 and 4mm × 5mm QFN-28
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60V Synchronous 4-Switch Buck-Boost Controller
VIN: 4.7V to 60V, VOUT: 1.2V to 60V, Regulates VOUT, IOUT, IIN, TSSOP-38
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5mm × 7mm QFN-38 and Modified TSSOP-38 for High Voltage
LTC®3789
High Efficiency Synchronous 4-Switch Buck-Boost
Controller
VIN: 4V to 38V, VOUT: 0.8V to 38V, Regulates VOUT, IOUT or IIN, 5mm × 5mm
QFN-32 and SSOP-24
LTC3780
High Efficiency Synchronous 4-Switch Buck-Boost
Controller
VIN: 4V to 36V, VOUT: 0.8V to 30V, Regulates VOUT, 4mm × 5mm QFN-28 and
SSOP-28
LT3763
60V High Current Step-Down LED Driver Controller
VIN: 6V to 60V, 4mm × 4mm QFN-20 and TSSOP-20
LT3757/LT3757A
Boost, Flyback, SEPIC and Inverting Controller
VIN: 2.9V to 40V, Positive or Negative VOUT, 3mm × 3mm DFN-10, MSOP-10
LT3758
High Input Voltage, Boost, Flyback, SEPIC and
Inverting Controller
VIN: 5.5V to 100V, Positive or Negative VOUT, 3mm × 3mm DFN-10, MSOP-10
LT8710
Synchronous SEPIC/Inverting/Boost Controller with
Output Current Control
VIN: 4.5V to 80V, Rail-to-Rail Output Current Monitor and Control, TSSOP-28
30
8390afa
LT 0917 REV A • PRINTED IN USA
For more information www.linear.com/LT8390A
www.linear.com/LT8390A
 LINEAR TECHNOLOGY CORPORATION 2017