Fujitsu MBM29SL160BD-10PBT 16m (2m x 8/1m x 16) bit Datasheet

FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20877-1E
FLASH MEMORY
CMOS
16M (2M × 8/1M × 16) BIT
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
■ FEATURES
• Single 1.8 V read, program, and erase
Minimizes system level power requirements
• Compatible with JEDEC-standard commands
Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
48-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
48-ball FBGA (Package suffix: PBT)
• Minimum 100,000 program/erase cycles
• High performance
100 ns maximum access time
• Sector erase architecture
Eight 4K word and thirty one 32K word sectors in word mode
Eight 8K byte and thirty one 64K byte sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
T = Top sector
B = Bottom sector
• One Time Protect (OTP) region
256 Byte of OTP, accessible through a new “OTP Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC input pin
At VIL, allows protection of boot sectors, regardless of sector protection/unprotection status
At VIH, allows removal of boot sector protection
At VHH, increases program performance
• Embedded EraseTM Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
(Continued)
Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
(Continued)
• Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode.
• Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
• Sector group protection
Hardware method disables any combination of sector groups from program or erase operations
• Sector Group Protection Set function by Extended sector group protection command
• Fast Programming Function by Extended Command
• Temporary sector group unprotection
Temporary sector group unprotection via the RESET pin.
• In accordance with CFI (Common Flash Memory Interface)
■ PACKAGE
48-pin plastic TSOP (I)
48-pin plastic TSOP (I)
Marking Side
Marking Side
(FPT-48P-M19)
(FPT-48P-M20)
48-ball FBGA
(BGA-48P-M13)
2
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
■ GENERAL DESCRIPTION
The MBM29SL160TD/BD are a 16M-bit, 1.8 V-only Flash memory organized as 2M bytes of 8 bits each or 1M
words of 16 bits each. The MBM29SL160TD/BD are offered in a 48-pin TSOP(I) and 48-ball FBGA Package.
These devices are designed to be programmed in-system with the standard system 1.8 V VCC supply. 12.0 V
VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in
standard EPROM programmers.
The standard MBM29SL160TD/BD offer access times 100 ns and 120 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE),
write enable (WE), and output enable (OE) controls.
The MBM29SL160TD/BD are pin and command set compatible with JEDEC standard E2PROMs. Commands
are written to the command register using standard microprocessor write timings. Register contents serve as
input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and erase operations. Reading data out of the devices
is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The MBM29SL160TD/BD are programmed by executing the program command sequence. This will invoke the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.7 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before executing the erase operation. During erase, the devices automatically time the erase pulse widths and
verify proper cell margin.
A sector is typically erased and verified in 1.5 second. (If already completely preprogrammed.)
The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29SL160TD/BD are erased when shipped from the
factory.
The devices feature single 1.8 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low VCC detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,
by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been
completed, the devices internally reset to the read mode.
Fujitsu’s Flash technology combines years of EPROM and E2PROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The MBM29SL160TD/BD memories electrically erase the entire chip
or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one
byte/word at a time using the EPROM programming mechanism of hot electron injection.
3
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
Table 1 .1
Sector Address Tables (MBM29SL160TD)
Sector Address
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
A19 A18 A17 A16 A15 A14 A13 A12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
0
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
0
1
0
1
Sector
Size
(Kbytes/
Kwords)
(×8)
Address Range
(×16)
Address Range
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
000000H to 00FFFFH
010000H to 01FFFFH
020000H to 02FFFFH
030000H to 03FFFFH
040000H to 04FFFFH
050000H to 05FFFFH
060000H to 06FFFFH
070000H to 07FFFFH
080000H to 08FFFFH
090000H to 09FFFFH
0A0000H to 0AFFFFH
0B0000H to 0BFFFFH
0C0000H to 0CFFFFH
0D0000H to 0DFFFFH
0E0000H to 0EFFFFH
0F0000H to 0FFFFFH
100000H to 10FFFFH
110000H to 11FFFFH
120000H to 12FFFFH
130000H to 13FFFFH
140000H to 14FFFFH
150000H to 15FFFFH
160000H to 16FFFFH
170000H to 17FFFFH
180000H to 18FFFFH
190000H to 19FFFFH
1A0000H to 1AFFFFH
1B0000H to 1BFFFFH
1C0000H to 1CFFFFH
1D0000H to 1DFFFFH
1E0000H to 1EFFFFH
1F0000H to 1F1FFFH
1F2000H to 1F3FFFH
1F4000H to 1F5FFFH
1F6000H to 1F7FFFH
1F8000H to 1F9FFFH
1FA000H to 1FBFFFH
1FC000H to 1FDFFFH
1FE000H to 1FFFFFH
000000H to 007FFFH
008000H to 00FFFFH
010000H to 017FFFH
018000H to 01FFFFH
020000H to 027FFFH
028000H to 02FFFFH
030000H to 037FFFH
038000H to 03FFFFH
040000H to 048000H
048000H to 04FFFFH
050000H to 058000H
058000H to 05FFFFH
060000H to 068000H
068000H to 06FFFFH
070000H to 078FFFH
078000H to 07FFFFH
080000H to 088000H
088000H to 08FFFFH
090000H to 098000H
098000H to 09FFFFH
0A0000H to 0A7FFFH
0A8000H to 00AFFFH
0B0000H to 0B7000H
0B8000H to 0BFFFFH
0C0000H to 0C7FFFH
0C8000H to 0CFFFFH
0D0000H to 0D7FFFH
0D8000H to 0DFFFFH
0E0000H to 0E7FFFH
0E8000H to 0EFFFFH
0F0000H to 0F7000H
0F8000H to 0F8FFFH
0F9000H to 0F9FFFH
0FA000H to 0FAFFFH
0FB000H to 0FBFFFH
0FC000H to 0FCFFFH
0FD000H to 0FDFFFH
0FE000H to 0FEFFFH
0FF000H to 0FFFFFH
Note: The address range is A19: A-1 if in byte mode (BYTE = VIL).
The address range is A19: A0 if in word mode (BYTE = VIH)
4
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
Table 1 .2
Sector Address Tables (MBM29SL160BD)
Sector Address
Sector
SA38
SA37
SA36
SA35
SA34
SA33
SA32
SA31
SA30
SA29
SA28
SA27
SA26
SA25
SA24
SA23
SA22
SA21
SA20
SA19
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
A19 A18 A17 A16 A15 A14 A13 A12
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
1
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
0
0
1
1
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
1
0
1
0
1
0
Sector
Size
(Kbytes/
Kwords)
(×8)
Address Range
(×16)
Address Range
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
1F0000H to 1FFFFFH
1E0000H to 1EFFFFH
1D0000H to 1DFFFFH
1C0000H to 1CFFFFH
1B0000H to 1BFFFFH
1A0000H to 1AFFFFH
190000H to 19FFFFH
180000H to 18FFFFH
170000H to 17FFFFH
160000H to 16FFFFH
150000H to 15FFFFH
140000H to 14FFFFH
130000H to 13FFFFH
120000H to 12FFFFH
110000H to 11FFFFH
100000H to 10FFFFH
0F0000H to 0FFFFFH
0E0000H to 0EFFFFH
0D0000H to 0DFFFFH
0C0000H to 0CFFFFH
0B0000H to 0BFFFFH
0A0000H to 0AFFFFH
090000H to 0FFFFFH
080000H to 08FFFFH
070000H to 07FFFFH
060000H to 06FFFFH
050000H to 05FFFFH
040000H to 04FFFFH
030000H to 03FFFFH
020000H to 02FFFFH
010000H to 01FFFFH
00E000H to 00FFFFH
00C000H to 00DFFFH
00A000H to 00BFFFH
008000H to 009FFFH
006000H to 007FFFH
004000H to 005FFFH
002000H to 003FFFH
000000H to 001FFFH
0F8000H to 0FFFFFH
0F0000H to 0F7FFFH
0E8000H to 0EFFFFH
0E0000H to 0E7FFFH
0D8000H to 0DFFFFH
0D0000H to 0D7FFFH
0C8000H to 0CFFFFH
0C0000H to 0C7FFFH
0B8000H to 0BFFFFH
0B0000H to 0B7FFFH
0A8000H to 0AFFFFH
0A0000H to 0A7FFFH
098000H to 09FFFFH
090000H to 097FFFH
088000H to 08FFFFH
080000H to 087FFFH
078000H to 07FFFFH
070000H to 077FFFH
068000H to 06FFFFH
060000H to 067FFFH
058000H to 05FFFFH
050000H to 057FFFH
048000H to 04FFFFH
040000H to 047FFFH
038000H to 03FFFFH
030000H to 037FFFH
028000H to 02FFFFH
020000H to 027FFFH
018000H to 01FFFFH
010000H to 017FFFH
008000H to 008FFFH
007000H to 007FFFH
006000H to 006FFFH
005000H to 005FFFH
004000H to 004FFFH
003000H to 003FFFH
002000H to 002FFFH
001000H to 001FFFH
000000H to 000FFFH
Note: The address range is A19: A-1 if in byte mode (BYTE = VIL).
The address range is A19: A0 if in word mode (BYTE = VIH).
5
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
Table 2 .1
Sector Group
A19
A18
A17
A16
A15
A14
A13
A12
Sectors
SGA0
0
0
0
0
0
X
X
X
SA0
0
0
0
0
1
X
X
X
0
0
0
1
0
X
X
X
0
0
0
1
1
X
X
X
SGA2
0
0
1
X
X
X
X
X
SA4 to SA7
SGA3
0
1
0
X
X
X
X
X
SA8 to SA11
SGA4
0
1
1
X
X
X
X
X
SA12 to SA15
SGA5
1
0
0
X
X
X
X
X
SA16 to SA19
SGA6
1
0
1
X
X
X
X
X
SA20 to SA23
SGA7
1
1
0
X
X
X
X
X
SA24 to SA27
1
1
1
0
0
X
X
X
1
1
1
0
1
X
X
X
1
1
1
1
0
X
X
X
SGA9
1
1
1
1
1
0
0
0
SA31
SGA10
1
1
1
1
1
0
0
1
SA32
SGA11
1
1
1
1
1
0
1
0
SA33
SGA12
1
1
1
1
1
0
1
1
SA34
SGA13
1
1
1
1
1
1
0
0
SA35
SGA14
1
1
1
1
1
1
0
1
SA36
SGA15
1
1
1
1
1
1
1
0
SA37
SGA16
1
1
1
1
1
1
1
1
SA38
SGA1
SGA8
6
Sector Group Addresses (MBM29SL160TD)
(Top Boot Block)
SA1 to SA3
SA28 to SA30
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
Table 2 .2
Sector Group Addresses (MBM29SL160BD)
(Bottom Boot Block)
Sector Group
A19
A18
A17
A16
A15
A14
A13
A12
Sectors
SGA0
0
0
0
0
0
0
0
0
SA0
SGA1
0
0
0
0
0
0
0
1
SA1
SGA2
0
0
0
0
0
0
1
0
SA2
SGA3
0
0
0
0
0
0
1
1
SA3
SGA4
0
0
0
0
0
1
0
0
SA4
SGA5
0
0
0
0
0
1
0
1
SA5
SGA6
0
0
0
0
0
1
1
0
SA6
SGA7
0
0
0
0
0
1
1
1
SA7
0
0
0
0
1
X
X
X
0
0
0
1
0
X
X
X
0
0
0
1
1
X
X
X
SGA9
0
0
1
X
X
X
X
X
SA11 to SA14
SGA10
0
1
0
X
X
X
X
X
SA15 to SA18
SGA11
0
1
1
X
X
X
X
X
SA19 to SA22
SGA12
1
0
0
X
X
X
X
X
SA23 to SA26
SGA13
1
0
1
X
X
X
X
X
SA27 to SA30
SGA14
1
1
0
X
X
X
X
X
SA31 to SA34
1
1
1
0
0
X
X
X
1
1
1
0
1
X
X
X
1
1
1
1
0
X
X
X
1
1
1
1
1
X
X
X
SGA8
SGA15
SGA16
SA8 to SA10
SA35 to SA37
SA38
7
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
■ PRODUCT LINE UP
Part No.
Ordering Part No.
MBM29SL160TD/MBM29SL160BD
VCC = 2.0 V±0.2V
-10
-12
Max. Address Access Time (ns)
100
120
Max. CE Access Time (ns)
100
120
Max. OE Access Time (ns)
35
50
■ BLOCK DIAGRAM
RY/BY
Buffer
DQ 0 to DQ 15
RY/BY
V CC
V SS
Erase Voltage
Generator
Input/Output
Buffers
WE
BYTE
State
Control
RESET
WP/ACC
Command
Register
Program Voltage
Generator
Chip Enable
Output Enable
Logic
CE
OE
STB
Low V CC Detector
A0 to A19
A-1
8
Timer for
Program/Erase
Address
Latch
STB
Data Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
■ CONNECTION DIAGRAMS
TSOP(I)
A15
A14
A13
A12
A11
A10
A9
A8
A19
N.C.
WE
RESET
NC
WP/ACC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
(Marking Side)
MBM29SL160TD/MBM29SL160BD
Standard Pinout
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
VSS
DQ 15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
VSS
CE
A0
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
A0
CE
VSS
OE
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
VCC
DQ4
DQ12
DQ5
DQ13
DQ6
DQ14
DQ7
DQ15/A-1
VSS
BYTE
A16
FPT-48P-M19
A1
A2
A3
A4
A5
A6
A7
A17
A18
RY/BY
WP/ACC
N.C.
RESET
WE
N.C.
A19
A8
A9
A10
A11
A12
A13
A14
A15
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
(Marking Side)
MBM29SL160TD/MBM29SL160BD
Reverse Pinout
FPT-48P-M20
9
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
(Continued)
FBGA
(TOP VIEW)
Marking side
A1
A2
A3
A4
A5
A6
B1
B2
B3
B4
B5
B6
C1
C2
C3
C4
C5
C6
D1
D2
D3
D4
D5
D6
E1
E2
E3
E4
E5
E6
F1
F2
F3
F4
F5
F6
G1
G2
G3
G4
G5
G6
H1
H2
H3
H4
H5
H6
(BGA-48P-M03)
10
A1
A3
A2
A7
A3
RY/BY
B1
A4
B2
A17
B3
C1
A2
C2
A6
D1
A1
D2
E1
A0
F1
A4
WE
A5
A9
A6
A13
WP/ACC B4
RESET
B5
A8
B6
A12
C3
A18
C4
N.C.
C5
A10
C6
A14
A5
D3
N.C.
D4
A19
D5
A11
D6
A15
E2
DQ0
E3
DQ2
E4
DQ5
E5
DQ7
E6
A16
CE
F2
DQ8
F3
DQ10
F4
DQ12
F5
DQ14
F6
BYTE
G1
OE
G2
DQ9
G3
DQ11
G4
VCC
G5
DQ13
G6
DQ15/A-1
H1
VSS
H2
DQ1
H3
DQ3
H4
DQ4
H5
DQ6
H6
VSS
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
■ LOGIC SYMBOL
Table 3 MBM29SL160TD/BD Pin Configuration
Pin
A–1
20
16 or 8
A0 to A19
DQ0 to DQ15
CE
OE
WE
RESET
BYTE
Function
A-1, A0 to A19
Address Inputs
DQ0 to DQ15
Data Inputs/Outputs
CE
Chip Enable
OE
Output Enable
WE
Write Enable
RY/BY
Ready/Busy Output
RESET
Hardware Reset Pin/Temporary Sector
Group Unprotection
RY/BY
WP/ACC
BYTE
WP/ACC
Selects 8-bit or 16-bit mode
Hardware Write Protection/Program
Acceleration
N.C.
No Internal Connection
VSS
Device Ground
VCC
Device Power Supply
11
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
Table 4 MBM29SL160TD/BD User Bus Operations (BYTE = VIH)
Operation
CE OE WE
A0
A1
A6
A9
DQ0 to DQ15 RESET WP/ACC
Auto-Select Manufacturer Code (1)
L
L
H
L
L
L
VID
Code
H
X
Auto-Select Device Code (1)
L
L
H
H
L
L
VID
Code
H
X
Read (3)
L
L
H
A0
A1
A6
A9
DOUT
H
X
Standby
H
X
X
X
X
X
X
HIGH-Z
H
X
Output Disable
L
H
H
X
X
X
X
HIGH-Z
H
X
Write (Program/Erase)
L
H
L
A0
A1
A6
A9
DIN
H
X
Enable Sector Group Protection (2), (4)
L
VID
L
H
L
VID
X
H
X
Verify Sector Group Protection (2), (4)
L
L
H
L
H
L
VID
Code
H
X
Temporary Sector Group Unprotection (5)
X
X
X
X
X
X
X
X
VID
X
Reset (Hardware)/Standby
X
X
X
X
X
X
X
HIGH-Z
L
X
Boot Block Sector Write Protection
X
X
X
X
X
X
X
X
X
L
Table 5 MBM29SL160TD/BD User Bus Operations (BYTE = VIL)
Operation
15/
CE OE WE DQ
A-1 A0
A1
A6
A9
DQ0 to DQ7 RESET WP/ACC
Auto-Select Manufacturer Code (1)
L
L
H
L
L
L
L
VID
Code
H
X
Auto-Select Device Code (1)
L
L
H
L
H
L
L
VID
Code
H
X
Read (3)
L
L
H
A-1
A0
A1
A6
A9
DOUT
H
X
Standby
H
X
X
X
X
X
X
X
HIGH-Z
H
X
Output Disable
L
H
H
X
X
X
X
X
HIGH-Z
H
X
Write (Program/Erase)
L
H
L
A-1
A0
A1
A6
A9
DIN
H
X
Enable Sector Group Protection
(2), (4)
L
VID
L
L
H
L
VID
X
H
X
Verify Sector Group Protection
(2), (4)
L
L
H
L
L
H
L
VID
Code
H
X
Temporary Sector Group
Unprotection (5)
X
X
X
X
X
X
X
X
X
VID
X
Reset (Hardware)/Standby
X
X
X
X
X
X
X
X
HIGH-Z
L
X
Boot Block Sector Write Protection
X
X
X
X
X
X
X
X
X
X
L
Legend: L = VIL, H = VIH, X = VIL or VIH,
= Pulse input. See DC Characteristics for voltage levels.
Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. See
Table 7.
2. Refer to the section on Sector Group Protection.
3. WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
4. VCC = 2.0 V ± 10%
5. It is also used for the extended sector group protection.
12
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
■ FUNCTIONAL DESCRIPTION
Read Mode
The MBM29SL160TD/BD have two control functions which must be satisfied in order to obtain data at the outputs.
CE is the power control and should be used for a device selection. OE is the output control and should be used
to gate data to the output pins if a device is selected.
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable
access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output
enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the
addresses have been stable for at least tACC-tOE time.) When reading out a data without changing addresses after
power-up, it is necessary to input hardware reset or to change CE pin from “H” to “L”
Standby Mode
There are two ways to implement the standby mode on the MBM29SL160TD/BD devices, one using both the
CE and RESET pins; the other via the RESET pin only.
When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC ± 0.3 V.
Under this condition the current consumed is less than 5 µA max. During Embedded Algorithm operation, VCC
active current (ICC2) is required even CE = “H”. The device can be read with standard access time (tCE) from either
of these standby modes.
When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS ± 0.3 V (CE
= “H” or “L”). Under this condition the current is consumed is less than 5 µA max. Once the RESET pin is taken
high, the device requires tRH of wake up time before outputs are valid for read access.
In the standby mode the outputs are in the high impedance state, independent of the OE input.
Automatic Sleep Mode
There is a function called automatic sleep mode to restrain power consumption during read-out of
MBM29SL160TD/BD data. This mode can be used effectively with an application requested low power
consumption such as handy terminals.
To activate this mode, MBM29SL160TD/BD automatically switch themselves to low power mode when
MBM29SL160TD/BD addresses remain stably during access fine of 150 ns. It is not necessary to control CE,
WE, and OE on the mode. Under the mode, the current consumed is typically 1 µA (CMOS Level).
During simultaneous operation, VCC active current (ICC2) is required.
Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed,
the mode is canceled automatically and MBM29SL160TD/BD read-out the data for changed addresses.
Output Disable
With the OE input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins
to be in a high impedance state.
Autoselect
The autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer
and type. This mode is intended for use by programming equipment for the purpose of automatically matching
the devices to be programmed with its corresponding programming algorithm. This mode is functional over the
entire temperature range of the devices.
To activate this mode, the programming equipment must force VID (10 V to 11 V) on address pin A9. Two identifier
bytes may then be sequenced from the devices outputs by toggling address A0 from VIL to VIH. All addresses are
DON’T CARES except A0, A1, and A6 (A-1). (See Tables 4 and 5.)
13
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
The manufacturer and device codes may also be read via the command register, for instances when the
MBM29SL160TD/BD are erased or programmed in a system without access to high voltage on the A9 pin. The
command sequence is illustrated in Table 7. (Refer to Autoselect Command section.)
Word 0 (A0 = VIL) represents the manufacturer’s code (Fujitsu = 04H) and word 1 (A0 = VIH) represents the device
identifier code (MBM29SL160TD = E4H and MBM29SL160BD = E7H for ×8 mode; MBM29SL160TD = 22E4H
and MBM29SL160BD = 22E7H for ×16 mode). These two bytes/words are given in the tables 6.1 to 6.2. All
identifiers for manufactures and device will exhibit odd parity with DQ7 defined as the parity bit. In order to read
the proper device codes when executing the autoselect, A1 must be VIL. (See Tables 6.1 to 6.2.)
Table 6 .1
MBM29SL160TD/BD Sector Group Protection Verify Autoselect Codes
Type
A12 to A19
A6
A1
A0
A-1*1
Code (HEX)
X
VIL
VIL
VIL
VIL
04H
VIL
E4H
X
VIL
VIL
VIH
X
22E4H
VIL
E7H
X
22E7H
VIL
01H*2
Manufacture’s Code
Byte
MBM29SL160TD
Word
Device
Code
Byte
MBM29SL160BD
X
VIL
VIL
VIH
Word
Sector Group
Addresses
Sector Group Protection
VIH
VIL
VIL
*1: A-1 is for Byte mode.
*2: Outputs 01H at protected sector group addresses and outputs 00H at unprotected sector group addresses.
Table 6 .2
Type
Code
Manufacturer’s Code
04H
(B)
Expanded Autoselect Code Table
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
0
0
0
0
0
1
0
0
E4H A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
E7H A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 1
1
1
0
0
1
1
1
A-1/0
0
0
0
0
0
0
0
MBM29SL160TD
(W) 22E4H 0
Device
Code
(B)
0
1
0
0
0
1
0
MBM29SL160BD
(W) 22E7H 0
Sector Group Protection
(B): Byte mode
(W): Word mode
14
01H
A-1/0
0
1
0
0
0
1
0
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
Write
Device erasure and programming are accomplished via the command register. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the function of the device.
The command register itself does not occupy any addressable memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The
command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on
the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,
whichever happens first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
Sector Group Protection
The MBM29SL160TD/BD feature hardware sector group protection. This feature will disable both program and
erase operations in any combination of seventeen sector groups of memory. (See Tables 2.1 and 2.2). The sector
group protection feature is enabled using programming equipment at the user’s site. The device is shipped with
all sector groups unprotected.
To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest
VID = 10V to 11V), CE = VIL and A0 = A6 = VIL, A1 = VIH. The sector group addresses (A19, A18, A17, A16, A15, A14,
A13, and A12) should be set to the sector to be protected. Tables 1.1 and 1.2 define the sector address for each
of the thirty nine (39) individual sectors, and tables 2.1 and 2.2 define the sector group address for each of the
seventeen (17) individual group sectors. Programming of the protection circuitry begins on the falling edge of
the WE pulse and is terminated with the rising edge of the same. Sector group addresses must be held constant
during the WE pulse. See figures 16 and 25 for sector group protection waveforms and algorithm.
To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9
with CE and OE at VIL and WE at VIH. Scanning the sector group addresses (A19, A18, A17, A16, A15, A14, A13, and
A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector.
Otherwise the device will produce “0” for unprotected sector. In this mode, the lower order addresses, except
for A0, A1, and A6 are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer
and device codes. A-1 requires to apply to VIL on byte mode.
It is also possible to determine if a sector group is protected in the system by writing an Autoselect command.
Performing a read operation at the address location XX02H, where the higher order addresses (A19, A18, A17,
A16, A15, A14, A13, and A12) are the desired sector group address will produce a logical “1” at DQ0 for a protected
sector group. See Tables 6.1 and 6.2 for Autoselect codes.
Temporary Sector Group Unprotection
This feature allows temporary unprotection of previously protected sector groups of the MBM29SL160TD/BD
devices in order to change data. The Sector Group Unprotection mode is activated by setting the RESET pin to
high voltage (VID). During this mode, formerly protected sector groups can be programmed or erased by selecting
the sector group addresses. Once the VID is taken away from the RESET pin, all the previously protected sector
groups will be protected again. Refer to Figures 17 and 26.
15
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
RESET
Hardware Reset
The MBM29SL160TD/BD devices may be reset by driving the RESET pin to VIL. The RESET pin has a pulse
requirement and has to be kept low (VIL) for at least “tRP” in order to properly reset the internal state machine.
Any operation in the process of being executed will be terminated and the internal state machine will be reset
to the read mode “tREADY” after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the
devices require an additional “tRH” before it will allow read access. When the RESET pin is low, the devices will
be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware
reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please
note that the RY/BY output signal should be ignored during the RESET pulse. See Figure 12 for the timing
diagram. Refer to Temporary Sector Group Unprotection for additional functionality.
Boot Block Sector Protection
The Write Protection function provides a hardware method of protecting certain boot sectors without using VID.
This function is one of two provided by the WP/ACC pin.
If the system asserts VIL on the WP/ACC pin, the device disables program and erase functions in the two
“outermost” 8K byte boot sectors independently of whether those sectors were protected or unprotected using
the method described in “Sector Protection/Unprotection”. The two outermost 8K byte boot sectors are the two
sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the
highest addresses in a top-boot-congfigured device.
(MBM29SL160TD: SA37 and SA38, MBM29SL160BD: SA0 and SA1)
If the system asserts VIH on the WP/ACC pin, the device reverts to whether the two outermost 8K byte boot
sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these two
sectors depends on whether they were last protected or unprotected using the method described in “Sector
protection/unprotection”.
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This is one of two functions provided
by the WP/ACC pin. This function is primarily intended to allow faster factory throughput by 50 percent.
If the system asserts VHH on this pin, the device automatically enters the after mentioned Fast mode, temporarily
unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program
operations. The system would use a two-cycle program command sequence as required by the Fast mode.
Removing VHH from the WP/ACC pin returns the device to normal operation.
If you use this function, please contact a Fujitsu representative for more information.
16
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
Table 7 MBM29SL160TD/BD Command Definitions
Command
Sequence
Read/Reset
Read/Reset
Autoselect
Program
Chip Erase
Sector Erase
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Erase Suspend
Erase Resume
Set to
Fast Mode
Word
Fast
Program *1
Word
Reset from
Fast Mode *1
Word
Extended
Sector Group
Protection *2
Query *3
Byte
Byte
Byte
Word
Byte
Word
Byte
OTP
Entry
Word
OTP
Program *4
Word
OTP
Exit *4
Word
Byte
Byte
Byte
Bus
Write
Cycles
Req’d
1
3
3
4
6
6
1
1
3
2
2
4
1
3
4
4
First Bus Second Bus Third Bus Fourth Bus
Fifth Bus
Sixth Bus
Write Cycle Write Cycle Write Cycle Read/Write
Write
Cycle
Write
Cycle
Cycle
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
XXXH F0H
555H
AAAH
555H
AAAH
555H
AAAH
555H
AAAH
555H
AAAH
XXXH
XXXH
555H
AAAH
XXXH
XXXH
XXXH
XXXH
AAH
AAH
AAH
AAH
AAH
B0H
30H
AAH
A0H
90H
XXXH 60H
55H
AAH
555H
AAAH
555H
AAAH
555H
AAAH
98H
—
2AAH
555H
2AAH
555H
2AAH
555H
2AAH
555H
2AAH
555H
—
—
2AAH
555H
PA
—
55H
55H
55H
55H
55H
—
—
55H
—
555H
AAAH
555H
AAAH
555H
AAAH
555H
AAAH
555H
AAAH
—
—
555H
AAAH
—
—
—
—
—
—
—
F0H
RA
RD
—
—
—
—
90H
—
—
—
—
—
—
A0H
PA
PD
—
—
—
—
555H
2AAH
555H
AAH
55H
10H
AAAH
555H
AAAH
555H
2AAH
80H
AAH
55H
SA
30H
AAAH
555H
—
—
—
—
—
—
—
—
—
—
—
—
—
—
80H
20H
—
—
—
—
—
—
PD
—
—
—
—
—
—
—
—
XXXH F0H
XXXH *5
—
—
—
—
—
—
—
—
SPA
60H
SPA
40H
SPA
SD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2AAH
555H
55H
88H
—
—
555H
AAAH
2AAH
555H
AAH
55H
A0H
PA
PD
555H
AAAH
2AAH
555H
AAH
55H
90H XXXH 00H
555H
AAAH
AAH
17
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
Notes: 1. Address bits A11 to A19 = X = “H” or “L” for all address commands except or Program Address (PA), Sector
Address (SA).
2. Bus operations are defined in Tables 4 and 5.
3. RA = Address of the memory location to be read
PA = Address of the memory location to be programmed
Addresses are latched on the falling edge of the write pulse.
SA = Address of the sector to be erased. The combination of A19, A18, A17, A16, A15, A14, A13, and A12 will
uniquely select any sector.
4. RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the falling edge of write pulse.
5. SPA = Sector group address to be protected. Set sector group address (SGA) and (A6, A1, A0) = (0, 1, 0).
SD = Sector group protection verify data. Output 01H at protected sector group addresses and output
00H at unprotected sector group addresses.
6. OTPA = Address of the OTP area
29SL160TD (Top Boot Type)
Word Mode: FFF7FH to FFFFFH
Byte Mode: 1FFEFFH to 1FFFFFH
29SL160BD (Bottom Boot Type) Word Mode: 00000H to 00080H
Byte Mode: 00000H to 00100H
*1: This command is valid while Fast Mode.
*2: This command is valid while RESET = VID.
*3: The valid addresses are A6 to A0.
*4: This command is valid while OTP mode.
*5: The data "00H" is also acceptable.
7. The system should generate the following address patterns:
Word Mode: 555H or 2AAH to addresses A0 to A10
Byte Mode: AAAH or 555H to addresses A–1 and A0 to A10
8. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
18
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
■ Command Definitions
Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing them in the improper sequence will reset the devices to the
read mode. Table 7 defines the valid register command sequences. Note that the Erase Suspend (B0H) and
Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Moreover both
Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that
commands are always written at DQ0 to DQ7 and DQ8 to DQ15 bits are ignored.
Read/Reset Command
In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to Read/Reset mode, the Read/
Reset operation is initiated by writing the Read/Reset command sequence into the command register.
Microprocessor read cycles retrieve array data from the memory. The devices remain enabled for reads until the
command register contents are altered.
The devices will automatically power-up in the Read/Reset state. In this case, a command sequence is not
required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures
that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for the specific timing parameters.
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the devices reside in the target system. PROM
programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high
voltage onto the address lines is not generally desired system design practice.
The device contains an Autoselect command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the Autoselect command sequence into the command register.
Following the command write, a read cycle from address (XX)00H retrieves the manufacture code of 04H. A
read cycle from address (XX)01H for ×16((XX)02H for ×8) returns the device code (MBM29SL160TD = E4H and
MBM29SL160BD = E7H for ×8 mode; MBM29SL160TD = 22E4H and MBM29SL160BD = 22E7H for ×16 mode),
(See Tables 6.1 and 6.2.)
All manufacturer and device codes will exhibit odd parity with DQ7 defined as the parity bit. Sector state (protection
or unprotection) will be informed by address (XX)02H for ×16 ((XX)04H for ×8). Scanning the sector group
addresses (A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” at device
output DQ0 for a protected sector group. The programming verification should be performed by verify sector
group protection on the protected sector. (See Tables 4 and 5.)
To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and
also to write the Autoselect command during the operation, execute it after writing Read/Reset command
sequence.
Byte/Word Programming
The devices are programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle
operation. There are two “unlock” write cycles. These are followed by the program set-up command and data
write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is
latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever
happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence,
the system is not required to provide further controls or timings. The device will automatically provide adequate
internally generated program pulses and verify the programmed cell margin.
19
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
The system can determine the status of the program operation by using DQ7 (Data Polling), DQ6 (Toggle Bit),
or RY/BY. The Data Polling and Toggle Bit must be performed at the memory location which is being programmed.
The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this
bit at which time the devices return to the read mode and addresses are no longer latched. (See Table 13,
Hardware Sequence Flags.) Therefore, the devices require that a valid address to the devices be supplied by
the system at this particular instance of time. Hence, Data Polling must be performed at the memory location
which is being programmed.
Any commands written to the chip during this period will be ignored. If hardware reset occurs during the
programming operation, it is impossible to guarantee the data are being written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from Read/Reset mode will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.
Figure 21 illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations.
Chip Erase
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the devices will automatically program and verify the entire memory for an all
zero data pattern prior to electrical erase (Preprogram function). The system is not required to provide any
controls or timings during these operations.
The system can determine the status of the erase operation by using DQ7 (Data Polling), DQ6 (Toggle Bit), or
RY/BY. The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command
sequence and terminates when the data on DQ7 is “1” (See Write Operation Status section.) at which time the
device returns to read the mode.
Chip Erase Time; Sector Erase Time × All sectors + Chip Program Time (Preprogramming)
Figure 22 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations.
Sector Erase
Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of CE or WE whichever
happens later, while the command (Data = 30H) is latched on the rising edge of CE or WE which happens first.
After time-out of 50µs from the rising edge of the last sector erase command, the sector erase operation will begin.
Multiple sectors may be erased concurrently by writing the six bus cycle operations on Table 7. This sequence
is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently
erased. The time between writes must be less than 50µs otherwise that command will not be accepted and
erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this
condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 50µs
from the rising edge of last CE or WE whichever happens first will initiate the execution of the Sector Erase
command(s). If another falling edge of CE or WE, whichever happens first occurs within the 50µs time-out window
the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still open, see section DQ3,
Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend during this time-out period will
reset the devices to the read mode, ignoring the previous command string. Resetting the devices once execution
has begun will corrupt the data in the sector. In that case, restart the erase on those sectors and allow them to
20
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
complete. (Refer to the Write Operation Status section for Sector Erase Timer operation.) Loading the sector
erase buffer may be done in any sequence and with any number of sectors (0 to 38).
Sector erase does not require the user to program the devices prior to erase. The devices automatically program
all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram function). When erasing
a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any
controls or timings during these operations.
The system can determine the status of the erase operation by using DQ7 (Data Polling), DQ6 (Toggle Bit), or
RY/BY.
The sector erase begins after the 50µs time out from the rising edge of CE or WE whichever happens first for
the last sector erase command pulse and terminates when the data on DQ7 is “1” (See Write Operation Status
section.) at which time the devices return to the read mode. Data polling and Toggle Bit must be performed at
an address within any of the sectors being erased.
Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time (Preprogramming)] × Number of Sector
Erase
Figure 22 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations.
Erase Suspend/Resume
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads
from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase
operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if
written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command
(B0H) during the Sector Erase time-out results in immediate termination of the time-out period and suspension
of the erase operation.
Writing the Erase Resume command (30H) resumes the erase operation. The address are DON’T CARES when
writing the Erase Suspend or Erase Resume command (30H).
When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum
of 20µs to suspend the erase operation. When the devices have entered the erase-suspended mode, the
RY/BY output pin will be at Hi-Z and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must
use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been
suspended. Further writes of the Erase Suspend command are ignored.
When the erase operation has been suspended, the devices default to the erase-suspend-read mode. Reading
data in this mode is the same as reading from the standard read mode except that the data must be read from
sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the
device is in the erase-suspend-read mode will cause DQ2 to toggle. (See the section on DQ2.)
After entering the erase-suspend-read mode, the user can program the device by writing the appropriate
command sequence for Program. This program mode is known as the erase-suspend-program mode. Again,
programming in this mode is the same as programming in the regular Program mode except that the data must
be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector
while the devices are in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erasesuspended Program operation is detected by the RY/BY output pin, Data polling of DQ7 or by the Toggle Bit I
(DQ6) which is the same as the regular Program operation. Note that DQ7 must be read from the Program address
while DQ6 can be read from any address.
To resume the operation of Sector Erase, the Resume command (30H) should be written. Any further writes of
the Resume command at this point will be ignored. Another Erase Suspend command can be written after the
chip has resumed erasing.
21
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
Extended Command
(1) Fast Mode
MBM29SL160TD/BD has Fast Mode function. This mode dispenses with the initial two unclock cycles
required in the standard program command sequence by writing Fast Mode command into the command
register. In this mode, the required bus cycle for programming is two cycles instead of four bus cycles in
standard program command. (Do not write erase command in this mode.) The read operation is also executed
after exiting this mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command
register. (Refer to the Figure 27.) The VCC active current is required even CE = VIH during Fast Mode.
(2) Fast Programming
During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program
Algorithm is executed by writing program set-up command (A0H) and data write cycles (PA/PD). (Refer to
the Figure 27.)
(3) Extended Sector Group Protection
In addition to normal sector group protection, the MBM29SL160TD/BD has Extended Sector Group
Protection as extended function. This function enable to protect sector group by forcing VID on RESET pin
and write a command sequence. Unlike conventional procedure, it is not necessary to force VID and control
timing for control pins. The only RESET pin requires VID for sector group protection in this mode. The extended
sector group protection requires VID on RESET pin. With this condition, the operation is initiated by writing
the set-up command (60H) into the command register. Then, the sector group addresses pins (A19, A18, A17,
A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set to the sector group to be protected
(recommend to set VIL for the other addresses pins), and write extended sector group protection command
(60H). A sector group is typically protected in 150 µs. To verify programming of the protection circuitry, the
sector group addresses pins (A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set
and write a command (40H). Following the command write, a logical “1” at device output DQ0 will produce
for protected sector in the read operation. If the output data is logical “0”, please repeat to write extended
sector group protection command (60H) again. To terminate the operation, it is necessary to set RESET pin
to VIH. (Refer to the Figures 19 and 28.)
(4) CFI (Common Flash Memory Interface)
The CFI (Common Flash Memory Interface) specification outlines device and host system software
interrogation handshake which allows specific vendor-specified software algorithms to be used for entire
families of devices. This allows device-independent, JEDEC ID-independent, and forward-and backwardcompatible software support for the specified flash device families. Refer to CFI specification in detail.
The operation is initiated by writing the query command (98H) into the command register. Following the
command write, a read cycle from specific address retrives device information. Please note that output data
of upper byte (DQ8 to DQ15) is “0” in word mode (16 bit) read. Refer to the CFI code table. To terminate
operation, it is necessary to write the read/reset command sequence into the register. (See Table 15.)
22
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
One Time Protect (OTP) Region
The OTP feature provides a Flash memory region that the system may access through a new command
sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the
device with the ESN protected against modification. Once the OTP region is protected, any further modification
of that region is impossible. This ensures the security of the ESN once the product is shipped to the field.
The OTP region is 256 bytes in length. The MBM29SL160TD occupies the address of the byte mode 1FFEFFH
to 1FFFFFH (word mode FFF7FH to FFFFFH) and the MBM29SL160BD type occupies the address of the byte
mode 00000H to 00100H (word mode 00000H to 00080H). After the system has written the Enter OTP command
sequence, the system may read the OTP region by using the addresses normally occupied by the boot sectors.
That is, the device sends all commands that would normally be sent to the boot sectors to the OTP region. This
mode of operation continues until the system issues the Exit OTP command sequence, or until power is removed
from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the
boot sectors.
If you request Fujitsu to program the ESN in the device, please contact a Fujitsu representative for more
information.
Write Operarion Status
Table 8 Hardware Sequence Flags
DQ7
DQ6
DQ5
DQ3
DQ2
DQ7
Toggle
0
0
1
0
Toggle
0
1
Toggle
(Note 2)
1
1
0
0
Toggle
Data
Data
DQ7
Toggle
(Note 1)
0
0
1
(Note 2)
Embedded Program Algorithm
DQ7
Toggle
1
0
1
Embedded Erase Algorithm
Exceeded
Time Limits Erase
Erase Suspend Program
Suspended
(Non-Erase Suspended Sector)
Mode
0
Toggle
1
1
N/A
DQ7
Toggle
1
0
N/A
Status
Embedded Program Algorithm
Embedded Erase Algorithm
In Progress
Erase Suspend Read
(Erase Suspended Sector)
Erase
Erase Suspend Read
Suspended
(Non-Erase Suspended Sector)
Mode
Erase Suspend Program
(Non-Erase Suspended Sector)
Data Data
Data
Notes: 1. Performing successive read operetions from any address will cause DQ6 to toggle.
2. Reading the byte address being programmed while in the erase-suspend program mode will indicate
logic "1" at the DQ2 bit. However, successive reads from the erase-suspend sector will cause DQ2 to
toggle.
3. DQ0 and DQ1 are reserve pins for future use.
4. DQ4 is Fujitsu internal use only
23
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
DQ7
Data Polling
The MBM29SL160TD/BD devices feature Data Polling as a method to indicate to the host that the Embedded
Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the
devices will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program
Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded
Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the
Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart
for Data Polling (DQ7) is shown in Figure 23.
For programming, the Data Polling is valid after the rising edge of fourth write pulse in the four write pulse
sequence.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased
and not a protected sector. Otherwise, the status may not be valid.
Once the Embedded Algorithm operation is close to being completed, the MBM29SL160TD/BD data pins (DQ7)
may change asynchronously while the output enable (OE) is asserted low. This means that the devices are
driving status information on DQ7 at one instant of time and then that byte’s valid data at the next instant of time.
Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device
has completed the Embedded Algorithm operation and DQ7 has a valid data, the data outputs on DQ0 to DQ6
may be still invalid. The valid data on DQ0 to DQ7 will be read on the successive read attempts.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm
or sector erase time-out. (See Table 8.)
See Figure 9 for the Data Polling timing specifications and diagrams.
DQ6
Toggle Bit I
The MBM29SL160TD/BD also feature the “Toggle Bit I” as a method to indicate to the host system that the
Embedded Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the devices will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm
cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During
programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written to is protected, the toggle bit will toggle for about 1 µs and then stop
toggling without the data having changed. In erase, the devices will erase all the selected sectors except for the
ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 400 µs
and then drop back into read mode, having changed none of the data.
Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will
cause the DQ6 to toggle. See Figure 10 for the Toggle Bit I timing specifications and diagrams.
24
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
DQ5
Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase
cycle was not successfully completed. Data Polling is the only operating function of the devices under this
condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA).
The OE and WE pins will control the output disable functions as described in Tables 4 and 5.
The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this
case the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the devices have exceeded timing limits, the
DQ5 bit will indicate a “1.” Please note that this is not a device failure condition since the devices were incorrectly
used. If this occurs, reset the device with command sequence.
DQ3
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will
remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may
be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled
erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low (“0”), the device will accept
additional sector erase commands. To insure the command has been accepted, the system software should
check the status of DQ3 prior to and following each subsequent Sector Erase command. If DQ3 were high on
the second status check, the command may not have been accepted.
See Table 8: Hardware Sequence Flags.
DQ2
Toggle Bit II
This toggle bit II, along with DQ6, can be used to determine whether the devices are in the Embedded Erase
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the
devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ2 to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte
address of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit.
DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized
as follows:
For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.
(DQ2 toggles while DQ6 does not.) See also Table 9 and Figure 18.
Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase
mode, DQ2 toggles if this bit is read from an erasing sector.
25
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
Table 9 Toggle Bit Status
DQ7
DQ6
DQ2
DQ7
Toggle
1
Erase
0
Toggle
Toggle
Erase-Suspend Read
(Erase-Suspended Sector)
1
1
Toggle
DQ7
Toggle (Note 1)
1 (Note 2)
Mode
Program
Erase-Suspend Program
Note: 1.Performing successive read operetions from any address will cause DQ6 to toggle.
2.Reading the byte address being programmed while in the erase-suspend program mode will indicate logic
"1" at the DQ2 bit. However, successive reads from the erase-suspend sector will cause DQ2 to toggle.
RY/BY
Ready/Busy
The MBM29SL160TD/BD provide a RY/BY open-drain output pin as a way to indicate to the host system that
the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are
busy with either a program or erase operation. If the output is high, the devices are ready to accept any read/
write or erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase
commands. If the MBM29SL160TD/BD are placed in an Erase Suspend mode, the RY/BY output will be high.
During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate
a busy condition during the RESET pulse. Refer to Figures 11 and 12 for a detailed timing diagram. The RY/BY
pin is pulled high in standby mode.
Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC.
Byte/Word Configuration
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29SL160TD/BD devices. When
this pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ0
to DQ15. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the DQ15/A-1 pin
becomes the lowest address bit and DQ8 to DQ14 bits are tri-stated. However, the command bus cycle is always
an 8-bit operation and hence commands are written at DQ0 to DQ7 and the DQ8 to DQ15 bits are ignored. Refer
to Figures 13, 14 and 15 for the timing diagram.
Data Protection
The MBM29SL160TD/BD are designed to offer protection against accidental erasure or programming caused
by spurious system level signals that may exist during power transitions. During power up the devices
automatically reset the internal state machine in the Read mode. Also, with its control register architecture,
alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command
sequences.
The devices also incorporate several features to prevent inadvertent write cycles resulting form VCC power-up
and power-down transitions or system noise.
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
26
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
27
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
Table 10 Common Flash Memory Interface Code
Description
Query-unique ASCII string
“QRY”
Primary OEM Command Set
2h: AMD/FJ standard type
Address for Primary
Extended Table
Alternate OEM Command
Set (00h = not applicable)
Address for Alternate OEM
Extended Table
VCC Min. (write/erase)
D7-4: volt, D3-0: 100 mvolt
VCC Max. (write/erase)
D7-4: volt, D3-0: 100 mvolt
VPP Min. voltage
VPP Max. voltage
Typical timeout per single
byte/word write 2N µs
Typical timeout for Min. size
buffer write 2N µs
Typical timeout per individual
block erase 2N ms
Typical timeout for full chip
erase 2N ms
Max. timeout for byte/word
write 2N times typical
Max. timeout for buffer write
2N times typical
Max. timeout per individual
block erase 2N times typical
Max. timeout for full chip
erase 2N times typical
Device Size = 2N byte
Flash Device Interface
description
Max. number of byte in
multi-byte write = 2N
Number of Erase Block
Regions within device
Erase Block Region 1
Information
28
A0 to A6
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
DQ0 to DQ15
1Ch
0027h
1Dh
1Eh
1Fh
0000h
0000h
0004h
20h
0000h
21h
000Ah
22h
0000h
23h
0005h
24h
0000h
0051h
0052h
0059h
0002h
0000h
0040h
0000h
0000h
0000h
0000h
0000h
0018h
25h
0004h
26h
0000h
27h
28h
29h
2Ah
2Bh
2Ch
0015h
0002h
0000h
0000h
0000h
0002h
2Dh
2Eh
2Fh
30h
0007h
0000h
0020h
0000h
Description
Erase Block Region 2
Information29SL160
Query-unique ASCII string
“PRI”
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock
0 = Required
1 = Not Required
Erase Suspend
0 = Not Supported
1 = To Read Only
2 = To Read & Write
Sector Protection
0 = Not Supported
X = Number of sectors in per
group
Sector Temporary
Unprotection
00 = Not Supported
01 = Supported
Sector Protection Algorithm
Number of Sector for Bank 2
00h = Not Supported
Burst Mode Type
00 = Not Supported
Page Mode Type
00 = Not Supported
ACC (Acceleration) Supply
Minimum
00h = Not Supported,
D7-4: volt, D3-0: 100 mvolt
ACC (Acceleration) Supply
Maximum
00h = Not Supported,
D7-4: volt, D3-0: 100 mvolt
Boot Type
02h = MBM29SL160BD
03h = MBM29SL160TD
A0 to A6
31h
32h
33h
34h
40h
41h
42h
43h
44h
45h
DQ0 to DQ15
46h
0002h
47h
0001h
48h
0001h
49h
4Ah
0004h
0000h
4Bh
0000h
4Ch
0000h
4Dh
0085h
4Eh
0095h
4Fh
00XXh
001Eh
0000h
0000h
0001h
0050h
0052h
0049h
0031h
0031h
0000h
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Conditions
Tstg
Rating
Unit
Min.
Max.
—
–55
+125
°C
TA
—
–40
+85
°C
Voltage with respect to Ground
All pins except A9, OE, RESET
(Note 1)
VIN, VOUT
—
–0.5
VCC + 0.5
V
Power Supply Voltage (Note 1)
VCC
—
–0.5
+3.0
V
A9, OE, and RESET (Note 2)
VIN
—
–0.5
+11.0
V
WP/ACC
VIN
—
–0.5
+10.5
V
Storage Temperature
Ambient Temperature with Power
Applied
Notes: 1. Minimum DC voltage on input or I/O pins are –0.5 V. During voltage transitions, inputs may negative
overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins are VCC
+0.5 V. During voltage transitions, outputs may positive overshoot to VCC +2.0 V for periods of up to 20 ns.
2. Minimum DC input voltage on A9, OE and RESET pins are –0.5 V. During voltage transitions, A9, OE
and RESET pins may negative overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC input
voltage on A9, OE and RESET pins are +11.0 V which may positive overshoot to 12.0 V for periods of
up to 20 ns. Voltage difference between input voltage and supply voltage (VIN – VCC) do not exceed 9 V.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Conditions
Ambient Temperature
TA
Power Supply Voltage
VCC
Value
Unit
Min.
Max.
—
–40
+85
°C
—
+1.8
+2.2
V
Operating ranges define those limits between which the functionality of the devices are guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
29
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
■ MAXIMUM OVERSHOOT
20 ns
20 ns
0.2 × V CC
–0.5 V
–2.0 V
20 ns
Figure 1
Maximum Negative Overshoot Waveform
20 ns
V CC +2.0 V
V CC +0.5 V
0.8 × V CC
20 ns
Figure 2
20 ns
Maximum Positive Overshoot Waveform 1
20 ns
+12.0 V
+11.0 V
V CC +0.5 V
20 ns
20 ns
*: This waveform is applied for A9, OE, and RESET.
Figure 3
30
Maximum Positive Overshoot Waveform 2
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
■ DC CHARACTERISTICS
Parameter
Symbol
Parameter Description
Test Conditions
Min.
Max.
Unit
ILI
Input Leakage Current
VIN = VSS to VCC, VCC = VCC Max.
–1.0
+1.0
µA
ILO
Output Leakage Current
VOUT = VSS to VCC, VCC = VCC Max.
–1.0
+1.0
µA
ILIT
A9, OE, RESET Inputs Leakage
Current
VCC = VCC Max.
A9, OE, RESET = 11 V
—
35
µA
ILIA
WP/ACC Inputs Leakage Current
VCC = VCC Max.
WP/ACC = VHH Max.
—
20
mA
CE = VIL, OE = VIH,
f=10 MHz
ICC1
Byte
25
—
Word
mA
25
VCC Active Current (Note 1)
CE = VIL, OE = VIH,
f=5 MHz
Byte
15
—
Word
mA
15
ICC2
VCC Active Current (Note 2)
CE = VIL, OE = VIH
—
25
mA
ICC3
VCC Current (Standby)
VCC = VCC Max., CE = VCC ± 0.3 V,
RESET = VCC ± 0.3 V
—
5
µA
ICC4
VCC Current (Standby, Reset)
VCC = VCC Max.,
RESET = VSS ± 0.3 V
—
5
µA
ICC5
VCC = VCC Max., CE = VSS ± 0.3 V,
VCC Current
RESET = VCC ± 0.3 V
(Automatic Sleep Mode) (Note 3)
VIN = VCC ± 0.3 V or VSS ± 0.3 V
—
5
µA
VIL
Input Low Level
—
–0.5
0.2 x VCC
V
VIH
Input High Level
—
0.8 x VCC
VCC+0.3
V
VACC
Voltage for WP/ACC Sector
Protection/Unprotection and
Program Accelaration
—
8.5
9.5
V
VID
Voltage for Autoselect and Sector
Protection (A9, OE, RESET)
(Note 4, 5)
—
10
11
V
VOL
Output Low Voltage Level
IOL = 0.1 mA, VCC = VCC Min.
—
0.1
V
VOH
Output High Voltage Level
IOH = –100 µA
VCC–0.1
—
V
Notes: 1.
2.
3.
4.
5.
The ICC current listed includes both the DC operating current and the frequency dependent component.
ICC active while Embedded Algorithm (program or erase) is in progress.
Automatic sleep mode enables the low power mode when address remain stable for 150 ns.
This timing is for Sector Protection operation.
Applicable for only VCC applying.
31
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
■ AC CHARACTERISTICS
• Read Only Operations Characteristics
Parameter
Symbols
Description
-10
(Note)
-12
(Note)
Unit
Min.
100
120
ns
Test Setup
JEDEC
Standard
tAVAV
tRC
Read Cycle Time
tAVQV
tACC
Address to Output Delay
CE = VIL
Max.
OE = VIL
100
120
ns
tELQV
tCE
Chip Enable to Output Delay
OE = VIL Max.
100
120
ns
tGLQV
tOE
Output Enable to Output Delay
—
Max.
35
50
ns
tEHQZ
tDF
Chip Enable to Output High-Z
—
Max.
30
40
ns
tGHQZ
tDF
Output Enable to Output High-Z
—
Max.
30
40
ns
tAXQX
tOH
Output Hold Time From
Addresses,
CE or OE, Whichever Occurs First
—
Min.
0
0
ns
—
tREADY
RESET Pin Low to Read Mode
—
Max.
20
20
µs
—
tELFL
tELFH
CE or BYTE Switching Low or
High
—
Max.
5
5
ns
—
Notes: Test Conditions:
Output Load:1 TTL gate and 30 pF (MBM29SL160TD/BD-10)
1 TTL gate and 100 pF (MBM29SL160TD/BD-12)
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to VCC
Timing measurement reference level
Input: 0.5 x VCC
Output: 0.5 x VCC
VCC
IN3064
or Equivalent
2.7 kΩ
Device
Under
Test
6.2 kΩ
CL
Diodes = IN3064
or Equivalent
Notes: CL = 30 pF including jig capacitance (MBM29SL160TD/BD-10)
CL = 100 pF including jig capacitance (MBM29SL160TD/BD-12)
Figure 4
32
Test Conditions
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
• Write/Erase/Program Operations
Parameter Symbols
Description
-10
-12
Unit
Min.
100
120
ns
Address Setup Time
Min.
0
0
ns
tAH
Address Hold Time
Min.
50
60
ns
tDVWH
tDS
Data Setup Time
Min.
50
60
ns
tWHDX
tDH
Data Hold Time
Min.
0
0
ns
—
tOES
Output Enable Setup Time
Min.
0
0
ns
Min.
0
0
ns
tOEH
Output
Enable Hold
Time
Read
—
Toggle and Data Polling
Min.
10
10
ns
JEDEC
Standard
tAVAV
tWC
Write Cycle Time
tAVWL
tAS
tWLAX
tGHWL
tGHWL
Read Recover Time Before Write
Min.
0
0
ns
tGHEL
tGHEL
Read Recover Time Before Write
Min.
0
0
ns
tELWL
tCS
CE Setup Time
Min.
0
0
ns
tWLEL
tWS
WE Setup Time
Min.
0
0
ns
tWHEH
tCH
CE Hold Time
Min.
0
0
ns
tEHWH
tWH
WE Hold Time
Min.
0
0
ns
tWLWH
tWP
Write Pulse Width
Min.
50
60
ns
tELEH
tCP
CE Pulse Width
Min.
50
60
ns
tWHWL
tWPH
Write Pulse Width High
Min.
30
30
ns
tEHEL
tCPH
CE Pulse Width High
Min.
30
30
ns
tWHWH1
tWHWH1
Byte Programming Operation
Typ.
10.6
10.6
µs
tWHWH2
tWHWH2
Sector Erase Operation (Note 1)
Typ.
1.5
1.5
sec
—
tVCS
VCC Setup Time
Min.
50
50
µs
—
tVIDR
Rise Time to VID (Note 2)
Min.
500
500
ns
—
tVACCR
Rise Time to VACC
Min.
500
500
ns
—
tVLHT
Voltage Transition Time (Note 2)
Min.
4
4
µs
—
tWPP
Write Pulse Width (Note 2)
Min.
100
100
µs
—
tOESP
OE Setup Time to WE Active (Note 2)
Min.
4
4
µs
—
tCSP
CE Setup Time to WE Active (Note 2)
Min.
4
4
µs
—
tRB
Recover Time From RY/BY
Min.
0
0
ns
—
tRP
RESET Pulse Width
Min.
500
500
ns
—
tRH
RESET Hold Time Before Read
Min.
200
200
ns
(Continued)
33
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
(Continued)
Parameter Symbols
Description
-10
-12
Unit
Max.
30
40
ns
BYTE Switching High to Output Active
Min.
30
40
ns
tBUSY
Program/Erase Valid to RY/BY Delay
Max.
90
90
ns
—
tEOE
Delay Time from Embedded Output Enable
Max.
100
120
ns
—
tPS
Power On/Off Timing
Min.
0
0
ns
JEDEC
Standard
—
tFLQZ
BYTE Switching Low to Output High-Z
—
tFHQV
—
Notes: 1. This does not include the preprogramming time.
2. This timing is for Sector Group Protection operation.
34
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
■ SWITCHING WAVEFORMS
• Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Must Be
Steady
Will Be
Steady
May
Change
from H to L
Will Be
Changing
from H to L
May
Change
from L to H
Will Be
Changing
from L to H
“H” or “L”
Any Change
Permitted
Changing
State
Unknown
Does Not
Apply
Center Line is
HighImpedance
“Off” State
t RC
Addresses
Addresses Stable
t ACC
CE
t OE
t DF
OE
t OEH
WE
t CE
Outputs
High-Z
Figure 5.1
Output Valid
High-Z
AC Waveforms for Read Operations
35
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
t RC
Addresses
Addresses Stable
t ACC
t RH
RESET
t OH
High-Z
Outputs
Figure 5.2
36
Output Valid
AC Waveforms for Hardware Reset/Read Operations
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
Data Polling
3rd Bus Cycle
Addresses
555H
t WC
PA
t AS
PA
t RC
t AH
CE
t CH
t CS
t CE
OE
t GHWL
t WP
t WPH
t OE
t WHWH1
WE
t OH
t DS
t DH
A0H
Data
Notes: 1.
2.
3.
4.
5.
6.
PD
DQ 7
D OUT
D OUT
PA is address of the memory location to be programmed.
PD is data to be programmed at byte address.
DQ7 is the output of the complement of the data written to the device.
DOUT is the output of the data written to the device.
Figure indicates last two bus cycles out of four bus cycle sequence.
These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
Figure 6
AC Waveforms for Alternate WE Controlled Program Operations
37
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
3rd Bus Cycle
Addresses
Data Polling
PA
555H
t WC
t AS
PA
t AH
WE
t WS
t WH
OE
t GHEL
t CP
t CPH
t WHWH1
CE
t DS
t DH
Data
Notes: 1.
2.
3.
4.
5.
6.
PD
DQ 7
D OUT
PA is address of the memory location to be programmed.
PD is data to be programmed at byte address.
DQ7 is the output of the complement of the data written to the device.
DOUT is the output of the data written to the device.
Figure indicates last two bus cycles out of four bus cycle sequence.
These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
Figure 7
38
A0H
AC Waveforms for Alternate CE Controlled Program Operations
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
Addresses
2AAH
555H
t WC
t AS
555H
555H
2AAH
SA
t AH
CE
t CS
t CH
OE
t GHWL
t WP
t WPH
WE
t DS
AAH
Data
t DH
55H
80H
AAH
55H
10H/
30H
t VCS
V CC
Notes: 1. SA is the sector address for Sector Erase. Addresses = 555H (Word), AAAH (Byte)
for Chip Erase.
2. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
Figure 8
AC Waveforms Chip/Sector Erase Operations
39
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
CE
t CH
t OE
t DF
OE
t OEH
WE
t CE
*
DQ7
Data
High-Z
DQ7 =
Valid Data
DQ7
t WHWH1 or 2
DQ0 to DQ6
Data
DQ0 to DQ6 = Output Flag
High-Z
DQ0 to DQ6
Valid Data
t EOE
* : DQ7 = Valid Data (The device has completed the Embedded operation).
Figure 9
AC Waveforms for Data Polling during Embedded Algorithm Operations
CE
tOEH
WE
tOES
OE
*
DQ 6
Data
DQ 6 = Toggle
DQ 6 =
Stop Toggling
DQ 6 = Toggle
Valid
tOE
* : DQ6 stops toggling (The device has completed the Embedded operation).
Figure 10
40
AC Waveforms for Toggle Bit I during Embedded Algorithm Operations
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
CE
The rising edge of the last WE signal
WE
Entire programming
or erase operations
RY/BY
t BUSY
Figure 11
RY/BY Timing Diagram during Program/Erase Operations
WE
RESET
tRP
t RB
RY/BY
tREADY
Figure 12
RESET/RY/BY Timing Diagram
41
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
CE
BYTE
Data Output
(DQ0 to DQ7)
DQ0 to DQ14
tELFH
DQ15/A-1
Data Output
(DQ0 to DQ14)
tFHQV
DQ15
A-1
Figure 13
Timing Diagram for Word Mode Configuration
CE
BYTE
DQ0 to DQ14
tELFL
DQ15/A-1
Data Output
(DQ0 to DQ7)
Data Output
(DQ0 to DQ14)
DQ15
A-1
tFLQZ
Figure 14
Timing Diagram for Byte Mode Configuration
The falling edge of the last write signal
CE or WE
Input
Valid
BYTE
tSET
(tAS)
Figure 15
42
tHOLD (tAH)
BYTE Timing Diagram for Write Operations
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
A18, A17, A16
A15, A14
A13, A12
SAX
SAY
A0
A1
A6
VID
VIH
A9
t VLHT
VID
VIH
OE
t VLHT
t VLHT
t VLHT
t WPP
WE
t OESP
t CSP
CE
Data
01H
t VCS
t OE
VCC
SGAX:Sector Group Address for initial sector
SGAY:Sector Group Address for next sector
Note: A-1 is VIL on byte mode.
Figure 16
AC Waveforms for Sector Group Protection Timing Diagram
43
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
VCC
tVIDR
tVCS
VID
VIH
RESET
CE
WE
tVLHT
tVLHT
Program or Erase Command Sequence
RY/BY
Figure 17
Enter
Embedded
Erasing
WE
Temporary Sector Group Unprotection Timing Diagram
Erase
Suspend
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Suspend
Program
Erase
Resume
Erase Suspend
Read
DQ6
DQ2
Toggle
DQ2 and DQ6
with OE
Note: DQ2 is read from the erase-suspended sector.
Figure 18
44
DQ2 vs. DQ6
Erase
Erase
Complete
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
VCC
tVCS
RESET
tVLHT
tVIDR
Add
SGAX
SGAX
SGAY
A0
A1
A6
CE
OE
TIME-OUT
tWP
WE
Data
60H
60H
40H
01H
60H
SGAX : Sector Group Address to be protected
SGAY : Next Sector Group Address to be protected
TIME-OUT : Time-Out window = 50 µs (min)
Figure 19
Extended Sector Group Protection Timing Diagram
45
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
t PS
t PS
RESET
VCC
0V
VIH
1.8 V
Input Valid
Addresses
Data
Output Valid
t RH
Figure 20
46
t ACC
Power ON/OFF Timing Diagram
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
VCC
tVACCR
tVCS
tVLHT
VACC
3V
VIH
WP/ACC
CE
WE
tVLHT
tVLHT
Program Command Sequence
RY/BY
Accelerated Program
Figure 21
Accelerated Program Operation Timing Diagram
47
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
EMBEDDED ALGORITHMS
Start
Write Program Command
Sequence
(See below)
Data Polling Device
No
Increment Address
Last Address
?
Yes
Programming Completed
Program Command Sequence* (Address/Command):
555H/AAH
2AAH/55H
555H/A0H
Program Address/Program Data
* : The sequence is applied for × 16 mode.
The addresses differ from × 8 mode.
Figure 22
48
Embedded ProgramTM Algorithm
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
EMBEDDED ALGORITHMS
Start
Write Erase Command
Sequence
(See below)
Data Polling or Toggle Bit
Successfully Completed
Erasure Completed
Chip Erase Command Sequence*
(Address/Command):
Individual Sector/Multiple Sector*
Erase Command Sequence
(Address/Command):
555H/AAH
555H/AAH
2AAH/55H
2AAH/55H
555H/80H
555H/80H
555H/AAH
555H/AAH
2AAH/55H
2AAH/55H
555H/10H
Sector Address/30H
Sector Address/30H
Additional sector
erase commands
are optional.
Sector Address/30H
* : The sequence is applied for × 16 mode.
The addresses differ from × 8 mode.
Figure 23
Embedded EraseTM Algorithm
49
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
Start
Read
(DQ 0 to DQ 7)
Addr. = VA
DQ 7 = Data?
VA = Byte address for programming
= Any of the sector addresses within
the sector being erased during
sector erase or multiple sector
erases operation
= Any of the sector addresses within
the sector not being protected
during chip erase
Yes
No
No
DQ 5 = 1?
Yes
Read
(DQ 0 to DQ 7)
Addr. = VA
DQ 7 = Data?
Yes
No
Fail
Pass
Note: DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
Figure 24
50
Data Polling Algorithm
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
Start
Read
(DQ 0 to DQ 7)
Addr. = "H" or "L"
DQ 6 = Toggle
?
No
Yes
No
DQ 5 = 1?
Yes
Read
(DQ 0 to DQ 7)
Addr. = VA
DQ 6 = Toggle
?
No
Yes
Fail
Pass
Note: DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as
DQ5 changing to “1” .
Figure 25
Toggle Bit Algorithm
51
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
Start
Setup Sector Addr.
(A18, A17, A16, A15, A14, A13, A12)
PLSCNT = 1
OE = V ID, A 9 = V ID,
A 6 = CE = V IL, RESET = V IH
A 0 = V IL, A 1 = V IH
Activate WE Pulse
Time out 100 µs
Increment PLSCNT
WE = V IH, CE = OE = V IL
(A 9 should remain V ID)
Read from Sector
(Addr. = SA, A 0 = V IL,
A 1 = V IH, A 6 = V IL)*
No
No
PLSCNT = 25?
Yes
Remove V ID from A 9
Write Reset Command
Data = 01H?
Yes
Yes
Protect Another Sector?
No
Device Failed
Remove V ID from A 9
Write Reset Command
Sector Protection
Completed
* : A-1 is V IL on byte mode.
Figure 26
52
Sector Protection Algorithm
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
Start
RESET = VID
(Note 1)
Perform Erase or
Program Operations
RESET = VIH
Temporary Sector
Unprotection Completed
(Note 2)
Notes: 1. All protected sectors are unprotected.
2. All previously protected sectors are protected once again.
Figure 27
Temporary Sector Unprotection Algorithm
53
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
FAST MODE ALGORITHM
Start
555H/AAH
Set Fast Mode
2AAH/55H
555H/20H
XXXH/A0H
Program Address/Program Data
Data Polling Device
Verify Byte?
No
In Fast Program
Yes
Increment Address
No
Last Address
?
Yes
Programming Completed
XXXH/90H
Reset Fast Mode
XXXH/F0H
* : The sequence is applied for × 16 mode.
The addresses differ from × 8 mode.
Figure 28
54
Embedded ProgramTM Algorithm for Fast Mode
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
FAST MODE ALGORITHM
Start
RESET = VID
Wait to 4 µs
Device is Operating in
Temporary Sector
Unprotection Mode
No
Extended Sector
Protection Entry?
Yes
To Setup Sector Protection
Write XXXH/60H
PLSCNT = 1
To Sector Protection
Write SPA/60H
(A0 = VIL, A1 = VIH, A6 = VIL)
Time Out 150 µs
Increment PLSCNT
To Verify Sector Protection
Write SPA/40H
(A0 = VIL, A1 = VIH, A6 = VIL)
Setup Next Sector Address
Read from Sector Address
(A0 = VIL, A1 = VIH, A6 = VIL)
No
No
PLSCNT = 25?
Yes
Data = 01H?
Yes
Remove VID from RESET
Write Reset Command
Protection Other Sector
?
No
Yes
Remove VID from RESET
Write Reset Command
Device Failed
Sector Protection
Completed
Figure 29
Extended Sector Protection Algorithm
55
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
■ ERASE AND PROGRAMMING PERFORMANCE
Limits
Parameter
Unit
Comments
Min.
Typ.
Max.
Sector Erase Time
—
1.5
20
sec
Word Programming Time
—
14.6
360
µs
Byte Programming Time
—
10.6
300
µs
Chip Programming Time
—
15.4
160
sec
100,000
—
—
cycles
Program/Erase Cycle
Excludes programming time
prior to erasure
Excludes system-level
overhead
Excludes system-level
overhead
—
Note:
■ TSOP(I) PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Test Setup
Typ.
Max.
Unit
7.5
9.5
pF
CIN
Input Capacitance
VIN = 0
COUT
Output Capacitance
VOUT = 0
8
10
pF
CIN2
Control Pin Capacitance
VIN = 0
8
13
pF
Typ.
Max.
Unit
7.5
9.5
pF
Note: Test conditions TA = 25°C, f = 1.0 MHz
■ FBGA PIN CAPACITANCE
Parameter
Symbol
Parameter Description
CIN
Input Capacitance
VIN = 0
COUT
Output Capacitance
VOUT = 0
8
10
pF
CIN2
Control Pin Capacitance
VIN = 0
8
13
pF
Note: Test conditions TA = 25°C, f = 1.0 MHz
56
Test Setup
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
■ ORDERING INFORMATION
Standard Products
Fujitsu standard products are available in several packages. The order number is formed by a combination of:
MBM29SL160
T
D
-10
PFTN
PACKAGE TYPE
PFTN = 48-Pin Thin Small Outline Package
(TSOP) Standard Pinout
PFTR = 48-Pin Thin Small Outline Package
(TSOP) Reverse Pinout
PBT = 48-Ball Fine pitch Ball Grid Array
Package (FBGA)
SPEED OPTION
See Product Selector Guide
DEVICE REVISION
BOOT CODE SECTOR ARCHITECTURE
T = Top sector
B = Bottom sector
DEVICE NUMBER/DESCRIPTION
MBM29SL160
16Mega-bit (2M × 8-Bit or 1M × 16-Bit) CMOS Flash Memory
1.8 V-only Read, Program, and Erase
57
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
■ PACKAGE DIMENSIONS
48-pin plastic TSOP(I)
(FPT-48P-M19)
* Resin Protrusin. (Each Side: 0.15 (.006)Max)
LEAD No.
1
48
Details of "A" part
INDEX
0.15(.006)
MAX
0.35(.014)
MAX
"A"
0.15(.006)
24
25
* 12.00±0.20
20.00±0.20
(.787±.008)
* 18.40±0.20
(.724±.008)
0.10(.004)
(.472±.008)
11.50REF
(.460)
19.00±0.20
(.748±.008)
1996 FUJITSU LIMITED F48029S-2C-2
+0.10
1.10 –0.05
+.004
.043 –.002
(Mounting height
0.50(.0197)
TYP
0.15±0.05
(.006±.002)
C
0.25(.010)
0.05(0.02)MIN
(STAND OFF)
0.20±0.10
(.008±.004)
0.10(.004)
M
0.50±0.10
(.020±.004)
Dimensions in mm (inches)
(Continued)
58
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
(Continued)
48-pin plastic TSOP(I)
(FPT-48P-M20)
* Resin Protrusin. (Each Side: 0.15 (.006)Max)
LEAD No.
1
48
Details of "A" part
INDEX
0.15(.006)
MAX
0.35(.014)
MAX
"A"
0.15(.006)
24
0.25(.010)
25
19.00±0.20
(.748±.008)
0.50±0.10
(.020±.004)
0.15±0.10
(.006±.002)
0.10(.004)
0.20±0.10
(.008±.004)
0.50(.0197)
TYP
0.10(.004)
M
0.05(0.02)MIN
(STAND OFF)
+0.10
1.10 –0.05
* 18.40±0.20
(.724±.008)
20.00±0.20
(.787±.008)
C
1996 FUJITSU LIMITED F48030S-2C-2
11.50(.460)REF
+.004
.043 –.002
(Mounting height)
* 12.00±0.20(.472±.008)
Dimensions in mm (inches)
(Continued)
59
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
(Continued)
48-pin plastic FBGA
(BGA-48P-M13)
Note: The actual shape of corners may differ from the dimension.
+0.15
9.00±0.20(.354±.008)
+.006
1.05 –0.10 .041 –.004
(Mounting height)
0.38±0.10(.015±.004)
(Stand off)
5.60(.221)
0.80(.031)TYP
6
5
8.00±0.20
(.315±.008)
4
4.00(.157)
3
INDEX
2
1
H
C0.25(.010)
G
F
E
D
48-Ø0.45±0.10
(48-.018±.004)
C
B
A
Ø0.08(.003)
M
0.10(.004)
C
60
1998 FUJITSU LIMITED B480013S-1C-1
Dimensions in mm (inches)
MBM29SL160TD-10/-12/MBM29SL160BD-10/-12
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: 81(44) 754-3763
Fax: 81(44) 754-3329
http://www.fujitsu.co.jp/
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Semiconductor Division
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Fax: (408) 922-9179
Customer Response Center
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D-63303 Dreieich-Buchschlag
Germany
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Fax: (06103) 690-122
http://www.fujitsu-ede.com/
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FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
http://www.fmap.com.sg/
F9910
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