TI MSP430F447IPZ Mixed signal microcontroller Datasheet

 SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
D Low Supply-Voltage Range, 1.8 V to 3.6 V
D Ultralow-Power Consumption:
D
D
D
D
D
D
D
D
D
D
– Active Mode: 280 µA at 1 MHz, 2.2 V
– Standby Mode: 1.1 µA
– Off Mode (RAM Retention): 0.1 µA
Five Power Saving Modes
Wake-Up From Standby Mode in 6 µs
16-Bit RISC Architecture,
125-ns Instruction Cycle Time
12-Bit A/D Converter With Internal
Reference, Sample-and-Hold and Autoscan
Feature
16-Bit Timer With Three† or Seven‡
Capture/Compare-With-Shadow Registers,
Timer_B
16-Bit Timer With Three Capture/Compare
Registers, Timer_A
On-Chip Comparator
Serial Communication Interface (USART),
Select Asynchronous UART or
Synchronous SPI by Software;
Two USARTs (USART0, USART1) In
MSP430x44x Devices
One USART (USART0) In MSP430x43x
Devices
Brownout Detector
Supply Voltage Supervisor/Monitor With
Programmable Level Detection
D Serial Onboard Programming,
D
D
D
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
Integrated LCD Driver for Up to
160 Segments
Family Members Include:
– MSP430F435:
16KB+256B Flash Memory,
512B RAM
– MSP430F436:
24KB+256B Flash Memory,
1KB RAM
– MSP430F437:
32KB+256B Flash Memory,
1KB RAM
– MSP430F447:
32KB+256B Flash Memory,
1KB RAM
– MSP430F448:
48KB+256B Flash Memory,
2KB RAM
– MSP430F449:
60KB+256B Flash Memory,
2KB RAM
For Complete Module Descriptions, See
The MSP430x4xx Family User’s Guide,
Literature Number SLAU056
† ’F435, ’F436, and ’F437 devices
‡ ’F447, ’F448, and ’F449 devices
description
The Texas Instruments MSP430 series is an ultralow-power microcontroller family consisting of several devices
featuring different sets of modules targeted to various applications. The microcontroller is designed to be battery
operated for use in extended-time applications. The MSP430 achieves maximum code efficiency with its 16-bit
RISC architecture, 16-bit CPU-integrated registers, and a constant generator. The digitally-controlled oscillator
provides wake-up from low-power mode to active mode in less than 6 µs. The MSP430x43x and the
MSP430x44x series are microcontroller configurations with two built-in 16-bit timers, a fast 12-bit A/D converter,
one or two universal serial synchronous/asynchronous communication interfaces (USART), 48 I/O pins, and
a liquid crystal driver (LCD) with up to 160 segments.
Typical applications include sensor systems that capture analog signals, convert them to digital values, and
process and transmit the data to a host system, or process this data and displays it on a LCD panel. The timers
make the configurations ideal for industrial control applications such as ripple counters, digital motor control,
EE-meters, hand-held meters, etc. The hardware multiplier enhances the performance and offers a broad code
and hardware-compatible family solution.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2002, Texas Instruments Incorporated
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SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
–40°C to 85°C
PLASTIC 80-PIN QFP
(PN)
PLASTIC 100-PIN QFP
(PZ)
MSP430F435IPN†
MSP430F436IPN†
MSP430F437IPN†
MSP430F435IPZ
MSP430F436IPZ
MSP430F437IPZ
MSP430F447IPZ
MSP430F448IPZ
MSP430F449IPZ
† Advanced Information
AVCC
DVSS1
AVSS
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
TDI
TDO/TDI
XT2IN
XT2OUT
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/TBOUTH/SVSOUT
PN PACKAGE
(TOP VIEW)
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
P1.6/CA0
pin designation, MSP430x435IPN, MSP430x436IPN, MSP430x437IPN†
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
60
2
59
3
58
4
57
5
56
6
55
7
54
8
53
9
10
11
MSP430F435IPN
MSP430F436IPN
MSP430F437IPN
52
51
50
12
49
13
48
14
47
15
46
16
45
17
44
18
43
19
42
20
41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P4.0/S9
S10
S11
S12
S13
S14
S15
S16
S17
P2.7/ADC12CLK/S18
P2.6/CAOUT/S19
S20
S21
S22
S23
P3.7/S24
P3.6/S25
P3.5/S26
P3.4/S27
P3.3/UCLK0/S28
DVCC1
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7/SVSin
VREF+
XIN
XOUT/TCLK
VeREF+
VREF–/VeREF–
P5.1/S0
P5.0/S1
P4.7/S2
P4.6/S3
P4.5/S4
P4.4/S5
P4.3/S6
P4.2/S7
P4.1/S8
2
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P1.7CA1
P2.0/TA2
P2.1/TB0
P2.2/TB1
P2.3/TB2
P2.4/UTXD0
P2.5/URXD0
DVSS2
DVCC2
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P3.0/STE0/S31
P3.1/SIMO0/S30
P3.2/SOMI0/S29
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
pin designation, MSP430x435IPZ, MSP430x436IPZ, MSP430x437IPZ
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
AVCC
DVSS1
AVSS
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
TDI
TDO/TDI
XT2IN
XT2OUT
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
P1.6/CA0
P1.7/CA1
P2.0/TA2
P2.1/TB0
P2.2/TB1
P2.3/TB2
PZ PACKAGE
(TOP VIEW)
MSP430F435IPZ
MSP430F436IPZ
MSP430F437IPZ
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P2.4/UTXD0
P2.5/URXD0
P2.6/CAOUT
P2.7/ADC12CLK
P3.0/STE0
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
DVSS2
DVCC2
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P4.2/S39
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
P4.7/S34
P4.6/S35
P4.5/S36
P4.4/S37
P4.3/S38
DVCC1
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7/SVSin
VREF+
XIN
XOUT/TCLK
VeREF+
VREF–/VeREF–
P5.1/S0
P5.0/S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
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SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
pin designation, MSP430x447IPZ, MSP430x448IPZ, MSP430x449IPZ
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
AVCC
DVSS1
AVSS
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
TDI
TDO/TDI
XT2IN
XT2OUT
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
P1.6/CA0
P1.7/CA1
P2.0/TA2
P2.1/TB0
P2.2/TB1
P2.3/TB2
PZ PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
MSP430F447IPZ
MSP430F448IPZ
MSP430F449IPZ
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
P4.7/S34
P4.6/S35
P4.5/UCLK1/S36
P4.4/SOMI1/S37
4.3/SIMO1/S38
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DVCC1
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7/SVSin
VREF+
XIN
XOUT/TCLK
VeREF+
VREF–/VeREF–
P5.1/S0
P5.0/S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
4
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75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P2.4/UTXD0
P2.5/URXD0
P2.6/CAOUT
P2.7/ADC12CLK
P3.0/STE0
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
P3.4/TB3
P3.5/TB4
P3.6/TB5
P3.7/TB6
P4.0/UTXD1
P4.1/URXD1
DVSS2
DVCC2
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P4.2/STE1/S39
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
MSP430x43x functional block diagrams
XIN
XOUT/TCLK
Oscillator
XT2IN
FLL+
DVCC
DVSS
AVCC
AVSS
RST/NMI
ACLK
16 kB Flash
512 B RAM
12 Bit ADC
SMCLK
24 kB Flash
1 kB RAM
8 Channels
32 kB Flash
1 kB RAM
<10 µs Conv.
XT2OUT
P5
P6
I/O Port 5/6
P3
P4
I/O Port 3/4
16 I/Os
P1
P2
I/O Port 1/2
USART0
16 I/Os, With
UART or
SPI
Function
Interrupt
Capability
MCLK
Test
MAB,
4 Bit
MAB, 16 Bit
JTAG
CPU
MCB
Emulation
Module
Incl. 16 Reg.
Bus
Conv
MDB, 16 Bit
MDB, 8 Bit
4
TMS
Watchdog
Timer
TCK
TDI
15 / 16 Bit
TDO/TDI
Timer_B3
3 CC–Reg
Shadow
Reg.
Timer_A3
POR
SVS
Brownout
3 CC-Reg.
Comparator
A
Basic
Timer1
1 Interrupt
Vector
LCD
160
Segments
1,2,3,4 MUX
fLCD
MSP430x44x functional block diagrams
XIN
XOUT/TCLK
Oscillator
XT2IN
FLL+
DVCC
DVSS
AVCC
AVSS
RST/NMI
ACLK
32 kB Flash
1 kB RAM
12 Bit ADC
SMCLK
48 kB Flash
2 kB RAM
8 Channels
60 kB Flash
2 kB RAM
<10 µs Conv.
XT2OUT
P5
P6
I/O Port 5/6
P3
P4
I/O Port 3/4
16 I/Os
P1
P2
I/O Port 1/2
USART0
USART1
16 I/Os, With
UART or
SPI
Function
Interrupt
Capability
MCLK
Test
MAB,
4 Bit
MAB, 16 Bit
JTAG
CPU
MCB
Emulation
Module
Incl. 16 Reg.
Bus
Conv
MDB, 16 Bit
MDB, 8 Bit
4
TMS
Multipy
TCK
MPY, MPYS
MAC,MACS
8×8 Bit
8×16 Bit
16×8 Bit
16×16 Bit
TDI
TDO/TDI
Watchdog
Timer
15 / 16 Bit
Timer_B7
7 CC-Reg.
Shadow
Reg.
Timer_A3
3 CC-Reg.
POR
SVS
Brownout
Comparator
A
Basic
Timer1
1 Interrupt
Vector
LCD
160
Segments
1,2,3,4 MUX
fLCD
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SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
MSP430x43x Terminal Functions
TERMINAL
PN
NAME
NO.
PZ
I/O
NAME
NO.
DESCRIPTION
I/O
DVCC1
1
2
I/O
DVCC1
P6.3/A3
1
P6.3/A3
2
I/O
General-purpose digital I/O, analog input a3—12-bit ADC
P6.4/A4
3
I/O
P6.4/A4
3
I/O
General-purpose digital I/O, analog input a4—12-bit ADC
P6.5/A5
4
I/O
P6.5/A5
4
I/O
General-purpose digital I/O, analog input a5—12-bit ADC
P6.6/A6
5
I/O
P6.6/A6
5
I/O
General-purpose digital I/O, analog input a6—12-bit ADC
P6.7/A7/SVSin
6
I/O
P6.7/A7/SVSin
6
I/O
General-purpose digital I/O, analog input a7—12-bit ADC, analog input
to brownout, supply voltage supervisor
VREF+
7
O
VREF+
7
O
Output of positive terminal of the reference voltage in the ADC
XIN
8
I
XIN
8
I
Input port for crystal oscillator XT1. Standard or watch crystals can be
connected.
XOUT/TCLK
9
I/O
XOUT/TCLK
9
I/O
VeREF+
10
I
VeREF+
10
I
Input for an external reference voltage to the ADC
VREF–/VeREF–
11
I
VREF–/VeREF–
11
I
Negative terminal for the ADC’s reference voltage for both sources, the
internal reference voltage, or an external applied reference voltage.
P5.1/S0
12
I/O
P5.1/S0
12
I/O
General-purpose I/O / LCD segment output 0
P5.0/S1
13
I/O
P5.0/S1
13
I/O
General-purpose I/O / LCD segment output 1
P4.7/S2
14
I/O
S2
14
O
General-purpose I/O / LCD segment output 2
P4.6/S3
15
I/O
S3
15
O
General-purpose I/O / LCD segment output 3
P4.5/S4
16
I/O
S4
16
O
General-purpose I/O / LCD segment output 4
P4.4/S5
17
I/O
S5
17
O
General-purpose I/O / LCD segment output 5
P4.3/S6
18
I/O
S6
18
O
General-purpose I/O / LCD segment output 6
P4.2/S7
19
I/O
S7
19
O
General-purpose I/O / LCD segment output 7
P4.1/S8
20
I/O
S8
20
O
General-purpose I/O / LCD segment output 8
P4.0/S9
21
I/O
S9
21
O
General-purpose I/O / LCD segment output 9
S10
22
O
S10
22
O
LCD segment output 10
S11
23
O
S11
23
O
LCD segment output 11
S12
24
O
S12
24
O
LCD segment output 12
S13
25
O
S13
25
O
LCD segment output 13
S14
26
O
S14
26
O
LCD segment output 14
S15
27
O
S15
27
O
LCD segment output 15
S16
28
O
S16
28
O
LCD segment output 16
S17
29
O
S17
29
O
LCD segment output 17
P2.7/ADC12CLK/
S18
30
I/O
S18
30
O
General-purpose digital I/O / conversion clock—12-bit ADC
LCD segment output 18
P2.6/CAOUT/S19
31
I/O
S19
31
O
General-purpose digital I/O / Comparator_A output / LCD segment
output 19
S20
32
O
S20
32
O
LCD segment output 20
S21
33
O
S21
33
O
LCD segment output 21
S22
34
O
S22
34
O
LCD segment output 22
S23
35
O
S23
35
O
LCD segment output 23
P3.7/S24
36
I/O
S24
36
O
General-purpose digital I/O / LCD segment output 24
P3.6/S25
37
I/O
S25
37
O
General-purpose digital I/O / LCD segment output 25
P3.5/S26
38
I/O
S26
38
O
General-purpose digital I/O / LCD segment output 26
P3.4/S27
39
I/O
S27
39
O
General-purpose digital I/O / LCD segment output 27
6
Digital supply voltage, positive terminal. Supplies all digital parts
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• DALLAS, TEXAS 75265
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
MSP430x43x Terminal Functions (Continued)
TERMINAL
PN
PZ
I/O
NAME
NO.
DESCRIPTION
I/O
NAME
NO.
P3.3/UCLK0/S28
40
I/O
S28
40
O
General-purpose digital I/O / ext. clock i/p—USART0/UART or SPI
mode, clock o/p—USART0/SPI mode / LCD segment output 28
P3.2/SOMI0/S29
41
I/O
S29
41
O
General-purpose digital I/O / slave out/master in of USART0/SPI mode
/ LCD segment output 29
P3.1/SIMO0/S30
42
I/O
S30
42
O
General-purpose digital I/O / slave out/master out of USART0/SPI
mode / LCD segment output 30
P3.0/STE0/S31
43
I/O
S31
43
O
General-purpose digital I/O / slave transmit enable-USART0/SPI
mode / LCD segment output 31
S32
44
O
LCD segment output 32
S33
45
O
LCD segment output 33
P4.7/S34
46
I/O
General-purpose digital I/O / LCD segment output 34
P4.6/S35
47
I/O
General-purpose digital I/O / LCD segment output 35
P4.5/S36
48
I/O
General-purpose digital I/O / LCD segment output 36
P4.4/S37
49
I/O
General-purpose digital I/O / LCD segment output 37
P4.3/S38
50
I/O
General-purpose digital I/O / LCD segment output 38
P4.2/S39
51
I/O
General-purpose digital I/O / LCD segment output 39
COM0
44
O
COM0
52
O
COM0–3 are used for LCD backplanes.
P5.2/COM1
45
I/O
P5.2/COM1
53
I/O
General-purpose digital I/O / common output, COM0–3 are used for
LCD backplanes.
P5.3/COM2
46
I/O
P5.3/COM2
54
I/O
General-purpose digital I/O / common output, COM0–3 are used for
LCD backplanes.
P5.4/COM3
47
I/O
P5.4/COM3
55
I/O
General-purpose digital I/O / common output, COM0–3 are used for
LCD backplanes.
R03
48
I
R03
56
I
P5.5/R13
49
I/O
P5.5/R13
57
I/O
General-purpose digital I/O / input port of third most positive analog
LCD level (V4 or V3)
P5.6/R23
50
I/O
P5.6/R23
58
I/O
General-purpose digital I/O / input port of second most positive analog
LCD level (V2)
P5.7/R33
51
I/O
P5.7/R33
59
I/O
General-purpose digital I/O / output port of most positive analog LCD
level (V1)
DVCC2
52
53
DVCC2
DVSS2
60
DVSS2
P4.1
62
I/O
General-purpose digital I/O
P4.0
63
I/O
General-purpose digital I/O
P3.7
64
I/O
General-purpose digital I/O
P3.6
65
I/O
General-purpose digital I/O
P3.5
66
I/O
General-purpose digital I/O
P3.4
67
I/O
General-purpose digital I/O
P3.3/UCLK0
68
I/O
General-purpose digital I/O / external clock input—USART0/UART or
SPI mode, clock output—USART0/SPI mode
P3.2/SOMI0
69
I/O
General-purpose digital I/O / slave out/master in of USART0/SPI mode
P3.1/SIMO0
70
I/O
General-purpose digital I/O / slave in/master out of USART0/SPI mode
P3.0/STE0
71
I/O
General-purpose digital I/O / slave transmit enable USART0/SPI mode
P2.7/ADC12CLK
72
I/O
General-purpose digital I/O / conversion clock—12-bit ADC
P2.6/CAOUT
73
I/O
General-purpose digital I/O / Comparator_A output
P2.5/URXD0
74
I/O
General-purpose digital I/O / receive data in—USART0/UART mode
P2.5/URXD0
54
I/O
Input port of fourth positive (lowest) analog LCD level (V5)
61
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SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
MSP430x43x Terminal Functions (Continued)
TERMINAL
PN
NAME
NO.
PZ
I/O
NAME
NO.
DESCRIPTION
I/O
P2.4/UTXD0
55
I/O
P2.4/UTXD0
75
I/O
General-purpose digital I/O / transmit data out—USART0/UART mode
P2.3/TB2
56
I/O
P2.3/TB2
76
I/O
General-purpose digital I/O / Timer_B3 CCR2.
Capture: CCI2A/CCI2B input, compare: Out2 output
P2.2/TB1
57
I/O
P2.2/TB1
77
I/O
General-purpose digital I/O / Timer_B3 CCR1.
Capture: CCI1A/CCI1B input, compare: Out1 output
P2.1/TB0
58
I/O
P2.1/TB0
78
I/O
General-purpose digital I/O / Timer_B3 CCR0.
Capture: CCI0A/CCI0B input, compare: Out0 output
P2.0/TA2
59
I/O
P2.0/TA2
79
I/O
General-purpose digital I/O / Timer_A
Capture: CCI2A input, compare: Out2 output
P1.7/CA1
60
I/O
P1.7/CA1
80
I/O
General-purpose digital I/O / Comparator_A input
P1.6/CA0
61
I/O
P1.6/CA0
81
I/O
General-purpose digital I/O / Comparator_A input
82
I/O
General-purpose digital I/O / Timer_A, clock signal TACLK input /
ACLK output (divided by 1, 2, 4, or 8)
P1.5/TACLK/
ACLK
62
I/O
P1.5/TACLK/
ACLK
P1.4/TBCLK/
SMCLK
63
I/O
P1.4/TBCLK/
SMCLK
83
I/O
General-purpose digital I/O / input clock TBCLK—Timer_B3 / submain
system clock SMCLK output
P1.3/TBOUTH/
SVSOUT
64
I/O
P1.3/TBOutH/
SVSOut
84
I/O
General-purpose digital I/O / switch all PWM digital output ports to high
impedance—Timer_B3 TB0 to TB2 / SVS: output of SVS comparator
P1.2/TA1
65
I/O
P1.2/TA1
85
I/O
General-purpose digital I/O / Timer_A, Capture: CCI1A, compare:
Out1 output
P1.1/TA0/MCLK
66
I/O
P1.1/TA0/MCLK
86
I/O
General-purpose digital I/O / Timer_A. Capture: CCI0B / MCLK output.
Note: TA0 is only an input on this pin.
P1.0/TA0
67
I/O
P1.0/TA0
87
I/O
General-purpose digital I/O / Timer_A. Capture: CCI0A input,
compare: Out0 output
XT2OUT
68
O
XT2OUT
88
O
Output terminal of crystal oscillator XT2
XT2IN
69
I
XT2IN
89
I
Input port for crystal oscillator XT2. Only standard crystals can be
connected.
TDO/TDI
70
I/O
TDO/TDI
90
I/O
Test data output port. TDO/TDI data output or programming data input
terminal
TDI
71
I
TDI
91
I
Test data input. TDI is used as a data input port. The device protection
fuse is connected to TDI.
TMS
72
I
TMS
92
I
Test mode select. TMS is used as an input port for device programming
and test.
TCK
73
I
TCK
93
I
Test clock. TCK is the clock input port for device programming and test.
RST/NMI
74
I
RST/NMI
94
I
General-purpose digital I/O / reset input or nonmaskable interrupt input
port
P6.0/A0
75
I/O
P6.0/A0
95
I/O
General-purpose digital I/O / analog input a0 – 12-bit ADC
P6.1/A1
76
I/O
P6.1/A1
96
I/O
General-purpose digital I/O / analog input a1 – 12-bit ADC
P6.2/A2
77
I/O
P6.2/A2
97
I/O
General-purpose digital I/O / analog input a2 – 12-bit ADC
AVSS
78
AVSS
98
Negative terminal that supplies SVS, brownout, oscillator, FLL+,
comparator_A, port 1, and LCD resistive divider circuitry.
DVSS1
79
DVSS1
99
Digital supply voltage, negative terminal. Supplies all digital parts,
except those which are supplied via AVCC/AVSS.
AVCC
80
AVCC
100
Positive terminal that supplies SVS, brownout, oscillator, FLL+,
comparator_A, port 1, and LCD resistive divider circuitry; must not
power up prior to DVCC1/DVCC2.
8
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MSP430x44x Terminal Functions
TERMINAL
PN
NAME
I/O
DESCRIPTION
NO.
DVCC1
1
P6.3/A3
2
I/O
Digital supply voltage, positive terminal. Supplies all digital parts
General-purpose digital I/O, analog input a3—12-bit ADC
P6.4/A4
3
I/O
General-purpose digital I/O, analog input a4—12-bit ADC
P6.5/A5
4
I/O
General-purpose digital I/O, analog input a5—12-bit ADC
P6.6/A6
5
I/O
General-purpose digital I/O, analog input a6—12-bit ADC
P6.7/A7/SVSin
6
I/O
General-purpose digital I/O, analog input a7—12-bit ADC, analog input to brownout, supply voltage
supervisor
VREF+
XIN
7
O
Output of positive terminal of the reference voltage in the ADC
8
I
Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT/TCLK
9
I/O
VeREF+
10
I
Input for an external reference voltage to the ADC
VREF–/VeREF–
11
I
Negative terminal for the ADC’s reference voltage for both sources, the internal reference voltage, or an
external applied reference voltage
P5.1/S0
12
O
General-purpose digital I/O, LCD segment output 0
P5.0/S1
13
O
General-purpose digital I/O, LCD segment output 1
S2
14
O
LCD segment output 2
S3
15
O
LCD segment output 3
S4
16
O
LCD segment output 4
S5
17
O
LCD segment output 5
S6
18
O
LCD segment output 6
S7
19
O
LCD segment output 7
S8
20
O
LCD segment output 8
S9
21
O
LCD segment output 9
S10
22
O
LCD segment output 10
S11
23
O
LCD segment output 11
S12
24
O
LCD segment output 12
S13
25
O
LCD segment output 13
S14
26
O
LCD segment output 14
S15
27
O
LCD segment output 15
S16
28
O
LCD segment output 16
S17
29
O
LCD segment output 17
S18
30
O
LCD segment output 18
S19
31
O
LCD segment output 19
S20
32
O
LCD segment output 20
S21
33
O
LCD segment output 21
S22
34
O
LCD segment output 22
S23
35
O
LCD segment output 23
S24
36
O
LCD segment output 24
S25
37
O
LCD segment output 25
S26
38
O
LCD segment output 26
S27
39
O
LCD segment output 27
S28
40
O
LCD segment output 28
Output terminal of crystal oscillator XT1 or test clock input
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SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
MSP430x44x Terminal Functions (Continued)
TERMINAL
PN
NAME
I/O
DESCRIPTION
NO.
S29
41
O
LCD segment output 29
S30
42
O
LCD segment output 30
S31
43
O
LCD segment output 31
S32
44
O
LCD segment output 32
S33
45
O
LCD segment output 33
P4.7/S34
46
I/O
General-purpose digital I/O / LCD segment output 34
P4.6/S35
47
I/O
General-purpose digital I/O / LCD segment output 35
P4.5/UCLK1/S36
48
I/O
General-purpose digital I/O / external clock input—USART1/UART or SPI mode, clock
output—USART1/SPI MODE / LCD segment output 36
P4.4/SOMI1/S37
49
I/O
General-purpose digital I/O / slave out/master in of USART1/SPI mode / LCD segment output 37
P4.3/SIMO1/S38
50
I/O
General-purpose digital I/O / slave in/master out of USART1/SPI mode / LCD segment output 38
P4.2/STE1/S39
51
I/O
General-purpose digital I/O / slave transmit enable—USART1/SPI mode / LCD segment output 39
COM0
52
O
COM0–3 are used for LCD backplanes.
P5.2/COM1
53
I/O
General-purpose digital I/O / Common output, COM0–3 are used for LCD backplanes.
P5.3/COM2
54
I/O
General-purpose digital I/O / Common output, COM0–3 are used for LCD backplanes.
P5.4/COM3
55
I/O
General-purpose digital I/O / Common output, COM0–3 are used for LCD backplanes.
R03
56
I
P5.5/R13
57
I/O
General-purpose digital I/O / Input port of third most positive analog LCD level (V4 or V3)
P5.6/R23
58
I/O
General-purpose digital I/O / Input port of second most positive analog LCD level (V2)
P5.7/R33
59
I/O
General-purpose digital I/O / Output port of most positive analog LCD level (V1)
DVCC2
60
DVSS2
61
P4.1/URXD1
62
I/O
General-purpose digital I/O / receive data in—USART1/UART mode
P4.0/UTXD1
63
I/O
General-purpose digital I/O / transmit data out—USART1/UART mode
P3.7/TB6
64
I/O
General-purpose digital I/O / Timer_B7 CCR6 / Capture: CCI6A/CCI6B input, compare: Out6 output
P3.6/TB5
65
I/O
General-purpose digital I/O / Timer_B7 CCR5 / Capture: CCI5A/CCI5B input, compare: Out5 output
P3.5/TB4
66
I/O
General-purpose digital I/O / Timer_B7 CCR4 / Capture: CCI4A/CCI4B input, compare: Out4 output
P3.4/TB3
67
I/O
General-purpose digital I/O / Timer_B7 CCR3 / Capture: CCI3A/CCI3B input, compare: Out3 output
P3.3/UCLK0
68
I/O
General-purpose digital I/O / external clock input—USART0/UART or SPI mode, clock
output—USART0/SPI mode
P3.2/SOMI0
69
I/O
General-purpose digital I/O / slave out/master in of USART0/SPI mode
P3.1/SIMO0
70
I/O
General-purpose digital I/O / slave in/master out of USART0/SPI mode
P3.0/STE0
71
I/O
General-purpose digital I/O / slave transmit enable—USART0/SPI mode
P2.7/ADC12CLK
72
I/O
General-purpose digital I/O / conversion clock—12-bit ADC
P2.6/CAOUT
73
I/O
General-purpose digital I/O / Comparator_A output
P2.5/URXD0
74
I/O
General-purpose digital I/O / receive data in—USART0/UART mode
P2.4/UTXD0
75
I/O
General-purpose digital I/O / transmit data out—USART0/UART mode
P2.3/TB2
76
I/O
General-purpose digital I/O / Timer_B7 CCR2. Capture: CCI2A/CCI2B input, compare: Out2 output
P2.2/TB1
77
I/O
General-purpose digital I/O / Timer_B7 CCR1. Capture: CCI1A/CCI1B input, compare: Out1 output
P2.1/TB0
78
I/O
General-purpose digital I/O / Timer_B7 CCR0. Capture: CCI0A/CCI0B input, compare: Out0 output
P2.0/TA2
79
I/O
General-purpose digital I/O / Timer_A Capture: CCI2A input, compare: Out2 output
P1.7/CA1
80
I/O
General-purpose digital I/O / Comparator_A input
10
Input port of fourth positive (lowest) analog LCD level (V5)
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MSP430x44x Terminal Functions (Continued)
TERMINAL
PN
NAME
I/O
DESCRIPTION
NO.
P1.6/CA0
81
I/O
General-purpose digital I/O / Comparator_A input
P1.5/TACLK/
ACLK
82
I/O
General-purpose digital I/O / Timer_A, clock signal TACLK input / ACLK output (divided by 1, 2, 4, or 8)
P1.4/TBCLK/
SMCLK
83
I/O
General-purpose digital I/O / input clock TBCLK—Timer_B7 / submain system clock SMCLK output
P1.3/TBOutH/
SVSOut
84
I/O
General-purpose digital I/O / switch all PWM digital output ports to high impedance—Timer_B7 TB0 to TB6
/ SVS: output of SVS comparator
P1.2/TA1
85
I/O
General-purpose digital I/O / Timer_A, Capture: CCI1A, compare: Out1 output
P1.1/TA0/MCLK
86
I/O
General-purpose digital I/O / Timer_A. Capture: CCI0B / MCLK output.
Note: TA0 is only an input on this pin.
P1.0/TA0
87
I/O
General-purpose digital I/O / Timer_A. Capture: CCI0A input, compare: Out0 output
XT2OUT
88
O
Output terminal of crystal oscillator XT2
XT2IN
89
I
Input port for crystal oscillator XT2. Only standard crystals can be connected.
TDO/TDI
90
I/O
TDI
91
I
Test data input. TDI is used as a data input port. The device protection fuse is connected to TDI.
TMS
92
I
Test mode select. TMS is used as an input port for device programming and test.
TCK
93
I
Test clock. TCK is the clock input port for device programming and test.
RST/NMI
94
I
Reset input or nonmaskable interrupt input port
P6.0/A0
95
I/O
General-purpose digital I/O, analog input a0—12-bit ADC
P6.1/A1
96
I/O
General-purpose digital I/O, analog input a1—12-bit ADC
P6.2/A2
97
I/O
General-purpose digital I/O, analog input a2—12-bit ADC
AVSS
98
DVSS1
99
AVCC
100
Test data output port. TDO/TDI data output or programming data input terminal
Negative terminal that supplies SVS, brownout, oscillator, FLL+, comparator_A, port 1, and LCD resistive
divider circuitry.
Digital supply voltage, negative terminal. Supplies all digital parts, except those which are supplied via
AVCC/AVSS.
Positive terminal that supplies SVS, brownout, oscillator, FLL+, comparator_A, port 1, and LCD resistive
divider circuitry; must not power up prior to DVCC1/DVCC2.
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SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
short-form description
processing unit
The processing unit is based on a consistent and orthogonal CPU and instruction set. This design structure
results in a RISC-like architecture, highly transparent to the application development and notable for its ease
of programming. All operations, other than program-flow instructions, are consequently performed as register
operations in conjunction with seven addressing modes for source and four modes for destination operand.
CPU
The CPU has 16 registers that provide reduced
instruction execution time. This reduces the
register-to-register operation execution time to
one cycle of the processor frequency.
Program Counter
PC/R0
Stack Pointer
SP/R1
Status Register
Constant Generator
SR/CG1/R2
CG2/R3
Four of the registers are reserved for special use
as program counter, stack pointer, status register,
and constant generator. The remaining registers
are available as general-purpose registers.
General-Purpose Register
R4
General-Purpose Register
R5
Peripherals are connected to the CPU using
a data address and control bus, and can be
easily handled with all memory manipulation
instructions.
General-Purpose Register
R14
General-Purpose Register
R15
instruction set
The instruction set for this register-to-register architecture constitutes a powerful and easy-to-use assembler
language. The instruction set consists of 51 instructions with three formats and seven address modes. Table 1
provides a summary and example of the three types of instruction formats; the address modes are listed in
Table 2.
Table 1. Instruction Word Formats
Dual operands, source-destination
e.g. ADD R4,R5
R4 + R5 –––> R5
Single operands, destination only
e.g. CALL
PC ––>(TOS), R8––> PC
Relative jump, un/conditional
e.g. JNE
R8
Jump-on-equal bit = 0
Each instruction operating on word and byte data is identified by the suffix B.
Examples:
12
WORD INSTRUCTIONS
BYTE INSTRUCTIONS
MOV
EDE, TONI
MOV.B
EDE,TONI
ADD
#235h, and MEM
ADD.B
#35h, and MEM
PUSH
R5
PUSH.B
R5
SWPB
R5
—
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instruction set (continued)
Table 2. Address Mode Descriptions
ADDRESS MODE
S D
Register
n n
MOV Rs,Rd
MOV R10,R11
Indexed
n n
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
Symbolic (PC relative)
n n
MOV EDE,TONI
M(EDE) ––> M(TONI)
n n
MOV and MEM,and
TCDAT
M(MEM) ––> M(TCDAT)
Absolute
SYNTAX
EXAMPLE
OPERATION
R10
––> R11
M(2+R5)––> M(6+R6)
Indirect
n
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) ––> M(Tab+R6)
Indirect
autoincrement
n
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) ––> R11
R10 + 2––> R10
Immediate
n
MOV #X,TONI
MOV #45,TONI
NOTE: S = source
#45
––> M(TONI)
D = destination
Computed branches (BR) and subroutine call (CALL) instructions use the same address modes as other
instructions. These address modes provide indirect addressing, which is ideally suited for computed branches
and calls. The full use of this programming capability results in a program structure which is different from
structures used with conventional 8- and 16-bit controllers. For example, numerous routines can be easily
designed to deal with pointers and stacks instead of using flag-type programs for flow control.
operating modes
The MSP430 operating modes support various advanced requirements for ultralow power and ultralow energy
consumption. The intelligent management of the operations during the different module operation modes and
CPU states achieves this. The requirements are fully supported during interrupt event handling. An interrupt
event awakens the system from each of the various operating modes and returns with the RETI instruction to
the mode that was selected before the interrupt event. The clocks used are ACLK, SMCLK and MCLK.
ACLK is the crystal frequency, MCLK and SMCLK are either multiples of ACLK or come from the crystal
oscillators. MCLK and SMCLK are used as the system clock and subsystem clock.
The software can configure six operating modes:
D Active mode AM; SCG1=0, SCG0=0, OscOff=0, CPUOff=0:
CPU clocks are active
D Low-power mode 0 (LPM0); SCG1=0, SCG0=0, OscOff=0, CPUOff=1:
–
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
FLL+ Loop control remains active
D Low-power mode 1 (LPM1); SCG1=0, SCG0=1, OscOff=0, CPUOff=1:
–
CPU is disabled
FLL+ Loop control is disabled
ACLK and SMCLK remain active. MCLK is disabled
D Low-power mode 2 (LPM2); SCG1=1, SCG0=0, OscOff=0, CPUOff=1:
–
CPU is disabled
MCLK and FLL+ loop control and DCOCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
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SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
operating modes (continued)
D Low-power mode 3 (LPM3); SCG1=1, SCG0=1, OscOff=0, CPUOff=1:
–
CPU is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
D Low-power mode 4 (LPM4); SCG1=X, SCG0=X, OscOff=1, CPUOff=1:
–
CPU is disabled
ACLK is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped
SMCLK is disabled with SMCLKOFF bit in register FLL+CTL1 (054h). The selected clock source (DCOCLK or
XT2CLK) can be switched off only if SMCLKOFF = 1.
NOTE:
Peripheral operation is not halted by CPUOff. Peripherals are controlled by their individual control
registers.
The various operating modes are controlled by the software through control of the internal clock system
operation. This clock system gives a large combination of hardware and software capabilities to run the
application with the lowest power consumption and with optimized system costs:
D Use of the internal clock (DCO) generator without any external components
D Selection of an external crystal or ceramic resonator for lowest frequency and cost
D Application of an external clock source
The control bits that most influence the operation of the clock system and support fast turnon from low power
operating modes are located in the status register SR. Four bits control the CPU and the system clock generator:
SCG1, SCG0, OscOff, and CPUOff.
15
9
Reserved for Future
Enhancements
rw–0
8
V
rw–0
7
SCG1
rw–0
0
SCG0
rw–0
OscOff
rw–0
CPUOff
rw–0
GIE
rw–0
N
rw–0
Z
rw–0
C
rw–0
CPUOff, SCG1, SCG0, and OscOff are the most important bits in low-power control when the basic function
of the system clock generator is established. They are pushed to the stack whenever an interrupt is accepted
and saved for returning to the operation before an interrupt request. They can be manipulated via indirect access
to the data on the stack during execution of an interrupt handler so that program execution can resume in
another power operating mode after return-from-interrupt.
14
CPUOff:
The CPUOff bit, when set, disables CPU (MCLK is disabled).
SCG0:
The SCG0 bit, when set, disables the FLL+ loop control.
SCG1:
The SCG1 bit, when set, disables the DCOCLK signal.
OscOff:
The OscOff bit, when set, disables the LFXT1 crystal oscillator.
DC generator:
When both SCG0 and SCG1 are set, the dc generator for the DCO is disabled.
XT2Off:
The XT2Off bit, when set, disables the XT2 crystal oscillator. XT2 is disabled only if it is unused for MCLK (SELM≠2 or CPUOff=1) and if it is unused for SMCLK (SELS=0 or
SMCLKOFF=1). Both conditions prevent disabling of XT2 accidentially.
SMCLKOFF:
SMCLKOFF, when set, switches off clock SMCLK.
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interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh – 0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 3. Interrupt Sources, Flags, and Vectors of 4xx Configurations
INTERRUPT SOURCE
Power-up
External Reset
Watchdog
Flash memory
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD
ADDRESS
PRIORITY
Reset
0FFFEh
15, highest
WDTIFG
KEYV
(see Note 1)
NMI
Oscillator Fault
Flash memory access violation
Timer_B7†
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1 and 3)
(Non)maskable
(Non)maskable
(Non)maskable
0FFFCh
14
CCIFG0 (see Note 2)
Maskable
0FFFAh
13
Timer_B7†
CCIFG1 to CCIFG6
TBIFG (see Notes 1 and 2)
Maskable
0FFF8h
12
Comparator_A
CAIFG
Maskable
0FFF6h
11
Watchdog Timer
WDTIFG
Maskable
0FFF4h
10
USART0 receive
URXIFG0
Maskable
0FFF2h
9
USART0 transmit
UTXIFG0
Maskable
0FFF0h
8
ADC
ADCIFG (see Notes 1 and 2)
Maskable
0FFEEh
7
Timer_A3
CCIFG0 (see Note 2)
Maskable
0FFECh
6
Timer_A3
CCIFG1, CCIFG2,
TAIFG (see Notes 1 and 2)
Maskable
0FFEAh
5
I/O port P1 (eight flags)
P1IFG.0 (see Notes 1 and 2)
To
P1IFG.7 (see Notes 1 and 2)
Maskable
0FFE8h
4
USART1 receive‡
URXIFG1
Maskable
0FFE6h
3
USART1 transmit‡
UTXIFG1
Maskable
0FFE4h
2
I/O port P2 (eight flags)
P2IFG.0 (see Notes 1 and 2)
To
P2IFG.7 (see Notes 1 and 2)
Maskable
0FFE2h
1
Basic Timer1
BTIFG
Maskable
0FFE0h
0, lowest
‡ ’43x uses Timer_B3 with CCIFG0, CCIFG1 to CCIFG2 flags, and TBIFG. ’44x uses Timer_B7 with CCIFG0, CCIFG1 to CCIFG6, and TBIFG
‡ USART1 is implemented in ’44x only.
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable can not disable
it.
special function registers
Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits
not allocated to a functional purpose are not physically present in the device. This arrangement provides simple
software access.
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SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
interrupt enable 1 and 2
7
Address
0h
6
UTXIE0
rw–0
URXIE0
rw–0
5
4
ACCVIE
NMIIE
rw–0
3
2
1
OFIE
rw–0
rw–0
0
WDTIE
rw–0
WDTIE:
Watchdog-timer-interrupt enable signal
OFIE:
Oscillator-fault-interrupt enable signal
NMIIE:
Nonmaskable-interrupt enable signal
ACCVIE:
(Non)maskable-interrupt enable signal, access violation if FLASH memory/module is busy
URXIE0:
USART0, UART, and SPI receive-interrupt enable signal
UTXIE0:
USART0, UART, and SPI transmit-interrupt enable signal
7
Address
6
BTIE
01h
rw–0
5
4
UTXIE1
URXIE1
rw–0
3
2
1
0
rw–0
URXIE1:
USART1, UART, and SPI receive-interrupt enable signal (MSP430F44x devices only)
UTXIE1:
USART1, UART, and SPI transmit-interrupt enable signal (MSP430F44x devices only)
BTIE:
Basic timer interrupt enable signal
interrupt flag register 1 and 2
7
Address
02h
6
UTXIFG0
rw–1
4
3
rw–0
rw–0
rw–1
OFIFG:
Flag set on oscillator fault
NMIIFG:
Set via RST/NMI pin
URXIFG0:
USART0, UART, and SPI receive flag
UTXIFG0:
USART0, UART, and SPI transmit flag
03h
6
BTIFG
rw
1
OFIFG
Set on overflow or security key violation or
reset on VCC power-on or reset condition at RST/NMI
7
2
NMIIFG
WDTIFG:
Address
16
5
URXIFG0
5
4
UTXIFG1
URXIFG1
rw–1
3
2
rw–0
URXIFG1:
USART1, UART, and SPI receive flag (MSP430F44x devices only)
UTXIFG1:
USART1, UART, and SPI transmit flag (MSP430F44x devices only)
BTIFG:
Basic timer flag
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0
WDTIFG
rw–0
1
0
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
module enable registers 1 and 2
7
UTXE0
Address
04h
rw–0
6
URXE0
USPIE0
5
4
3
2
1
rw–0
URXE0:
USART0, UART receive enable
UTXE0:
USART0, UART transmit enable
USPIE0:
USART0, SPI (synchronous peripheral interface) transmit and receive enable
Address
0
7
6
5
UTXE1
05h
rw–0
4
URXE1
USPIE1
3
2
1
0
rw–0
URXE1:
USART1, UART receive enable (MSP430F44x devices only)
UTXE1:
USART1, UART transmit enable (MSP430F44x devices only)
USPIE1:
USART1, SPI (synchronous peripheral interface) transmit and receive enable (MSP430F44x
devices only)
Bit Can Be Read and Written
Bit Can Be Read and Written. It Is Reset by PUC.
SFR Bit Not Present in Device
Legend: rw:
rw–0:
memory organization
MSP430F435
MSP430F436
MSP430F437
MSP430F447
MSP430F448
MSP430F449
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
16KB
0FFFFh – 0FFE0h
0FFFFh – 0C000h
24KB
0FFFFh – 0FFE0h
0FFFFh – 0A000h
32KB
0FFFFh – 0FFE0h
0FFFFh – 08000h
48KB
0FFFFh – 0FFE0h
0FFFFh – 04000h
60KB
0FFFFh – 0FFE0h
0FFFFh – 01100h
Information memory
Size
Flash
256 Byte
010FFh – 01000h
256 Byte
010FFh – 01000h
256 Byte
010FFh – 01000h
256 Byte
010FFh – 01000h
256 Byte
010FFh – 01000h
Boot memory
Size
ROM
1KB
0FFFh – 0C00h
1KB
0FFFh – 0C00h
1KB
0FFFh – 0C00h
1KB
0FFFh – 0C00h
1KB
0FFFh – 0C00h
Size
512 Byte
03FFh – 0200h
1KB
05FFh – 0200h
1KB
05FFh – 0200h
2KB
09FFh – 0200h
2KB
09FFh – 0200h
16-bit
8-bit
8-bit SFR
01FFh – 0100h
0FFh – 010h
0Fh – 00h
01FFh – 0100h
0FFh – 010h
0Fh – 00h
01FFh – 0100h
0FFh – 010h
0Fh – 00h
01FFh – 0100h
0FFh – 010h
0Fh – 00h
01FFh – 0100h
0FFh – 010h
0Fh – 00h
RAM
Peripherals
boot ROM containing bootstrap loader
The intention of the bootstrap loader is to download data into the flash memory module. Various write, read, and
erase operations are needed for a proper download environment.
functions of the bootstrap loader:
Definition of read:
write:
Apply data to pin P1.0/TA0 (BSLTX) and transmit peripheral registers or memory data to
pin P1.0/TA0.
Read data from pin P1.1/TA0/MCLK (BSLRX) and write it to flash memory.
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SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
boot ROM containing bootstrap loader (continued)
unprotected functions
Mass erase, erase of the main memory (segment 0 to segment n)
Access to the MSP430 via the bootstrap loader is protected. It must be enabled before any protected function
can be performed. The 256 bits in 0FFE0h to 0FFFFh provide the access key.
protected functions
All protected functions can be executed only if the access is enabled.
D Write/program byte into flash memory. The parameters passed are start address and number of bytes (the
flash segment-write feature of the flash memory is not supported and not used with the UART protocol).
D Segment erase of segment 0 to segment n in main memory, and segment erase of segments A and B in
the information memory
D Reading of all data in main memory and information memory
D Reading and writing to all peripheral modules and RAM
D Modifying PC and start program execution immediately
NOTE:
Unauthorized readout of code and data is prevented by the user’s definition of the data in the
interrupt memory locations.
features of the bootstrap loader are:
D
D
D
D
D
UART communication protocol, fixed to 9600 baud
Port pin P1.0/TA0 for transmit, P1.1/TA0/MCLK for receive
TI standard serial protocol definition
Loader implemented in flash memory version only
Program execution starts with the user vector at 0FFFEh or with the bootstrap loader (address 0C00h)
hardware resources used for serial input/output:
D
D
D
D
D
D
D
D
Pins P1.0/TA0 and P1.1/TA0/MCLK for serial data transmission
TCK and RST/NMI to start program execution at the reset or bootstrap loader vector
FLL+ module: SCFI0=0, SCFI1=098h, SCG0=1
Timer_A: Timer_A operates in continuous mode with SMCLK source selected, input divider set to 1, and
using CCR0 and polling CCIFG0.
WDT: Watchdog Timer is halted
Interrupt: GIE=0, NMIIE=0, OFIFG=0, ACCVIFG=0
Using the stack depends on the start condition:
Starting via RST/NMI and TCK pin: 6 bytes used, stack pointer initialized to 220h
Start via SW (e.g., BR &0C02h): 6 bytes used, on top of the actual stack pointer
RAM: 20 bytes used, start at address 0200h, last address used: 0219h
NOTE:
When writing RAM data via the bootstrap loader, make sure the stack is outside the range of data
to be written.
Program execution begins with the user’s reset vector at FFFEh (standard method) if TCK is held high while
RST/NMI goes from low to high.
18
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SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
boot ROM containing bootstrap loader (continued)
VCC
RST/NMI
TCK
Reset Condition
User program starts
Program execution begins with the bootstrap vector at 0C00h (boot ROM) if TCK has applied a minimum of two
negative edges at signal/pin TCK, and if TCK is low while RST/NMI goes from low to high.
VCC
RST/NMI
TCK
Reset Condition
Bootloader starts
TMS
NOTES: 4. The default level of TCK is high. An active low has to be applied to enter the bootstrap loader. Other MSP430s which have a pin
function used with a low default level can use an inverted signal.
5. The TMS signal must be high while TCK clocks are applied. This ensures that the JTAG controller function remains in its default
mode.
The bootstrap loader does not start (via the vector in address 0C00h) if:
D
D
D
D
D
There are less than two negative edges at TCK while RST/NMI is low
TCK is high when RST/NMI goes from low to high
JTAG has control over the MSP430 resources
The supply voltage VCC drops and a POR is executed
RST/NMI pin is configured for NMI function (NMI bit is set)
flash memory
D Flash memory has n segments of main memory and two segments of information memory (A and B) of 128
bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased.
D Segments A and B can be erased individually, or as a group with segments 0–n.
Segments A and B are also called information memory.
D A security fuse burning is irreversible; no further access to JTAG is possible afterwards.
D Internal generation of the programming/erase voltage: no external VPP has to be applied, but VCC increases
the supply current requirements.
D Program and erase timing is controlled by hardware in the flash memory – no software intervention is
needed.
D The control hardware is called the flash-timing generator. The input frequency of the flash-timing generator
should be in the proper range and should be maintained until the write/program or erase operation is
completed.
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19
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
flash memory (continued)
D During program or erase, no code can be executed from flash memory and all interrupts must be disabled
by setting the GIE, NMIIE, ACCVIE, and OFIE bits to zero. If a user program requires execution concurrent
with a flash program or erase operation, the program must be executed from memory other than the flash
memory (e.g., boot ROM, RAM). In the event a flash program or erase operation is initiated while the
program counter is pointing to the flash memory, the CPU will execute JMP $ instructions until the flash
program or erase operation is completed. Normal execution of the previously running software then
resumes.
D Unprogrammed, new devices may have some bytes programmed in the information memory (needed for
test during manufacturing). The user should perform an erase of the information memory prior to the first
use.
16KB
24KB
32KB
48KB
60KB
0FFFFh
0FFFFh
0FFFFh
0FFFFh
0FFFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
Segment 1
0FC00h
0FBFFh
0FC00h
0FBFFh
0FC00h
0FBFFh
0FC00h
0FBFFh
0FC00h
0FBFFh
Segment 2
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
0C400h
0C3FFh
0A400h
0A3FFh
08400h
083FFh
04400h
043FFh
01400h
013FFh
0C200h
0C1FFh
0A200h
0A1FFh
08200h
081FFh
04200h
041FFh
01200h
011FFh
0C000h
010FFh
0A000h
010FFh
08000h
010FFh
04000h
010FFh
01100h
010FFh
01080h
0107Fh
01080h
0107Fh
01080h
0107Fh
01080h
0107Fh
01080h
0107Fh
01000h
01000h
01000h
01000h
01000h
Segment 0
w/ Interrupt Vectors
Main
Memory
Segment n-1
Segment n
Segment A
Information
Memory
Segment B
flash memory, control register FCTL1, FCTL2, and FCTL3
All control bits are reset during PUC. PUC is active after VCC is applied, a reset condition is applied to the
RST/NMI pin or the Watchdog Timer expires, a watchdog access violation occurs, or an improper flash operation
has been performed. Any write to control register FCTL1 during erase, mass erase, or write (programming) ends
in an access violation with ACCVIFG=1. In an active segment write mode the control register may be written
if wait mode is active (WAIT=1). Read access is possible at any time without restrictions.
The control bits of control register FCTL1 hold all bits that apply write (programming) or erase modes. Writing
to the control register requires key word 0A5H in the high-byte. Any other data there generates a power-up clear
(PUC) which resets the controller.
20
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flash memory, control register FCTL1, FCTL2, and FCTL3 (continued)
8
15
7
FCTL1
0
SEG
WRT WRT
0128h
rw–0
FCTL1 Read:
FCTL1 Write:
res.
rw–0 r–0
res.
r–0
res.
r–0
MEras Erase res.
rw–0
rw–0 r–0
096h
0A5h
The bits control erase or mass erase of the flash, write (WRT), programming, or segment write (SEGWRT).
The control register FCTL2 determines the operation of the timing generator that generates all the timing signals
necessary for write, erase, and mass erase from the selected clock source. One of three different clock sources
may be selected. The selected clock source must be divided to meet the frequency requirements specified in
the recommended operating conditions.
NOTE:
The mass erase duration generated by the flash timing generator is at least 11.1 ms. The cumulative
mass erase time needed is 200 ms. This can be achieved by repeating the mass erase operation
until the cumulative mass erase time is met (a minimum of 19 cycles may be required).
15
8
7
0
FCTL2
SSEL1 SSEL0
012Ah
rw–0
FCTL2 Read:
FCTL2 Write:
FN5
FN4
FN3
FN2
rw–1 rw–0 rw–0 rw–0 rw–0
FN1
FN0
rw–1 rw–0
096h
0A5h
Control register FCTL3 determines the access and flags the status and error conditions of the flash operation.
There are no restrictions to modify this control register. Control bits are reset or set (WAIT) with PUC but key
violation bit KEYV is reset with POR.
8
15
7
0
FCTL3
res.
012Ch
FCTL3 Read:
FCTL3 Write:
r–0
res.
r–0
EMEX
Lock
WAIT
rw–0
rw–1 r–1
ACCV
KEYV BUSY
IFG
rw–0
rw–(0) r(w)–0
096h
0A5h
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21
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
flash memory, interrupt and security key violation
ACCV
Flash Module
S
ACCVIFG
Flash Module
Flash Module
FCTL1.1
ACCVIE
IE1.5
____
RST/NMI
Clear
KEYV
PUC
Vcc
POR PUC
PUC
System Reset Generator
POR
NMIIFG
S
NMIRS
IFG1.4 Clear
NMIES TMSEL
WDTQn
NMI
EQU
PUC
POR
PUC
NMIIE
IE1.4 Clear
WDTIFG
IRQ
S
PUC
IFG1.0 Clear
OSCFault
S
OFIFG
POR
Counter
WDT_IRQA
TMSEL
IFG1.1
WDTIE
OFIE
IE1.0 Clear
IE1.1 Clear
PUC
PUC
NMI_IRQA
Watchdog Timer Module
IRQA: Interrupt request accepted
Figure 1. Block Diagram of NMI Interrupt Sources
One NMI vector is used for three NMI events: RST/NMI (NMIIFG), oscillator fault (OFIFG), and flash memory
access violation (ACCVIFG). The software can determine the source of the interrupt request since all flags
remain set until they are reset by the software. The enable flag(s) must be set only within one instruction directly
before the return-from-interrupt (RETI) instruction. This ensures that the stack remains under control. A pending
NMI interrupt request does not increase stack demand unnecessarily.
22
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SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
peripherals
Peripherals, which are connected to the CPU through data, address, and control busses, can be easily handled
using all memory-manipulation instructions.
oscillator and system clock
Three clocks are used in the system:
D Main system (master) clock (MCLK), used by the CPU and the system
D Subsystem (master) clock (SMCLK), used by the peripheral modules
D Auxiliary clock (ACLK), originated by LFXT1CLK (crystal frequency) and used by the peripheral modules
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23
/1, /2, /4, /8
f
or
ACLK
crystal
LFXT1 oscillator
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Figure 2. Block Diagram of FLL+ Oscillator and System Clock
455 kHz
...8 MHz
(XTS_FLL=1)
ACLK/n
XIN
XOUT
Osc
PUC
Auxiliary Clock
SCG0
FLL
Cap
/(N+1)
SELM†
= Frequency Integrator
3
f crystal
0
0,1
Eternal Capacitors May or May Not Be
Needed Depending On Crystal Reqquriements.
N DCO
2
fDCOCLK
/1, /2, /4, /8
DCO
f
1
MCLK
†
(f System )
CPUOff
Modulation
DCO+
DCOCLK = f crystal x D x (N+1)
1
fDCOCLK = fcrystal x (N+1)
455 kHz
...8 MHz
0
DCOCLK
XT2IN
XT2 oscillator
SELS
0
0
SMCLK
XT2CLK
1
XT2OUT
§
XT2Off
1
SMCLKOFF
Oscillator Fault
DCO Fault
LF–Osc. Fault
DCOF
LFOF
OFIFG
XTS_FLL
External Capacitors Required
XT1OF
Set Osc. Fault flag
XT1–Osc. Fault
XT2–Osc. Fault
XT2OF
† The clock source for MCLK is forced to DCOCLK if the selected clock source for MCLK fails. Failing includes the crystal oscillator has not
started, or stopped working. Note that if MCLK is automaticaly switched to DCLOCK because of a failure, the SELM bits will NOT change. They
will retain their previous setting and should be reset by software.
‡ OscOff bit switches off the LFXT1 oscillator only if the oscillator is unused by MCLK (SELM≠3 or CPUOff=1)
§ XT2Off bit switches off the XT2 oscillator only if it is unused by MCLK (SELM≠2 or CPUOff = 1) and SMCLK (SELS=0 or SMCLKOFF=1)
P1.5/TACLK/ACLK
XTS_FLL
OscOff ‡
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
32.768 kHz
crystal
(XTS_FLL=0)
oscillator and system clock (continued)
24
FLL_DIV
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
oscillator and system clock (continued)
The ACLK is defined by connecting a low-power, low-frequency, or high-frequency crystal to the oscillator, or
by applying an external clock source (XTS_FLL must be set). The crystal oscillator may be switched off when
the ACLK oscillator is not needed for the present operation mode.
The software selects the DCOCLK frequency. The DCOCLK is active if SCG1 is reset and stopped if SCG1 is
set. The dc generator can be stopped when SCG0 and SCG1 are set. The dc generator, which defines the basic
DCO frequency, can be adjusted in five steps using control bits FN_2, FN_3, FN_4, and FN_8.
When the target frequency needs modification of the FN_x bits, increasing D or setting DCO+, the following
sequence ensures that the maximum system frequency [f(system)] is not exceeded:
1.
2.
3.
4.
5.
6.
Save FLL lock bit (SCG0 in status register) and set it; loop control goes off.
Load modulation control register SCFQCTL with new data (modulation bit M, multiply factor N).
Set DCO control bits and MSB’s of modulator: SCFI1 = 0Fh to lowest possible frequency.
Select DCO+ control bit to be set or reset.
Load control register SCFI0 with new data.
Restore or set/reset the FLL control bit.
NOTE:
The system clock generator starts with the DCOCLK for MCLK (CPU clock) and program execution
starts quickly. The software defines the ACLK clock generation through control bit manipulation.
The MCLK is selected from DCOCLK (SELM {0,1}), XT2CLK (SELM=2), or ACLK (SELM=3). The initial source
for MCLK is DCOCLK. The SMCLK selects between two clock sources, the DCOCLK (SELS=0, initial state)
and XT2CLK (SELS=1). The XT2CLK is defined by connecting a high-frequency crystal to the oscillator (XT2IN,
XT2OUT), or by applying an external clock source to XT2IN. The crystal oscillator may be switched off when
the XT2 oscillator is not needed for the present operation mode.
The start conditions for MCLK and SMCLK frequency are identical to the FLL in MSP430x3xx devices, but the
correct capacitors at pin XIN and XOUT have to be selected with OscCap bits in register FLL+CTL0 at address
053h.
The ACLK, supplied for external use via port P1.5, may be divided by 1, 2, 4, or 8. This ensures clock signal
compatibility to the MSP430x3xx and MSP430x4xx families.
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25
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
oscillator and system clock (continued)
7
0
SCFI0
D
050h
rw–0
FN_8
rw–1
rw–0
FN_4
rw–0
FN_3
rw–0
FN_2
rw–0
2^ 1
2^0
rw–0
rw–0
0
7
SCFI1
051h
2^9
rw–0
2^8
2^7
rw–0
rw–0
2^6
rw–0
2^5
rw–0
2^4
rw–0
2^3
2^2
rw–0
rw–0
N DCO
NOTE: DCOF indicates that the upper (NDCO ≥ 28) and lower (NDCO = 0) limit of the DCO
frequency range is used.
0
7
SCFQCTL
M
052h
rw–0
2^6
2^5
rw–0
rw–0
2^4
rw–1
2^3
rw–1
2^2
rw–1
2^1
2^0
rw–1
rw–1
0
7
FLL+CTL0
053h
DCO+
rw–0
7
XTS_FLL
rw–0
OscCap
rw–0
rw–0
XT2OF
r–0
XT1OF
r–0
LFOF
r–(1)
DCOF
r–1
0
FLL+CTL1
054h
reserved SMCLK OFF XT2OFF
r–0
r–0
rw–(1)
SELM
rw–(0)
rw–(0)
SELS
rw–(0)
FLL_DIV
rw–(0)
rw–(0)
Additional Control Bits in FLL+ vs. FLL in 3xx
Additional Control Bits in FLL+ vs. FLL+ in 41x and FLL in 3xx
Figure 3. Registers and Control Bits of FLL+ Oscillator and System Clock
Four oscillator-fault bits, DCOF, XT1OF, LFOF, and XT2OF indicate if the DCO, LFXT1 oscillator-HF mode,
LFXT1 oscillator-LF mode, and XT2 oscillator respectively, are operating properly. The oscillator fault XT1OF
is applicable only if XTS_FLL=1, and LFOF is applicable only if XTS_FLL=0. If one of the four oscillator faults
occurs, the OSCFault signal set the OFIFG flag. An NMI service is requested if the interrupt enable bit OFIE
is set.
WARNING:
The oscillator fault flag is set if the oscillator is inactive. Inactivity can be caused by system
failure such as crystal damage, broken leads, etc., but also if the oscillator is switched on
or switched from nonselected to selected.
The clock signals ACLK, MCLK, and SMCLK can be used externally via port pins.
Different application requirements and system conditions dictate different system clock requirements. The FLL+
clock system supports the following conditions:
D
D
D
D
26
High frequency for quick reaction to system hardware requests or events (DCO/FLL+XT1+XT2)
Low frequency to minimize current consumption, EMI, etc. (LF)
Stable peripheral clock for timer applications, such as real-time clock (RTC)
Enabling of start-stop operation with minimum delay (DCO)
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SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
brownout, supply voltage supervisor
The brownout circuit detects if a supply voltage is applied to or removed from the VCC terminal and resets the
device appropriately.
The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops to a user selectable level and
supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring
(SVM, the device is not automatically reset). The SVS circuitry is shown in Figure 4. The initial condition for the
SVS is off to conserve current consumption. The user’s software should enable it when desired.
RST/NMI
NMI
Tau ~ 50nS
D
U
S
G
AV
CC
D
U
S
G
TCK
Brownout
VCC
AVCC
G
D
S
15
P6.7/A7/SVSin
t(Delay1) ~ 50uS
14
13
3
2
1
’L’ if VLD=0
–
Set POR
+
t(Delay2) ~ 50uS
Open, if
VLD=0 or VLD=15
SVSCTL
056h
tReset~ 50uS
Voltage
Reference
of 1.25 V
P1.3/TBOUTH/SVSOut
Set SVSFG
Reset
VLD
PORON SVSon
rw–(0) rw–(0) rw–(0) rw–(0) rw–(0) r
SVSOP SVSFG
r
SVSCTL Bits
rw–(0)
Figure 4. Block Diagram of Brownout and Supply Voltage Supervision
The VLD bits control the on/off state of the SVS circuitry. The SVS is off if VLD=0, and on if VLD=1. Bit PORON
enables or disables the automatic reset of the MSP430 upon a low-voltage detection. If PORON=1, a
low-voltage detection generates a POR signal and resets the MSP430. Bit SVSOP is used to watch the actual
SVS comparator output. Bit SVSFG is set as long as a low-voltage situation is detected and remains set until
no low voltage is detected and the software resets it. SVSFG latches such events, whereas SVSOP represents
the actual output of the comparator.
If it is desired to only monitor the supply voltage, but not reset the device if it dips below the determined level,
the user simply resets the PORON bit and sets the level normally. This provides the SVM function. The SVM
function is useful for example, when performing A/D conversions and the user wants to know if the supply
voltage dipped below the minimum operating voltage while the conversion took place.
The SVS circuitry uses hysteresis to reduce sensitivity on voltage drops when the VCC is close to the threshold
level. The hystersis for each SVS level is shown in the table below.
The SVS/SVM has some delay as shown below. The Delay1 is used to avoid erroneous SVS/SVM operation
if it is enabled (VLD changes from 0 to > 0). SVSon bit is L for t(Delay2) whenever the value of VLD (register
SVSCTL) is changed. It is L if VLD = 0.
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SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
brownout, supply voltage supervisor (continued)
The SVS level is user programmable as shown in the table below. In addition, any other voltage can be
monitored if it is applied to A7.
VLD
15
14
4
3
2
1
0
0>1
Delay 1
1>2
2>2
2 > 15
15 > 3
3>0
1
0
0
1
2
2
15
3
VLD vs Time
t(Delay1)
Delay 2
1
0
t(Delay2)
t(Delay2)
t(Delay2)
t(Delay2)
t(SVSON) = t(Delay1) = t(Delay2)
Figure 5. Timing of t(Delay1) and t(Delay2) Triggered by VLD
28
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VLD vs Time
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
brownout, supply voltage supervisor (continued)
The levels for monitoring and supervision are defined by the control bits VLD:
VCC(min)
[V]
VLD
COMMENT
0
0
0
0
NA
SVS/SVM function is off
0
0
0
1
1.9
SVS/SVM on. Hysteresis is typ 110 mV.
0
0
1
0
2.1
SVS/SVM on. Hysteresis is 8 mV to 30 mV.
0
0
1
1
2.2
SVS/SVM on. Hysteresis is 8 mV to 30 mV.
0
1
0
0
2.3
SVS/SVM on. Hysteresis is 8 mV to 30 mV.
0
1
0
1
2.4
SVS/SVM on. Hysteresis is 8 mV to 30 mV.
0
1
1
0
2.5
SVS/SVM on. Hysteresis is 8 mV to 30 mV.
0
1
1
1
2.65
SVS/SVM on. Hysteresis is 8 mV to 30 mV.
1
0
0
0
2.8
SVS/SVM on. Hysteresis is 8 mV to 30 mV.
1
0
0
1
2.9
SVS/SVM on. Hysteresis is 8 mV to 30 mV.
1
0
1
0
3.05
SVS/SVM on. Hysteresis is 8 mV to 30 mV.
1
0
1
1
3.2
SVS/SVM on. Hysteresis is 8 mV to 30 mV.
1
1
0
0
3.35
SVS/SVM on. Hysteresis is 8 mV to 30 mV.
1
1
0
1
1
1
0
3.5
3.7{
SVS/SVM on. Hysteresis is 8 mV to 30 mV.
1
1
1
1
1
(1.2)
SVS/SVM on. Hysteresis is 8 mV to 30 mV.
External analog input is used (input comes from the P6.7/A7/SVSin pin) and internally
compared with 1.2 V.
† The recommended operation voltage range is limited to 3.6 V.
multiplication
The multiplication operation is supported by a dedicated peripheral module. The module performs 16x16, 16x8,
8x16, and 8x8 bit operations. The module is capable of supporting signed and unsigned multiplication as well
as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed
immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are
required.
digital I/O
There are six 8-bit I/O ports implemented—ports P1 through P6. Ports P1 and P2 use seven control registers,
while ports P3, P4, P5, and P6 use only four of the control registers to provide maximum digital input/output
flexibility to the application:
D
D
D
D
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Interrupt processing of external events is fully implemented for all eight bits of ports P1 and P2.
Read/write access to all registers using all instructions is possible.
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digital I/O (continued)
The seven control registers are:
D
D
D
D
D
D
D
Input register
Output register
Direction register
Interrupt edge select
Interrupt flags
Interrupt enable
Selection (port or module)
8 bits at ports P1 through P6
8 bits at ports P1 through P6
8 bits at ports P1 through P6
8 bits at ports P1 and P2
8 bits at ports P1 and P2
8 bits at ports P1 and P2
8 bits at ports P1 through P6
Each of these registers contains eight bits. Two interrupt vectors are implemented: one commonly used for any
interrupt event on ports P1.0 to P1.7, and another commonly used for any interrupt event on ports P2.0 to P2.7.
Ports P3, P4, P5, and P6 have no interrupt capability.
Basic Timer1
The Basic Timer1 (BT1) divides the frequency of SMCLK or ACLK, as selected with the SSEL bit, to provide
low-frequency control signals. This is done within the system by one central divider, the Basic Timer1, to support
low-current applications. The BTCTL control register contains the flags that control or select the different
operational functions. When the supply voltage is applied or when a device is reset (RST/NMI pin), a watchdog
overflow or a watchdog security key violation occurs; all bits in the register hold undefined or unchanged status.
The user software usually configures the operational conditions on the BT during initialization. The Basic Timer1
has two eight-bit timers which can be cascaded to a sixteen-bit timer. Both timers can be read and written by
software. Two bits in the SFR address range handle the system control interaction according to the function
implemented in the Basic Timer1. These two bits are the Basic Timer1 interrupt flag (BTIFG) and the Basic
Timer1 interrupt enable (BTIE) bit.
LCD drive
The liquid crystal displays (LCDs) for static, 2-MUX, 3-MUX, and 4-MUX operation can be driven directly. The
operation of the controller LCD logic is defined by software through memory-bit manipulation. The LCD memory
is part of the LCD module, not part of data memory. Eight mode and control bits define the operation and current
consumption of the LCD drive. The information for the individual digits can be easily obtained using table
programming techniques combined with the proper addressing mode. The segment information is stored into
LCD memory using instructions for memory manipulation.
The drive capability is defined by the external resistor divider that supports analog levels for 2-, 3-, and 4-MUX
operation. Groups of the digital I/O-LCD segment lines can be selected to have either digital I/O or LCD function.
Digital I/Os are selected by default after POR and PUC. The LCD provides four common lines and four terminals
for adjusting the analog levels. The configuration for MSP430x44x and MSP430x43x with 100 pins has
40 segment lines and the configuration for MSP430x43x with 80 pins has 32 segment lines.
30
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Table 4. MSP430x43xIPN Terminal Function, Selected by Bits 5/6/7 in LCD Mode Control Register LCDM
TERMINAL
NAME
NO
I/O
BITS 5/6/7 IN LCD MODE CONTROL REGISTER LCDM
000X XXXX
001X XXXX
010X XXX
011X XXXX
100X XXXX
12
I/O
P5.1
S0
P5.0/S1
13
I/O
P5.0
S1
P4.7/S2
14
I/O
P4.7
S2
P4.6/S3
15
I/O
P4.6
S3
P4.5/S4
16
I/O
P4.5
S4
P4.4/S5
17
I/O
P4.4
S5
P4.3/S6
18
I/O
P4.3
S6
P4.2/S7
19
I/O
P4.2
S7
P4.1/S8
20
I/O
P4.1
S8
P4.0/S9
21
I/O
P4.0
S10–S17
22–29
O
30
I/O
P2.7/ADC10CLK
P2.7/ADC10CLK
P2.6/CAOUT
P2.6/CAOUT
P2.7/ADC10CLK/S18
P2.6/CAOUT/S19
101X XXXX
110X XXX
111X XXXX
S9
S10–S17
S18
31
I/O
S20–S23
32–35
O
S19
P3.7/S24
36
I/O
P3.7
P3.7
P3.7
P3.7
S24
P3.6/S25
37
I/O
P3.6
P3.6
P3.6
P3.6
S25
P3.5/S26
38
I/O
P3.5
P3.5
P3.5
P3.5
S26
P3.4/S27
39
I/O
P3.4
P3.4
P3.4
P3.4
P3.3/UCLK0/S28
40
I/O
P3.3/UCLK0
P3.3/UCLK0
P3.3/UCLK0
P3.3/UCLK0
P3.3/UCLK0
S28
P3.2/SOMI0/S29
41
I/O
P3.2/SOMI0
P3.2/SOMI0
P3.2/SOMI0
P3.2/SOMI0
P3.2/SOMI0
S29
P3.1/SIMO0/S30
42
I/O
P3.1/SIMO0
P3.1/SIMO0
P3.1/SIMO0
P3.1/SIMO0
P3.1/SIMO0
S30
P3.0/STE0/S31
43
I/O
P3.0/STE0
P3.0/STE0
P3.0/STE0
P3.0/STE0
P3.0/STE0
S31
S20–S23
S27
,
, , 31
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
P5.1/S0
NAME
I/O
NO
000X XXXX
001X XXXX
010X XXX
011X XXXX
100X XXXX
101X XXXX
110X XXXX
111X XXXX
P5.1/S0
12
I/O
P5.1
S0
P5.0/S1
13
I/O
P5.0
S1
S2–S33
14–45
O
P4.7/S34
46
I/O
P4.7
P4.7
P4.7
P4.7
P4.7
P4.7
P4.6/S35
47
I/O
P4.6
P4.6
P4.6
P4.6
P4.6
P4.6
P4.5/S36
48
I/O
P4.5
P4.5
P4.5
P4.5
P4.5
P4.5
P4.5
S36
P4.4/S36
48
I/O
P4.4
P4.4
P4.4
P4.4
P4.4
P4.4
P4.4
S37
P4.3/S36
48
I/O
P4.3
P4.3
P4.3
P4.3
P4.3
P4.3
P4.3
S38
P4.2/S36
48
I/O
P4.2
P4.2
P4.2
P4.2
P4.2
P4.2
P4.2
S39
S2–S33
S34
S35
•
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Table 6. MSP430x44xIPZ Terminal Functions, Selected by Bits 5/6/7 in LCD Mode Control Register LCDM
BITS 5/6/7 IN LCD MODE CONTROL REGISTER LCDM
TERMINAL
NAME
P5.1/S0
I/O
NO
000X XXXX
001X XXXX
010X XXX
011X XXXX
100X XXXX
101X XXXX
110X XXXX
111X XXXX
12
I/O
P5.1
S0
P5.0/S1
13
I/O
P5.0
S2–S33
14–45
O
P4.7/S34
46
I/O
P4.6/S35
47
I/O
P4.6
P4.6
P4.6
P4.6
P4.6
P4.6
P4.5/UCLK1/S36
48
I/O
P4.5/UCLK1
P4.5UCLK1
P4.5/UCLK1
P4.5/UCLK1
P4.5/UCLK1
P4.5/UCLK1
P4.5/UCLK1
S36
P4.4/SOMI1/S37
49
I/O
P4.4/SOMI1
P4.4/SOMI1
P4.4/SOMI1
P4.4/SOMI1
P4.4/SOMI1
P4.4/SOMI1
P4.4/SOMI1
S37
P4.3/SIMO1/S38
50
I/O
P4.3/SIMO1
P4.3/SIMO1
P4.3/SIMO1
P4.3/SIMO1
P4.3/SIMO1
P4.3/SIMO1
P4.3/SIMO1
S38
P4.2/STE1/S39
51
I/O
P4.2/STE1
P4.2/STE1
P4.2/STE1
P4.2/STE1
P4.2/STE1
P4.2/STE1
P4.2/STE1
S39
S1
S2–S33
P4.7
P4.7
P4.7
P4.7
P4.7
P4.7
S34
S35
,
, , BITS 5/6/7 IN LCD MODE CONTROL REGISTER LCDM
TERMINAL
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
32
Table 5. MSP430x43xIPZ Terminal Functions, Selected by Bits 5/6/7 in LCD Mode Control Register LCDM
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
watchdog timer
The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a
software upset has occurred. A system reset is generated if the selected time interval expires. If an application
does not require this watchdog function, the module can work as an interval timer, which generates an interrupt
after a selected time interval.
The watchdog timer counter (WDTCNT) is a 15/16-bit up-counter not directly accessible by software. The
WDTCNT is controlled using the watchdog timer control register (WDTCTL), which is an 8-bit read/write register.
Writing to WDTCTL in either operating mode (watchdog or timer) is only possible when using the correct
password (05Ah) in the high byte. If any value other than 05Ah is written to the high-byte of the WDTCTL, a
system reset PUC is generated. The password is read as 069h to minimize accidental write operations to the
WDTCTL register. The low byte stores data written to the WDTCTL. In addition to the watchdog timer control
bits, there are two bits included in the WDTCTL that configure the NMI pin.
USART0 and USART1
There are two USART peripherals implemented in the MSP430x44x: USART0 and USART1; but only one in
the MSP430x43x configuration: USART0. Both have an identical function as described in the applicable
chapters of the MSP430x4xx User’s Guide. They use different pins to communicate, and different registers for
module control. Registers with identical functions have different addresses.
The universal synchronous/asynchronous interface is a dedicated peripheral module used in serial
communications. The USART supports synchronous SPI (3- or 4-pin), and asynchronous UART
communication protocols, using double-buffered transmit and receive channels. Data streams of 7 or 8 bits in
length can be transferred at a rate determined by the program, or by an external clock. Low-power applications
are optimized by UART mode options which allow for the reception of only the first byte of a complete frame.
The application software should then decide if the succeeding data is to be processed. This option reduces
power consumption.
Two dedicated interrupt vectors are assigned to each USART module—one for the receive and one for the
transmit channels.
timer_A (three capture/compare registers)
The timer module offers one 16-bit counter and three capture/compare registers. The timer clock source can
be selected from the external source TACLK (noninverted via SSEL=0 or inverted via SSEL=3), or from two
internal sources—ACLK (SSEL=1) or SMCLK (SSEL=2)). The clock source can be divided by one, two, four,
or eight. The timer can be fully controlled (in word mode)—it can be halted, read, and written. It can be stopped,
run continuously, or made to count up or up/down using one compare block to determine the period. The three
capture/compare blocks are configured by the application to run in capture or compare mode.
The capture mode is mostly used to individually measure internal or external events from any combination of
positive, negative, or positive and negative edges. It can also be stopped by software. Three different external
events (TA0, TA1, and TA2) can be selected. In the capture/compare register CCR2, ACLK is the capture signal
if CCI2B is selected. Software capture is chosen if CCISx=2 or CCISx=3.
The compare mode is mostly used to generate timing for the software or application hardware, or to generate
pulse-width modulated output signals for various purposes such as D/A conversion functions or motor control.
An individual output module is assigned to each of the three capture/compare registers. This module can run
independently of the compare function or can be triggered in several ways.
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timer_A (three capture/compare registers) (continued)
P1.5/TACLK/
ACLK
P1.5/TACLK/
ACLK
TACLK
ACLK
SMCLK
INCLK
32–kHz to 8–MHz
Timer Clock
SSEL1 SSEL0
0
1
2
Data
15
0
16-Bit Timer
CLK
RC
Input
Divider
3
ID1
16-Bit Timer
ID0
POR/CLR
Mode
Control
Carry/Zero
MC1
P1.0/TA0
P1.1/TA0/MCLK
0
15
Capture
Capture
Mode
Set_TAIFG
MC0
Timer Bus
CCIS01CCIS00
0
CCI0A
1
CCI0B
2
GND
3
VCC
Equ0
Capture/Compare
Register CCR0
OM02
OM01 OM00
Out 0
0
15
Capture/Compare Register CCR0
P1.0/TA0
Output Unit 0
Comparator 0
EQU0
CCI0 CCM01 CCM00
P1.2/TA1
CAOUT
from
Comparator_A
CCIS11CCIS10
0
CCI1A
1
CCI1B
2
GND
3
VCC
Capture
Capture
Mode
P2.0/TA2
ACLK
Capture/Compare
Register CCR1
Capture/Compare Register CCR1
OM12
Out 1
P1.2/TA1
0
15
OM11 OM10
Output Unit 1
to ADC1211
Comparator 1
EQU1
CCI1 CCM11
CCIS21CCIS20
0
CCI2A
1
CCI2B
2
GND
3
VCC
0
15
CCM10
0
15
Capture
Capture
Mode
Capture/Compare
Register CCR2
OM22
OM21 OM20
Out 2
0
15
Capture/Compare Register CCR2
P2.0/TA2
Output Unit 2
Comparator 2
EQU2
CCI2 CCM21 CCM20
Figure 6. Timer_A Configuration With Three Capture/Compare Registers (CCRs)
The module uses two interrupt vectors. One individual vector is assigned to capture/compare block CCR0 and
one common interrupt vector is implemented for the timer and the other two capture/compare blocks. The three
interrupt events using the same vector are identified by an individual interrupt vector word. The interrupt vector
word is used to add an offset to the program counter to continue the interrupt handler software on the
corresponding program location. This simplifies the interrupt handler and gives each interrupt event the same
overhead of five cycles in the interrupt handler.
34
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timer_B (7 capture/compare registers in ’x44x and three capture/compare registers in ’x43x)
Timer_B7 is identical to Timer_A3, except for the following:
D The timer counter can be configured to operate in 8-, 10-, 12-, or 16-bit mode.
D The function of the capture/compare registers is slightly different when in compare mode. In Timer_B, the
compare data is written to the capture/compare register, but is then transferred to the associated compare
latch for the comparison.
D All output level Outx can be set to Hi-Z from the TboutH external signal.
D The SCCI bit is not implemented in Timer_B
D Timer_B7 has seven capture compare registers
The timer module has one 16-bit counter and seven capture/compare registers. The timer clock source can be
selected from an external source TBCLK (SSEL=0) or TBCLK (SSEL=3), or from two internal sources: ACLK
(SSEL=1) and SMCLK (SSEL=2)). The clock source can be divided by one, two, four, or eight. The timer can
be fully controlled (in word mode): it can be halted, read, and written; it can be stopped, run continuously, or
made to count up or up/down using one compare block to determine the period. The seven capture/compare
blocks are configured by the application to run in capture or in compare mode.
The capture mode is mostly used to measure external or internal events from any combination of positive,
negative, or positive and negative edges. It can also be stopped by software. Any of seven different external
events TB0 to TB6 can be selected. In the capture/compare register CCR6, ACLK is the capture signal if CCI6B
is selected. Software capture is chosen if CCISx=2 or CCISx=3.
The compare mode is mostly used to generate timing for the software or application hardware, or to generate
pulse-width modulated output signals for various purposes such as D/A conversion functions or motor control.
An individual output module is assigned to each of the seven capture/compare registers. This module can run
independently of the compare function, or can be triggered in several ways. The comparison is made from the
data in the compare latches (TBCLx) and not from the compare register.
Two interrupt vectors are used by the module. One vector is assigned to capture/compare block CCR0, and one
common interrupt vector is implemented for the timer and the other six capture/compare blocks. The seven
interrupt events using the same vector are identified by an individual interrupt vector word. The interrupt vector
word is used to add an offset to the program counter so that the interrupt handler software continues at the
corresponding program location. This simplifies the interrupt handler and assigns each interrupt event the same
5-cycle overhead.
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compare latches (TBCLx)
The compare latches can be loaded directly by software or via selected conditions triggered by the PWM
function and they are reset by the POR signal.
Load TBCLx immediate, CLLD=0:
Capture/compare register CCRx and the corresponding compare
latch are loaded simultaneously.
Load TBCLx at Zero, CLLD=1:
The data in capture/compare register CCRx is loaded to the
corresponding compare latch when the 16-bit timer TBR counts to
zero.
Load TBCLx at Zero + Period, CLLD=2: The data in capture/compare register CCRx is loaded to the
corresponding compare latch when the 16-bit timer TBR counts to
zero or when the next period starts (in UP/DOWN mode).
Load TBCLx at EQUx, CLLD=3:
The data in capture/compare register CCRx is loaded when CCRx
is equal to TBR.
Loading the compare latches can be done individually or in groups. Individually means that whenever the
selected load condition (see above) is true, the CCRx data is loaded into TBCLx.
Load TBCLx individually, TBCLGRP=0:
Compare latch TBCLx is loaded when the selected load condition
(CLLD) is true.
Dual load TBCLx mode, TBCLGRP=1:
Two compare latches TBCLx are loaded when data are written to
both CCRx registers of the same group and the load condition
(CLLD) is true. Three groups are defined: CCR1+CCR2,
CCR3+CCR4, and CCR5+CCR6.
Triple load TBCLx mode, TBCLGRP=2: Three compare latches TBCLx are loaded when data are written
to all CCRx registers of the same group and then the selected load
condition (CLLD) is true. Two groups are defined:
CCR1+CCR2+CCR3 and CR4+CCR5+CCR6.
Full load TBCLx mode, TBCLGRP=3:
All seven compare latches TBCLx are loaded when data are
written to all seven CCRx registers and then the selected load
condition (CLLD) is true. All CCRx data, CCR0+CCR1+
CCR2+CCR3+CCR4+CCR5+CCR6, are simultaneously loaded
to the corresponding SHRx compare latches.
36
POST OFFICE BOX 655303
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compare latches (TBCLx) (continued)
Data
SSEL1
P1.4/
TBCLK/
SMCLK
P1.4/
TBCLK/
SMCLK
SSEL0
1
ACLK
2
SMCLK
3
INCLK
Input
Clk
P2.1/TB0
0
CCI0B
1
GND
2
VCC
3
Mode
Control
RC
Carry/Zero
POR/CLR
Set_TBIFG
MC1 MC0
15
0
Capture/Compare
Register CCR0
Capture
Capture
15
Mode
Equ0
MDB
Timer Bus
CCIS01 CCIS00
CCI0A
16–bit Timer
Divider
ID1 ID0
P2.1/TB0
0
15
0
TBCLK
16–bit Timer
Timer Clock
0
OM02 OM01 OM00
Compare Latch
TBCL0
CCI0 CCM01 CCM00
Out0
Output Unit0
ADC12I2
i/p at
ADC12
Comparator 0
EQU0
P2.2/TB1
CCI1A
0
CCI1B
1
GND
2
VCC
3
EQU0
MDB
CCIS11 CCIS10
P2.2/TB1
15
0
Capture/Compare
Register CCR1
Capture
Capture
15
Mode
0
OM12 OM11 OM10
Compare Latch
TBCL1
CCI1 CCM11 CCM10
Out1
Output Unit1
Comparator 1
EQU1
P2.3/TB2
Capture/Compare Reg. CCR3
P3.5/TB4
Capture/Compare Reg. CCR4
P3.6/TB5
Capture/Compare Reg. CCR5
CCI6A
0
CCI6B
1
GND
2
VCC
3
P2.2/TB1
ADC12I3
i/p at
ADC12
P2.3/TB2
P3.4/TB3
P3.5/TB4
P3.6/TB5
MDB
CCIS61 CCIS60
ACLK
EQU0
Capture/Compare Reg. CCR2
P3.4/TB3
P3.7/TB6
P2.1TB0
15
Capture
Mode
CCI6 CCM61 CCM60
0
Capture/Compare
Register CCR6
Capture
15
0
OM62 OM61 OM60
Compare Latch
TBCL6
Out6
P3.7/TB6
Output Unit6
Comparator 6
EQU6
POST OFFICE BOX 655303
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EQU0
37
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
comparator_A
The primary functions of the comparator module are: support of precision slope conversion in A/D applications,
battery voltage supervision, and external analog signal monitoring. The comparator is connected to port pins
P1.6/CA0 (+ terminal) and P1.7/CA1 (– terminal). It is controlled by eight control bits in the CACTL register. A
block diagram of comparator_A is shown in Figure 7.
0 V VCC
P2CA0
0
P1.6/
CA0
CA0
1
CAF
CAON
0
Low Pass Filter
1
1
0
P1.7/
CA1
0
CAEX
+
_
CA1
0
0
0
1
1
CCI1B
CAOUT
1
0V
1
0 V VCC
P2CA1
0
0V
1
Set CAIFG
Flag
τ ≈ 2 µs
CAON
P2.6/CAOUT/S19
3
2
1
0
CAREF
CARSEL
0
1
2
0
1
VCAREF
0.5 x VCC
0.25 x VCC
3
0V
0V
Figure 7. Block Diagram of Comparator_A
The eight control bits are used to connect the comparator to the supply voltage, apply external or internal signals
to the + terminal and – terminal, and select the comparator output, including a small filter.
Eight additional bits in register CAPD are implemented into the Comparator_A module and enable the SW to
switch off the input buffer of Port P1. A CMOS input buffer dissipates supply current when the input is not near
VSS or VCC. Control bits CAPI0 to CAPI7 are initially reset and the port input buffer is active. The port input buffer
is inactive if the corresponding control bit is set.
38
POST OFFICE BOX 655303
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SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
A/D converter
The 12-bit analog-to-digital converter (ADC) uses a 10-bit weighted capacitor array plus a 2-bit resistor string.
The CMOS threshold detector in the successive-approximation conversion technique determines each bit by
examining the charge on a series of binary-weighted capacitors. The features of the ADC are:
D 12-bit converter with ±1-LSB linearity
D Built-in sample-and-hold
D Eight external and four internal analog channels. The external ADC input terminals are shared with digital
port I/O pins.
D Internal reference voltage VREF+ of 1.5 V or 2.5 V, software-selectable by control bit 2_5V
D Internal-temperature sensor for temperature measurement:
D
D
D
D
D
D
D
D
–
T = [V_SENSOR(T) – V_SENSOR(0°C)] / TC_SENSOR in °C
Battery-voltage measurement: N = 0.5 × (AVCC – AVSS) × 4096/1.5 V; VREF+ is selected for 1.5 V.
Source of positive reference voltage level (VR+) can be selected as internal (1.5 V or 2.5 V), external, or
AVCC. The source is selected individually for each channel.
Source of negative reference voltage level (VR-) can be selected as external or AVSS. The source is selected
individually for each channel.
Conversion time can be selected from various clock sources: ACLK, MCLK, SMCLK, or the internal
ADC12CLK oscillator. The clock source is divided by an integer from 1 to 8, as selected by software.
Channel conversion: individual channels, a group of channels, or repeated conversion of a group of
channels. If conversion of a group of channels is selected, the sequence, the channels, and the number
of channels in the group can be defined by software. For example, a1-a2-a5-a2-a2-….
The conversion is enabled by the ENC bit, and can be triggered by software via sample and conversion
control bit ADC12SC, Timer_A3, or Timer_Bx. Most of the control bits can be modified only if the ENC
control bit is low. This prevents unpredictable results caused by unintended modification.
Sampling time can be 4 × n0 × ADC12CLK or 4 × n1 × ADC12CLK. It can be selected to sample as long
as the sample signal is high (ISSH=0) or low (ISSH=1). SHT0 defines n0 and SHT1 defines n1.
The conversion result is stored in one of 16 registers. The 16 registers have individual addresses and can
be accessed via software. Each of the 16 registers is linked to an 8-bit register that defines the positive and
negative reference source and the channel assigned.
POST OFFICE BOX 655303
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39
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
A/D converter (continued)
VeREF
2_5V
VERF–/VeREF–
AVCC
AVSS
AVCC
Ref_X
ADC12SSEL
AVSS
P6.0/A0
P6.1/A1
P6.2/A2
P6.6/A6
P6.7/A.7/
SVSin
on
on
Reference
1.5 V or 2.5 V
ADC12CTLx.0..3
P6.4/A4
P6.5/A5
INCH= 0Ah
VREF+
VREF+
P6.3/A3
REFON
ADC12ON
ADC12CTLx.4..6
Analog
V R–
Sample
and
Hold
Multiplexer
ADC12DIV
ADC12CLK
V R+
ACLK
MCLK
SMCLK
Divide by
1,2,3,4,5,6,7,8
P2.6/ADC12CLK
SHP
12 : 1
S/H
a8
a9
a10
a11
ISSH
Sampling
Timer
SAMPCON
ADC12SC
Timer_A3.Out
Timer_Bx.Out
Timer_Bx.Out
SYNC
SHI
MSC
Conversion CTL
12-Bit SAR
ENC
AVCC
Ref_X
T
AVSS
0140h
0142h
0144h
0146h
ADC12MEM0
ADC12MEM1
ADC12MEM2
ADC12MEM3
0148h
014Ah
014Ch
014Eh
0150h
0152h
0154h
0156h
0158h
015Ah
015Ch
015Eh
ADC12MEM4
ADC12MEM5
ADC12MEM6
ADC12MEM7
ADC12MEM8
ADC12MEM9
ADC12MEM10
ADC12MEM11
ADC12CTL0
ADC12CTL1
ADC12CTL2
ADC12CTL3
ADC12CTL4
ADC12CTL5
ADC12CTL6
ADC12CTL7
ADC12CTL8
ADC12CTL9
ADC12CTL10
ADC12CTL11
ADC12CTL12
ADC12CTL13
ADC12CTL14
ADC12CTL15
ADC12MEM12
ADC12MEM13
ADC12MEM14
ADC12MEM15
16 x 12-bit
ADC Memory (leading bits 15 to 12
are 0)
40
ADC12OSC
SHT0
SHT1
12-bitA/D Converter Core
Internal
Oscillator
POST OFFICE BOX 655303
080h
081h
082h
083h
084h
085h
086h
087h
088h
089h
08Ah
08Bh
08Ch
08Dh
08Eh
08Fh
16 x 8-bit
ADC Memory Control
• DALLAS, TEXAS 75265
SHS
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
A/D converter (continued)
Table 7. Reference Voltage Configurations
SREF
VOLTAGE AT VR+
VOLTAGE AT VR–
0
1
AVCC
VREF+ (internal)
AVSS
AVSS
2, 3
VeREF+ (external)
4
5
AVCC
VREF+ (internal)
AVSS
VREF–/VeREF– (internal or external)
6, 7
VeREF+ (external)
VREF–/VeREF– (internal or external)
VREF–/VeREF– (internal or external)
control registers ADC12CTL0 and ADC12CTL1
All control bits are reset during POR. POR is active after VCC or a reset condition is applied to pin RST/NMI.
A more detailed description of the control bit functions is found in the ADC12 module description (in the user’s
guide). Most of the control bits in registers ADC12CTL0, ADC12CTL1, and ADC12MCTLx can only be modified
if ENC is low.
The following illustration highlights these bits. Six bits are excluded and can be unrestrictedly modified:
ADC12SC, ENC, ADC12TOVIE, ADC12OVIE, and CONSEQ.
The control bits of control registers ADC12CTL0 and ADC12CTL1 are:
15
8
7
0
ADC12CTL0
SHT1
SHT0
rw–(0)
rw–(0)
MSC
2_5 V
01A0h
REF
ON
ADC12 ADC12 ADC12
ON
OVIE TOVIE
ADC12
ENC
SC
rw–(0) rw–(0) rw–(0) rw–(0) rw–(0) rw–(0) rw–(0) rw–(0)
ADC12SC
01A0h, bit0
Sample and convert. The ADC12SC bit is used to control the conversion by software. It
is recommended that ISSH=0.
SHP=1: Changing the ADC12SC bit from 0 to 1 starts the sample and conversion
operation. Bit ADC12SC is automatically reset when the conversion is complete
(BUSY=0).
SHP=0: A high level of bit ADC12SC determines the sample time. Conversion starts once
it is reset (by software). The conversion takes 13 ADC12CLK cycles.
ENC
01A0h, bit1
Enable conversion. A conversion can be started by software (via ADC12SC) or by external
signals, only if the enable conversion bit ENC is high. Most of the control bits in
ADC12CTL0 and ADC12CTL1, and all the bits in ADCMCTL.x can only be changed if ENC
is low.
0: No conversion can be started. This is the initial state.
1: The first sample and conversion starts with the first rising edge of the sampling signal.
The operation selected proceeds as long as ENC is set.
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41
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
control registers ADC12CTL0 and ADC12CTL1 (continued)
ADC12TOVIE
01A0h, bit2
Conversion time overflow interrupt enable.
The timing overflow takes place and a timing overflow vector is generated if another start
of sample and conversion is requested while the current conversion or sequence of
conversions is still active. The timing overflow enable, if set, may request an interrupt.
ADC12OVIE
01A0h, bit3
Overflow interrupt enables the individual enable for the overflow-interrupt vector.
The overflow takes place if the next conversion result is written into ADC memory
ADC12MEMx but the previous result was not read. If an overflow vector is generated, the
overflow-interrupt enable flag ADC12OVIE and the general-interrupt enable GIE are set
and an interrupt service is requested.
ADC12ON
01A0h, bit4
Switch on the 12-bit ADC core. Make sure that the settling timing constraints are met if ADC
core is powered up.
0: Power consumption of the core is off. No conversion is started.
1: ADC core is supplied with power. If no A/D conversion is required, ADC12ON can be
reset to conserve power.
REFON
01A0h, bit5
Reference voltage on
0: The internal reference voltage is switched off. No power is consumed by the reference
voltage generator.
1: The internal reference voltage is switched on and consumes additional power. The
settling time of the reference voltage should be over before the first sample and
conversion is started.
2_5V
01A0h, bit6
Reference voltage level
0: The internal-reference voltage is 1.5 V if REFON = 1.
1: The internal-reference voltage is 2.5 V if REFON = 1.
MSC
01A0h, bit7
Multiple sample and conversion. Works only when the sample timer is selected to generate
the sample signal and to repeat single channel, sequence of channel, or when repeat
sequence of channel (CONSEQ≠0) is selected.
0: Only one sample is taken.
1: If SHP is set and CONSEQ = {1, 2, or 3}, then the rising edge of the sample timer’s input
signal starts the repeat and/or the sequence of channel mode. Then the second and all
further conversions are immediately started after the current conversion is completed.
SHT0
01A0h, bit8–11
Sample-and-hold Time0
SHT1
01A0h, bit12–15
Sample-and-hold Time1
The sample time is a multiple of the ADC12CLK × 4:
tsample = 4 × ADC12CLK × n
SHT0/1
0
1
2
3
4
5
6
7
8
9
10
11
12–15
n
1
2
4
8
16
24
32
48
64
96
128
192
256
The sampling time defined by SHT0 is used when ADC12MEM0 through ADC12MEM7
are used during conversion. The sampling time defined by SHT1 is used when
ADC12MEM8 through ADC12MEM15 are used during conversion.
42
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SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
control registers ADC12CTL0 and ADC12CTL1 (continued)
15
ADC12CTL1
8
CSStartAdd
SHS
SHP
ISSH
7
0
ADC12DIV
ADC12SSEL
CONSEQ
01A2h
ADC12
BUSY
rw–(0) rw–(0) rw–(0) rw–(0) rw–(0) rw–(0) rw–(0) rw–(0) rw–(0) rw–(0) rw–(0) rw–(0) rw–(0) rw–(0) rw–(0) r–(0)
ADC12BUSY
01A2h, bit0
The BUSY signal indicates an active sample and conversion operation.
0: No conversion is active. The enable conversion bit ENC can be reset normally.
1: A sample period. Conversion or conversion sequence is active.
CONSEQ
01A2h, bit1/2
Select the conversion mode. Repeat mode is on if CONSEQ.1 (bit 1) is set.
0: One single channel is converted
1: One single sequence of channels is converted
2: Repeating conversion of one single channel
3: Repeating conversion of a sequence of channels
ADC12SSEL
01A2h, bit3/4
Selects the clock source for the converter core
0: Internal oscillator embedded in the ADC12 module
1: ACLK
2: MCLK
3: SMCLK
ADC12DIV
01A2h, bit5,6,7
Selects the division rate for the clock source selected by ADC12SSEL. The clock-operation
signal ADC12CLK is used in the converter core. The conversion, without sampling time,
requires 13 ADC12CLK clocks.
0 to 7: Divide the selected clock source by an integer from 1 to 8.
ISSH
01A2h, bit8
Invert source for the sample signal
0: The source for the sample signal is not inverted.
1: The source for the sample signal is inverted.
SHP
01A2h, bit9
Sample-and-hold pulse, programmable length of sample pulse
0: The sample operation lasts as long as the sample-and-hold signal is 1. The conversion
operation starts if the sample-and-hold signal goes from 1 to 0.
1: The sample time (sample signal is high) is defined by nx4x(1/fADC12CLK). SHTx holds
the data for n. The conversion starts when the sample signal goes from 1 to 0.
SHS
01A2h, bit10/11
Source for sample-and-hold
0: Control bit ADC12SC triggers sample-and-hold followed by the A/D conversion.
1: The trigger signal for sample-and-hold and conversion comes from Timer_A3.EQU1.
2: The trigger signal for sample-and-hold and conversion comes from Timer_B.EQU0.
3: The trigger signal for sample-and-hold and conversion comes from Timer_B.EQU1.
CStartAdd
01A2h, bit12 to
bit15
Conversion start address CstartAdd is used to define which ADC12 control memory is used
to start a (first) conversion. The value of CstartAdd ranges from 0 to 0Fh, corresponding
to ADC12MEM0 to ADC12MEM15 and the associated control registers ADC12MCTL0 to
ADC12MCTL15.
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43
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
control register ADC12MCTLx and conversion memory ADC12MEMx
All control bits are reset during POR. POR is active after application of VCC, or after a reset condition is applied
to pin RST/NMI. Control registers ADC12MCTL.x can be modified only if enable conversion control bit ENC is
reset. Any instruction that writes to an ADC12MCTLx register while the ENC bit is reset has no effect. A more
detailed description of the control bit functions is found in the ADC12 module description (in the MSP430x3xx
User’s Guide).
There are 16 ADC12MCTLx 8-bit memory control registers and 16 ADC12MEMx 16-bit registers. Each of the
memory control registers is associated with one ADC12MEMx register; for example, ADC12MEM0 is
associated with ADC12MCTL0, ADC12MEM1 is associated with ADC12MCTL1, etc.
7
0
ADC12MCTLx
EOS
Sref, Source of Reference
INCH, Input Channel a0 to a11
080h....08Fh
rw–(0)
rw–(0)
rw–(0)
The control register bits are used to select the analog channel, the reference voltage sources for VR+ and VR–,
and a control signal which marks the last channel in a group of channels. The sixteen 16-bit registers
ADC12MEMx are used to hold the conversion results.
The following illustration shows the conversion-result registers ADC12MEM0 to ADC12MEM15:
15
ADC12MEM
12
0
0140h...015Eh
r0
0
r0
0
r0
0
r0
11
0
LSB
MSB
rw–(0) rw–(0) rw–(0) rw–(0) rw–(0) rw–(0) rw–(0) rw–(0) rw–(0) rw–(0) rw–(0) rw–(0)
ADC12MEM0
to
0140h, bit0,
The 12 bits of the conversion result are stored in 16 control registers
ADC12MEM0 to ADC12MEM15.
ADC12MEM15
015Eh, bit15
The 12 bits are right-justified and the upper four bits are always read as 0.
ADC12 interrupt flags ADC12IFG.x and enable registers ADC12IEN.x
There are 16 ADC12IFG.x interrupt flags, 16 ADC12IE.x interrupt-enable bits, and one interrupt-vector word.
The 16 interrupt flags and enable bits are associated with the 16 ADC12MEMx registers. For example, register
ADC12MEM0, interrupt flag ADC12IFG.0, and interrupt-enable bit ADC12IE.0 form one conversion-result
block.
ADC12IFG.0 has the highest priority and ADC12IFG.15 has the lowest priority.
All interrupt flags and interrupt-enable bits are reset during POR. POR is active after application of VCC or after
a reset condition is applied to the RST/NMI pin.
ADC12 interrupt vector register
The 12-bit ADC has one interrupt vector for the overflow flag, the timing overflow flag, and 16 interrupt flags.
This vector indicates that a conversion result is stored into registers ADC12MEMx. Handling of the 18 flags is
assisted by the interrupt-vector word. The 16-bit vector word ADC12IV indicates the highest pending interrupt.
The interrupt-vector word is used to add an offset to the program counter so that the interrupt-handler software
continues at the corresponding program location according to the interrupt event. This simplifies the interrupthandler operation and assigns each interrupt event the same 5-cycle overhead.
44
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SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
peripheral file map
PERIPHERALS WITH WORD ACCESS
Watchdog
Watchdog Timer control
WDTCTL
0120h
Timer_B7
_
Timer_B3
(see Note 6)
Capture/compare register 6
CCR6
019Eh
Capture/compare register 5
CCR5
019Ch
Capture/compare register 4
CCR4
019Ah
Capture/compare register 3
CCR3
0198h
Capture/compare register 2
CCR2
0196h
Capture/compare register 1
CCR1
0194h
Capture/compare register 0
CCR0
0192h
Timer_B register
TBR
0190h
Capture/compare control 6
CCTL6
018Eh
Capture/compare control 5
CCTL5
018Ch
Capture/compare control 4
CCTL4
018Ah
Capture/compare control 3
CCTL3
0188h
Capture/compare control 2
CCTL2
0186h
Capture/compare control 1
CCTL1
0184h
Capture/compare control 0
CCTL0
0182h
Timer_B control
TBCTL
0180h
Timer_B interrupt vector
TBIV
011Eh
Timer_A3
_
Reserved
017Eh
Reserved
017Ch
Reserved
017Ah
Reserved
0178h
Capture/compare register 2
CCR2
0176h
Capture/compare register 1
CCR1
0174h
Capture/compare register 0
CCR0
0172h
Timer_A register
TAR
0170h
Reserved
016Eh
Reserved
016Ch
Reserved
016Ah
Reserved
Multiply
py
In MSP430x44x
only
0168h
Capture/compare control 2
CCTL2
0166h
Capture/compare control 1
CCTL1
0164h
Capture/compare control 0
CCTL0
0162h
Timer_A control
TACTL
0160h
Timer_A interrupt vector
TAIV
012Eh
Sum extend
SumExt
013Eh
Result high word
ResHi
013Ch
Result low word
ResLo
013Ah
Second operand
OP_2
0138h
Multiply signed + accumulate/operand1
MACS
0136h
Multiply + accumulate/operand1
MAC
0134h
Multiply signed/operand1
MPYS
0132h
Multiply unsigned/operand1
MPY
0130h
NOTE 6: Timer_B7 in the MSP430x44x family has seven CCRs; Timer_B3 in the MSP430x43x family has three CCRs.
POST OFFICE BOX 655303
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45
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
peripheral file map (continued)
PERIPHERALS WITH WORD ACCESS (CONTINUED)
Flash
46
Flash control 3
FCTL3
012Ch
Flash control 2
FCTL2
012Ah
Flash control 1
FCTL1
0128h
ADC12
Conversion memory 15
ADC12MEM15
015Eh
See also Peri
Peripherals
herals
with Byte
y Access
Conversion memory 14
ADC12MEM14
015Ch
Conversion memory 13
ADC12MEM13
015Ah
Conversion memory 12
ADC12MEM12
0158h
Conversion memory 11
ADC12MEM11
0156h
Conversion memory 10
ADC12MEM10
0154h
Conversion memory 9
ADC12MEM9
0152h
Conversion memory 8
ADC12MEM8
0150h
Conversion memory 7
ADC12MEM7
014Eh
Conversion memory 6
ADC12MEM6
014Ch
Conversion memory 5
ADC12MEM5
014Ah
Conversion memory 4
ADC12MEM4
0148h
Conversion memory 3
ADC12MEM3
0146h
Conversion memory 2
ADC12MEM2
0144h
Conversion memory 1
ADC12MEM1
0142h
Conversion memory 0
ADC12MEM0
0140h
Interrupt-vector-word register
ADC12IV
01A8h
Inerrupt-enable register
ADC12IE
01A6h
Inerrupt-flag register
ADC12IFG
01A4h
Control register 1
ADC12CTL1
01A2h
Control register 0
ADC12CTL0
01A0h
ADC12
ADC memory-control register15
(Memory control
ADC memory-control register14
registers require byte
ADC memory-control register13
access)
ADC memory-control register12
ADC12MCTL15
08Fh
ADC12MCTL14
08Eh
ADC12MCTL13
08Dh
ADC12MCTL12
08Ch
ADC memory-control register11
ADC12MCTL11
08Bh
ADC memory-control register10
ADC12MCTL10
08Ah
ADC memory-control register9
ADC12MCTL9
089h
ADC memory-control register8
ADC12MCTL8
088h
ADC memory-control register7
ADC12MCTL7
087h
ADC memory-control register6
ADC12MCTL6
086h
ADC memory-control register5
ADC12MCTL5
085h
ADC memory-control register4
ADC12MCTL4
084h
ADC memory-control register3
ADC12MCTL3
083h
ADC memory-control register2
ADC12MCTL2
082h
ADC memory-control register1
ADC12MCTL1
081h
ADC memory-control register0
ADC12MCTL0
080h
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SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS
LCD
LCD memory 20
:
LCD memory 16
LCD memory 15
:
LCD memory 1
LCD control and mode
LCDM20
:
LCDM16
LCDM15
:
LCDM1
LCDCTL
0A4h
:
0A0h
09Fh
:
091h
090h
UART1
(Only in ‘x44x)
Transmit buffer
UTXBUF1
07Fh
Receive buffer
URXBUF1
07Eh
Baud rate
UBR11
07Dh
Baud rate
UBR01
07Ch
Modulation control
UMCTL1
07Bh
Receive control
URCTL1
07Ah
Transmit control
UTCTL1
079h
UART control
UCTL1
078h
Transmit buffer
UTXBUF0
077h
Receive buffer
URXBUF0
076h
Baud rate
UBR10
075h
Baud rate
UBR00
074h
Modulation control
UMCTL0
073h
Receive control
URCTL0
072h
Transmit control
UTCTL0
071h
UART control
UCTL0
070h
Comp._A port disable
CAPD
05Bh
Comp._A control2
CACTL2
05Ah
Comp._A control1
CACTL1
059h
BrownOUT, SVS
SVS control register (Reset by brownout signal)
SVSCTL
056h
System
clock FLL+
y
FLL+ Control1
FLL+CTL1
054h
FLL+ Control0
FLL+CTL0
053h
System clock frequency control
SCFQCTL
052h
System clock frequency integrator
SCFI1
051h
System clock frequency integrator
SCFI0
050h
Basic Timer1
BT counter2
BT counter1
BT control
BTCNT2
BTCNT1
BTCTL
047h
046h
040h
Port P6
Port P6 selection
P6SEL
037h
Port P6 direction
P6DIR
036h
Port P6 output
P6OUT
035h
Port P6 input
P6IN
034h
Port P5 selection
P5SEL
033h
Port P5 direction
P5DIR
032h
Port P5 output
P5OUT
031h
Port P5 input
P5IN
030h
UART0
Comparator_A
p
_
Port P5
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
47
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS
Port P4
Port P3
Port P2
Port P1
Special
functions
p
Port P4 selection
P4SEL
01Fh
Port P4 direction
P4DIR
01Eh
Port P4 output
P4OUT
01Dh
Port P4 input
P4IN
01Ch
Port P3 selection
P3SEL
01Bh
Port P3 direction
P3DIR
01Ah
Port P3 output
P3OUT
019h
Port P3 input
P3IN
018h
Port P2 selection
P2SEL
02Eh
Port P2 interrupt enable
P2IE
02Dh
Port P2 interrupt-edge select
P2IES
02Ch
Port P2 interrupt flag
P2IFG
02Bh
Port P2 direction
P2DIR
02Ah
Port P2 output
P2OUT
029h
Port P2 input
P2IN
028h
Port P1 selection
P1SEL
026h
Port P1 interrupt enable
P1IE
025h
Port P1 interrupt-edge select
P1IES
024h
Port P1 interrupt flag
P1IFG
023h
Port P1 direction
P1DIR
022h
Port P1 output
P1OUT
021h
Port P1 input
P1IN
020h
SFR module enable2
ME2
005h
SFR module enable1
ME1
004h
SFR interrupt flag2
IFG2
003h
SFR interrupt flag1
IFG1
002h
SFR interrupt enable2
IE2
001h
SFR interrupt enable1
IE1
000h
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.1 V
Voltage applied to any pin (referenced to VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA
Storage temperature, Tstg: (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
(programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE: All voltages referenced to VSS.
48
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
recommended operating conditions
MIN
NOM
MAX
UNITS
Supply voltage during program execution,
VCC (AVCC = DVCC2 = VCC)
MSP430F43x,
MSP430F44x
1.8
3.6
V
Supply voltage during flash memory programming, VCC
(AVCC = DVCC2 = VCC)
MSP430F43x,
MSP430F44x
2.7
3.6
V
Supply voltage during program execution, SVS enabled (see
Note 1),
VCC (VCC = DVCC = VCC)
MSP430F43x,
MSP430F44x
2
3.6
V
0
0
V
–40
85
°C
Supply voltage, VSS
MSP430x43x
MSP430x44x
Operating free-air temperature range, TA
LFXT1 crystal frequency, f(LFXT1)
(see Note 2)
LF selected,
XTS_FLL=0
Watch crystal
XT1 selected,
XTS_FLL=1
Ceramic resonator
XT1 selected,
XTS_FLL=1
Crystal
Ceramic resonator
XT2 crystal
cr stal frequency,
freq enc f(XT2)
Crystal
32.768
kHz
450
8000
kHz
1000
8000
kHz
450
8000
1000
8000
DC
4.15
DC
8
257
476
kHz
3
ms
kH
kHz
Processor frequency
freq enc (signal MCLK)
MCLK), f(System)
VCC = 1.8 V
VCC = 3.6 V
Flash-timing-generator frequency, f(FTG)
MSP430F43x,
MSP430F44x
Cumulative program time, t(CPT) (see Note 3)
VCC = 2.7 V/3.6 V
MSP430F43x
MSP430F44x
Mass erase time, t(MEras) (See also the flash memory, timing
generator, control register FCTL2 section, see Note 4)
VCC = 2.7 V/3.6 V
Low-level input voltage (TCK, TMS, TDI, RST/NMI), VIL
(excluding Xin, Xout)
VCC = 2.2 V/3 V
VSS
VSS + 0.6
V
High-level input voltage (TCK, TMS, TDI, RST/NMI), VIH
(excluding Xin, Xout)
VCC = 2.2 V/3 V
0.8 × VCC
VCC
V
VCC = 2.2 V/3 V
VSS
0.8 × VCC
0.2 × VSS
V
Input levels at Xin and Xout
VIL(Xin, Xout)
VIH(Xin, Xout)
200
MH
MHz
ms
VCC
NOTES: 1. The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing the supply
voltage. POR is going inactive when the supply voltage is raised above the minimum supply voltage plus the hysteresis of the SVS
circuitry.
2. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.
3. The cumulative program time must not be exceeded during a segment-write operation. This parameter is only relevant if segment
write option is used.
4. The mass erase duration generated by the flash timing generator is at least 11.1 ms. The cumulative mass erase time needed is
200 ms. This can be achieved by repeating the mass erase operation until the cumulative mass erase time is met (a minimum of
19 cycles may be required).
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
49
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
typical characteristics
f (MHz)
8 MHz
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
Supply voltage range,
’F43x/’F44x, during
program execution
4.15 MHz
1.8
Supply voltage range, ’F43x/’F44x,
during flash memory programming
2.7
3
Supply Voltage – V
3.6
Figure 8. Frequency vs Supply Voltage, MSP430F43x or MSP430F44x
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
supply current into AVCC + DVCC excluding external current, f(System) = 1 MHz
PARAMETER
TEST CONDITIONS
Active mode, (see Note 1)
f(MCLK) = f(SMCLK) = 1 MHz,
f(ACLK) = 32,768 Hz
XTS=0, SELM=(0,1)
F43x,
F44x
40°C to 85°C
TA = –40°C
I(LPM0)
Low ower mode, (LPM0)
Low-power
(see Note 1)
F43x,
F44x
TA = –40°C
40°C to 85°C
I(LPM2)
Low-power mode, (LPM2),
f(MCLK) = f (SMCLK) = 0 MHz,
MHz
f(ACLK) = 32.768 Hz, SCG0 = 0 (see Note 2)
I(AM)
TA = –40°C
40°C to 85°C
TA = –40°C
TA = 25°C
I(LPM3)
Low ower mode, (LPM3)
Low-power
f((MCLK)) = f((SMCLK)) = 0 MHz,
f(ACLK) = 32,768
32 768 Hz,
Hz SCG0 = 1 (see Note 3)
TA = 60°C
TA = 85°C
TA = –40°C
TA = 25°C
TA = 60°C
TA = 85°C
TA = –40°C
TA = 25°C
I(LPM4)
Low-power mode, (LPM4)
f(MCLK) = 0 MHz,
MHz,
MHz f(SMCLK) = 0 MHz
f(ACLK) = 0 Hz,
SCG0 = 1 (see Note 2)
TA = 60°C
TA = 85°C
TA = –40°C
TA = 25°C
TA = 60°C
TA = 85°C
MIN
NOM
MAX
VCC = 2.2 V
280
350
VCC = 3 V
420
560
VCC = 2.2 V
VCC = 3 V
32
45
55
70
VCC = 2.2 V
11
14
VCC = 3 V
17
22
UNIT
A
µA
VCC = 2.2
22V
VCC = 3 V
22V
VCC = 2.2
VCC = 3 V
1
1.5
1.1
1.5
2
3
3.5
6
1.8
2.2
1.6
1.9
2.5
3.5
4.2
7.5
0.1
0.5
0.1
0.5
0.7
1.1
1.7
3
0.1
0.5
0.1
0.5
0.8
1.2
1.9
3.5
µA
A
µA
A
µA
A
µA
A
A
µA
µA
A
NOTES: 1. Timer_B is clocked by f(DCOCLK) = 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
2. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
3. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The current consumption in LPM3 is measured with
active Basic Timer1 and LCD (ACLK selected). The current consumption of the Comparator_A and the SVS module are specified
in the respective sections. The LPM3 currents are characterized with a KDS Daishinku DT–38 (6 pF) crystal and OscCap=1.
50
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Current consumption of active mode versus system frequency, F-version:
I(AM) = I(AM) [1 MHz] × f(System) [MHz]
Current consumption of active mode versus supply voltage, F-version:
I(AM) = I(AM) [3 V] + 175 µA/V × (VCC – 3 V)
SCHMITT-trigger inputs – ports P1, P2, P3, P4, P5, and P6; RST/NMI; JTAG: TCK, TMS, TDI, TDO
PARAMETER
TEST CONDITIONS
VIT+
Positi e going input
Positive-going
inp t threshold voltage
oltage
VIT–
Negati e going inp
Negative-going
inputt threshold voltage
oltage
Vhys
h
Input voltage hysteresis (VIT
IT+ – VIT
IT–)
MIN
TYP
MAX
VCC = 2.2 V
VCC = 3 V
VCC = 2.2 V
1.1
1.5
1.5
1.9
0.4
0.9
VCC = 3 V
VCC = 2.2 V
0.9
1.3
0.3
1.1
VCC = 3 V
0.5
1
UNIT
V
V
V
outputs – ports P1, P2, P3, P4, P5, and P6
PARAMETER
VOH
VOL
High level output voltage
High-level
Low level output voltage
Low-level
TEST CONDITIONS
MIN
IOH(max) = –1.5 mA,
IOH(max) = –6 mA,
VCC = 2.2 V,
VCC = 2.2 V,
See Note 1
IOH(max) = –1.5 mA,
IOH(max) = –6 mA,
VCC = 3 V,
VCC = 3 V,
See Note 1
IOL(max) = 1.5 mA,
IOL(max) = 6 mA,
VCC = 2.2 V,
VCC = 2.2 V,
See Note 1
IOL(max) = 1.5 mA,
IOL(max) = 6 mA,
VCC = 3 V,
VCC = 3 V,
See Note 1
See Note 2
See Note 2
See Note 2
See Note 2
TYP
MAX
VCC–0.25
VCC–0.6
VCC
VCC
VCC–0.25
VCC–0.6
VCC
VCC
VSS
VSS
VSS+0.25
VSS+0.6
VSS
VSS
VSS+0.25
VSS+0.6
UNIT
V
V
NOTES: 1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to satisfy the maximum
specified voltage drop.
2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to satisfy the maximum
specified voltage drop.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
51
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
typical characteristics
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
25
TA = 25°C
VCC = 2.2 V
P2.7
14
12
I OL – Typical High-level Output Current – mA
I OL – Typical High-level Output Current – mA
16
TA = 85°C
10
8
6
4
2
0
0.0
0.5
1.0
1.5
2.0
VCC = 3 V
P2.7
TA = 85°C
15
10
5
0
0.0
2.5
TA = 25°C
20
0.5
VOL – Low-Level Output Voltage – V
1.0
Figure 9
I OL – Typical High-level Output Current – mA
I OL – Typical High-level Output Current – mA
–6
–8
TA = 85°C
–12
TA = 25°C
0.5
3.5
1.0
1.5
2.0
2.5
VCC = 3 V
P2.7
–5
–10
–15
–20
TA = 85°C
–25
–30
0.0
VOH – High-Level Output Voltage – V
TA = 25°C
0.5
1.0
1.5
Figure 12
POST OFFICE BOX 655303
2.0
2.5
3.0
VOH – High-Level Output Voltage – V
Figure 11
52
3.0
0
VCC = 2.2 V
P2.7
–4
–14
0.0
2.5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0
–10
2.0
Figure 10
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
–2
1.5
VOL – Low-Level Output Voltage – V
• DALLAS, TEXAS 75265
3.5
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
input frequency – ports P1, P2, P3, P4, P5, and P6
PARAMETER
TEST CONDITIONS
f(IN)
MIN
TYP
VCC = 2.2 V
VCC = 3 V
t(h) = t(L)
MAX
8
10
UNIT
MHz
capture timing _ Timer_A3: TA0, TA1, TA2; Timer_B7: TB0 to TB6
PARAMETER
t(int)
TEST CONDITIONS
Ports
P
t P2
P2, P4
P4:
External trigger signal for the interrupt flag (see Note 1 and Note 2)
MIN
VCC = 2.2 V/3 V
VCC = 2.2 V
TYP
MAX
1.5
UNIT
Cycle
62
VCC = 3 V
50
NOTES: 1. The external signal sets the interrupt flag every time t(int) is met. It may be set even with trigger signals shorter than t(int).
The conditions to set the flag must be met independently of this timing constraint. t(int) is defined in MCLK cycles.
2. The external signal needs additional timing because of the maximum input-frequency constraint.
ns
output frequency
PARAMETER
f(Px.y)
(1 ≤ x ≤ 6,
6 0 ≤ y ≤ 7)
CL = 20 pF,
F,
IL = ±1.5mA
f(ACLK)
f(MCLK)
P1.1/TA0/MCLK,
P1
1/TA0/MCLK P1.5/TACLK/
P1 5/TACLK/
ACLK P1.4/TBCLK/SMCLK
P1 4/TBCLK/SMCLK
CL = 20 pF
F
TEST CONDITIONS
MIN
VCC = 2.2 V
VCC = 3 V
DC
TYP
MAX
5
DC
7.5
f(System)
UNIT
MH
MHz
MHz
f(SMCLK)
P1.5/TACLK/ACLK,
CL = 20 pF
F
VCC = 2.2 V / 3 V
t(Xdc)
Duty cycle of output frequency
P1.1/TA0/MCLK,
CL = 20 pF,
VCC = 2.2 V / 3 V
f(ACLK) = f(LFXT1) = f(XT1)
f(ACLK) = f(LFXT1) = f(LF)
f(ACLK) = f(LFXT1)
f(MCLK) = f(XT1)
f(MCLK) = f(DCOCLK)
P1.4/TBCLK/SMCLK,
CL = 20 pF,
VCC = 2.2 V / 3 V
60%
30%
70%
50%
40%
60%
50%–
15 ns
50%+
15 ns
f(SMCLK) = f(XT2)
f(SMCLK) = f(DCOCLK)
40%
50%
40%
60%
50%–
15 ns
50%
50%+
15 ns
external interrupt timing
PARAMETER
t(int)
TEST CONDITIONS
Ports
P
t P1
P1, P2
P2:
External trigger signal for the interrupt flag (see Note 3 and Note 4)
VCC = 2.2 V/3 V
VCC = 2.2 V
MIN
TYP
MAX
1.5
UNIT
Cycle
62
VCC = 3 V
50
NOTES: 3. The external signal sets the interrupt flag every time t(int) is met. It may be set even with trigger signals shorter than t(int).
The conditions to set the flag must be met independently of this timing constraint. t(int) is defined in MCLK cycles.
4. The external signal needs additional timing because of the maximum input-frequency constraint.
ns
wake-up LPM3
PARAMETER
TEST CONDITIONS
f = 1 MHz
td(LPM3)
Delay time
f = 2 MHz
TYP
MAX
UNIT
6
VCC = 2.2 V/3 V
f = 3 MHz
POST OFFICE BOX 655303
MIN
• DALLAS, TEXAS 75265
6
µs
6
53
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
leakage current (see Notes 1 and 2)
PARAMETER
Ilkg(P1.x)
Ilkg(P6.x)
Leakage
current
TEST CONDITIONS
Port P1
Port 1: V(P1.x)
Port P6
Port 6: V(P6.x)
MIN
TYP
MAX
±50
VCC = 2
2.2
2 V/3 V
±50
UNIT
nA
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The port pin must be selected as input and there must be no optional pullup or pulldown resistor.
RAM
PARAMETER
TEST CONDITIONS
VRAMh
MIN
CPU halted (see Note 3)
TYP
MAX
1.6
UNIT
V
NOTE 3: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution
should take place during this supply voltage condition.
LCD
PARAMETER
V(33)
V(23)
V(13)
V(33) – V(03)
2.5
Voltage at P5.5/R13
R03 = VSS
Input leakage
g
P5.5/R13 = VCC/3
P5.6/R23 = 2 × VCC/3
Segment line
voltage
g
I(Sxx)
3 µA
µA,
(S ) = –3
2.5
No load at all
segment and
common lines
lines,
VCC = 3 V
VCC = 3 V
V(Sxx3)
54
POST OFFICE BOX 655303
TYP
MAX
UNIT
VCC + 0.2
[V(33)–V(03)] × 2/3 + V(03)
[V(33)–V(03)] × 1/3 + V(03)
VCC = 3 V
Voltage at R33 to R03
I(R23)
V(Sxx0)
V(Sxx1)
V(Sxx2)
MIN
Voltage at P5.6/R23
Analog voltage
oltage
I(R03)
I(R13)
TEST CONDITIONS
Voltage at P5.7/R33
V
VCC + 0.2
±20
±20
nA
±20
V(03)
V(13)
V(03) – 0.1
V(13) – 0.1
V(23)
V(33)
V(23) – 0.1
V(33) + 0.1
• DALLAS, TEXAS 75265
V
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Comparator_A (see Note 1)
PARAMETER
TEST CONDITIONS
I(CC)
CAON 1 CARSEL
CAON=1,
CARSEL=0,
0 CAREF
CAREF=0
0
I(Refladder/RefDiode)
CAON=0, CARSEL=0, CAREF=1/2/3,
No load at P2.3/CA0/TA1
P2 3/CA0/TA1 and
P2.4/CA1/TA2
V(Ref025)
Voltage @ 0.25 V
MAX
VCC = 2.2 V
VCC = 3 V
25
40
45
60
VCC = 2.2 V
30
50
VCC = 3 V
45
71
UNIT
µA
A
µA
A
PCA0=1, CARSEL=1, CAREF=1,
No load at P2.3/CA0 and P2.4/CA1
VCC = 2.2 V / 3 V
0.23
0.24
0.25
node
PCA0=1, CARSEL=1, CAREF=2,
No load at P2.3/CA0 and P2.4/CA1
VCC = 2.2V / 3 V
0.47
0.48
0.5
PCA0=1, CARSEL=1, CAREF=3,
No load at P2.3/CA0
P2 3/CA0 and P2.4/CA1;
P2 4/CA1;
TA = 85°C
VCC = 2.2 V
390
480
540
VCC = 3 V
400
490
550
Common-mode input
voltage range
CAON=1
VCC = 2.2 V / 3 V
0
VCC–1
Offset voltage
See Note 2
VCC = 2.2 V / 3 V
–30
30
mV
Input hysteresis
CAON = 1
VCC = 2.2 V / 3 V
VCC = 2.2 V
0
0.7
1.4
mV
160
210
300
80
150
240
1.4
1.9
3.4
0.9
1.5
2.6
130
210
300
80
150
240
1.4
1.9
3.4
CC
V
V(Ref050)
V
CC
CC
V(RefVT)
Vp–VS
Vhys
TYP
node
CC
Voltage @ 0.5 V
VIC
MIN
TA = 25
25°C,
C,
Overdrive 10 mV, without filter: CAF = 0
t(response LH)
TA = 25
25°C
C
Overdrive 10 mV, with filter: CAF = 1
TA = 25
25°C
C
Overdrive 10 mV, without filter: CAF = 0
t(response HL)
25°C,
TA = 25
C,
Overdrive 10 mV, with filter: CAF = 1
mV
VCC = 3 V
VCC = 2.2 V
VCC = 3 V
VCC = 2.2 V
VCC = 3 V
VCC = 2.2 V
V
ns
µss
ns
µss
VCC = 3 V
0.9
1.5
2.6
NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification.
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.
The two successive measurements are then summed together.
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SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
typical characteristics
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
650
650
VCC = 3 V
VCC = 2.2 V
VREF – Reference Voltage – V
VREF – Reference Voltage – V
600
Typical
550
500
450
400
–45
–25
–5
15
35
55
75
600
Typical
550
500
450
400
–45
95
TA – Free-Air Temperature – °C
–25
–5
15
35
55
Figure 13. V(RefVT) vs Temperature
Figure 14. V(RefVT) vs Temperature
0 V VCC
0
1
CAF
CAON
Low-Pass Filter
V+
V–
+
_
0
0
1
1
To Internal
Modules
CAOUT
Set CAIFG
Flag
τ ≈ 2 µs
Figure 15. Block Diagram of Comparator_A Module
VCAOUT
Overdrive
V–
400 mV
V+
t(response)
Figure 16. Overdrive Definition
56
75
TA – Free-Air Temperature – °C
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95
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
POR/brownout reset (BOR) (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
dVCC/dt ≥ 30 V/ms (see Note 2)
dVCC/dt ≤ 30 V/ms (see Note 2)
td(BOR)
V(B_IT–)
Vhys(B_IT–)
2000
0.7 × V(B_IT–)
dVCC/dt ≤ 3 V/s (see Figure 17 through Figure 19)
dVCC/dt ≤ 3 V/s (see Figure 17)
Brownout
MAX
150
dVCC/dt ≤ 3 V/s (see Figure 17)
VCC(start)
TYP
5
UNIT
µs
V
0.9
1.35
1.71
V
70
130
180
mV
Pulse length needed at RST/NMI pin to accepted reset internally,
2
µs
VCC = 2.2 V/3 V
NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT–)
+ Vhys(B_IT–) is ≤ 1.8 V.
2. This parameter is not production tested, assured by design.
t(reset)
typical characteristics
VCC
Vhys(B_IT–)
V(B_IT–)
VCC(start)
1
0
t d(BOR)
Figure 17. POR/Brownout Reset (BOR) vs Supply Voltage
VCC
3V
2
VCC(min)– V
Vcc = 3 V
typical conditions
t pw
1.5
1
VCC(min)
0.5
0
0.001
1
1000
1 ns
tpw – Pulse Width – µs
1 ns
tpw – Pulse Width – µs
Figure 18. V(CC)min Level With a Square Voltage Drop to Generate a POR/Brownout Signal
POST OFFICE BOX 655303
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57
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
typical characteristics
VCC
VCC(min)– V
2
1.5
t pw
3V
Vcc = 3 V
typical conditions
1
VCC(min)
0.5
0
0.001
tf = tr
1
1000
tf
tr
tpw – Pulse Width – µs
tpw – Pulse Width – µs
Figure 19. VCC(min) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
SVS (supply voltage supervisor/monitor)
PARAMETER
TEST CONDITIONS
MIN
t(SVSR)
dVCC/dt ≥ 30 V/ms (see Figure 20)
dVCC/dt ≤ 30 V/ms
5
td(SVSon)
tsettle
SVSon, switch from VLD=0 to VLD ≠ 0, VCC = 3 V
VLD ≠ 0‡
20
V(SVSstart)
VLD ≠ 0, VCC/dt ≤ 3 V/s (see Figure 20)
NOM
1.55
VLD = 1
VCC/dt ≤ 3 V/s (see Figure 20)
VLD = 2 .. 14
Vhys(B_IT–)
hys(B IT–)
VCC/dt ≤ 3 V/s (see Figure 20), External voltage applied
on A7
VCC/dt ≤ 3 V/s (see Figure 20)
V(SVS
IT )
(SVS_IT–)
VCC/dt ≤ 3 V/s (see Figure 20), External voltage applied
on A7
VLD = 15
70
120
V(SVS_IT–)
x 0.004
MAX
UNIT
150
µs
2000
µs
150
µs
12
µs
1.7
V
155
mV
V(SVS_IT–)
x 0.008
4.4
10.4
VLD = 1
1.8
1.9
2.05
VLD = 2
1.94
2.1
2.25
VLD = 3
2.05
2.2
2.37
VLD = 4
2.14
2.3
2.48
VLD = 5
2.24
2.4
2.6
VLD = 6
2.33
2.5
2.71
VLD = 7
2.46
2.65
2.86
VLD = 8
2.58
2.8
3
VLD = 9
2.69
2.9
3.13
VLD = 10
2.83
3.05
3.29
VLD = 11
2.94
3.2
VLD = 12
3.11
3.35
VLD = 13
3.24
VLD = 14
3.43
3.5
3.7†
3.42
3.61†
3.76†
VLD = 15
1.1
1.2
mV
V
3.99†
1.3
ICC(SVS)
VLD ≠ 0, VCC = 2.2 V/3 V
10
15
µA
(see Note 1)
† The recommended operating voltage range is limited to 3.6 V.
‡ tsettle is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD ≠ 0 to a different VLD value somewhere
between 2 and 15. The overdrive is assumed to be > 50 mV.
NOTE 1: The current consumption of the SVS module is not included in the ICC current consumption data.
58
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SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
Software sets VLD >0:
SVS is active
VCC
V(SVS_IT–)
V(SVSstart)
Vhys(SVS_IT–)
Vhys(B_IT–)
V(B_IT–)
VCC(start)
Brownout
Region
Brownout
Region
Brownout
1
0
SVSOut
1
td(BOR)
t d(BOR)
SVS Circuit is Active From VLD > to VCC < V(B_IT–)
0
td(SVSon)
Set POR
1
td(SVSR)
undefined
0
Figure 20. SVS Reset (SVSR) vs Supply Voltage
VCC
3V
t pw
2
Rectangular Drop
VCC(min)– V
1.5
Triangular Drop
1
1 ns
1 ns
0.5
VCC
t pw
3V
0
1
10
100
1000
tpw – Pulse Width – µs
VCC(min)
tf = tr
tf
tr
t – Pulse Width – µs
Figure 21. VCC(min) With a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal
POST OFFICE BOX 655303
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59
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
DCO
PARAMETER
f(DCOCLK)
TEST CONDITIONS
N(DCO)=01E0h, FN_8=FN_4=FN_3=FN_2=0, D = 2, DCO+= 0
f(DCO2)
FN 8 FN 4 FN 3 FN 2 0 , DCO+
FN_8=FN_4=FN_3=FN_2=0
DCO = 1
f(DCO27)
FN 8 FN 4 FN 3 FN 2 0 DCO+
FN_8=FN_4=FN_3=FN_2=0,
DCO = 1,
1 (see Note 1)
VCC
2.2 V/3 V
MIN
TYP
2.2 V
0.23
0.41
0.82
3V
0.3
0.57
1.2
2.2 V
2.25
4
8
3V
3
5.6
11.2
2.2 V
0.45
0.85
1.75
3V
0.6
1.2
2.4
2.2 V
4.4
8
16.5
3V
6
11
22.5
2.2 V
0.73
1.3
2.7
3V
1
1.85
3.9
2.2 V
6.5
12
24
3V
9
16.5
34
2.2 V
1.1
2.1
4.3
3V
1.6
2.9
6
2.2 V
9.5
18
38
3V
13
25
52
2.2 V
2.2
4
8.2
3V
3
5.6
12
2.2 V
17.5
32
65
3V
24
45
94
2 < TAP ≤ 20
1.06
FN_8=FN_4=FN_3=0, FN_2=1
FN_2=1; DCO+ = 1
f(DCO2)
f(DCO27)
FN 8 FN 4 FN 3 0 FN
FN_8=FN_4=FN_3=0,
FN_2=1;
2 1 DCO
DCO+ = 1
1, (see Note 1)
f(DCO2)
FN 8 FN 4 0 FN
3 1
FN 2 x DCO+
DCO = 1
FN_8=FN_4=0,
FN_3=
1, FN_2=x;
f(DCO27)
FN 8 FN 4 0 FN
FN_8=FN_4=0,
FN_3=
3 1
1, FN
FN_2=x;,
2
DCO
DCO+ = 1
1, (see Note 1)
f(DCO2)
FN 8 0 FN_4=
FN_8=0,
FN 4 1,
1 FN_3=
FN 3 FN_2=x;
FN 2
DCO+
DCO = 1
f(DCO27)
FN 8 0 FN
FN_8=0,
FN_4=1,
4 1 FN
FN_3=
3 FN
FN_2=x;
2
DCO
DCO+ = 1
1, (see Note 1)
f(DCO2)
FN 8 1 FN
FN_8=1,
FN_4=FN_3=FN_2=x;
4 FN 3 FN 2
DCO
DCO+ = 1
f(DCO27)
FN 8 1 FN 4 FN 3 FN 2 x DCO = 1,
1 (see Note 1)
FN_8=1,FN_4=FN_3=FN_2=x,DCO+
S
f(NDCO)+1 = f(NDCO)
Dt
1
MH
MHz
MH
MHz
MH
MHz
MH
MHz
MHz
MH
MHz
MH
MHz
MH
MHz
MH
MHz
MHz
1.13
1.1
2.2 V
–0.2
–0.3
–0.4
3V
–0.2
–0.3
–0.4
0
5
15
40
60
Drift with VCC variation, N(DCO) = 01E0h, FN_8=FN_4=FN_3=FN_2=0
D = 2, DCO+ = 0 (see Note 2)
UNIT
MHz
TAP > 20
Tem erature drift, N(DCO) = 01E0h, FN_8=FN_4=FN_3=FN_2=0
Temperature
D = 2, DCO+ = 0, (see Note 2)
DV
MAX
1.17
%/_C
%/V
NOTES: 1. Please do not exceed the maximum system frequency.
2. This parameter not production tested.
f(DCO)
f(DCO3V)
f(DCO)
f(DCO20oC)
1
1
1.8
2.2
2.4
3.0
3.6
VCC – V
–40
0
20
Figure 22. DCO Frequency vs Supply Voltage (VCC) and vs Ambient Temperature
60
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
85
TA – °C
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
Legend
Tolerance at Tap 27
DCO Frequency
Adjusted by Bits
29 to 2 5 in SCFI1 {N (DCO)}
Tolerance at Tap 2
Overlapping DCO Ranges:
uninterrupted frequency range
FN_2=0
FN_3=0
FN_4=0
FN_8=0
FN_2=1
FN_3=0
FN_4=0
FN_8=0
FN_2=x
FN_3=1
FN_4=0
FN_8=0
FN_2=x
FN_3=x
FN_4=1
FN_8=0
FN_2=x
FN_3=x
FN_4=x
FN_8=1
Figure 23. Five Overlapping DCO Ranges Controlled by FN_x Bits
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
crystal oscillator, LFXT1 oscillator (see Note 1 and 2)
PARAMETER
C(XIN)
C(XOUT)
Integrated input
inp t capacitance
Integrated output
o tp t capacitance
TEST CONDITIONS
OscCap = 0, VCC = 2.2 V / 3 V
OscCap = 1, VCC = 2.2 V / 3 V
MIN
TYP
UNIT
10
OscCap = 2, VCC = 2.2 V / 3 V
OscCap = 3, VCC = 2.2 V / 3 V
14
OscCap = 0, VCC = 2.2 V / 3 V
OscCap = 1, VCC = 2.2 V / 3 V
0
OscCap = 2, VCC = 2.2 V / 3 V
OscCap = 3, VCC = 2.2 V / 3 V
MAX
0
pF
18
10
14
pF
18
NOTES: 1. The parasitic capacitance from the package and board may be estimated to be 2 pF. The effective load capacitor for the crystal is
(X(CIN) x X(COUT)) / (X(CIN) + X(COUT)). This is independent of XST_FLL.
2. To improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines should be observed.
– Keep as short of a trace as possible between the F43x/44x and the crystal.
– Design a good ground plane around the oscillator pins.
– Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
– Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
– Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
– If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
– Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
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61
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
crystal oscillator, XT2 oscillator (see Note 1)
PARAMETER
XCIN
XCOUT
XINL
XINH
Integrated input capacitance
TEST CONDITIONS
Integrated output capacitance
VCC = 2.2 V/3 V
VCC = 2.2 V/3 V
Input levels at XIN
XIN, XOUT
VCC = 2.2
2 2 V/3 V
MIN
NOM
VSS
0.8 × VCC
MAX
UNIT
2
pF
2
pF
0.2 × VCC
V
VCC
V
NOTE 1: The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.
USART0, USART1 (see Note 2)
PARAMETER
t(τ)
( )
USART0/1: deglitch time
TEST CONDITIONS
VCC = 2.2 V
VCC = 3 V
MIN
NOM
MAX
200
430
800
150
280
500
UNIT
ns
NOTE 2: The signal applied to the USART0/1 receive signal/terminal (URXD0/1) should meet the timing requirements of t(t) to ensure that the
URXS flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t(t). The operating
conditions to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative
transitions on the URXD0/1 line.
62
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SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, power supply and input range conditions (see Note 1)
PARAMETER
AVCC
Analog supply
voltage
TEST CONDITIONS
AVCC and DVCC are connected together
AVSS and DVSS are connected together
V(AVSS) = V(DVSS) = 0 V
0 mA ≤ I(Load) ≤ 0.5 mA
VCC(min)
CC( i )
0.5 mA ≤ I(Load) ≤ 1.5 mA
VO(REF+)
O(REF )
IL(VREF+)
L(VREF )
IL(VREF+)†
Positive built-in
reference voltage
output
2_5 V = 1 for 2.5-V built-in
reference
2
5 V = 0 for 1
5 V built-in
built in
2_5
1.5-V
reference
I(VREF+) ≤ I(VREF+_max)
Load current out of
VREF+ terminal
Load-current
regulation VREF+
terminal
I((VREF+)) = 500 µA ±100 µA
Analog input voltage ~0.75
0 75 V;
2_5 V = 0
I(VREF+) = 500 µA ± 100 µA
Analog input voltage ~1.25 V;
2_5 V = 1
VCC = 3 V
MIN
NOM
MAX
2.2
3.6
VREF+
VREF+ +
150 mV
VREF+
VREF+ +
350 mV
2.4
2.5
UNIT
V
2.6
V
VCC = 2.2 V/3 V
1.44
VCC = 2.2 V
VCC = 3 V
0.01
1.5
1.56
–0.5
–1
mA
VCC = 2.2 V
±2
VCC = 3 V
±2
VCC = 3 V
±2
LSB
20
ns
LSB
IL(VREF+)‡
Load current
regulation VREF+
terminal
I(VREF+) =100 µA → 900 µA,
VCC = 3 V, ax ~0.5 x VREF+
C(VREF+)
(VREF ) = 5 µF
Error of conversion result
≤ 1 LSB
Vref(VREF+)
Positive external
reference voltage
input
VeREF+ > VeREF–/VeREF– (see Note 2)
1.4
V(AVCC)
V
Vref(VREF– /VeREF–)
Negative external
reference voltage
input
VeREF+ > VeREF–/VeREF– (see Note 3)
0
1.2
V
† Not production tested, limits characterized
‡ Not production tested, limits verified by design
NOTES: 1. The leakage current is defined in the leakage current table with P6.x/Ax parameter.
2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
3. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
4. The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
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SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
12-bit ADC, power supply and input range conditions (see Note 1) (continued)
PARAMETER
(VeREF+ –
VREF–/VeREF–)
Differential external
reference voltage
input
VI(P6.x/Ax)
Analog input voltage
range (see Note 5)
TEST CONDITIONS
VeREF+ > VeREF–/VeREF– (see Note 4)
All P6.0/A0 to P6.7/A7/SVSin terminals. Analog
inputs selected in ADC12MCTLx register and
P6Sel.x=1
0 ≤ x ≤ 7; V(AVSS) ≤ VI(P6.x/Ax) ≤ V(AVCC)
f(ADC12CLK) = 5 MHz
VCC = 2.2 V
ADC12ON = 1, REFON = 0
SHT0=0, SHT1=0,
VCC = 3 V
ADC12DIV=0
Operating supply
current into AVCC
terminal (see
Note 6)
Operating supply
current into AVCC
terminal (see
Note 7)
IDD(ADC12)
IDD(REF+)
MIN
f(ADC12CLK) = 5 MHz
ADC12ON = 0,
REFON = 1, 2_5V = 1
NOM
MAX
UNIT
1.4
V(AVCC)
V
0
V(AVCC)
V
0.65
1.3
0.8
1.6
VCC = 3 V
0.5
0.8
VCC = 2.2 V
0.5
0.8
VCC = 3 V
0.5
0.8
mA
mA
f((ADC12CLK)) = 5 MHz
ADC12ON = 0,
0
REFON = 1, 2_5V = 0
O erating su
Operating
supply
ly
current (see Note 7)
NOTES: 5. The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results.
6. The internal reference supply current is not included in current consumption parameter IDD(ADC12).
7. The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
12-bit ADC, built-in reference (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
IDD(VeREF+)
Static input current
(see Note 2)
0 V ≤ VeREF+ ≤ V(AVCC)
VCC = 2.2 V/3 V
±1
µA
IDD(VREF–/VeREF–)
Static input current
(see Note 2)
0 V ≤ VeREF– ≤ V(AVCC)
VCC = 2.2 V/3 V
±1
µA
C(VREF+)
Capacitance at pin
VREF+ (see Note 3)
REFON = 1,
0 mA ≤ I(VREF+) ≤ I(VREF_max)
VCC = 2.2 V/3 V
Ci‡
Input capacitance
(see Note 4)
Only one terminal can be selected
at one time, P6.x/Ax
VCC = 2.2 V
Zi‡
Input MUX ON
resistance (see Note 4)
0 V ≤ V(Ax) ≤ V(AVCC)
T(REF+)†
Temperature coefficient
of built-in reference
I(VREF+) is a constant in the range
of 0 mA ≤ I(VREF+) ≤ 1 mA
5
µF
10
40
pF
VCC = 3 V
2000
Ω
VCC = 2.2 V/3 V
±100 ppm/°C
† Not production tested, limits characterized
‡ Not production tested, limits verified by design
NOTES: 1. The voltage source on VeREF+ and VREF–/VeREF– needs to have low-dynamic impedance for 12-bit accuracy to allow the charge
to settle for this accuracy (See Figures 16 and 17).
2. The external reference is used during conversion to charge and discharge the capacitance array. The dynamic impedance should
follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
3. The internal buffer operational amplifier and the accuracy specifications require an external capacitor.
4. The input capacitance is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference
supply should follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy. All INL
and DNL tests uses two capacitors between pins VREF+ and AVSS and VREF–/VeREF– and AVSS: 10-µF tantalum and
100-nF ceramic.
64
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timing requirements
12-bit ADC, timing parameters
PARAMETER
Settle time of internal
reference voltage (see
Figure 24 and Note 1)
ts(REF_ON)†
f(ADC12OSC)
tc
Con ersion time
Conversion
ts(ADC12ON)‡
t(Sample)
(S
l )‡
Settle time of the ADC
Sampling time
TEST CONDITIONS
MIN
NOM
I(VREF+) = 0.5 mA, C(VREF+) = 10 µF,
VREF+ = 1.5 V, V(AVCC) = 2.2 V
MAX
UNIT
17
ms
ADC12DIV=0 [f(ADC12CLK) =
f(ADC12OSC)]
VCC = 2
2.2
2 V/3 V
37
3.7
63
6.3
MHz
MH
AVCC(min)≤ V(AVCC)≤ AVCC(max),
C(VREF+) ≥ 5 µF, internal oscillator,
fOSC = 3.7 MHz to 6.3 MHz
VCC = 2.2 V/3 V
2.06
3.51
µs
AVCC(min) ≤ V(AVCC) ≤ AVCC(max),
External fADC12(CLK) from ACLK or MCLK or SMCLK:
ADC12SSEL ≠ 0
AVCC(min) ≤ V(AVCC) ≤ AVCC(max) (see Note 2)
V(AVCC_min) < V(AVCC) <
VCC = 3 V
V(AVCC_max)
Ri(source) = 400 Ω, Zi = 1000 Ω,
Ci = 30 pF
τ = [Ri(source) x+ Zi] x Ci,
VCC = 2.2 V
(see Note 3)
13×ADC12DIV×
1/fADC12(CLK)
µs
100
ns
1220
ns
1400
† Not production tested, limits characterized
‡ Not production tested, limits verified by design
NOTES: 1. The condition is that the error in a conversion started after ts(REF_ON) is less than ±0.5 LSB. The settling time depends on the external
capacitive load.
2. The condition is that the error in a conversion started after ts(ADC12ON) is less than ±0.5 LSB. The reference and input signal are
already settled.
3. Ten Tau (τ) are needed to get an error of less than ±0.5 LSB. t(Sample) = 10 x (Ri + Zi) x Ci + 800 ns
C(VREF+)
100 µF
t(REF_ON) ~ 0.66 x C(VREF+) [ms] With C(VREF+) in µF
10 µF
1 µF
0
1 ms
10 ms
100 ms
t(REF_ON)
Figure 24. Typical Settling Time of Internal Reference t(REF_ON) vs External Capacitor on VREF+
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
65
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
12-bit ADC, linearity parameters, VCC = 2.2 V/3 V
PARAMETER
TEST CONDITIONS
MIN
NOM
1.4 V ≤ (VeREF+ – VREF–/VeREF–) min ≤ 1.6 V
E(I)
Integral linearity
linearit error
ED
Differential linearity error
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
C(VREF+) = 10 µF (tantalum) and 100 nF (ceramic)
EO
Offset error†
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
Internal impedance of source Ri < 100 Ω,
C(VREF+) = 10 µF (tantalum) and 100 nF (ceramic)
EG
Gain error†
E(T)
Total unadjusted error†
MAX
±2
±1.7
LSB
±1
LSB
±2
±4
LSB
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
C(VREF+) = 10 µF (tantalum) and 100 nF (ceramic)
±1.1
±2
LSB
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
C(VREF+) = 10 µF (tantalum) and 100 nF (ceramic)
±2
±5
LSB
1.6 V < [V(eREF+) – V(REF–)/V(eREF–)] min ≤ [V(AVCC)]
† Not production tested, limits characterized
From
Power
Supply
DVCC1/DVCC2
+
–
10 µ F
DVSS2/DVCC2
100 nF
AVCC
+
–
10 µ F
Apply External Reference (VeREF+)
or Use Internal Reference (VREF+)
AVSS
10 µ F
MSP430F44x
VREF+ or VeREF+
100 nF
VREF–/VeREF–
+
–
10 µ F
MSP430F43x
100 nF
+
–
Apply
External
Reference
100 nF
Figure 25. Supply Voltage and Reference Voltage Design VREF–/VeREF– External Supply
66
UNIT
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
From
Power
Supply
DVCC
+
–
10 µ F
DVSS
100 nF
AVCC
+
–
10 µ F
Apply External Reference (VeREF+)
or Use Internal Reference (VREF+)
AVSS
MSP430F44x
100 nF
VREF+ or VeREF+
+
–
10 µ F
MSP430F43x
100 nF
Reference Is Internally
Switched to AVSS
VREF–/VeREF–
Figure 26. Supply Voltage and Reference Voltage Design VREF–/VeREF– = AVSS, Internally Connected
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
12-bit ADC, temperature sensor and built-in Vmid
PARAMETER
ICC(SENSOR)
Operating supply current
into AVCC terminal
(see Note 1)
TEST CONDITIONS
V(REFON) = 0, INCH = 0Ah,
ADC12ON = NA, TA = 25_C
MIN
NOM
MAX
VCC = 2.2 V
40
120
VCC = 3 V
60
160
UNIT
µA
A
V(SENSOR)†
ADC12ON = 1, INCH = 0Ah,
TA = 0°C
2 V/3 V
VCC = 2
2.2
986
986±5%
mV
TC(SENSOR)†
ADC12ON = 1
1, INCH = 0Ah
2 V/3 V
VCC = 2
2.2
3 55
3.55
3
55±3%
3.55±3%
mV/°C
ts(SENSOR)†
Sample time required if
channel 10 is selected
(see Note 2)
ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
VCC = 2
2.2
2 V/3 V
V(MID)
AVCC divider
di ider at channel 11
ADC12ON = 1, INCH = 0Bh,
V(MID) is ~0.5 x V(AVCC)
VCC = 2.2 V
VCC = 3 V
t(ON_VMID)
(ON VMID)
On-time
On
time if channel 11 is
selected (see Note 3)
ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
2 V/3 V
VCC = 2
2.2
µss
30
1.1
1.1±0.04
1.5
1.5±0.04
NA
V
ns
† Not production tested, limits characterized
‡ Not production tested, limits verified by design
NOTES: 1. The sensor current ISENSOR is consumed if (ADC12ON = 1 and V(REFON) = 1), or (ADC12ON=1 AND INCH=0Ah and sample signal
is high). Therefore it includes the constant current through the sensor and the reference.
2. The typical equivalent impedance of the sensor is 51 kΩ. The sample time needed is the sensor-on time t(SENSOR_ON)
3. The on-time t(ON_VMID) is identical to sampling time t(Sample); no additional on time is needed.
POST OFFICE BOX 655303
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67
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
JTAG, program memory and fuse
PARAMETER
f(TCK)
JTAG/Testt
JTAG/T
(see Note 4)
TEST CONDITIONS
MIN
VCC = 2.2 V
VCC = 3 V
TCK freq
frequency
enc
Pull-up resistors on TMS, TCK, TDI (see Note 1)
V(FB)
I(FB)
I(DD-PGM)
I(DD-Erase)
t(retention)
( t ti )
NOTES: 1.
2.
3.
4.
68
Fuse-blow voltage, F versions (see Note 3)
JTAG/fuse
JTAG/f
(see Note 2)
VCC = 2.2 V/3 V
VCC = 2.2 V/3 V
NOM
DC
5
DC
10
25
60
6
Supply current on TDI with fuse blown
F versions only
F-versions
Current from DVCC when programming is active
Current from DVCC when erase is active
90
7
100
Time to blow the fuse
F versions only
F-versions
(see Note 4)
MAX
VCC = 2.7 V/3.6 V
VCC = 2.7 V/3.6 V
Write/erase cycles
104
Data retention TJ = 25°C
100
UNIT
MH
MHz
kΩ
V
mA
1
ms
3
5
mA
3
5
10
5
mA
cycles
years
TMS, TDI, and TCK pull-up resistors are implemented in all F versions.
Once the fuse is blown, no further access to the MSP430 JTAG/test feature is possible. The JTAG block is switched to bypass mode.
The supply voltage to blow the fuse is applied to the TDI pin.
f(TCK) may be restricted to meet the timing requirements of the module selected. Duration of the program/erase cycle is determined
by f(FTG) applied to the flash timing controller. It can be calculated as follows:
t(word write) = 33 x 1/f(FTG)
t(segment write, byte 0) = 30 x 1/f(FTG)
t(segment write end sequence) =5 x 1/f(FTG)
t(mass erase) = 5296 x 1/f(FTG)
t(segment erase) = 4817 x 1/f(FTG)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
input/output schematic
Port P1, P1.0 to P1.5, input/output with Schmitt-trigger
Pad Logic
CAPD.x
P1SEL.x
0: input
1: output
0
P1DIR.x
Direction Control
From Module
P1OUT.x
1
0
P1.x
1
Module X OUT
Bus
keeper
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/TBOutH/SVSOut
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
P1IN.x
EN
D
Module X IN
P1IE.x
P1IRQ.x
P1IFG.x
Q
EN
Set
Interrupt
Edge
Select
P1IES.x
Note: 0 < x< 5
Note: Port function is active if CAPD.x = 0
Direction
PnOUT.x
Control
From Module
P1SEL.x
Module X
OUT
PnSel.x
PnDIR.x
P1Sel.0
P1DIR.0
P1DIR.0
P1OUT.0
Out0 sig.
P1Sel.1
P1DIR.1
P1DIR.1
P1OUT.1
MCLK
P1Sel.2
P1DIR.2
P1DIR.2
P1OUT.2
Out1 sig.
P1Sel.3
P1DIR.3
P1DIR.3
P1OUT.3
SVSOut
†
†
PnIN.x
Module X IN
P1IN.0
CCI0A
P1IN.1
CCI0B
†
†
†
PnIE.x
PnIFG.x
PnIES.x
P1IE.0
P1IFG.0
P1IES.0
P1IE.1
P1IFG.1
P1IES.1
P1IE.2
P1IFG.2
P1IES.2
P1IN.2
CCI1A
P1IN.3
TBOutH
‡
P1IE.3
P1IFG.3
P1IES.3
‡
TBCLK
P1IE.4
P1IFG.4
P1IES.4
P1IE.5
P1IFG.5
P1IES.5
P1Sel.4
P1DIR.4
P1DIR.4
P1OUT.4
SMCLK
P1IN.4
P1Sel.5
P1DIR.5
P1DIR.5
P1OUT.5
ACLK
P1IN.5
TACLK
†
† Timer_A
‡ Timer_B
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
69
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
input/output schematic (continued)
Port P1, P1.6, P1.7, input/output with Schmitt-trigger
Pad Logic
Note: Port function is active if CAPD.6 = 0
CAPD.6
P1SEL.6
0: input
1: output
0
P1DIR.6
P1.6/
CA0
1
P1DIR.6
0
P1OUT.6
1
DVSS
Bus
keeper
P1IN.6
EN
unused
D
P1IE.7
P1IRQ.07
EN
Interrupt
Edge
Select
Q
P1IFG.7
Set
P1IES.x
P1SEL.x
Comparator_A
P2CA
AVcc
CAREF
CAEX
CA0
CAF
CCI1B
+
to Timer_Ax
–
CA1
2
CAREF
Reference Block
Pad Logic
CAPD.7
Note: Port function is active if CAPD.7 = 0
P1SEL.7
0: input
1: output
0
P1DIR.7
P1.7/
CA1
1
P1DIR.7
0
P1OUT.7
1
DVSS
Bus
keeper
P1IN.7
EN
unused
D
P1IE.7
P1IRQ.07
EN
Q
P1IFG.7
Set
Interrupt
Edge
Select
P1IES.7
70
P1SEL.7
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
input/output schematic (continued)
port P2, P2.0, P2.4 to P2.5, input/output with Schmitt-trigger
Pad Logic
DVSS
DVSS
P2SEL.x
0: input
1: output
0
P2DIR.x
Direction Control
From Module
1
0
1
P2OUT.x
Module X OUT
Bus
keeper
P2.0/TA2
P2.4/UTXD0
P2IN.x
P2.5/URXD0
EN
Module X IN
D
P2IE.x
P2IRQ.x
P2IFG.x
EN
Interrupt
Edge
Select
Q
Set
P2IES.x
Note:
P2SEL.x
x {0,4,5}
PnSel.x
PnDIR.x
Dir. Control
from module
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
PnIE.x
PnIFG.x
P2Sel.0
P2DIR.0
P2DIR.0
P2OUT.0
Out2 sig. †
P2IN.0
CCI2A †
P2IE.0
P2IFG.0
P2IES.0
P2IN.4
unused
P2IE.4
P2IFG.4
P2IES.4
P2IN.5
URXD0 ‡
P2IE.5
P2IFG.5
P2IES.5
P2Sel.4
P2DIR.4
DVCC
P2OUT.4
UTXD0
P2Sel.5
P2DIR.5
DVSS
P2OUT.5
DVSS
‡
PnIES.x
†Timer_A
‡USART0
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
71
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
input/output schematic (continued)
port P2, P2.1 to P2.3, input/output with Schmitt-trigger
Pad Logic
DVSS
DVSS
Module IN of pin
P1.3/TBOutH/SVSOut
P1DIR.3
P1SEL.3
P2SEL.x
0: input
1: output
0
P2DIR.x
Direction Control
From Module
P2OUT.x
1
0
1
Module X OUT
Bus
keeper
P2.1/TB0
P2.2/TB1
P2IN.x
P2.3/TB2
EN
D
Module X IN
P2IE.x
P2IRQ.x
Q
P2IFG.x
EN
Interrupt
Edge
Select
Set
P2IES.x
Note:
P2SEL.x
1<x <3
PnSel.x
PnDIR.x
Dir. Control
from module
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
PnIE.x
PnIFG.x
P2Sel.1
P2DIR.1
P2DIR.1
P2OUT.1
Out0 sig. †
P2IN.1
CCI0A †
CCI0B
P2IE.1
P2IFG.1
P2IES.1
P2IE.2
P2IFG.2
P2IES.2
P2IE.3
P2IFG.3
P2IES.3
P2Sel.2
P2DIR.2
P2DIR.2
P2OUT.2
Out1 sig. †
P2IN.2
CCI1A †
CCI1B
P2Sel.3
P2DIR.3
P2DIR.3
P2OUT.3
Out2 sig. †
P2IN.3
CCI2A †
CCI2B
†Timer_B
72
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PnIES.x
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
input/output schematic (continued)
port P2, P2.6 to P2.7, input/output with Schmitt-trigger
0: Port active
1: Segment xx function active
Pad Logic
Port/LCD‡
Segment xx‡
P2SEL.x
0: input
1: output
0
P2DIR.x
Direction Control
From Module
1
0
P2OUT.x
1
Module X OUT
Bus
keeper
P2.6/CAOUT/S19‡
P2.7/ADC12CLK/S18‡
P2IN.x
‡Segment function
only available with
MSP430x43xIPN
EN
D
Module X IN
P2IE.x
P2IRQ.x
P2IFG.x
EN
Q
Set
Interrupt
Edge
Select
P2IES.x
Note:
P2SEL.x
6<x <7
PnSel.x
PnDIR.x
Dir. Control
from module
PnOUT.x
P2Sel.6
P2DIR.4
P2DIR.6
P2OUT.6
P2Sel.7
P2DIR.5
P2DIR.7
P2OUT.7
Module X
OUT
Port/LCD
‡
PnIN.x
Module X IN
PnIE.x
PnIFG.x
PnIES.x
CAOUT †
P2IN.6
unused
P2IE.6
P2IFG.6
P2IES.6
0: LCDM<40h ‡
ADC12CLK§
P2IN.7
unused
P2IE.7
P2IFG.7
P2IES.7
0: LCDM<40h
‡
† Comparator_A
‡Port/LCD signal is 1 only with MSP430xIPN and LCDM ≥40h.
§ ADC12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
73
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
input/output schematic (continued)
port P3, P3.0 to P3.3, input/output with Schmitt-trigger
MSP430x43xIPN (80-Pin) Only
0: Port active
1: Segment xx function active
LCDM.5
LCDM.6
LCDM.7
Pad Logic
Segment xx
x43xIPZ and’x44xIPZ Have not Segment
Function on Port P3: Both Lines are LOW.
P3SEL.x
0: input
1: output
0
P3DIR.x
Direction Control
From Module
1
0
1
P3OUT.x
Module X OUT
Bus
keeper
P3.0/STEO/S31†
P3.1/SIMO0/S30†
P3.2/SOMI0/S29†
P3.3/UCLK0/S28†
P3IN.x
EN
Module X IN
Note:
D
0<x<3
Direction
PnOUT.x
Control
From Module
Module X
OUT
PnIN.x
Module X IN
DVSS
P3IN.0
STE0(in)
DCM_SIMO0 P3OUT.1
SIMO0(out)
P3IN.1
SIMO0(in)
P3DIR.2
DCM_SOMI0 P3OUT.2
SOMIO(out)
P3IN.2
SOMI0(in)
P3DIR.3
DCM_UCLK0 P3OUT.3
UCLK0(out)
P3IN.3
UCLK0(in)
PnSel.x
PnDIR.x
P3Sel.0
P3DIR.0
P3Sel.1
P3DIR.1
P3Sel.2
P3Sel.3
DVSS
P3OUT.0
† S24 TO S31 Shared with port function only at MSP430x43xIPN (80-pin QFP)
Direction Control for SIMO0 and UCLK0
SYNC
MM
74
DCM_SIMO0
DCM_UCLK0
Direction Control for SOMI0
SYNC
MM
STC
STC
STE
STE
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
DCM_SOMI0
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
port P3, P3.4 to P3.7, input/output with Schmitt-trigger
LCDM.7† or DVSS‡
0: Port active
1: Segment xx function active
Pad Logic
Segmentxx† or DVSS‡
TBoutHiZ# or DVSS§
P3SEL.x
0: input
1: output
0
P3DIR.x
Direction Control
From Module
P3OUT.x
1
0
1
Module XOUT
Bus
keeper
’x43xIPN
’x43xIPZ
80–pin
100–pin
P3.4/S27
P3.5/S26
P3.6/S25
P3.7/S24
P3.4
P3.5
P3.6
P3.7
’x44x
P3IN.x
EN
Module X IN
Note:
D
P3.4/TB3
P3.5/TB4
P3.6/TB5
P3.7/TB6
4<x <7
Module IN of pin
P1.3/TBOutH/SVSOut
P1DIR.3
P1SEL.3
P3DIR.x
P3SEL.x
TBoutHiZ
PnSel.x
PnDIR.x
Dir. Control
from module
PnOUT.x
P3Sel.4
P3DIR.4
P3DIR.4
P3OUT.4
P3Sel.5
P3DIR.5
P3DIR.5
P3OUT.5
P3Sel.6
P3DIR.6
P3DIR.6
P3OUT.6
P3Sel.7
P3DIR.7
P3DIR.7
P3OUT.7
Module X
OUT
DVSS
OUT3
DVSS
OUT4
DVSS
OUT5
DVSS
OUT6
§
#
§
#
§
#
§
#
PnIN.x
P3IN.4
P3IN.5
P3IN.6
P3IN.7
Module X IN
unused §
CCI3A/B#
unused §
CCI4A/B#
unused §
CCI5A/B#
unused §
CCI6A/B#
† MSP430x43xIPN
‡ MSP430x43xIPZ, MSP430x44xIPZ
§ MSP430x43x
# MSP430x44x
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
75
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
input/output schematic (continued)
port P4, P4.0 to P4.7, input/output with Schmitt-trigger
0: Port active
1: Segment xx function active
Pad Logic
Port/LCD§
Segment xx
P4SEL.x
0: input
1: output
0
P4DIR.x
Direction Control
From Module
1
0
1
P4OUT.x
Module X OUT
Bus
keeper
x43xIPN
80-pin
QFP:
x43xIPZ
100-pin
QFP:
P4.7/S2
P4.6/S3
P4.5/S4
P4.3/S6
P4.4/S5
P4.2/S7
P4.1/S8
P4.0/S9
P4.7/S34
P4.6/S35
P4.5/S36
P4.3/S37
P4.4/S38
P4.2/S39
P4.0
P4.1
x44x
P4IN.x
EN
Module X IN
Note:
D
0<x<7
PnSel.x
PnDIR.x
Direction
PnOUT.x
Control
From Module
P4Sel.0
P4DIR.0
P4DIR.0†
DVCC‡
P4OUT.0
P4Sel.1
P4DIR.1
P4DIR.1†
DVSS‡
P4Sel.2
P4DIR.2
P4Sel.3
P4DIR.3
P4Sel.4
P4DIR.4
P4Sel.5
P4DIR.5
P4Sel.6
P4DIR.4
P4Sel.7
P4DIR.5
Module X
PnIN.x
Module X IN
UTXD1‡
DVSS†
P4IN.0
unused
P4OUT.1
DVSS
P4IN.1
URXD1‡
P4DIR.2†
DVSS‡
P4OUT.2
DVSS
P4IN.2
STE1(in)‡
P4DIR3.†
DCM_SIMO1‡
P4OUT.3
DVSS†
SIMO1(out)‡
P4IN.3
SIMO1(in)‡
P4OUT.4
DVSS†
SOMI1(out)‡
P4IN.4
SOMI1(in)‡
P4OUT.5
DVSS†
UCLK1(out)‡
P4IN.5
UCLK1(in)‡
P4DIR.6
P4OUT.6
DVSS
P4IN.6
unused
P4DIR.7
P4OUT.7
DVSS
P4IN.7
unused
P4DIR4.†
DCM_SOMI1‡
P4DIR5.†
DCM_UCLK1‡
OUT
unused†
unused†
unused†
unused
unused†
† Signal at MSP430x43x
‡ Signal at MSP430x44x
§
DEVICE
76
PORT BITS
PORT FUNCTION
LCD SEG. FUNCTION
x43xIPN 80-pin QFP
P4.0 . . .P4.7
LCDM < 020h
LVDM ≥ 020h
x43xIPZ 100-pin QFP
P4.2 . . .P4.5
LCDM < 0E0h
LVDM ≥ 0E0h
x44xIPZ 100-pin QF
P4.6 . . .P4.7
LCDM < 0C0h
LVDM ≥ 0C0h
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P4.7/S34
P4.6/S35
P4.5/UCLK1/S36
P4.4/SMO1/S37
P4.3/SIMO1/S38
P4.2/STE1/S39
P4.1/URXD1
P4.0/UTXD1
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
input/output schematic (continued)
Direction Control for SIMO1 and UCLK1
Direction Control for SOMI1
SYNC
SYNC
MM
DCM_SIMO1
DCM_UCLK1
MM
DCM_SOMI1
STC
STC
STE
STE
port P5, P5.0 to P5.1, input/output with Schmitt-trigger
0: Port active
1: Segment function active
Port/LCD
Segment Pad Logic
Segment
Port Pad Logic
P5SEL.x
0
P5DIR.x
Direction Control
From Module
0: input
1
1: output
0
P5OUT.x
1
Module X OUT
Bus
keeper
P5.0/S1
P5.1/S0
P5IN.x
EN
Module X IN
Note:
D
0 <x <1
PnSel.x
PnDIR.x
P5Sel.0
P5DIR.0
P5Sel.1
P5DIR.1
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
Segment
Port/LCD
P5DIR.0
P5OUT.0
DVSS
P5IN.0
unused
S1
0: LCDM<20h
P5DIR.1
P5OUT.1
DVSS
P5IN.1
unused
S0
0: LCDM<20h
Dir. Control
from module
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77
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
input/output schematic (continued)
port P5, P5.2 to P5.4, input/output with Schmitt-trigger
0: Port active
1: LCD function active
Port/LCD
LCD signal
Pad Logic
P5SEL.x
0: input
1: output
0
P5DIR.x
Direction Control
From Module
1
0
1
P5OUT.x
Module X OUT
Bus
keeper
P5.2/COM1
P5.3/COM2
P5.4/COM3
P5IN.x
EN
Module X IN
D
Note:
78
2<x <4
PnSel.x
PnDIR.x
Dir. Control
from module
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
P5Sel.2
P5DIR.2
P5DIR.2
P5OUT.2
DVSS
P5IN.2
unused
COM1
P5SEL.2
P5Sel.3
P5DIR.3
P5DIR.3
P5OUT.3
DVSS
P5IN.3
unused
COM2
P5SEL.3
P5Sel.4
P5DIR.4
P5DIR.4
P5OUT.4
DVSS
P5IN.4
unused
COM3
P5SEL.4
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LCD signal
Port/LCD
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
input/output schematic (continued)
port P5, P5.5 to P5.7, input/output with Schmitt-trigger
0: Port active
1: LCD function active
Port/LCD
LCD signal
Pad Logic
P5SEL.x
0: input
1: output
0
P5DIR.x
Direction Control
From Module
1
0
1
P5OUT.x
Module X OUT
Bus
keeper
P5.5/R13
P5.6/R23
P5.7/R33
P5IN.x
EN
Module X IN
D
Note:
5<x <7
PnSel.x
PnDIR.x
Dir. Control
from module
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
P5Sel.5
P5DIR.5
P5DIR.5
P5OUT.5
DVSS
P5IN.5
unused
R13
P5SEL.5
P5Sel.6
P5DIR.6
P5DIR.6
P5OUT.6
DVSS
P5IN.6
unused
R23
P5SEL.6
P5Sel.7
P5DIR.7
P5DIR.7
P5OUT.7
DVSS
P5IN.7
unused
R33
P5SEL.7
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LCD signal
Port/LCD
79
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
input/output schematic (continued)
port P6, P6.0 to P6.7, input/output with Schmitt-trigger
P6SEL.x
0
P6DIR.x
Direction Control
From Module
1
0: Input
1: Output
Pad Logic
P6.0/A0 ..
P6.7/A7/SVSin
0
P6OUT.x
Module X OUT
1
Bus Keeper
P6IN.x
EN
Module X IN
D
From ADC
To ADC
To Brownout/SVS Module
x: Bit Identifier, 0 to 7 for Port P6
NOTE: Analog signals applied to digital gates can cause current flow from the positive to the negative terminal. The throughput current flows if
the analog signal is in the range of transitions 0→1 or 1←0. The value of the throughput current depends on the driving capability of the
gate. For MSP430, it is approximately 100 µA.
Use P6SEL.x=1 to prevent throughput current. P6SEL.x should be set, even if the signal at the pin is not being used by the ADC12.
PnSel.x
PnDIR.x
Dir. Control
From Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
P6Sel.0
P6DIR.0
P6DIR.0
P6OUT.0
DVSS
P6IN.0
unused
P6Sel.1
P6DIR.1
P6DIR.1
P6OUT.1
DVSS
P6IN.1
unused
P6Sel.2
P6DIR.2
P6DIR.2
P6OUT.2
DVSS
P6IN.2
unused
P6Sel.3
P6DIR.3
P6DIR.3
P6OUT.3
DVSS
P6IN.3
unused
P6Sel.4
P6DIR.4
P6DIR.4
P6OUT.4
DVSS
P6IN.4
unused
P6Sel.5
P6DIR.5
P6DIR.5
P6OUT.5
DVSS
P6IN.5
unused
P6Sel.6
P6DIR.6
P6DIR.6
P6OUT.6
DVSS
P6IN.6
unused
P6Sel.7
P6DIR.7
P6DIR.7
P6OUT.7
DVSS
P6IN.7
unused
NOTE: The signal at pins P6.x/Ax is used by the 12-bit ADC module.
The signal at pin P6.7/A7/SVSin is also connected to the input multiplexer in the module brownout/supply voltage supervisor.
80
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SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
input/output schematic (continued)
JTAG pins TMS, TCK, TDI, TDO/TDI, input/output with Schmitt-trigger or output
TDO
Controlled by JTAG
Controlled by JTAG
TDO/TDI
JTAG
Controlled
by JTAG
DVCC
TDI
Burn and Test
Fuse
TDI
Test
and
Emulation
DVCC
TMS
Module
TMS
DVCC
TCK
TCK
RST/NMI
Tau ~ 50 ns
Brownout
TCK
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G
D
U
S
G
D
U
S
81
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
JTAG fuse check mode
MSP430 devices that have the fuse on the TDI terminal have a fuse check mode that tests the continuity of the
fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current
(I(TF)) of 1 mA at 3 V can flow from the TDI pin to ground if the fuse is not burned. Care must be taken to avoid
accidentally activating the fuse check mode and increasing overall system power consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see
Figure 27). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition). The JTAG pins are terminated internally and therefore do not require external termination.
Time TMS Goes Low After POR
TMS
I(TF)
I(TDI)
Figure 27. Fuse Check Mode Current MSP430x43x, MSP430x44x
82
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SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
MECHANICAL DATA
PN (S-PQFP-G80)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
0,08 M
41
60
61
40
80
21
0,13 NOM
1
20
Gage Plane
9,50 TYP
12,20
SQ
11,80
14,20
SQ
13,80
0,25
0°–ā7°
0,05 MIN
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040135/B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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83
SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002
MECHANICAL DATA
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
0,08 M
51
76
50
100
26
1
0,13 NOM
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
16,20
SQ
15,80
0,05 MIN
1,45
1,35
0,25
0°–ā7°
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040149/B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
84
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