ATMEL AT49F040T-12TC 4-megabit 512k x 8 5-volt only cmos flash memory Datasheet

AT49F040
Features
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Single Voltage Operation
- 5V Read
- 5V Reprogramming
Fast Read Access Time - 90 ns
Internal Program Control and Timer
16K bytes Boot Block With Lockout
Fast Erase Cycle Time - 10 seconds
Byte By Byte Programming - 50 µs/Byte
Hardware Data Protection
DATA Polling For End Of Program Detection
Low Power Dissipation
- 50 mA Active Current
- 100 µA CMOS Standby Current
Typical 10,000 Write Cycles
Description
The AT49F040 is a 5-volt-only in-system Flash Memory. Its 4 megabits of memory is
organized as 524,288 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 90 ns with power dissipation
of just 275 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is less than 100 µA.
To allow for simple in-system reprogrammability, the AT49F040 does not require high
input voltages for programming. Five-volt-only commands determine the read and
programming operation of the device. Reading data out of the device is similar to
reading from an EPROM. Reprogramming the AT49F040 is performed by erasing
the entire 4 megabits of memory and then programming on a byte by byte basis. The
byte programming time is a fast 50 µs. The end of a program cycle can be optionally
detected by the DATA polling feature. Once the end of a byte program cycle has been
detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles.
(continued)
DIP Top View
4 Megabit
(512K x 8)
5-volt Only
CMOS Flash
Memory
Preliminary
AT49F040
Pin Configurations
Pin Name
Function
A0 - A18
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
I/O0 - I/O7 Data Inputs/Outputs
PLCC Top View
TSOP Top View
Type 1
0359C
4-209
Description (Continued)
The optional 16K bytes boot block section includes a reprogramming write lock out feature to provide data integrity. The boot sector is designed to contain user secure
code, and when the feature is enabled, the boot sector is
permanently protected from being reprogrammed.
Block Diagram
Device Operation
READ: The AT49F040 is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dualline control gives designers flexibility in preventing bus
contention.
ERASURE: Before a byte can be reprogrammed, the
512K bytes memory array (or 496K bytes if the boot block
featured is used) must be erased. The erased state of the
memory bits is a logical “1". The entire device can be
erased at one time by using a 6-byte software code. The
software chip erase code consists of 6-byte load commands to specific address locations with a specific data
pattern (please refer to the Chip Erase Cycle Waveforms).
After the software chip erase has been initiated, the device
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
the whole chip is tEC. If the boot block lockout feature has
been enabled, the data in the boot sector will not be
erased.
BYTE PROGRAMMING: Once the memory array is
erased, the device is programmed (to a logical “0") on a
byte-by-byte basis. Please note that a data ”0" cannot be
programmed back to a “1"; only erase operations can convert ”0"s to “1"s. Programming is accomplished via the internal device command register and is a 4 bus cycle operation (please refer to the Command Definitions table).
The device will automatically generate the required internal program pulses.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified tBP cy4-210
AT49F040
cle time. The DATA polling feature may also be used to
indicate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has a programming
lockout feature. This feature prevents programming of
data in the designated block once the feature has been
enabled. The size of the block is 16K bytes. This block,
referred to as the boot block, can contain secure code that
is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data
in the rest of the device is updated. This feature does not
have to be activated; the boot block’s usage as a write
protected region is optional to the user. The address range
of the boot block is 00000H to 03FFFH.
Once the feature is enabled, the data in the boot block can
no longer be erased or programmed. Data in the main
memory block can still be changed through the regular
programming method. To activate the lockout feature, a
series of six program commands to specific addresses
with specific data must be performed. Please refer to the
Command Definitions table.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the
boot block section is locked out. When the device is in the
software product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H will show if programming the boot
block is locked out. If the data on I/O0 is low, the boot
block can be programmed; if the data on I/O0 is high, the
program lockout feature has been activated and the block
cannot be programmed. The software product identification code should be used to return to standard operation.
(continued)
AT49F040
Device Operation (Continued)
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external programmer to identify the correct programming algorithm for
the Atmel product.
TOGGLE BIT: In addition to DATA polling the AT49F040
provides another method for determining the end of a program or erase cycle. During a program or erase operation,
successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid
data will be read. Examining the toggle bit may begin at
any time during a program cycle.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT49F040 in
the following ways: (a) VCC sense: if VCC is below 3.8V
(typical), the program function is inhibited. (b) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (c) Noise filter: pulses of less than
15 ns (typical) on the WE or CE inputs will not initiate a
program cycle.
DATA POLLING: The AT49F040 features DATA polling
to indicate the end of a program cycle. During a program
cycle an attempted read of the last byte loaded will result
in the complement of the loaded data on I/O7. Once the
program cycle has been completed, true data is valid on
all outputs and the next cycle may begin. DATA polling
may begin at any time during the program cycle.
Command Definition (in Hex)
Command Bus
Sequence Cycles
1st Bus
Cycle
Addr
Data
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
6th Bus
Cycle
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
2AAA
55
5555
10
2AAA
55
5555
40
Read
1
Addr
DOUT
Chip Erase
6
5555
AA
2AAA
55
5555
80
5555
AA
Byte
Program
4
5555
AA
2AAA
55
5555
A0
Addr
DIN
Boot Block
(1)
Lockout
6
5555
AA
2AAA
55
5555
80
5555
AA
Product ID
Entry
3
5555
AA
2AAA
55
5555
90
Product ID
(2)
Exit
3
5555
AA
2AAA
55
5555
F0
Product ID
(2)
Exit
1
XXXX
F0
Note:
5th Bus
Cycle
1. The 16K byte boot sector has the address range 00000H to 03FFFH.
2. Either one of the Product ID exit commands can be used.
Absolute Maximum Ratings*
Temperature Under Bias................. -55°C to +125°C
Storage Temperature...................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground .............-0.6V to VCC + 0.6V
Voltage on OE
with Respect to Ground .................. -0.6V to + 13.5V
*NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
4-211
DC and AC Operating Range
AT49F040-90
AT49F040-12
AT49F040-15
0°C - 70°C
0°C - 70°C
0°C - 70°C
-40°C - 85°C
-40°C - 85°C
-40°C - 85°C
5V ± 10%
5V ± 10%
5V ± 10%
Com.
Operating
Temperature (Case)
Ind.
VCC Power Supply
Operating Modes
Mode
CE
OE
WE
Ai
I/O
Read
VIL
VIL
VIH
Ai
DOUT
Program (2)
VIL
VIH
VIL
Ai
DIN
VIH
(1)
X
X
High Z
Standby/Write Inhibit
X
Program Inhibit
X
X
VIH
Program Inhibit
X
VIL
X
Output Disable
X
VIH
X
High Z
Product Identification
Hardware
VIL
VIL
VIH
A1 - A18 = VIL, A9 = VH, (3)
A0 = VIL
A1 - A18 = VIL, A9 = VH, (3)
A0 = VIH
Software (5)
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
Manufacturer Code (4)
Device Code (4)
A0 = VIL, A1 - A18 = VIL
Manufacturer Code (4)
A0 = VIH, A1 - A18 = VIL
Device Code (4)
4. Manufacturer Code: 1FH, Device Code: 13H
5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol
Parameter
Condition
Min
Max
Units
ILI
Input Load Current
VIN = 0V to VCC
10
µA
ILO
Output Leakage Current
VI/O = 0V to VCC
10
µA
ISB1
VCC Standby Current CMOS
CE = VCC - 0.3V to VCC
Com.
100
µA
Ind.
300
µA
ISB2
VCC Standby Current TTL
CE = 2.0V to VCC
3
mA
VCC Active Current
f = 5 MHz; IOUT = 0 mA
50
mA
0.8
V
ICC
(1)
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 2.1 mA
VOH1
Output High Voltage
IOH = -400 µA
2.4
V
VOH2
Output High Voltage CMOS
IOH = -100 µA; VCC = 4.5V
4.2
V
Note:
4-212
1. In the erase mode, ICC is 90 mA.
AT49F040
2.0
V
.45
V
AT49F040
AC Read Characteristics
AT49F040-90
AT49F040-12
AT49F040-15
Min
Min
Max
Units
120
150
ns
120
150
ns
0
70
ns
0
40
ns
Symbol
Parameter
tACC
Address to Output Delay
90
tCE (1)
CE to Output Delay
90
tOE (2)
OE to Output Delay
0
40
0
50
tDF (3, 4)
CE or OE to Output Float
0
25
0
30
tOH
Output Hold from OE, CE or
Address, whichever occurred
first
0
Min
Max
Max
0
0
ns
AC Read Waveforms (1, 2, 3, 4)
Notes: 1. CE may be delayed up to tACC - tCE after the address
transition without impact on tACC .
2. OE may be delayed up to tCE - tOE after the falling
edge of CE without impact on tCE or by tACC - tOE
after an address change without impact on tACC .
3. tDF is specified from OE or CE whichever occurs first
(CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and Measurement Level
Output Test Load
tR, tF < 5 ns
Pin Capacitance (f = 1 MHz, T = 25°C) (1)
Typ
Max
Units
CIN
4
6
pF
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
Conditions
1. This parameter is characterized and is not 100% tested.
4-213
AC Byte Load Characteristics
Symbol
Parameter
tAS, tOES
Address, OE Set-up Time
0
ns
tAH
Address Hold Time
50
ns
tCS
Chip Select Set-up Time
0
ns
tCH
Chip Select Hold Time
0
ns
tWP
Write Pulse Width (WE or CE)
90
ns
tDS
Data Set-up Time
50
ns
tDH, tOEH
Data, OE Hold Time
0
ns
tWPH
Write Pulse Width High
90
ns
AC Byte Load Waveforms
WE Controlled
CE Controlled
4-214
AT49F040
Min
Max
Units
AT49F040
Program Cycle Characteristics
Symbol
Parameter
Min
Typ
Max
Units
tBP
Byte Programming Time
10
50
µs
tAS
Address Set-up Time
0
ns
tAH
Address Hold Time
50
ns
tDS
Data Set-up Time
50
ns
tDH
Data Hold Time
0
ns
tWP
Write Pulse Width
90
ns
tWPH
Write Pulse Width High
90
ns
tEC
Erase Cycle Time
10
seconds
Program Cycle Waveforms
Chip Erase Cycle Waveforms
Note:
OE must be high only when WE and CE are both low.
4-215
Data Polling Characteristics
Symbol
Parameter
tDH
Data Hold Time
tOEH
OE Hold Time
(1)
Min
Typ
Max
Units
10
ns
10
ns
(2)
tOE
OE to Output Delay
tWR
Write Recovery Time
ns
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
Toggle Bit Characteristics
(1)
Symbol
Parameter
Min
Typ
Max
Units
tDH
Data Hold Time
10
ns
tOEH
OE Hold Time
10
ns
Delay (2)
tOE
OE to Output
tOEHP
OE High Pulse
tWR
Write Recovery Time
ns
150
ns
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms (1, 2, 3)
Notes: 1. Toggling either OE or CE or both OE and CE will
operate toggle bit. The tOEHP specification must be
met by the toggling input(s).
4-216
AT49F040
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address
should not vary.
AT49F040
Software Product (1)
Identification Entry
Boot Block Lockout
(1)
Feature Enable Algorithm
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 90
TO
ADDRESS 5555
LOAD DATA 80
TO
ADDRESS 5555
ENTER PRODUCT
IDENTIFICATION
MODE (2, 3, 5)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
Software Product (1)
Identification Exit
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
OR
LOAD DATA 40
TO
ADDRESS 5555
LOAD DATA F0
TO
ANY ADDRESS
EXIT PRODUCT
IDENTIFICATION
MODE (4)
LOAD DATA F0
TO
ADDRESS 5555
PAUSE 1 second (2)
Notes for boot block lockout feature enable:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Boot block lockout feature enabled.
EXIT PRODUCT
IDENTIFICATION
MODE (4)
Notes for software product identification:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A18 = VIL.
Manufacture Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 1FH
Device Code: 13H
4-217
Ordering Information (1)
ICC (mA)
tACC
(ns)
Active
Standby
90
50
120
150
Note:
Ordering Code
Package
0.1
AT49F040-90JC
AT49F040-90PC
AT49F040-90TC
32J
32P6
32T
Commercial
(0° to 70°C)
50
0.3
AT49F040-90JI
AT49F040-90PI
AT49F040-90TI
32J
32P6
32T
Industrial
(-40° to 85°C)
50
0.1
AT49F040-12JC
AT49F040-12PC
AT49F040-12TC
32J
32P6
32T
Commercial
(0° to 70°C)
50
0.3
AT49F040-12JI
AT49F040-12PI
AT49F040-12TI
32J
32P6
32T
Industrial
(-40° to 85°C)
50
0.1
AT49F040-15JC
AT49F040-15PC
AT49F040-15TC
32J
32P6
32T
Commercial
(0° to 70°C)
50
0.3
AT49F040-15JI
AT49F040-15PI
AT49F040-15TI
32J
32P6
32T
Industrial
(-40° to 85°C)
1. The AT49F040 has as optional boot block feature. The part number shown in the Ordering Information table is for devices
with the boot block in the lower address range (i.e., 00000H to 03FFFH). Users requiring the boot block to be in the
higher address range should contact Atmel.
Package Type
32J
32 Lead, Plastic, J-Leaded Chip Carrier Package (PLCC)
32P6
32 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
32T
32 Lead, Thin Small Outline Package (TSOP)
4-218
Operation Range
AT49F040
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