ESMT F25L08PA-50DG 3v only 8 mbit serial flash memory with dual Datasheet

ESMT
F25L08PA
Flash
„
3V Only 8 Mbit Serial Flash Memory with Dual
FEATURES
y
y
Single supply voltage 2.7~3.6V
Standard, Dual SPI
y
Speed
- Read max frequency: 33MHz
- Fast Read max frequency: 50MHz; 100MHz
- Fast Read Dual max frequency: 50MHz / 100MHz
(100MHz / 200MHz equivalent Dual SPI)
y
Page Programming
- 256 byte per programmable page
y
Auto Address Increment (AAI) WORD Programming
- Decrease total chip programming time over
Byte Program operations
y
Lockable 4K bytes OTP security sector
y
SPI Serial Interface
- SPI Compatible: Mode 0 and Mode 3
y
Low power consumption
- Active current: 35 mA
- Standby current: 30 μ A
y
End of program or erase detection
y
Reliability
- 100,000 typical program/erase cycles
- 20 years Data Retention
y
Write Protect ( WP )
y
Program
- Byte programming time: 7 μ s (typical)
- Page programming time: 1.5 ms (typical)
y
Hold Pin ( HOLD )
y
All Pb-free products are RoHS-Compliant
y
Erase
- Chip erase time 10 sec (typical)
- Block erase time 1 sec (typical)
- Sector erase time 90 ms (typical)
„
ORDERING INFORMATION
Product ID
„
Speed
Package
COMMENTS
F25L08PA –50PG
50MHz
8 lead SOIC
150mil
Pb-free
F25L08PA –100PG
100MHz
8 lead SOIC
150mil
Pb-free
F25L08PA –50PAG
50MHz
8 lead SOIC
200mil
Pb-free
F25L08PA –100PAG
100MHz
8 lead SOIC
200mil
Pb-free
F25L08PA –50DG
50MHz
8 lead PDIP
300mil
Pb-free
F25L08PA –100DG
100MHz
8 lead PDIP
300mil
Pb-free
GENERAL DESCRIPTION
The F25L08PA is a 8Megabit, 3V only CMOS Serial Flash
memory device. The device supports the standard Serial
Peripheral Interface (SPI), and a Dual SPI. ESMT’s memory
devices reliably store memory data even after 100,000
programming and erase cycles.
The memory array can be organized into 4,096 programmable
pages of 256 byte each. 1 to 256 byte can be programmed at a
time with the Page Program instruction. The device also can be
programmed to decrease total chip programming time with Auto
Address Increment (AAI) programming.
The device features sector erase architecture. The memory array
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is divided into 256 uniform sectors with 4K byte each; 16 uniform
blocks with 64K byte each. Sectors can be erased individually
without affecting the data in other sectors. Blocks can be erased
individually without affecting the data in other blocks. Whole chip
erase capabilities provide the flexibility to revise the data in the
device. The device has Sector, Block or Chip Erase but no page
erase.
The sector protect/unprotect feature disables both program and
erase operations in any combination of the sectors of the
memory.
Publication Date: Jul. 2009
Revision: 1.7
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ESMT
„
F25L08PA
PIN CONFIGURATIONS
8-PIN SOIC
CE
1
8
VDD
SO
2
7
HOLD
WP
3
6
SCK
VSS
4
5
SI
CE
1
8
VDD
SO
2
7
HOLD
WP
3
6
SCK
VSS
4
5
SI
8-PIN PDIP
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Publication Date: Jul. 2009
Revision: 1.7
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ESMT
„
„
F25L08PA
PIN DESCRIPTION
Symbol
Pin Name
Functions
SCK
Serial Clock
To provide the timing for serial input and
output operations
SI
Serial Data Input
To transfer commands, addresses or data
serially into the device.
Data is latched on the rising edge of SCK.
SO
Serial Data Output
To transfer data serially out of the device.
Data is shifted out on the falling edge of
SCK.
CE
Chip Enable
To activate the device when CE is low.
WP
Write Protect
The Write Protect ( WP ) pin is used to
enable/disable BPL bit in the status
register.
HOLD
Hold
VDD
Power Supply
VSS
Ground
To temporality stop serial communication
with SPI flash memory without resetting
the device.
To provide power.
FUNCTIONAL BLOCK DIAGRAM
Address
Buffers
and
Latches
Flash
X-Decoder
Y-Decoder
I/O Butters
and
Data Latches
Control Logic
Serial Interface
CE
SCK
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SI
SO
WP
HOLD
Publication Date: Jul. 2009
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„
F25L08PA
SECTOR STRUCTURE
Table 1: F25L08PA Sector Address Table
Block
15
14
13
12
11
10
9
8
7
6
5
4
3
Sector
Sector Size
(Kbytes)
255
4KB
:
:
Address range
A19 A18
A17
A16
0FF000H – 0FFFFFH
:
240
4KB
0F0000H – 0F0FFFH
239
4KB
0EF000H – 0EFFFFH
:
:
:
224
4KB
0E0000H – 0E0FFFH
223
4KB
0DF000H – 0DFFFFH
:
:
208
4KB
0D0000H – 0D0FFFH
207
4KB
0CF000H – 0CFFFFH
:
:
:
192
4KB
0C0000H – 0C0FFFH
191
4KB
0BF000H – 0BFFFFH
:
:
:
176
4KB
0B0000H – 0B0FFFH
175
4KB
0AF000H – 0AFFFFH
:
:
:
160
4KB
0A0000H – 0A0FFFH
159
4KB
09F000H – 09FFFFH
:
:
:
:
144
4KB
090000H – 090FFFH
143
4KB
08F000H – 08FFFFH
:
:
:
128
4KB
080000H – 080FFFH
127
4KB
07F000H – 07FFFFH
:
:
112
4KB
070000H – 070FFFH
111
4KB
06F000H – 06FFFFH
:
:
:
:
96
4KB
060000H – 060FFFH
95
4KB
05F000H – 05FFFFH
:
:
:
80
4KB
050000H – 050FFFH
79
4KB
04F000H – 04FFFFH
:
:
:
64
4KB
040000H – 040FFFH
63
4KB
03F000H – 03FFFFH
:
:
48
4KB
Elite Semiconductor Memory Technology Inc.
Block Address
:
1
1
1
1
1
1
1
0
1
1
0
1
1
1
0
0
1
0
1
1
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
0
1
0
1
0
0
0
0
1
1
030000H – 030FFFH
Publication Date: Jul. 2009
Revision: 1.7
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ESMT
F25L08PA
Table 1: F25L08PA Sector Address Table - Continued
Block
2
1
0
„
Block Address
Sector
Sector Size
(Kbytes)
47
4KB
:
:
:
32
4KB
020000H – 020FFFH
31
4KB
01F000H – 01FFFFH
:
:
:
16
4KB
010000H – 010FFFH
15
4KB
00F000H – 00FFFFH
:
:
:
0
4KB
000000H – 000FFFH
Address range
A19 A18
A17
A16
02F000H – 02FFFFH
0
0
1
0
0
0
0
1
0
0
0
0
STATUS REGISTER
The software status register provides status on whether the flash
memory array is available for any Read or Write operation,
whether the device is Write enabled, and the state of the memory
Write protection. During an internal Erase or Program operation,
the status register may be read only to determine the completion
of an operation in progress. Table 2 describes the function of
each bit in the software status register.
Table 2: Software Status Register
Bit
Name
0
BUSY
1
WEL
2
3
4
5
BP0
BP1
BP2
RESERVED
6
AAI
7
BPL
Function
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
1 = Device is memory Write enabled
0 = Device is not memory Write enabled
Indicate current level of block write protection (See Table 3)
Indicate current level of block write protection (See Table 3)
Indicate current level of block write protection (See Table 3)
Reserved for future use
Auto Address Increment Programming status
1 = AAI programming mode
0 = Page Program mode
1 = BP2,BP1,BP0 are read-only bits
0 = BP2,BP1,BP0 are read/writable
Default at
Power-up
Read/Write
0
R
0
R
1
1
1
0
R/W
R/W
R/W
N/A
0
R
0
R/W
Note:
1. Only BP0, BP1, BP2 and BPL are writable.
2. All register bits are volatility
3. All area are protected at power-on (BP2=BP1=BP0=1)
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F25L08PA
WRITE ENABLE LATCH (WEL)
BUSY
The Write-Enable-Latch bit indicates the status of the internal
memory Write Enable Latch. If this bit is set to “1”, it indicates the
device is Write enabled. If the bit is set to “0” (reset), it indicates
the device is not Write enabled and does not accept any memory
Write (Program/ Erase) commands. This bit is automatically reset
under the following conditions:
The Busy bit determines whether there is an internal Erase or
Program operation in progress. A “1” for the Busy bit indicates
the device is busy with an operation in progress. A “0” indicates
the device is ready for the next valid operation.
•
•
•
•
•
•
•
•
Power-up
Write Disable (WRDI) instruction completion
Page Program instruction completion
Auto Address Increment (AAI) Programming is completed and
reached its highest unprotected memory address
Sector Erase instruction completion
Block Erase instruction completion
Chip Erase instruction completion
Write Status Register instructions
Auto Address Increment (AAI)
The Auto-Address-Increment-Programming-Status bit provides
status on whether the device is in AAI Programming mode or
Page Program mode. The default at power up is Page Program
mode.
Table 3: F25L08PA Block Protection Table
Protection Level
Status Register Bit
BP2
BP1
Protected Memory Area
BP0
Block Range
Address Range
0
0
0
0
None
None
Upper 1/16
0
0
1
Block 15
F0000H – FFFFFH
Upper 1/8
0
1
0
Block 14~15
E0000H – FFFFFH
Upper 1/4
0
1
1
Block 12~15
C0000H – FFFFFH
Upper 1/2
1
0
0
Block 8~15
80000H – FFFFFH
All Blocks
1
0
1
Block 0~15
00000H – FFFFFH
All Blocks
1
1
0
Block 0~15
00000H – FFFFFH
All Blocks
1
1
1
Block 0~15
00000H – FFFFFH
Block Protection (BP2, BP1, BP0)
Block Protection Lock-Down (BPL)
The Block-Protection (BP2, BP1, BP0) bits define the size of the
memory area, as defined in Table 3, to be software protected
against any memory Write (Program or Erase) operations. The
Write Status Register (WRSR) instruction is used to program the
WP pin driven low (VIL), enables the Block-ProtectionLock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP2, BP1, and BP0 bits. When the
BP2, BP1, BP0 bits as long as WP is high or the BlockProtection-Look (BPL) bit is 0. Chip Erase can only be executed if
Block-Protection bits are all 0. After power-up, BP2, BP1 and BP0
are set to1.
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WP pin is driven high (VIH), the BPL bit has no effect and its
value is “Don’t Care”. After power-up, the BPL bit is reset to 0.
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Revision: 1.7
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„
F25L08PA
HOLD OPERATION
HOLD pin is used to pause a serial sequence underway with the
SPI flash memory without resetting the clocking sequence. To
Hold mode when the SCK next reaches the active low state. See
Figure 1 for Hold Condition waveform.
activate the HOLD mode, CE must be in active low state. The
Once the device enters Hold mode, SO will be in high impedance
state while SI and SCK can be VIL or VIH.
HOLD mode begins when the SCK active low state coincides
with the falling edge of the HOLD signal. The HOLD mode ends
when the HOLD signal’s rising edge coincides with the SCK
active low state.
If the falling edge of the HOLD signal does not coincide with the
SCK active low state, then the device enters Hold mode when the
SCK next reaches the active low state.
If CE is driven active high during a Hold condition, it resets the
internal logic of the device. As long as HOLD signal is low, the
memory remains in the Hold condition. To resume
communication with the device, HOLD must be driven active
high, and CE must be driven active low. See Figure 26 for Hold
timing.
Similarly, if the rising edge of the HOLD signal does not
coincide with the SCK active low state, then the device exits in
S CK
HO L D
A ctive
A ctive
Ho ld
Ho ld
A ctive
Figure 1: HOLD Condition Waveform
„
WRITE PROTECTION
F25L08PA provides software Write Protection.
The Write-Protect pin ( WP ) enables or disables the lock-down
function of the status register. The Block-Protection bits (BP2,
BP1, BP0, and BPL) in the status register provide Write
protection to the memory array and the status register. See Table
3 for Block-Protection description.
Write Protect Pin ( WP )
Table 4: Conditions to Execute Write-Status-Register (WRSR)
Instruction
WP
BPL
Execute WRSR Instruction
L
1
Not Allowed
L
0
Allowed
H
X
Allowed
The Write-Protect ( WP ) pin enables the lock-down function of
the BPL bit (bit 7) in the status register. When WP is driven low,
the execution of the Write Status Register (WRSR) instruction is
determined by the value of the BPL bit (see Table 4). When WP
is high, the lock-down function of the BPL bit is disabled.
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Publication Date: Jul. 2009
Revision: 1.7
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„
F25L08PA
INSTRUCTIONS
Instructions are used to Read, Write (Erase and Program), and
configure the F25L08PA. The instruction bus cycles are 8 bits
each for commands (Op Code), data, and addresses. Prior to
executing any Page Program, Auto Address Increment (AAI)
Programming, Write Status Register, Sector Erase, Block Erase,
or Chip Erase instructions, the Write Enable (WREN) instruction
must be executed first. The complete list of the instructions is
provided in Table 5. All instructions are synchronized off a high to
low before an instruction is entered and must be driven high after
the last bit of the instruction has been shifted in (except for Read,
Read ID, Read Status Register, Read Electronic Signature
instructions). Any low to high transition on CE , before receiving
the last bit of an instruction bus cycle, will terminate the
instruction in progress and return the device to the standby
mode.
low transition of CE . Inputs will be accepted on the rising edge
Instruction commands (Op Code), addresses, and data are all
input from the most significant bit (MSB) first.
of SCK starting with the most significant bit. CE must be driven
Table 5: Device Operation Instructions
Operation
Read
Fast Read
Fast Read Dual
12,13
Output
Sector Erase4 (4K Byte)
Block Erase4, (64K Byte)
Max.
Freq
SIN
33 MHz 03H
0BH
Chip Erase
Page Program (PP)
Auto Address Increment
word programming5 (AAI)
Read Status Register
6
(RDSR)
Enable Write Status
7
Register (EWSR)
50MHz
Write Status Register
7
(WRSR)
Write Enable (WREN) 10
Write Disable (WRDI)/
Exit secured OTP mode
Enter secured OTP mode
(ENSO)
100MHz
Read Electronic
8
Signature (RES)
RES in secured OTP
mode & not lock down
RES in secured OTP
mode & lock down
Jedec Read ID
9
(JEDEC-ID)
Read ID (RDID) 11
Enable SO to output
RY/
Status during AAI
(EBSY)
Disable SO to output
Status during AAI
RY/
(DBSY)
1
2
SOUT
SIN
Hi-Z A23-A16
Hi-Z A23-A16
3BH
20H
D8H
60H /
C7H
Bus Cycle 1~3
4
SOUT SIN SOUT SIN SOUT SIN
Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z
X
Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z
X
3
A23-A16
A15-A8
A7-A0
5
6
SOUT
DOUT0
X
SIN
X
X
X
N
SOUT
DOUT1
DOUT0
SIN
SOUT
X
X
cont.
cont.
cont.
DOUT0~1
Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z
Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z
-
-
-
-
-
-
Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
Up to
256 Hi-Z
bytes
02H
Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z
DIN0
Hi-Z
DIN1
Hi-Z
ADH
Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z
DIN0
Hi-Z
DIN1
Hi-Z
-
-
05H
Hi-Z
X
DOUT
-
-
-
-
-
-
-
-
-
-
50H
Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
01H
Hi-Z
DIN
Hi-Z
-
-
-.
-
-
-
-
-
-
-
06H
Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
04H
Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
B1H
Hi-Z
-
-
-
-
-.
-
-
-
-
-
-
-
ABH
Hi-Z
X
13H
-
-
-
-
-
-
-
-
-
-
ABH
Hi-Z
X
33H
-
-
-.
-
-
-
-
-
-
-
ABH
Hi-Z
X
73H
-
-
-.
-
-
-
-
-
-
-
9FH
Hi-Z
X
8CH
X
20H
X
14H
-
-
-
-
-
-
90H
Hi-Z
00H
Hi-Z
00H
Hi-Z
00H
01H
Hi-Z
Hi-Z
X
X
8CH
13H
X
X
13H
8CH
-
-
70H
Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
80H
Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
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Publication Date: Jul. 2009
Revision: 1.7
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ESMT
F25L08PA
Note:
1.
2.
3.
4.
5.
6.
7.
Operation: SIN = Serial In, SOUT = Serial Out, Bus Cycle 1 = Op Code
X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary); cont. = continuous
One bus cycle is eight clock periods.
Sector Earse addresses: use AMS -A12, remaining addresses can be VIL or VIH
Block Earse addresses: use AMS -A16, remaining addresses can be VIL or VIH
To continue programming to the next sequential address location, enter the 8-bit command, followed by the data to be
programmed.
The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE .
The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in
conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR
instruction to make both instructions effective.
8.
9.
The Read-Electronic-Signature is continuous with on going clock cycles until terminated by a low to high transition on CE .
The Jedec-Read-ID is output first byte 8CH as manufacture ID; second byte 20H as top memory type; third byte 14H as
memory capacity.
10. The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each
other. The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both
instructions effective. Both EWSR and WREN can enable WRSR, user just need to execute one of it. A successful WRSR
can reset WREN.
11. The Manufacture ID and Device ID output will repeat continuously until CE terminates the instruction.
12. Dual commands use bidirectional IO pins. DOUT and cont. are serial data out; others are serial data in.
13. Dual output data:
IO0 = (D6, D4, D2, D0), (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1), (D7, D5, D3, D1)
DOUT0
DOUT1
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F25L08PA
Read (33MHz)
The Read instruction supports up to 33 MHz, it outputs the data
starting from the specified address location. The data output
stream is continuous through all addresses until terminated by a
the data from address location FFFFFH had been read, the next
output will be from address location 000000H.
low to high transition on CE . The internal address pointer will
automatically increment until the highest memory address is
reached. Once the highest memory address is reached, the
address pointer will automatically increment to the beginning
(wrap-around) of the address space, i.e. for 8Mbit density, once
The Read instruction is initiated by executing an 8-bit command,
03H, followed by address bits [A23 -A0]. CE must remain active
low for the duration of the Read cycle. See Figure 2 for the Read
sequence.
Figure 2: Read Sequence
Fast Read (50 MHz; 100 MHz)
The Fast Read instruction supporting up to 100 MHz is initiated
by executing an 8-bit command, 0BH, followed by address bits
all addresses until terminated by a low to high transition on CE .
The internal address pointer will automatically increment until the
highest memory address is reached. Once the highest memory
address is reached, the address pointer will automatically
increment to the beginning (wrap-around) of the address space,
i.e. for 8Mbit density, once the data from address location
FFFFFH has been read, the next output will be from address
location 000000H.
[A23 -A0] and a dummy byte. CE must remain active low for the
duration of the Fast Read cycle. See Figure 3 for the Fast Read
sequence.
Following a dummy byte (8 clocks input dummy cycle), the Fast
Read instruction outputs the data starting from the specified
address location. The data output stream is continuous through
CE
MODE3
SCK MODE0
0 1 2 3 4 5 6 7 8
ADD.
0B
SI
MSB
SO
15 16
23 24
ADD.
31 32
ADD.
39 40
47 48
55 56
63 64
71 72
80
X
MSB
HIGH IMPENANCE
N
N+1
N+2
N+3
N+4
DOUT
DOUT
DOUT
DOUT
DOUT
MSB
Note : X = Dummy Byte : 8 Clocks Input Dummy (VIL or VIH)
Figure 3: Fast Read Sequence
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Publication Date: Jul. 2009
Revision: 1.7
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F25L08PA
Fast Read Dual Output (50 MHz; 100 MHz)
The Fast Read Dual Output (3BH) instruction is similar to the
standard Fast Read (0BH) instruction except the data is output
on SI and SO pins. This allows data to be transferred from the
device at twice the rate of standard SPI devices. This instruction
is for quickly downloading code from Flash to RAM upon
power-up or for applications that cache code- segments to RAM
for execution.
The Fast Read Dual Output instruction is initiated by executing
an 8-bit command, 3BH, followed by address bits [A23 -A0] and a
dummy byte. CE must remain active low for the duration of the
Fast Read Dual Output cycle. See Figure 4 for the Fast Read
Dual Output sequence.
Figure 4: Fast Read Dual Output Sequence
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Publication Date: Jul. 2009
Revision: 1.7
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F25L08PA
Page Program (PP)
The Page Program instruction allows many bytes to be
programmed in the memory. The bytes must be in the erased
state (FFH) when initiating a Program operation. A Page
Program instruction applied to a protected memory area will be
ignored.
latched data are discarded and the last 256 bytes Data are
guaranteed to be programmed correctly within the same page. If
less than 256 bytes Data are sent to device, they are correctly
programmed at the requested addresses without having any
effects on the other bytes of the same page.
Prior to any Write operation, the Write Enable (WREN) instruction
CE must be driven high before the instruction is executed. The
user may poll the Busy bit in the software status register or wait
TPP for the completion of the internal self-timed Page Program
operation. While the Page Program cycle is in progress, the Read
Status Register instruction may still be accessed for checking the
status of the Busy bit. It is recommended to wait for a duration of
TBP before reading the status register to check the BUSY bit. The
BUSY bit is a 1 during the Page Program cycle and becomes a 0
when the cycle is finished and the device is ready to accept other
instructions again. After the Page Program cycle has finished, the
Write-Enable-Latch (WEL) bit in the Status Register is cleared to
0. See Figure 7 for the Page Program sequence.
must be executed. CE must remain active low for the duration
of the Page Program instruction. The Page Program instruction is
initiated by executing an 8-bit command, 02H, followed by
address bits [A23-A0]. Following the address, at least one byte
Data is input (the maximum of input data can be up to 256 bytes).
If the 8 least significant address bits [A7-A0] are not all zero, all
transmitted data that goes beyond the end of the current page
are programmed from the start address of the same page (from
the address whose 8 least significant bits [A7-A0] are all zero).
If more than 256 bytes Data are sent to the device, previously
Figure 7: Page Program Sequence
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Publication Date: Jul. 2009
Revision: 1.7
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ESMT
F25L08PA
Auto Address Increment (AAI) WORD Program
The AAI program instruction allows multiple bytes of data to be
programmed without re-issuing the next sequential address
location. This feature decreases total programming time when
the multiple bytes or entire memory array is to be programmed.
An AAI program instruction pointing to a protected memory area
will be ignored. The selected address range must be in the
erased state (FFH) when initiating an AAI program instruction.
While within AAI WORD programming sequence, the only valid
instructions are AAI WORD program operation, RDSR, WRDI.
Users have three options to determine the completion of each
AAI WORD program cycle: hardware detection by reading the
SO; software detection by polling the BUSY in the software status
register or wait TBP. Refer to End of Write Detection section for
details.
Prior to any write operation, the Write Enable (WREN) instruction
must be executed. The AAI WORD program instruction is
initiated by executing an 8-bit command, ADH, followed by
address bits [A23 -A0]. Following the addresses, two bytes of data
is input sequentially. The data is input sequentially from MSB (bit
7) to LSB (bit 0). The first byte of data (D0) will be programmed
into the initial address [A23 -A1] with A0 =0; the second byte of
data (D1) will be programmed into the initial address [A23 -A1] with
A0 =1. CE must be driven high before the AAI WORD program
instruction is executed. The user must check the BUSY status
before entering the next valid command. Once the device
indicates it is no longer busy, data for next two sequential
addresses may be programmed and so on. When the last desired
byte had been entered, check the busy status using the hardware
method or the RDSR instruction and execute the WRDI
instruction, to terminate AAI. User must check BUSY status after
WRDI to determine if the device is ready for any command.
Please refer to Figure 10 and Figure 11.
There is no wrap mode during AAI programming; once the
highest unprotected memory address is reached, the device will
exit AAI operation and reset the Write-Enable-Latch bit (WEL = 0)
and the AAI bit (AAI=0).
End of Write Detection
There are three methods to determine completion of a program
cycle during AAI WORD programming: hardware detection by
reading the SO, software detection by polling the BUSY bit in the
Software Status Register or wait TBP. The Hardware End of Write
Detection method is described in the section below.
Hardware End of Write Detection
The Hardware End of Write Detection method eliminates the
overhead of polling the BUSY bit in the Software Status Register
during an AAI Word program operation. The 8-bit command, 70H,
configures the SO pin to indicate Flash Busy status during AAI
WORD programming (refer to Figure 8). The 8-bit command, 70H,
must be executed prior to executing an AAI WORD program
instruction. Once an internal programming operation begins,
asserting CE will immediately drive the status of the internal flash
Figure 8: Enable SO as Hardware RY/ BY
during AAI Programming
Elite Semiconductor Memory Technology Inc.
status on the SO pin. A “0”
Indicates the device is busy; a “1” Indicates the device is ready
for the next instruction. De-asserting CE will return the SO pin
to tri-state. The 8-bit command, 80H,disables the SO pin to
output busy status during AAI WORD program operation and
return SO pin to output Software Status Register data during AAI
WORD programming (refer to Figure 9).
Figure 9: Disable SO as Hardware RY/ BY
during AAI Programming
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Revision: 1.7
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ESMT
F25L08PA
Figure 10: AAI Word Program Sequence with Hardware End of Write Detection
Figure 11: AAI Word Program Sequence with Software End of Write Detection
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ESMT
F25L08PA
64K Byte Block Erase
The 64K-byte Block Erase instruction clears all bits in the
selected block to FFH. A Block Erase instruction applied to a
protected memory area will be ignored. Prior to any Write
operation, the Write Enable (WREN) instruction must be
-A0]. Address bits [AMS -A16] (AMS = Most Significant address) are
used to determine the block address (BAX), remaining address
bits can be VIL or VIH. CE must be driven high before the
instruction is executed. The user may poll the Busy bit in the
Software Status Register or wait TBE for the completion of the
internal self-timed Block Erase cycle. See Figure 13 for the Block
Erase sequence.
executed. CE must remain active low for the duration of the any
command sequence. The Block Erase instruction is initiated by
executing an 8-bit command, D8H, followed by address bits [A23
Figure 13: 64K-byte Block Erase Sequence
4K Byte Sector Erase
[AMS -A12] (AMS = Most Significant address) are used to determine
the sector address (SAX), remaining address bits can be VIL or
The Sector Erase instruction clears all bits in the selected sector
to FFH. A Sector Erase instruction applied to a protected memory
area will be ignored. Prior to any Write operation, the Write
VIH. CE must be driven high before the instruction is executed.
The user may poll the Busy bit in the Software Status Register or
wait TSE for the completion of the internal self-timed Sector Erase
cycle. See Figure 14 for the Sector Erase sequence.
Enable (WREN) instruction must be executed. CE must remain
active low for the duration of the any command sequence. The
Sector Erase instruction is initiated by executing an 8-bit
command, 20H, followed by address bits [A23 -A0]. Address bits
CE
MODE3
15 16
0 1 2 3 4 5 6 7 8
31
23 24
SCK MODE0
20
SI
MSB
SO
ADD.
ADD.
ADD.
MSB
HIGH IMPENANCE
Figure 14: 32K-byte Sector Erase Sequence
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ESMT
F25L08PA
Chip Erase
The Chip Erase instruction clears all bits in the device to FFH. A
Chip Erase instruction will be ignored if any of the memory area is
protected. Prior to any Write operation, the Write Enable (WREN)
instruction must be executed. CE must remain active low for
the duration of the Chip-Erase instruction sequence. The Chip
Erase instruction is initiated by executing an 8-bit command, 60H
or C7H. CE must be driven high before the instruction is
executed. The user may poll the Busy bit in the Software Status
Register or wait TCE for the completion of the internal self-timed
Chip Erase cycle. See Figure 15 for the Chip Erase sequence.
CE
MODE3
SCK MODE0
0 1 2 3 4 5 6 7
60 or C7
SI
MSB
SO
HIGH IMPENANCE
Figure 15: Chip Erase Sequence
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows reading of
the status register. The status register may be read at any time
even during a Write (Program/Erase) operation.
When a Write operation is in progress, the Busy bit may be
checked before sending any new commands to assure that the
new commands are properly received by the device.
CE must be driven low before the RDSR instruction is entered
and remain low until the status data is read. Read Status
Register is continuous with ongoing clock cycles until it is
terminated by a low to high transition of the CE . See Figure 16
for the RDSR instruction sequence.
Figure 16: Read Status Register (RDSR) Sequence
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ESMT
F25L08PA
Write Enable (WREN)
The Write Enable (WREN) instruction sets the Write-EnableLatch bit in the Software Status Register to 1 allowing Write
operations to occur.
The WREN instruction must be executed prior to any Write
(Program/Erase) operation. CE must be driven high before the
WREN instruction is executed.
CE
0 1 2 3 4 5 6 7
MODE3
SCK MODE0
06
SI
MSB
HIGH IMPENANCE
SO
Figure 17: Write Enable (WREN) Sequence
Write Disable (WRDI)
The Write Disable (WRDI) instruction resets the Write-EnableLatch bit to 0 disabling any new Write operations from occurring
or exits from OTP mode to normal mode.
CE must be driven high before the WRDI instruction is
executed.
CE
MODE3
SCK MODE0
0 1 2 3 4 5 6 7
04
SI
MSB
SO
HIGH IMPENANCE
Figure 18: Write Disable (WRDI) Sequence
Enable Write Status Register (EWSR)
The Enable Write Status Register (EWSR) instruction arms the
Write Status Register (WRSR) instruction and opens the status
register for alteration. The Enable Write Status Register
instruction does not have any effect and will be wasted, if it is not
followed immediately by the Write Status Register (WRSR)
Elite Semiconductor Memory Technology Inc.
instruction. CE must be driven low before the EWSR instruction
is entered and must be driven high before the EWSR instruction
is executed.
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ESMT
F25L08PA
Write Status Register (WRSR)
The Write Status Register instruction writes new values to the
BP2, BP1, BP0, and BPL bits of the status register. CE must be
driven low before the command sequence of the WRSR
instruction is entered and driven high before the WRSR
instruction is executed. See Figure 19 for EWSR or WREN and
WRSR instruction sequences.
Executing the Write Status Register instruction will be ignored
when WP is low and BPL bit is set to “1”. When the WP is
low, the BPL bit can only be set from “0” to “1” to lock down the
status register, but cannot be reset from “1” to “0”.
When WP is high, the lock-down function of the BPL bit is
disabled and the BPL, BP0, BP1,and BP2 bits in the status
register can all be changed. As long as BPL bit is set to 0 or WP
pin is driven high (VIH) prior to the low-to-high transition of the
CE pin at the end of the WRSR instruction, the bits in the status
register can all be altered by the WRSR instruction. In this case,
a single WRSR instruction can set the BPL bit to “1” to lock down
the status register as well as altering the BP0; BP1 and BP2 bits
at the same time. See Table 4 for a summary description of WP
and BPL functions.
CE
MODE3
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7 8 9 1011 12 13 1415
SCK MODE0
50 or 06
SI
MSB
SO
01
STATUS
REGISTER IN
7 6 5 4 3 2 1 0
MSB
HIGH IMPENANCE
Figure 19: Enable Write Status Register (EWSR) or Write Enable (WREN) and Write Status Register (WRSR)
Enter Secured OTP Mode (ENSO)
The ENSO (B1H) instruction is for entering the additional 4K
bytes secured OTP mode. The additional 4K bytes secured OTP
sector is independent from main array, which may use to store
unique serial number for system identifier. User must unprotect
whole array (BP0=BP1=BP2=0), prior to any Program operation
in OTP sector. After entering the secured OTP mode, only the
secured OTP sector can be accessed and user can only follow
the Read or Program procedure with OTP address range
(address bits [A23 –A12] must be “0”). The secured OTP data
cannot be updated again once it is lock down or has been
programmed. In secured OTP mode, WRSR command will
ignore the input data and lock down the secured OTP sector
(OTP_lock bit =1). To exit secured OTP mode, user must
execute WRDI command. RES can be used to verify the secured
OTP status as shown in Table 6.
Figure 20: Enter OTP Mode (ENSO) Sequence
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ESMT
F25L08PA
OTP Sector Address
Size
Address Range
4K bytes
000000H ~ 000FFFH
Note: The OTP sector is an independent Sector.
Read-Electronic-Signature (RES)
The RES instruction can be used to read the 8-bit Electronic
Signature of the device on the SO pin. The RES instruction can
provide access to the Electronic Signature of the device (except
while an Erase, Program or WRSR cycle is in progress), Any
RES instruction executed while an Erase, Program or WRSR
cycle is in progress is no decoded, and has no effect on the cycle
in progress. In OTP mode, user also can execute RES to confirm
the status.
Figure 21: Read-Electronic-Signature (RES) Instruction
Table 6: Electronic Signature Data
Command
RES
Mode
Electronic Signature Data
Normal
13H
In secured OTP mode &
non lock down (OTP_lock =0)
33H
In secured OTP mode &
lock down (OTP_lock =1)
73H
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ESMT
F25L08PA
JEDEC Read-ID
The JEDEC Read-ID instruction identifies the device as
F25L08PA and the manufacturer as ESMT. The device
information can be read from executing the 8-bit command, 9FH.
Following the JEDEC Read-ID instruction, the 8-bit
manufacturer’s ID, 8CH, is output from the device. After that, a
16-bit device ID is shifted out on the SO pin. Byte1, 8CH,
identifies the manufacturer as ESMT. Byte2, 20H, identifies the
memory type as SPI Flash. Byte3, 14H, identifies the device as
F25L08PA. The instruction sequence is shown in Figure 22.
The JEDEC Read ID instruction is terminated by a low to high
transition on CE at any time during data output. If no other
command is issued after executing the JEDEC Read-ID
instruction, issue a 00H (NOP) command before going into
Standby Mode ( CE =VIH).
Figure 22: JEDEC Read-ID Sequence
Table 7: JEDEC Read-ID Data
Manufacturer’s ID
(Byte 1)
8CH
Elite Semiconductor Memory Technology Inc.
Device ID
Memory Type
(Byte 2)
Memory Capacity
(Byte 3)
20H
14H
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ESMT
F25L08PA
Read-ID (RDID)
The Read-ID instruction (RDID) identifies the devices as
F25L08PA and manufacturer as ESMT. This command is
backward compatible to all ESMT SPI devices and should be
used as default device identification when multiple versions of
ESMT SPI devices are used in one design. The device
information can be read from executing an 8-bit command, 90H,
followed by address bits [A23 -A0]. Following the Read-ID
instruction, the manufacturer’s ID is located in address 00000H
and the device ID is located in address 00001H.
Once the device is in Read-ID mode, the manufacturer’s and
device ID output data toggles between address 00000H and
00001H until terminated by a low to high transition on CE .
Figure 23: Read-ID Sequence
Table 8: Product ID Data
Address
00000H
00001H
Elite Semiconductor Memory Technology Inc.
Byte1
Byte2
8CH
13H
Manufacturer’s ID
Device ID
ESMT F25L08PA
13H
8CH
Device ID
ESMT F25L08PA
Manufacturer’s ID
Publication Date: Jul. 2009
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ESMT
„
F25L08PA
ELECTRICAL SPECIFICATIONS
Absolute Maximum Stress Ratings
(Applied conditions are greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the
operational sections of this datasheet is not implied. Exposure to absolute maximum stress rating conditions may affect device
reliability.)
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
( Note 1: Output shorted for no more than one second. No more than one output shorted at a time. )
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . . . . . CL = 15 pF for ≧75MHz
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .CL = 30 pF for ≦50MHz
See Figures 28 and 29
OPERATING RANGE
Parameter
Operating Supply Voltage
Symbol
Value
VDD (for FCLK <= 50MHz)
2.7 ~ 3.6
VDD (for FCLK = 100MHz)
3.0 ~3.6
TA
0 ~ 70
Ambient Operating Temperature
Unit
V
℃
Table 9: DC OPERATING CHARACTERISTICS
Symbol
Parameter
IDDW
Standard
Read Current
@33 MHz
Dual
Standard
Read Current
@ 50MHz
Dual
Standard
Read Current
@ 100MHz
Dual
Program and Erase Current
ISB
ILI
ILO
VIL
VIH
VOL
VOH
Standby Current
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
IDDR1
IDDR2
IDDR3
Limits
Max
15
18
20
23
25
28
35
Min
30
1
1
0.8
0.7 x VDD
0.2
VDD-0.2
Test Condition
Unit
mA
CE =0.1 VDD/0.9 VDD, SO=open
mA
CE =0.1 VDD/0.9 VDD, SO=open
mA
CE =0.1 VDD/0.9 VDD, SO=open
mA
CE =VDD
µA
µA
µA
V
V
V
V
CE =VDD, VIN =VDD or VSS
VIN=GND to VDD, VDD=VDD Max
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
VDD=VDD Max
IOL=100 µA, VDD=VDD Min
IOH=-100 µA, VDD=VDD Min
Table 10: LATCH UP CHARACTERISTIC
Symbol
ILTH1
Parameter
Latch Up
Minimum
Unit
Test Method
100 + IDD
mA
JEDEC Standard 78
Note 1: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
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ESMT
F25L08PA
Table 11: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
Unit
TPU-READ1
VDD Min to Read Operation
10
µs
TPU-WRITE1
VDD Min to Write Operation
10
µs
Test Condition
Maximum
VOUT = 0V
12 pF
VIN = 0V
6 pF
Table 12: CAPACITANCE (TA = 25°C, f=1 MHz, other pins open)
Parameter
Description
COUT1
Output Pin Capacitance
CIN1
Input Capacitance
Note 1: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Table 13: AC OPERATING CHARACTERISTICS
Normal 33MHz
Symbol
Fast 50 MHz Fast 100 MHz
Parameter
Unit
Min
Max
Min
Min
Serial Clock Frequency
TSCKH
Serial Clock High Time
13
9
5
ns
TSCKL
Serial Clock Low Time
13
9
5
ns
CE Active Setup Time
5
5
5
ns
TCEH1
CE Active Hold Time
5
5
5
ns
TCHS1
CE Not Active Setup Time
5
5
5
ns
TCHH1
CE Not Active Hold Time
5
5
5
ns
TCPH
CE High Time
100
100
100
ns
TCHZ
CE High to High-Z Output
TCLZ
SCK Low to Low-Z Output
0
0
0
ns
TDS
Data In Setup Time
3
3
3
ns
TDH
Data In Hold Time
3
3
3
ns
THLS
HOLD Low Setup Time
5
5
5
ns
THHS
HOLD High Setup Time
5
5
5
ns
THLH
HOLD Low Hold Time
5
5
5
ns
THHH
HOLD High Hold Time
5
5
5
ns
THZ
HOLD Low to High-Z Output
9
9
9
ns
TLZ
HOLD High to Low-Z Output
9
9
9
ns
TOH
Output Hold from SCK Change
TV
Output Valid from SCK
TCES
50
Max
FCLK
1
33
Max
9
0
9
0
12
100
9
0
8
MHz
ns
ns
7
ns
Note 1: Relative to SCK.
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ESMT
„
F25L08PA
ERASE AND PROGRAMMING PERFORMANCE
Limit
Parameter
Symbol
Typ
2
Max3
Unit
Sector Erase Time
TSE
90
200
ms
Block Erase Time
TBE
1
2
s
Chip Erase Time
TCE
10
30
s
Byte Programming Time
TBP
7
30
us
Page Programming Time
TPP
1.5
5
ms
Chip Programming Time
25
100
s
Erase/Program Cycles1
100,000
-
Cycles
20
-
Years
Data Retention
Notes:
1. Not 100% Tested, Excludes external system level over head.
2. Typical values measured at 25°C, 3V.
3. Maximum values measured at 85°C, VDD(min)
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ESMT
F25L08PA
Figure 24: Serial Input Timing Diagram
Figure 25: Serial Output Timing Diagram
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ESMT
F25L08PA
Figure 26: HOLD Timing Diagram
VCC
VCC (max)
Program, Erase and Write command is ignored
CE must track VCC
VCC (min)
TVSL
Reset
State
Read command
is allowed
Device is fully
accessible
VWI
TPUW
Time
Figure 27: Power-Up Timing Diagram
Table 14: Power-Up Timing and VWI Threshold
Parameter
Symbol
Min.
VCC(min) to CE low
TVSL
200
Time Delay before Write instruction
TPUW
Write Inhibit Threshold Voltage
VWI
1
Max.
Unit
us
10
ms
2
V
Note: These parameters are characterized only.
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ESMT
F25L08PA
Input timing reference level
Output timing reference level
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AC
Measurement
Level
0.5VCC
Note : Input pulse rise and fall time are <5ns
Figure 28: AC Input/Output Reference Waveforms
Figure 29: A Teat Load Example
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ESMT
F25L08PA
PACKAGING DIMENSIONS
8-LEAD
SOIC ( 150 mil )
5
GAUGE PLANE
0
0.25
H
E
8
L
DETAIL "X"
1
4
e
b
A
L1
"X"
A1
A2
C
D
SEATING PLANE
Dimension in mm
Dimension in inch
Symbol
Dimension in mm
Dimension in inch
Symbol
Min
Norm
Max
Min
Norm
Max
Min
Norm
Max
Min
Norm
Max
A
1.35
1.60
1.75
0.053
0.063
0.069
D
4.80
4.90
5.00
0.189
0.193
0.197
A1
0.10
0.15
0.25
0.004
0.006
0.010
E
3.80
3.90
4.00
0.150
0.154
0.157
A2
1.25
1.45
1.55
0.049
0.057
0.061
L
0.40
0.66
0.86
0.016
0.026
0.034
b
0.33
0.406
0.51
0.013
0.016
0.020
e
c
0.19
0.203
0.25
0.0075
0.008
0.010
L1
1.00
1.05
1.10
0.039
0.041
0.043
H
5.80
6.00
6.20
0.228
0.236
0.244
θ
0°
---
8°
0°
---
8°
1.27 BSC
0.050 BSC
Controlling dimension : millimenter
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ESMT
F25L08PA
PACKING DIMENSIONS
8-LEAD SOIC 200 mil ( official name – 209 mil )
5
1
4
E1
8
E
θ
b
e
A
A2
D
L
A1
L1
SEATING PLANE
Dimension in mm
Dimension in inch
Symbol
DETAIL "X"
Dimension in mm
Dimension in inch
Symbol
Min
Norm
Max
Min
Norm
Max
Min
Norm
Max
Min
Norm
Max
A
---
---
2.16
---
---
0.085
E
7.70
7.90
8.10
0.303
0.311
0.319
A1
0.05
0.15
0.25
0.002
0.006
0.010
E1
5.18
5.28
5.38
0.204
0.208
0.212
A2
1.70
1.80
1.91
0.067
0.071
0.075
L
0.50
0.65
0.80
0.020
0.026
0.032
b
0.36
0.41
0.51
0.014
0.016
0.020
e
c
0.19
0.20
0.25
0.007
0.008
0.010
L1
1.27
1.37
1.47
0.050
0.054
0.058
D
5.13
5.23
5.33
0.202
0.206
0.210
θ
0°
---
8°
0°
---
8°
1.27 BSC
0.050 BSC
Controlling dimension : millimenter
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2009
Revision: 1.7
29/32
ESMT
F25L08PA
PACKING
DIMENSIONS
8-LEAD P-DIP ( 300 mil )
D
8
5
E
A
eB
E1
1
A2
0
4
b
L
A1
S e a t in g P la n e
b
1
e
Dimension in mm
Symbol
Min
Norm
A
Dimension in inch
Max
Min
Norm
5.00
Max
0.21
A1
0.38
A2
3.18
3.30
3.43
0.125
0.130
0.135
D
9.02
9.27
10.16
0.355
0.365
0.400
E
0.015
7.62 BSC.
0.300 BSC.
E1
6.22
6.35
6.48
0.245
0.250
0.255
L
9.02
9.27
10.16
0.115
0.130
0.150
e
eB
2.54 TYP.
8.51
b
θ
9.53
0.335
0.46 TYP.
b1
O
9.02
0.100 TYP.
0
7
O
0.375
0.018 TYP.
1.52 TYP.
O
0.355
0.060 TYP.
15
O
0
O
7O
15O
Controlling dimension : Inch.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2009
Revision: 1.7
30/32
ESMT
F25L08PA
Revision History
Revision
Date
1.0
2008.02.25
Original
1.1
2008.03.18
Add tBP1 and tBP2 (page1,12,23)
1.2
2008.06.30
1.
2.
3.
1.3
2008.07.17
Modify tSE timing
1.4
2008.11.19
1.5
2009.05.11
1.6
2009.06.04
Add 8 lead SOIC (150mil) package
1.7
2009.07.20
Modify the description of OTP mode
Elite Semiconductor Memory Technology Inc.
Description
Add Dual SPI function
Add power-up timing specification
Add Revision History
1. Modify the error of Device ID
2. Delete TBP1 and TBP2
1.Modify headline
2.Delete the rating of Temperature Under Bias
Publication Date: Jul. 2009
Revision: 1.7
31/32
ESMT
F25L08PA
Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form or
by any means without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at
the time of publication. ESMT assumes no responsibility for any error in
this document, and reserves the right to change the products or
specification in this document without notice.
The information contained herein is presented only as a guide or
examples for the application of our products. No responsibility is
assumed by ESMT for any infringement of patents, copyrights, or other
intellectual property rights of third parties which may result from its use.
No license, either express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of ESMT or
others.
Any semiconductor devices may have inherently a certain rate of failure.
To minimize risks associated with customer's application, adequate
design and operating safeguards against injury, damage, or loss from
such failure, should be provided by the customer when making
application designs.
ESMT's products are not authorized for use in critical applications such
as, but not limited to, life support devices or system, where failure or
abnormal operation may directly affect human lives or cause physical
injury or property damage. If products described here are to be used for
such kinds of application, purchaser must do its own quality assurance
testing appropriate to such applications.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2009
Revision: 1.7
32/32