60A CY7C460A/CY7C462A CY7C464A/CY7C466A Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs Features Functional Description • High-speed, low-power, first-in first-out (FIFO) memories • 8K x 9 FIFO (CY7C460A) • 16K x 9 FIFO (CY7C462A) • 32K x 9 FIFO (CY7C464A) • 64K x 9 FIFO (CY7C466A) • 10-ns access times, 20-ns read/write cycle times • High-speed 50-MHz read/write independent of depth/width • Low operating power — ICC= 60 mA — ISB =8 mA Asynchronous read/write Empty and Full flags Half Full flag (in standalone mode) Retransmit (in standalone mode) TTL-compatible Width and Depth Expansion Capability 5V ± 10% supply PLCC, LCC, 300-mil and 600-mil DIP packaging Three-state outputs Pin compatible density upgrade to CY7C42X/46X family Pin compatible and functionally equivalent to IDT7205, IDT7206, IDT7207, IDT7208 A Half Full (HF) output flag is provided that is valid in the standalone (single device) and width expansion configurations. In the depth expansion configuration, this pin provides the expansion out (XO) information that is used to tell the next FIFO that it will be activated. In the standalone and width expansion configurations, a LOW on the Retransmit (RT) input causes the FIFOs to retransmit the data. Read Enable (R) and Write Enable (W) must both be HIGH during a retransmit cycle, and then R is used to access the data. The CY7C460A, CY7C462A, CY7C464A, and CY7C466A are fabricated using Cypress’s advanced 0.5µ RAM3 CMOS technology. Input ESD protection is greater than 2000V and latch-up is prevented by careful layout and the use of guard rings. Pin Configurations DATAINPUTS (D0−D 8) R RESET LOGIC 5 D1 6 28 D0 7 27 D7 NC XI 8 26 FL/RT 25 MR 24 EF 7C460A 7C462A 7C464A 7C466A D6 FF 9 Q0 10 Q1 11 23 XO/HF NC 12 22 Q7 Q2 13 21 14 15 16 17 18 19 20 Q6 MR C46XA–2 W D8 D3 D2 D1 D0 XI FF Q0 Q1 Q2 Q3 Q8 GND 1 28 2 27 3 26 4 25 5 8 24 7C460A 23 7C462A 7C464A 22 7C466A 21 9 20 10 19 11 18 12 17 13 16 14 15 6 7 VCC D4 D5 D6 D7 FL/RT MR EF XO/HF Q7 Q6 Q5 Q4 R FL/RT C46XA–3 FLAG LOGIC XI V cc D 4 D 5 D2 DATAOUTPUTS (Q0-Q 8) READ CONTROL 32 31 30 29 2 Q 3 Q 8 GND THREE– STATE BUFFERS 1 3 Q 4 Q 5 READ POINTER NC DUAL PORT RAM ARRAY 8K x 9 16K x 9 32K x 9 64K x 9 4 R WRITE CONTROL WRITE POINTER DIP Top View PLCC/LCC Top View NC Logic Block Diagram W The read and write operations may be asynchronous; each can occur at a rate of up to 50 MHz. The write operation occurs when the Write (W) signal is LOW. Read occurs when Read (R) goes LOW. The nine data outputs go to the high-impedance state when R is HIGH. D 3 D 8 W • • • • • • • • • • • The CY7C460A, CY7C462A, CY7C464A, and CY7C466A are respectively, 8K, 16K, 32K, and 64K words by 9-bit wide first-in first-out (FIFO) memories. Each FIFO memory is organized such that the data is read in the same sequential order that it was written. Full and Empty flags are provided to prevent overrun and underrun. Three additional pins are also provided to facilitate unlimited expansion in width, depth, or both. The depth expansion technique steers the control signals from one device to another by passing tokens. EXPANSION LOGIC EF FF XO/HF Cypress Semiconductor Corporation Document #: 38-06011 Rev. *A • C46XA–1 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 26, 2002 CY7C460A/CY7C462A CY7C464A/CY7C466A Selection Guide 7C460A-10 7C462A-10 7C464A-10 7C466A-10 7C460A-15 7C462A-15 7C464A-15 7C466A-15 7C460A-25 7C462A-25 7C464A-25 7C466A-25 Frequency (MHz) 50 40 28.5 Maximum Access Time (ns) 10 15 25 Maximum Ratings [1] Output Current, into Outputs (LOW)............................ 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................–65°C to +150°C Ambient Temperature with Power Applied.............................................–55°C to +125°C Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA Operating Range DC Voltage Applied to Outputs in High Z State ............................................... –0.5V to +7.0V Range Ambient Temperature VCC Commercial 0°C to + 70°C 5V ± 10% DC Input Voltage............................................ –0.5V to +7.0V Industrial –40°C to +85°C 5V ± 10% Power Dissipation ..........................................................1.0W Military[2] –55°C to +125°C 5V ± 10% Supply Voltage to Ground Potential ............... –0.5V to +7.0V Electrical Characteristics Over the Operating Range[3] 7C460A/462A/464A/466A (-10,-15,-25) Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = −2.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage VIL Input LOW Voltage IIX Input Leakage Current GND < VI < VCC IOZ Output Leakage Current R > VIH, GND < VO < VCC ICC Operating Current ISB Standby Current Min. Max. Unit 2.4 V 0.4 V 2.2 VCC V −0.5 0.8 V –10 +10 µA –10 +10 µA VCC = Max., IOUT = 0 mA, Freq. = 20 MHz 60 mA All Inputs = VIH min. 8 mA Capacitance[5] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 4.5V Max. Unit 10 pF 12 pF Notes: 1. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 2. TA is the “instant on” case temperature. 3. See the last page of this specification for Group A subgroup testing information. 4. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 1 second. 5. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-06011 Rev. *A Page 2 of 15 CY7C460A/CY7C462A CY7C464A/CY7C466A AC Test Loads and Waveforms R1 500Ω 5V R1 500Ω 5V OUTPUT ALL INPUT PULSES 3.0V OUTPUT R2 333Ω 30 pF INCLUDING JIG AND SCOPE C460A–4 (a) INCLUDING JIG AND SCOPE 10% GND R2 333Ω 5 pF 90% 10% 90% ≤ 5 ns ≤ 5 ns C460A–6 C460A–5 (b) Equivalent to: THÉVENIN EQUIVALENT 200Ω OUTPUT 2V Switching Characteristics Over the Operating Range[3, 6] 7C460A-10 7C462A-10 7C464A-10 7C466A-10 Parameter Description Min. Max. 20 7C460A-15 7C462A-15 7C464A-15 7C466A-15 Min. Max. 25 7C460A-25 7C462A-25 7C464A-25 7C466A-25 Min. Max. Read Cycle Time tA Access Time tRR Read Recovery Time 10 10 10 ns tPR Read Pulse Width 10 15 25 ns tLZR Read LOW to Low Z 3 3 3 ns tDVR[7] tHZR[7] Data Valid After Read HIGH 3 tWC Write Cycle Time 20 25 35 ns tPW Write Pulse Width 10 15 25 ns tHWZ Write HIGH to Low Z 5 5 5 ns tWR Write Recovery Time 10 10 10 ns tSD Data Set-Up Time 9 9 9 ns tHD Data Hold Time 0 0 0 ns tMRSC MR Cycle Time 20 25 35 ns tPMR MR Pulse Width 10 15 25 ns tRMR MR Recovery Time 10 10 10 ns tRPW Read HIGH to MR HIGH 10 15 25 ns tWPW Write HIGH to MR HIGH 10 15 25 ns tRTC Retransmit Cycle Time 20 25 35 ns tPRT Retransmit Pulse Width 10 15 25 ns tRTR Retransmit Recovery Time 10 tEFL MR to EF LOW 20 25 35 ns tHFH MR to HF HIGH 20 25 35 ns tFFH MR to FF HIGH 20 25 35 ns tREF Read LOW to EF LOW 10 15 25 ns tRFF Read HIGH to FF HIGH 10 15 25 ns 10 Read HIGH to High Z 35 Unit tRC 15 3 15 ns 25 3 15 10 ns ns 18 10 ns ns Notes: 6. Test conditions assume signal transmission time of 5 ns or less, timing reference levels of 1.5V and output loading of the specified IOL/IOH and 30-pF load capacitance, as in part (a) of AC Test Loads, unless otherwise specified. 7. tHZR and tDVR use capacitance loading as in part (b) of AC Test Loads. Document #: 38-06011 Rev. *A Page 3 of 15 CY7C460A/CY7C462A CY7C464A/CY7C466A Switching Characteristics Over the Operating Range[3, 6] (continued) 7C460A-10 7C462A-10 7C464A-10 7C466A-10 Parameter Description Min. Max. 7C460A-15 7C462A-15 7C464A-15 7C466A-15 Min. Max. 7C460A-25 7C462A-25 7C464A-25 7C466A-25 Min. Max. Unit tWEF Write HIGH to EF HIGH 10 15 25 ns tWFF Write LOW to FF LOW 10 15 25 ns tWHF Write LOW to HF LOW 10 15 35 ns tRHF Read HIGH to HF HIGH 10 15 35 ns tRAE Effective Read from Write HIGH 10 15 25 ns tRPE Effective Read Pulse Width After EF HIGH tWAF Effective Write from Read HIGH tWPF Effective Write Pulse Width After FF HIGH tXOL Expansion Out LOW Delay from Clock 10 15 25 ns tXOH Expansion Out HIGH Delay from Clock 10 15 25 ns Document #: 38-06011 Rev. *A 10 15 10 25 15 15 10 ns 25 25 ns ns Page 4 of 15 CY7C460A/CY7C462A CY7C464A/CY7C466A Switching Waveforms[7] Asynchronous Read and Write tRC tPR tA tRR tA R tLZR tDVR Q0−Q 8 tHZR DATA VALID tPW tWC DATA VALID tWR tPW W tSD D0−D 8 tSD DATA VALID tHD DATA VALID C460A–7 Master Reset tMRSC [10] tPMR MR R, W tHD [9] tEFL EF tRPW tWPW tRMR tHFH HF tFFH FF C460A–8 Half Full Flag HALF FULL HALF FULL+1 HALF FULL W tRHF R tWHF HF C460A–9 Notes: 8. A HIGH-to-LOW transition of either the write or read strobe causes a HIGH-to-LOW transition of the responding flag. Correspondingly, a LOW-to-HIGH strobe transition causes a LOW-to-HIGH flag transition. 9. W and R = VIH around the rising edge of MR. 10. tMSRC = t PMR + t RMR Document #: 38-06011 Rev. *A Page 5 of 15 CY7C460A/CY7C462A CY7C464A/CY7C466A Switching Waveforms[7] (continued) Last Write to First Read Full Flag LAST WRITE FIRST READ ADDITIONAL READS FIRST WRITE R W tRFF tWFF FF C460A–10 Last READ to First WRITE Empty Flag LAST READ FIRST WRITE ADDITIONAL WRITES FIRST READ W R tREF tWEF EF tA VALID DATA OUT VALID C460A–11 Retransmit [11,12] tRTC tPRT FL/RT R,W tRTR tRTC tRTR C460A–12 Notes: 11. tRTC = tPRT + tRTR. 12. EF, HF, and FF may change state during retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTC, except for the CY7C46x-20 (Military), whose flags will be valid after tRTC + 10 ns. Document #: 38-06011 Rev. *A Page 6 of 15 CY7C460A/CY7C462A CY7C464A/CY7C466A Switching Waveforms[7] (continued) Full Flag and Write Data Flow-Through Mode R tWAF tWPF W tWFF tRFF FF tHD DATA IN DATA VALID tA DATA OUT tSD DATA VALID C460A–13 Empty Flag and Read Data Flow-Through Mode DATA IN W tRAE R tREF EF tWEF tHWZ DATA OUT tRPE tA DATA VALID C460A–14 Document #: 38-06011 Rev. *A Page 7 of 15 CY7C460A/CY7C462A CY7C464A/CY7C466A Switching Waveforms[7] (continued) Expansion TimingDiagrams W tWR t XOL XO1(XI2) t XOH [13] tHD tSD D0−D 8 tHD tSD DATA VALID DATA VALID C460A–15 R tRR XO1(XI 2) t XOH tXOL [13] tHZR tLZR tDVR tDVR Q0 −Q8 DATA VALID DATA VALID tA tA C460A–16 Note: 13. Expansion out of device 1 (XO1) is connected to expansion in of device 2 (XI2). Architecture Resetting the FIFO Upon power-up, the FIFO must be reset with a master reset (MR) cycle. This causes the FIFO to enter the empty condition signified by the Empty flag (EF) being LOW, and both the Half Full (HF), and Full flags (FF) being HIGH. Read (R) and Write (W) must be HIGH tRPW/tWPW before and tRMR after the rising edge of MR for a valid reset cycle. If reading from the FIFO after a reset cycle is attempted, the outputs will all be in the high-impedance state. Writing Data to the FIFO The availability of at least one empty location is indicated by a HIGH FF. The falling edge of W initiates a write cycle. Data appearing at the inputs (D0−D8) tSD before and tHD after the rising edge of W will be stored sequentially in the FIFO. The EF LOW-to-HIGH transition occurs tWEF after the first LOW-to-HIGH transition of W for an empty FIFO. HF goes LOW tWHF after the falling edge of W following the FIFO actually being half full. Therefore, the HF is active once the FIFO is filled to half its capacity plus one word. HF will remain LOW while less than one half of total memory is available for writing. The LOW-to-HIGH transition of HF occurs tRHF after the rising edge of R when the FIFO goes from half full +1 to half full. HF Document #: 38-06011 Rev. *A is available in standalone and width expansion modes. FF goes LOW tWFF after the falling edge of W, during the cycle in which the last available location is filled. Internal logic prevents overrunning a full FIFO. Writes to a full FIFO are ignored and the write pointer is not incremented. FF goes HIGH tRFF after a read from a full FIFO. Reading Data from the FIFO The falling edge of R initiates a read cycle if the EF is not LOW. Data outputs (Q0−Q8) are in a high-impedance condition between read operations (R HIGH), when the FIFO is empty, or when the FIFO is not the active device in the depth expansion mode. When one word is in the FIFO, the falling edge of R initiates a HIGH-to-LOW transition of EF. When the FIFO is empty, the outputs are in a high-impedance state. Reads to an empty FIFO are ignored and do not increment the read pointer. From the empty condition, the FIFO can be read tWEF after a valid write. Retransmit The retransmit feature is beneficial when transferring packets of data. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. The retransmit (RT) input is active in the standalone and width expansion modes. The retransmit feature is intended for use when a Page 8 of 15 CY7C460A/CY7C462A CY7C464A/CY7C466A number of writes equal-to-or-less-than the depth of the FIFO have occurred since the last MR cycle. A LOW pulse on RT resets the internal read pointer to the first physical location of the FIFO. R and W must both be HIGH while and tRTR after retransmit is LOW. With every read cycle after retransmit, previously accessed data is read and the read pointer incremented until equal to the write pointer. Full, Half Full, and Empty flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. Data written to the FIFO after activation of RT are transmitted also. The full depth of the FIFO can be repeatedly retransmitted. Standalone/Width Expansion Modes Standalone and width expansion modes are set by grounding expansion in (XI) and tying first load (FL) to VCC prior to a MR cycle. FIFOs can be expanded in width to provide word widths greater than nine in increments of nine. During width expansion mode, all control line inputs are common to all devices, and flag outputs from any device can be monitored. Depth Expansion Mode (see Figure 1) Depth expansion mode is entered when, during a MR cycle, expansion out (XO) of one device is connected to expansion in (XI) of the next device, with XO of the last device connected to XI of the first device. In the depth expansion mode, the first load (FL) input, when grounded, indicates that this is the first part to be loaded. All other devices must have this pin HIGH. To enable the correct FIFO, XO is pulsed LOW when the last physical location of the previous FIFO is written to and is pulsed LOW again when the last physical location is read. Only one FIFO is enabled for Read and one is enabled for Write at any given time. All other devices are in standby. FIFOs can also be expanded simultaneously in depth and width. Consequently, any depth or width FIFO can be created with word widths in increments of nine. When expanding in depth, a composite FF is created by ORing the FFs together. Likewise, a composite EF is created by ORing EFs together. HF and RT functions are not available in depth expansion mode. XO R W EF FF D0-8 9 9 9 CY7C460A CY7C462A CY7C464A CY7C466A FL Q0-8 VCC XI XO FULL EF FF EMPTY CY7C460A CY7C462A CY7C464A CY7C466A 9 FL XI XO * FF 9 EF CY7C460A CY7C462A CY7C464A CY7C466A RS FL XI * FIRST DEVICE C460A–17 Figure 1. Depth Expansion Document #: 38-06011 Rev. *A Page 9 of 15 CY7C460A/CY7C462A CY7C464A/CY7C466A Ordering Information 8K x 9 Asynchronous FIFO Speed (ns) 10 15 25 Ordering Code Package Name Package Type Operating Range CY7C460A-10JC J65 32-Lead Plastic Leaded Chip Carrier Commercial CY7C460A-10PC P15 28-Lead (600-Mil) Molded DIP CY7C460A-10PTC P21 28-Lead (300-Mil) Molded DIP CY7C460A-10JI J65 32-Lead Plastic Leaded Chip Carrier Industrial CY7C460A-15JC J65 32-Lead Plastic Leaded Chip Carrier Commercial CY7C460A-15PC P15 28-Lead (600-Mil) Molded DIP CY7C460A-15PTC P21 28-Lead (300-Mil) Molded DIP CY7C460A-25JC J65 32-Lead Plastic Leaded Chip Carrier CY7C460A-25PC P15 28-Lead (600-Mil) Molded DIP CY7C460A-25PTC P21 28-Lead (300-Mil) Molded DIP Commercial 16K x 9 Asynchronous FIFO Speed (ns) 10 15 25 Ordering Code Package Name Package Type Operating Range CY7C462A-10JC J65 32-Lead Plastic Leaded Chip Carrier CY7C462A-10PC P15 28-Lead (600-Mil) Molded DIP Commercial CY7C462A-10PTC P21 28-Lead (300-Mil) Molded DIP CY7C462A-10JI J65 32-Lead Plastic Leaded Chip Carrier Industrial CY7C462A-15JC J65 32-Lead Plastic Leaded Chip Carrier Commercial CY7C462A-15PC P15 28-Lead (600-Mil) Molded DIP CY7C462A-15PTC P21 28-Lead (300-Mil) Molded DIP CY7C462A-25JC J65 32-Lead Plastic Leaded Chip Carrier CY7C462A-25PC P15 28-Lead (600-Mil) Molded DIP CY7C462A-25PTC P21 28-Lead (300-Mil) Molded DIP Commercial 32K x 9 Asynchronous FIFO Speed (ns) 10 15 25 Ordering Code Package Name Package Type Operating Range CY7C464A-10JC J65 32-Lead Plastic Leaded Chip Carrier CY7C464A-10PC P15 28-Lead (600-Mil) Molded DIP CY7C464A-10PTC P21 28-Lead (300-Mil) Molded DIP CY7C464A-10JI J65 32-Lead Plastic Leaded Chip Carrier Industrial CY7C464A-15JC J65 32-Lead Plastic Leaded Chip Carrier Commercial CY7C464A-15PC P15 28-Lead (600-Mil) Molded DIP CY7C464A-15PTC P21 28-Lead (300-Mil) Molded DIP CY7C464A-15LMB L55 32-Pin Rectangular Leadless Chip Carrier Military CY7C464A-25JC J65 32-Lead Plastic Leaded Chip Carrier Commercial CY7C464A-25PC P15 28-Lead (600-Mil) Molded DIP CY7C464A-25PTC P21 28-Lead (300-Mil) Molded DIP Document #: 38-06011 Rev. *A Commercial Page 10 of 15 CY7C460A/CY7C462A CY7C464A/CY7C466A Ordering Information (continued) 64K x 9 Asynchronous FIFO Speed (ns) 10 15 25 Ordering Code CY7C466A-10JC Package Name J65 Package Type 32-Lead Plastic Leaded Chip Carrier Operating Range Commercial CY7C466A-10PC P15 28-Lead (600-Mil) Molded DIP CY7C466A-10PTC P21 28-Lead (300-Mil) Molded DIP CY7C466A-10JI J65 32-Lead Plastic Leaded Chip Carrier Industrial CY7C466A-15JC J65 32-Lead Plastic Leaded Chip Carrier Commercial CY7C466A-15PC P15 28-Lead (600-Mil) Molded DIP CY7C466A-15PTC P21 28-Lead (300-Mil) Molded DIP CY7C466A-15LMB L55 32-Pin Rectangular Leadless Chip Carrier Military CY7C466A-25JC J65 32-Lead Plastic Leaded Chip Carrier Commercial CY7C466A-25PC P15 28-Lead (600-Mil) Molded DIP CY7C466A-25PTC P21 28-Lead (300-Mil) Molded DIP Document #: 38-06011 Rev. *A Page 11 of 15 CY7C460A/CY7C462A CY7C464A/CY7C466A MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter Switching Characteristics Subgroups Parameter Subgroups VOH 1, 2, 3 tRC 9, 10, 11 VOL 1, 2, 3 tA 9, 10, 11 VIH 1, 2, 3 tRR 9, 10, 11 VIL Max. 1, 2, 3 tPR 9, 10, 11 IIX 1, 2, 3 tLZR 9, 10, 11 ICC 1, 2, 3 tDVR 9, 10, 11 ISB1 1, 2, 3 tHZR 9, 10, 11 ISB2 1, 2, 3 tWC 9, 10, 11 IOS 1, 2, 3 tPW 9, 10, 11 IOZ 1, 2, 3 tHWZ 9, 10, 11 tWR 9, 10, 11 tSD 9, 10, 11 tHD 9, 10, 11 tMRSC 9, 10, 11 tPMR 9, 10, 11 tRMR 9, 10, 11 tRPW 9, 10, 11 tWPW 9, 10, 11 tRTC 9, 10, 11 tPRT 9, 10, 11 tRTR 9, 10, 11 tEFL 9, 10, 11 tHFH 9, 10, 11 tFFH 9, 10, 11 tREF 9, 10, 11 tRFF 9, 10, 11 tWEF 9, 10, 11 tWFF 9, 10, 11 tWHF 9, 10, 11 tRHF 9, 10, 11 tRAE 9, 10, 11 tRPE 9, 10, 11 tWAF 9, 10, 11 tWPF 9, 10, 11 tXOL 9, 10, 11 tXOH 9, 10, 11 Document #: 38-00627-A Document #: 38-06011 Rev. *A Page 12 of 15 CY7C460A/CY7C462A CY7C464A/CY7C466A Package Diagrams 32-Lead Plastic Leaded Chip Carrier J65 51-85002-B 32-Pin Rectangular Leadless Chip Carrier L55 MIL-STD-1835 C-12 51-80068 Document #: 38-06011 Rev. *A Page 13 of 15 CY7C460A/CY7C462A CY7C464A/CY7C466A Package Diagrams (continued) 28-Lead (600-Mil) Molded DIP P15 51-85017-A 28-Lead (300-Mil) Molded DIP P21 51-85014-B Document #: 38-06011 Rev. *A Page 14 of 15 © Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C460A/CY7C462A CY7C464A/CY7C466A Document Title: CY7C460A, CY7C462A, CY7C646A, CY7C466A Asynchronous, Cascadable 8K/16K/32K/64K X 9 FIFOs Document Number: 38-06011 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 106472 09/10/01 SZV Change from Spec number 38-00627 to 38-06011 *A 122263 12/26/02 RBI Power up requirements added to Maximum Ratings Information Document #: 38-06011 Rev. *A Page 15 of 15