MITSUBISHI STORAGE CARD ATA PC CARDS MF007M5-03ATxx MF0015M-03ATxx MF0030M-03ATxx MF0045M-03ATxx MF0060M-03ATxx MF0075M-03ATxx MF0090M-03ATxx MF0105M-03ATxx 8/16-bit Data Bus Flash ATA PC Card Connector Type Two- piece 68-pin FEATURES DESCRIPTION Mitsubishi’s Flash ATA cards provide large memory capacities on a device approximately the size of a credit card (85.6mm×54mm×3.3mm). The cards use a 8/16 bit data bus. Available in 7.5MB, 15MB, 30MB, 45MB, 60MB, 75MB, 90MB and 105MB capacities, Mitsubishi’s Flash ATA cards conform to the JEIDA/PCMCIA standard. 68 pin PC Card Standard Type-I PC Card Single 5V or 3.3V Supply Card density of up to 105MB maximum Four PC Card ATA and IDE ATA modes Nonvolatile, No Batteries Required High reliability based on internal ECC function Auto power-down mode In default mode, the ATA card operates in P C Card compliant sockets. It conforms to PCMCIA2.1, JEIDA4.2 and PC Card Standard. APPLICATIONS Computers Digital Camera Data Communication When the OE# signal is asserted low level by the Host system in power on cycle, the Mitsubishi’s Flash ATA cards can be selected in a IDE ATA interface. It uses the ATA command set so no software drivers are required. Office automation Industrial Consumer MITSUBISHI ELECTRIC 1 1997.Nov. Rev. 1.2 MITSUBISHI STORAGE CARD ATA PC CARDS PRODUCT LIST Memory capacity(Bytes) MF007M5-03ATxx MF0015M-03ATxx MF0030M-03ATxx MF0045M-03ATxx MF0060M-03ATxx MF0075M-03ATxx MF0090M-03ATxx MF0105M-03ATxx 7,864,320 15,728,640 31,457,280 47,185,920 62,914,560 78,643,200 94,371,840 110,100,480 Data Bus width(bits) Memory 64Mbit Flash x 1 64Mbit Flash x 2 64Mbit Flash x 4 64Mbit Flash x 6 64Mbit Flash x 8 64Mbit Flash x 10 64Mbit Flash x 12 64Mbit Flash x 14 8/16 Cylinder Head Sector 240 480 480 720 960 600 720 840 2 2 4 4 4 8 8 8 32 32 32 32 32 32 32 32 PIN ASSIGNMENT Pin PC Card Memory Mode Signal I/O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 GND D3 D4 D5 D6 D7 CE1# A10 OE# N.C A9 A8 N.C N.C WE# READY Vcc N.C N.C N.C N.C A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 WP GND I/O I/O I/O I/O I/O I I I I I I O I I I I I I I I I/O I/O I/O O - PC Card I/O Mode Signal I/O GND D3 D4 D5 D6 D7 CE1# A10 OE# N.C A9 A8 N.C N.C WE# IREQ# Vcc N.C N.C N.C N.C A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 IOIS16# GND I/O I/O I/O I/O I/O I I I I I I O I I I I I I I I I/O I/O I/O O - IDE ATA Interface Signal I/O GND D3 D4 D5 D6 D7 CS0# N.U ATA SEL# N.C N.U N.U N.C N.C WE# INTRQ Vcc N.C N.C N.C N.C N.U N.U N.U N.U N.U A2 A1 A0 D0 D1 D2 IOCS16# GND I/O I/O I/O I/O I/O I I I O I I I I/O I/O I/O O - Pin PC Card Memory Mode Signal I/O 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 GND CD1# D11 D12 D13 D14 D15 CE2# VS1# N.U N.U N.C N.C N.C N.C N.C Vcc N.C N.C N.C N.C CSEL VS2# RESET WAIT# N.U REG# BVD2 BVD1 D8 D9 D10 CD2# GND O I/O I/O I/O I/O I/O I O I O I O I O O I/O I/O I/O O - PC Card I/O Mode Signal I/O GND CD1# D11 D12 D13 D14 D15 CE2# VS1# IORD# IOWR# N.C N.C N.C N.C N.C Vcc N.C N.C N.C N.C CSEL VS2# RESET WAIT# INPACK# REG# SPKR# STSCHG# D8 D9 D10 CD2# GND O I/O I/O I/O I/O I/O I O I I I O I O O I O O I/O I/O I/O O - IDE ATA Interface Signal I/O GND CD1# D11 D12 D13 D14 D15 CS1# VS1# IORD# IOWR# N.C N.C N.C N.C N.C Vcc N.C N.C N.C N.C CSEL VS2# RESET# IORDY INPACK# REG# DASP# PDIAG# D8 D9 D10 CD2# GND O I/O I/O I/O I/O I/O I O I I I O I O O I I/O I/O I/O I/O I/O O - N.C = Not connected internally. N.U = Not used. MITSUBISHI ELECTRIC 2 1997.Nov. Rev. 1.2 MITSUBISHI STORAGE CARD ATA PC CARDS Signal Description Signal Name Address bus[A10-A0] I/O I Data bus[D15-D0] I/O Pin No. 8, 11, 12, 22, 23, 24, 25, 26, 27, 28, 29 41, 40, 39, 38, 37, 66, 65, 64, 6, 5, 4, 3, 2 ,32,31, 30 7, 42 Description Signals A10-A0 are address bus. A0 is invalid in word mode. A10 is the MSB and A0 is the LSB. Signals D15-D0 are data bus. D0 is the LSB of the Even Byte of the Word. D8 is the LSB of the Odd Byte of the Word. Card Enable[CE1#, CE2#] (PC Card Memory Mode) Card Enable[CE1#, CE2#] (PC Card I/O Mode) Chip Select[CS0#, CS1#] (IDE ATA Interface) I Output Enable[OE#] (PC Card Memory Mode) Output Enable[OE#] (PC Card I/O Mode) ATA SEL# (IDE ATA Interface) Write Enable[WE#] (PC Card Memory Mode) Write Enable[WE#] (PC Card I/O Mode) Write Enable[WE#] (IDE ATA Interface) I/O Read[IORD#] (PC Card I/O Mode) I/O Read[IORD#] (IDE ATA Interface) I/O Write[IOWR#] (PC Card I/O Mode) I/O Write[IOWR#] (IDE ATA Interface) Ready[READY] (PC Card Memory Mode) IREQ# (PC Card I/O Mode) I 9 I 15 I 44 IORD# is used to read data from the Card’s I/O space. I 45 IOWR# is used to write data to the Card’s I/O space. O 16 O 36, 67 O 33 READY signal is set high when the ATA Card is ready to accept a new data transfer operation. This signal of low level is indicates that the card is requesting software service to host, and high level indicates that the card is not requesting. This signal is active high interrupt request to the host. CD1# and CD2# provided for proper detection of PC Card insertion. This signal is held low because this card does not have a write protect switch. This output signal is asserted when the I/O port address is capable of 16-bit access. INTRQ (IDE ATA Interface) Card Detection[CD1#, CD2#] Write Protect[WP] (PC Card Memory Mode) IOIS16# (PC Card I/O Mode) IOCS16# (IDE ATA Interface) CE1# and CE2# are low active card select signals. In IDE ATA Interface, CS0 is used to select the Command Block Registers. CS1 is used to select the Control Block Registers. OE# is used to gate Attribute and Common Memory Read data from the ATA Card. OE# is used to gate Attribute Memory Read data from the ATA Card. To enable IDE ATA Interface, this input should be grounded by the host. WE# is used for strobing Attribute and Common Memory Write data into the ATA Card. WE# is used for strobing Attribute Memory Write data into the ATA Card. This input should be connected Vcc by the host. MITSUBISHI ELECTRIC 3 1997.Nov. Rev. 1.2 MITSUBISHI STORAGE CARD ATA PC CARDS Attribute Memory Select[REG#] (PC Card Memory Mode) Attribute Memory Select[REG#] (PC Card I/O Mode) Attribute Memory Select[REG#] (IDE ATA Interface) Battery Voltage Detect[BVD2] (PC Card Memory Mode) Audio Digital Waveform[SPKR#] (PC Card I/O Mode) DASP# (IDE ATA Interface) Card Reset[RESET] (PC Card Memory Mode) Card Reset[RESET] (PC Card I/O Mode) Card Reset[RESET#] (IDE ATA Interface) Wait[WAIT#] (PC card Memory Mode) Wait[WAIT#] (PC card I/O Mode) IORDY (IDE ATA Interface) Input Port Acknowledge[INPACK#] (PC Card I/O Mode) Input Port Acknowledge[INPACK#] (IDE ATA Interface) Battery Voltage Detect[BVD1] (PC Card Memory Mode) STSCHG# (PC Card I/O Mode) I O 61 When this signal is asserted, access is limited to Attribute Memory with OE#/WE# and I/O Space with IORD#/IOWR#. This input signal is not used for this mode and should be connected to Vcc by the host. This output is driven to a high-level. 62 SPKR# is kept negated because this Card does not have digital audio output. This signal is the DISK Active/Slave Present signal in the Master/Slave handshake protocol. By assertion of this signal, all registers of this Card are cleared. This signal should be kept to High-Z by the host for at least 1ms after Vcc applied. I/O I 58 This input pin is the active low hardware reset from the host. This signal is asserted to delay completion of the memory or I/O access cycle. O 59 O 60 This signal is asserted when the Card is selected and can respond to an I/O Read cycle at the address on the address bus. O 63 This output is driven to a high-level. O 43, 57 Cable Select[CSEL] (PC card Memory Mode) Cable Select[CSEL] (PC card I/O Mode) Cable Select[CSEL] (IDE ATA Interface) - 56 This signal is asserted low to alert the host to changes in the status of Configuration Status Register in the Attribute Memory Space. This signal is the Pass Diagnostic signal in the Master/Slave handshake protocol. VS1 is grounded so that the Card CIS can be read at 3.3V and VS2 is N.C. This signal is not used for this mode. Vcc GND - 17, 51 1, 34, 35, 68 This signal is used to configure this Card as a Master or a Slave. When this signal is grounded, this Card is configured as a Master. When this signal is Open, this Card is configure as a Slave. 5V or 3.3V power. Ground. PDIAG# (IDE ATA Interface) Voltage Sense[VS1, VS2] I/O I MITSUBISHI ELECTRIC 4 1997.Nov. Rev. 1.2 MITSUBISHI STORAGE CARD ATA PC CARDS BLOCK DIAGRAM Vcc GND Internal Vcc Controller A10-A0 CE1#/CS0# CE2#/CS1# OE#/ATA SEL# WE# IORD# IOWR# REG# RESET/RESET# POR# RES# 64Mbit AND 64Mbit AND Flash Memory Flash Memory (x14) (x14) CE# OE# WE# CDE# SC D15-D0 READY/IREQ#/INTRQ WP/IOIS16#/IOCS16# INPACK# BVD1/STSCHG#/PDIAG# BVD2/SPKR#/DASP# WAIT#/IORDY CSEL I/O7-I/O0 R/B# XIN XOUT X-TAL VS1 VS2 RESET Circuit Open CD1# CD2# MITSUBISHI ELECTRIC 5 1997.Nov. Rev. 1.2 MITSUBISHI STORAGE CARD ATA PC CARDS FUNCTION TABLE Function REG# CE2# CE1# A0 OE# WE# IORD# IOWR# D15-D8 D7-D0 H L L L H X L H X X X L L L L X H H H H X H H H H X H H H H High-Z High-Z High-Z Invalid Invalid High-Z Even Byte Invalid Even Byte High-Z H L L L H X L H X X X H H H H X L L L L X H H H H X H H H H don’t care don’t care don’t care don’t care don’t care don’t care Even Byte don’t care Even Byte don’t care H L L L H X L H X X X L L L L X H H H H X H H H H X H H H H High-Z High-Z High-Z Odd Byte Odd Byte High-Z Even Byte Odd Byte Even Byte High-Z H H H L L H L L L H X L H X X X H H H H X L L L L X H H H H X H H H H don’t care don’t care don’t care Odd Byte Odd Byte don’t care Even Byte Odd Byte Even Byte don’t care H H H L L H L L L H X L H X X X H H H H X H H H H X L L L L X H H H H High-Z High-Z High-Z Odd Byte Odd Byte High-Z Even Byte Odd Byte Even Byte High-Z H H H L L H L L L H X L H X X X H H H H X H H H H X H H H H X L L L L don’t care don’t care don’t care Odd Byte Odd Byte don’t care Even Byte Odd Byte Even Byte don’t care Attribute Memory Read Function Standby Byte Access Word Access Odd Byte X L L L L H H H L L Attribute Memory Write Function Standby Byte Access Word Access Odd Byte X L L L L H H H L L Common Memory Read Function Standby Byte Access Word Access Odd Byte X H H H H H H H L L Common Memory Write Function Standby Byte Access Word Access Odd Byte X H H H H I/O Read Function Standby Byte Access Word Access Odd Byte X L L L L I/O Write Function Standby Byte Access Word Access Odd Byte X L L L L MITSUBISHI ELECTRIC 6 1997.Nov. Rev. 1.2 MITSUBISHI STORAGE CARD ATA PC CARDS Memory mapped mode(Index=0) REG# CE2# CE1# A10 A9-A4 A3 A2 A1 A0 1 1 1 1 1 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 x 0 1 x x 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 x x x x 0 0 0 0 0 0 0 1 1 1 1 0 0 1 x x 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 x x x x 0 0 0 0 1 1 1 1 0 0 0 1 0 1 x x 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 x x x x x x x x 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 x x 0 1 x x 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 x x x x 1 1 1 1 1 1 1 1 0 0 0 1 0 1 x x 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 0 1 0 0 0 1 0 0 0 1 1 1 1 x x x x x x x 1 1 1 x x x x 1 1 1 x x x x 1 1 1 x x x x 0 1 x x 0 1 x Register OE#=”L” WE#=“L” Data Register(D15-D0) Data Register(D15-D0) Data Register[Even, Odd](D7-D0) Data Register[Even, Odd](D7-D0) Error Register(D7-D0) Feature Register(D7-D0) Error Register(D15-D8) Feature Register(D15-D8) Sector Count Register(D7-D0) Sector Count Register(D7-D0) Sector Number Register(D15-D8) Sector Number Register(D15-D8) Sector Count Register(D7-D0) Sector Count Register(D7-D0) Sector Number Register(D7-D0) Sector Number Register(D7-D0) Sector Number Register(D15-D8) Sector Number Register(D15-D8) Cylinder Low Register(D7-D0) Cylinder Low Register(D7-D0) Cylinder High Register(D15-D8) Cylinder High Register(D15-D8) Cylinder Low Register(D7-D0) Cylinder Low Register(D7-D0) Cylinder High Register(D7-D0) Cylinder High Register(D7-D0) Cylinder High Register(D15-D8) Cylinder High Register(D15-D8) Drive Head Register(D7-D0) Drive Head Register(D7-D0) Status Register(D15-D8) Command Register(D15-D8) Drive Head Register(D7-D0) Drive Head Register(D7-D0) Status Register(D7-D0) Command Register(D7-D0) Status Register(D15-D8) Command Register(D15-D8) Data Register(D15-D0) Data Register(D15-D0) Data Register[Even, Odd](D7-D0) Data Register[Even, Odd](D7-D0) Data Register[Odd](D7-D0) Data Register[Odd](D7-D0) Data Register[Odd](D15-D8) Data Register[Odd](D15-D8) invalid(D7-D0) invalid(D7-D0) Error Register(D15-D8) Feature Register(D15-D8) invalid invalid Error Register(D7-D0) Feature Register(D7-D0) Error Register(D15-D8) Feature Register(D15-D8) Alt. Status Register(D7-D0) Device Control Register(D7-D0) Drive Address Register(D15-D8) invalid Alt. Status Register(D7-D0) Device Control Register(D7-D0) Drive Address Register(D7-D0) invalid Drive Address Register(D15-D8) invalid Data Register(D15-D0) Data Register(D15-D0) Data Register[Even, Odd](D7-D0) Data Register[Even, Odd](D7-D0) Data Register[Odd](D7-D0) Data Register[Odd](D7-D0) Data Register[Odd](D15-D8) Data Register[Odd](D15-D8) MITSUBISHI ELECTRIC 7 1997.Nov. Rev. 1.2 MITSUBISHI STORAGE CARD ATA PC CARDS Contiguous I/O Map(Index=1) REG# CE2# CE1# A9-A4 A3 A2 A1 A0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 x 0 1 x 0 0 0 0 0 1 1 0 0 0 0 1 0 x x x x 0 0 0 0 0 0 0 1 1 1 1 0 0 1 x 0 0 0 0 0 1 1 0 0 0 0 1 0 x x x x 0 0 0 0 1 1 1 1 0 0 0 1 0 1 x 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 0 0 0 1 0 x x x x x x x x 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 x x 0 1 x 0 0 0 0 0 1 1 0 0 0 0 1 0 x x x x 1 1 1 1 1 1 1 1 0 0 0 1 0 1 x 0 0 0 0 1 1 0 0 0 1 x x x 1 1 1 1 1 1 1 1 1 0 1 x Register IORD#=”L” IOWR#=“L” Data Register(D15-D0) Data Register(D15-D0) Data Register[Even, Odd](D7-D0) Data Register[Even, Odd](D7-D0) Error Register(D7-D0) Feature Register(D7-D0) Error Register(D15-D8) Feature Register(D15-D8) Sector Count Register(D7-D0) Sector Count Register(D7-D0) Sector Number Register(D15-D8) Sector Number Register(D15-D8) Sector Count Register(D7-D0) Sector Count Register(D7-D0) Sector Number Register(D7-D0) Sector Number Register(D7-D0) Sector Number Register(D15-D8) Sector Number Register(D15-D8) Cylinder Low Register(D7-D0) Cylinder Low Register(D7-D0) Cylinder High Register(D15-D8) Cylinder High Register(D15-D8) Cylinder Low Register(D7-D0) Cylinder Low Register(D7-D0) Cylinder High Register(D7-D0) Cylinder High Register(D7-D0) Cylinder High Register(D15-D8) Cylinder High Register(D15-D8) Drive Head Register(D7-D0) Drive Head Register(D7-D0) Status Register(D15-D8) Command Register(D15-D8) Drive Head Register(D7-D0) Drive Head Register(D7-D0) Status Register(D7-D0) Command Register(D7-D0) Status Register(D15-D8) Command Register(D15-D8) Data Register(D15-D0) Data Register(D15-D0) Data Register[Even, Odd](D7-D0) Data Register[Even, Odd](D7-D0) Data Register[Odd](D7-D0) Data Register[Odd](D7-D0) Data Register[Odd](D15-D8) Data Register[Odd](D15-D8) invalid(D7-D0) invalid(D7-D0) Error Register(D15-D8) Feature Register(D15-D8) invalid invalid Error Register(D7-D0) Feature Register(D7-D0) Error Register(D15-D8) Feature Register(D15-D8) Alt. Status Register(D7-D0) Device Control Register(D7-D0) Drive Address Register(D15-D8) invalid Alt. Status Register(D7-D0) Device Control Register(D7-D0) Drive Address Register(D7-D0) invalid Drive Address Register(D15-D8) invalid MITSUBISHI ELECTRIC 8 1997.Nov. Rev. 1.2 MITSUBISHI STORAGE CARD ATA PC CARDS Primary(Secondary) I/O(Index=2, 3) REG# CE2# CE1# A9-A4 A3 A2 A1 A0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 1Fh(17h) 1Fh(17h) 1Fh(17h) 1Fh(17h) 1Fh(17h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 x 0 1 x 0 0 0 0 0 1 1 0 0 0 0 1 0 1Fh(17h) 1Fh(17h) 1Fh(17h) 1Fh(17h) 0 0 0 0 0 0 0 1 1 1 1 0 0 1 x 0 0 0 0 0 1 1 0 0 0 0 1 0 1Fh(17h) 1Fh(17h) 1Fh(17h) 1Fh(17h) 0 0 0 0 1 1 1 1 0 0 0 1 0 1 x 0 0 0 0 0 1 1 0 0 0 0 1 0 1Fh(17h) 1Fh(17h) 1Fh(17h) 3Fh(37h) 0 0 0 1 1 1 1 1 1 1 1 1 0 1 x 0 0 0 0 1 1 0 0 0 1 3Fh(37h) 3Fh(37h) 3Fh(37h) 1 1 1 1 1 1 1 1 1 0 1 x Register IORD#=”L” Data Register(D15-D0) Data Register[Even, Odd](D7-D0) Error Register(D7-D0) Error Register(D15-D8) Sector Count Register(D7-D0) Sector Number Register(D15-D8) Sector Count Register(D7-D0) Sector Number Register(D7-D0) Sector Number Register(D15-D8) Cylinder Low Register(D7-D0) Cylinder High Register(D15-D8) Cylinder Low Register(D7-D0) Cylinder High Register(D7-D0) Cylinder High Register(D15-D8) Drive Head Register(D7-D0) Status Register(D15-D8) Drive Head Register(D7-D0) Status Register(D7-D0) Status Register(D15-D8) Alt. Status Register(D7-D0) Drive Address Register(D15-D8) Alt. Status Register(D7-D0) Drive Address Register(D7-D0) Drive Address Register(D15-D8) IOWR#=“L” Data Register(D15-D0) Data Register[Even, Odd](D7-D0) Feature Register(D7-D0) Feature Register(D15-D8) Sector Count Register(D7-D0) Sector Number Register(D15-D8) Sector Count Register(D7-D0) Sector Number Register(D7-D0) Sector Number Register(D15-D8) Cylinder Low Register(D7-D0) Cylinder High Register(D15-D8) Cylinder Low Register(D7-D0) Cylinder High Register(D7-D0) Cylinder High Register(D15-D8) Drive Head Register(D7-D0) Command Register(D15-D8) Drive Head Register(D7-D0) Command Register(D7-D0) Command Register(D15-D8) Device Control Register(D7-D0) invalid Device Control Register(D7-D0) invalid invalid IDE ATA Interface CS1# CS0# A2-A0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0h 1h 2h 3h 4h 5h 6h 7h 6h 7h Register IORD#=”L” IOWR#=“L” Data Register(D15-D0) Data Register(D15-D0) Error Register(D7-D0) Feature Register(D7-D0) Sector Count Register(D7-D0) Sector Count Register(D7-D0) Sector Number Register(D7-D0) Sector Number Register(D7-D0) Cylinder Low Register(D7-D0) Cylinder Low Register(D7-D0) Cylinder High Register(D7-D0) Cylinder High Register(D7-D0) Drive Head Register(D7-D0) Drive Head Register(D7-D0) Status Register(D7-D0) Command Register(D7-D0) Alt. Status Register(D7-D0) Device Control Register(D7-D0) Drive Address Register(D7-D0) invalid MITSUBISHI ELECTRIC 9 1997.Nov. Rev. 1.2 MITSUBISHI STORAGE CARD ATA PC CARDS Configuration Register Specifications Pin Replacement Register Configuration Option Register This register is used for providing the signal state of READY signal when the card configured I/O card interface. This register is used for the configuration of the card configuration status and for the issuing soft reset to the card. D7 SRESET D6 LevIREQ Name SRESET R/W R/W LevIREQ R/W Index R/W D5 D4 D3 D2 Index D1 D7 0 D6 0 D5 CREADY Description Setting this bit to “1”, places the card in the reset state. When the host returns this bit to “0”, the function shall enter the same unconfigured, reset state as the card does following a powerup and hardware reset. If this bit is set to “0”, card generates pulse mode interrupt. If this bit is set to “1”, card generates level mode interrupts. This bits is used for select operation mode of the card as follows. When Power on, Card Hard Reset and Soft reset, this data is “000000” for the purpose of Memory card interface recognition. Index: 0 -> Memory mapped 1 -> Contiguous I/O mapped 2 -> Primary I/O mapped 3 -> Secondary I/O mapped Name CREADY R/W R/W Name Changed R/W R/O SigChg R/W Iois8 R/W PwrDwn R/W Intr R/W D5 Iois8 D4 0 D3 0 D2 PwrDwn D1 Intr D2 1 D1 RREADY D0 0 RREADY R/W Description This bit is set to “1” when the RREADY bit changes state. This bit may also be written by the host. When read, this bit indicates READY pin states. When written, this bit acts as a mask for writing the CREADY bit. Socket and Copy Register This register is used for identification of the card from the other cards. Host can read and write this register. This register should be set by host before this card’s Configuration Option register set. D7 0 D6 D5 D4 Copy Number Name Copy Number R/W R/W Socket Number R/W This register is used for observing the card state. D6 SigChg D3 1 D0 Configuration and Status Register D7 Changed D4 0 D0 0 Description This bit indicates that CREADY bit on the Pin Replacement register is set to “1”. When Changed bit is set to “1”, STSCHG# pin is held “L” if the SigChg bit is “1” and the card is configured for the I/O interface. This bit is set or reset by the host for enabling and disabling the status change signal(STSCHG# pin). When the card is configured I/O card interface and this bit is set to “1”, STSCHG# pin is controlled by Changed bit. If this bit is set to “0”, STSCHG# pin is kept “H”. This card is always configured for both 8-bit and 16-bit I/O, so this bit is ignored. When this bit is set to “1”, the card enters Power Down mode. When this bit is reset to “0”, the host is requesting the card to enter the active mode. RREADY bit on Pin Replacement Register becomes BUSY when this bit is changed. RREADY will not become Ready until the power state requested has been entered. This card automatically powers down when it is idle, and powers back up when it receives a command. This bit represents the internal state of the interrupt request. This bit state is available whether I/O card interface has been configured or not. This signal remains true until the condition which caused the interrupt request has been serviced. If interrupts are disabled by the nIEN bit in the Device Control Register, this bit is a zero. D3 D2 D1 Socket Number D0 Description This bit indicates the drive number of the card for twin card configuration. And the host can select and drive one card by comparing the number in this field with the drive number of Drive Head Register. In the way, the host can perform the card’s master/slave organization. This field indicates to the card that it is located in the n’th socket. MITSUBISHI ELECTRIC 10 1997.Nov. Rev. 1.2 MITSUBISHI STORAGE CARD ATA PC CARDS CIS Information CIS informatoins are defined as follows. Offset 0000h 0002h Data 01h 03h 7 6 5 0004h D9h 0006h 0008h 000Ah 000Ch 000Eh 01h FFh 1Ch 05h 02h 0010h DFh 0012h 0014h 0016h 0018h 001Ah 01h FFh 1Ch 04h 02h 001Ch D9h Device Type 001Eh 0020h 0022h 0024h 0026h 0028h 002Ah 002Ch 002Eh 0030h 0032h 0034h 0036h 0038h 003Ah 003Ch 003Eh 0040h 0042h 0044h 0046h 0048h 004Ah 004Ch 004Eh 0050h 0052h 0054h 0056h 0058h 005Ah 005Ch 005Eh 0060h 0062h 0064h 0066h 0068h 01h FFh 18h 02h DFh 01h 20h 04h 1Ch 00h 01h 00h 15h 26h 04h 01h 4Dh 49h 54h 53h 55h 42h 49h 53h 48h 49h 20h 41h 54h 41h 20h 43h 41h 52h 44h 00h 4Dh 46h 1x 2K Marks end of Other Conditions Device Info CISTPL_JEDEC_C TPL_LINK JEDEC identifier for first device info entry. JEDEC identifiers for remaining device info entries. CISTPL_MANFID TPL_LINK PC Card manufacturer code Device Type EXT 2 WPS 1 0 Device Speed 1x Marks end of Device Info fields CISTPL_DEVICE_OC TPL_LINK Reserved Vcc Device Type EXT 4 3 CISTPL_DEVICE TPL_LINK WPS 2K MWAIT Device Speed 1x 2K Marks end of Other Conditions Device Info CISTPL_DEVICE_OC TPL_LINK Reserved Vcc WPS MWAIT Device Speed manufacturer information CISTPL_VERS_1 TPL_LINK TPLLV1_MAJOR TPLLV1_MINOR TPLLV1_INFO Description Common Memory device information Link to next tuple Device Type=Dh : Function specific WPS=1 : No WPS Device Speed=1 : 250ns 2kBytes of address space Other Conditions Device information Link to next tuple EXT=0, Vcc=5.0V, Wait is not used. Device Type=Dh : Function specific WPS=1 : No WPS Device Speed=250ns 2kbytes of address space Other Conditions Device information Link to next tuple EXT=0, Vcc=3.3V, Wait is not used. Device Type=Dh : Function specific WPS=1 : No WPS Device Speed=250ns 2kbytes of address space JEDEC Identifier Tuples Link to next tuple PC Card ATA with no Vpp require for any operation Manufacturer Identification Tuple Link to next tuple 001Ch 0001h Level 1 Version / Product Information Link to next tuple PCMCIA2.0 / JEIDA4.1 PCMCIA2.0 / JEIDA4.1 M I T S U B I S H I A T A C A R D M F MITSUBISHI ELECTRIC 11 1997.Nov. Rev. 1.2 MITSUBISHI STORAGE CARD ATA PC CARDS 006Ah 006Ch 006Eh 0070h 0072h 0074h 0076h 0078h 007Ah 007Ch 007Eh 0080h 0082h 0084h 0086h 0088h 008Ah 008Ch 30h 78h 78h 78h 78h 2Dh 30h 33h 41h 54h 58h 78h 00 FFh 21h 02h 04h 01h 0 x x x x 0 3 A T x x 008Eh 0090h 0092h 0094h 0096h 0098h 009Ah 009Ch 22h 02h 01h 01h 22h 03h 02h 04h 009Eh 0Fh 00A0h 00A2h 00A4h 1Ah 05h 01h 00A6h 00A8h 00AAh 00ACh 00AEh 00B0h 00B2h 03h 00h 02h 0Fh 1Bh 08h C0h RFU RFU I D 00B4h 40h W R 00B6h 00B8h 00BAh 00BCh 00BEh 00C0h 00C2h 00C4h 00C6h A1h 01h 55h 08h 00h 21h 1Bh 05h 00h M R X DI X RFU I D CISTPL_FUNCID TPL_LINK Card Function Code Reserved RFU RFU ROM CISTPL_FUNCE TPL_LINK Disk Function Extension Tuple Type Disk Interface Type CISTPL_FUNCE TPL_LINK Disk Function Extension Tuple Type D U S I E N P3 P2 V P1 CISTPL_CONF TPL_LINK RMS RFS MS B P0 RAS TPCC_LAST TPCC_RADR (lsb) TPCC_RADR (msb) RFU E S P C CISTPL_CFTABLE_ENTRY TPL_LINK Configuration Index P POST I Interface Type IR IO T P PI AI SI HV LV NV Mantissa Exponent Length in 256 bytes pages (lsb) Length in 256 bytes pages (msb) P RO A T CISTPL_CFTABLE_ENTRY TPL_LINK Configuration Index Marks end of chain. Function Identification Tuple Link to next tuple PC Card ATA(Fixed Disk) ROM=0 : No BIOS ROM POST=1: Configure card at power on Function Extension Tuple Link to next tuple Disk Interface Type PC Card ATA Interface Function Extension Tuple Link to next tuple Basic PC Card ATA Interface tuple V=0 : No Vpp Required S=1 : Silicon U=0 : ID Drive Mfg/SN not Unique D=0 : Single Drive on Card P0=1 : Sleep Mode Supported P1=1 : Standby Mode Supported P2=1 : Idle Mode Supported P3=1 : Drive Auto Power Control N=0 : No Configs exclude I/O port 3F7H/377H E=0 : Index bit is not emulated I=0 : IOIS16# use is Unspecified on Twin Card Configurations Configuration Tuple Link to next tuple RFS=0 : No Reserved Field RMS=0 : 1 Byte Register Mask RAS=1 : 2 Byte Config Base Address Last Index = 3 Configuration Registers are located at 200H in Reg Space First 4 Configuration Registers present Configuration Table Entry Tuple Link to next tuple Interface Byte Follows, Default Entry, Configuration Index = 0 Mem Interface; Bvd's and wProt not used; Ready active and Wait not used for memory cycles. Has Vcc, Mem Space and Misc Info Nominal Voltage Only Follows Vcc Nominal is 5 Volts Length of Mem Space is 2 KB Starts at 0 on card Power Down, Twin Card supported. Configuration Table Entry Tuple Link to next tuple No Interface Byte, Non Default Entry, MITSUBISHI ELECTRIC 12 1997.Nov. Rev. 1.2 MITSUBISHI STORAGE CARD ATA PC CARDS 00C8h 00CAh 00CCh 00CEh 00D0h 00D2h 00D4h 01h 01h B5h 1Eh 1Bh 0Ah C1h M R X MS I D IR IO T P PI AI SI HV LV NV Mantissa Exponent Extension CISTPL_CFTABLE_ENTRY TPL_LINK Configuration Index 00D6h 41h W R P 00D8h 00DAh 00DCh 00DEh 99h 01h 55h 64h M R X R 00E0h 00E2h 00E4h 00E6h 00E8h 00EAh 00ECh F0h FFh FFh 21h 1Bh 05h 01h S IRQ7 IRQ15 X P IRQ6 IRQ14 RFU I D 00EEh 00F0h 00F2h 00F4h 00F6h 00F8h 00FAh 01h 01h B5h 1Eh 1Bh 0Fh C2h M R X DI I D IR IO T P PI AI SI HV LV NV Mantissa Exponent Extension CISTPL_CFTABLE_ENTRY TPL_LINK Configuration Index 00FCh 41h W R P 00FEh 0100h 0102h 0104h 99h 01h 55h EAh M R X R 0106h 61h 0108h 010Ah 010Ch 010Eh 0110h 0112h 0114h F0h 01h 07h F6h 03h 01h EEh 0116h 0118h 011Ah 011Ch 011Eh 0120h 0122h 0124h 0126h 0128h 012Ah DI MS DI S MS MS DI S IR PI AI Mantissa E Interface Type IO SI T HV P LV NV Exponent IO AddrLines L M Level or Mask IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ13 IRQ12 IRQ11 IRQ10 IRQ9 P RO A T CISTPL_CFTABLE_ENTRY TPL_LINK Configuration Index B IR PI AI Mantissa E LS P 21h 1Bh 05h 02h X RFU I D 01h 01h B5h 1Eh 1Bh 0Fh C3h M R X DI IO SI T HV P LV NV Exponent IO AddrLines N Ranges First I/O Base Address (LSB) First I/O Base Address (MSB) First I/O Length minus 1 Second I/O Base Address (LSB) Second I/O Base Address (MSB) Second I/O Length minus 1 L M IRQ Level P MS D IRQ0 IRQ8 Interface Type AS S I B RO A CISTPL_CFTABLE_ENTRY TPL_LINK Configuration Index T IR IO T P PI AI SI HV LV NV Mantissa Exponent Extension CISTPL_CFTABLE_ENTRY TPL_LINK Configuration Index Configuration Index = 0 Has Vcc Info Nominal Voltage Only Follows Vcc Nominal is 3.3 Volts Configuration Table Entry Tuple Link to next tuple Interface Byte Follows, Default Entry, Configuration Index = 1 I/O Interface; Bvd's and wProt not used; Ready active and Wait not used for memory cycles. Has Vcc, I/O, IRQ and Misc Info Nominal Voltage Only Follows Vcc Nominal is 5 Volts I/O : Range=0, Bus16=1, Bus8=1, IO AddrLines=4 Share=1, Pulse=1, Level=1, Mask=1 IRQ Level to be routed 0 - 15 recommended. Power Down, Twin Card supported. Configuration Table Entry Tuple Link to next tuple No Interface Byte, Non Default Entry, Configuration Index = 1 Has Vcc Info Nominal Voltage Only Follows Vcc Nominal is 3.3 Volts Configuration Table Entry Tuple Link to next tuple Interface Byte Follows, Default Entry, Configuration Index = 2 I/O Interface; Bvd's and wProt not used; Ready active and Wait not used for memory cycles. Has Vcc, I/O, IRQ and Misc Info Nominal Voltage Only Follows Vcc Nominal is 5 Volts I/O : Range=1, Bus16=1, Bus8=1, IO AddrLines=10 Number of Address Ranges = 2 Address Size = 2 Length Size = 1 First I/O Base Address = 1F0h First I/O Range is 8 Byte Length Second I/O Base Address = 3F6h Second I/O Range is 2 Byte Length Share=1, Pulse=1, Level=1, Mask=0, IRQ14 is recommended. Power Down, Twin Card supported. Configuration Table Entry Tuple Link to next tuple No Interface Byte, Non Default Entry, Configuration Index = 2 Has Vcc Info Nominal Voltage Only Follows Vcc Nominal is 3.3 Volts Configuration Table Entry Tuple Link to next tuple Interface Byte Follows, Default Entry, MITSUBISHI ELECTRIC 13 1997.Nov. Rev. 1.2 MITSUBISHI STORAGE CARD ATA PC CARDS 012Ch 41h W 012Eh 0130h 0132h 0134h 99h 01h 55h EAh M R X R 0136h 61h 0138h 013Ah 013Ch 013Eh 0140h 0142h 0144h 70h 01h 07h 76h 03h 01h EEh 0146h 0148h 014Ah 014Ch 014Eh 0150h 0152h 0154h 0156h R P MS DI S B IR PI AI Mantissa E LS Interface Type IO SI T HV P LV NV Exponent IO AddrLines AS S P 21h 1Bh 05h 03h X RFU I D 01h 01h B5h 1Eh FFh M R X DI N Ranges First I/O Base Address (LSB) First I/O Base Address (MSB) First I/O Length minus 1 Second I/O Base Address (LSB) Second I/O Base Address (MSB) Second I/O Length minus 1 L M IRQ Level P MS RO A CISTPL_CFTABLE_ENTRY TPL_LINK Configuration Index IR IO PI AI SI Mantissa Extension CISTPL_END T HV T P LV NV Exponent Configuration Index = 3 I/O Interface; Bvd's and wProt not used; Ready active and Wait not used for memory cycles. Has Vcc, I/O, IRQ and Misc Info Nominal Voltage Only Follows Vcc Nominal is 5 Volts I/O : Range=1, Bus16=1, Bus8=1, IO AddrLines=10 Number of Address Ranges = 2 Address Size = 2 Length Size = 1 First I/O Base Address = 170h First I/O Range is 8 Byte Length Second I/O Base Address = 376h Second I/O Range is 2 Byte Length Share=1, Pulse=1, Level=1, Mask=0, IRQ14 is recommended. Power Down, Twin Card supported. Configuration Table Entry Tuple Link to next tuple No Interface Byte, Non Default Entry, Configuration Index = 3 Has Vcc Info Nominal Voltage Only Follows Vcc Nominal is 3.3 Volts End of List Tuple MITSUBISHI ELECTRIC 14 1997.Nov. Rev. 1.2 MITSUBISHI STORAGE CARD ATA PC CARDS ATA Register Specifications Sector Number Register This register is written by the host with the starting sector number to be used in the subsequent Cylinder-HeadSector command. After the command is complete, the host may read the final sector number from this register. When logical block addressing is used, this register is written by the host with bit7 to 0 of the starting logical block number and contains bit7 to 0 of the final logical block number after the command is complete. Data Register This register is a 16 bit register which is used to transfer data blocks between the card data buffer and the host. Data may be transferred by either a series of word accesses to the Data register or a series of byte accesses to the Data register. D15 D7 D14 D6 D13 D12 D11 Data Word Odd Data Byte D10 D4 D3 Data Word Data Byte D2 D5 D9 D8 D7 D1 D0 Field BBK UNC IDNF ABRT AMNF D5 0 D4 IDNF D3 0 D2 ABRT D1 0 D0 AMNF function This bit is set when a Bad Block is detected in requested ID field. Host can not read/write on data area that is marked as a Bad Block. This bit is set when Uncorrectable error is occurred at reading the card. The requested sector ID is in error or cannot be found. This bit is set if the command has been aborted because of the card status condition. (Not ready, Write fault, etc.) or when an invalid command has been issued. This bit is set in case of a general error. Feature Register This register is written by the host to provide command specific information to the drive regarding features of the drive which the host wish to utilize. The Feature register is a write only register. D7 D6 D5 D4 D3 Feature byte D2 D1 D0 D5 D4 D3 Sector Count D0 D6 D5 D4 D3 D2 D1 Cylinder Low Byte Logical Block Number bits A15-A08(LBA Addressing) D0 Cylinder High Register This register is written by the host with the high-order byte of the starting cylinder address to be used in the subsequent Cylinder-Head-Sector command. After the command is complete, the host may read the high-order byte of the final cylinder number from this register. When logical block addressing is used, this register is written by the host with bits 23 to 16 of the starting logical block number and contains bits23 to 16 of the final logical block number after the command is complete. D6 D5 D4 D3 D2 D1 Cylinder High Byte Logical Block Number bits A23-A16(LBA Addressing) D0 Drive/Head Register The Drive/Head register is used to specify the selected drive of a pair of drives sharing a set of registers. This register is written by the host with the number of sectors or blocks to be processed in the subsequent command. After the command is complete, the host may read this register to obtain the count of sectors left unprocessed by the command. D6 D7 D7 Sector Count Register D7 D4 D3 D2 D1 Sector Number Logical Block Number bits A07-A00(LBA Addressing) This register is written by the host with the low-order byte of the starting cylinder address to be used in the subsequent Cylinder-Head-Sector command. After the command is complete, the host may read the low-order byte of the final cylinder number from this register. When logical block addressing is used, this register is written by the host with bits15 to 8 of the starting logical block number and contains bits15 to 8 of the final logical block number after the command complete. This register contains additional information about the source of an error which has occurred in processing of the preceding command. This register should be checked by the host when ERR bit in the Status register is set. The Error register is a read only register. D6 UNC D5 Cylinder Low Register Error Register D7 BBK D6 D2 D1 D7 X D6 LBA Field X LBA D0 DRV D5 X D4 DRV D3 HS3 LBA27 D2 HS2 LBA26 D1 HS1 LBA25 D0 HS0 LBA24 function Undefined . “0” or “1”. This bit is “0” for CHS addressing and “1” for Logical Block addressing. This bit is number of the drive which the host has selected. When DRV is cleared, Drive0 is selected. When DRV is set, Drive1 is selected. The card is selected to be Drive0 or to be Drive1 using the “Copy” field of the PC Card Socket Copy Register. MITSUBISHI ELECTRIC 15 1997.Nov. Rev. 1.2 MITSUBISHI STORAGE CARD ATA PC CARDS HS3-0 LBA27-24 HS3-0 of the head number in CHS addressing or LBA2724 of the Logical Block Number in LBA addressing. D7 X D6 nWTG D5 D4 D3 nHS3-0 D2 D1 nDS1 D0 nDS0 Status and Alternate Status Registers The Status register and the Alternate Status register return the card status when read by the host. Reading the Status register clears a pending interrupt request while reading the Alternate Status register does not. The Status register and the Alternate Status register are read only registers. Field X nWTG nHS3-0 nDS1 D7 BSY D6 DRDY Field BSY D5 DWF D4 DSC D3 DRQ D2 CORR D1 IDX D0 ERR nDS0 function This bit is unknown. This bit is set to “0” when a Flash write operation is in progress, otherwise it is set to “1”. These bits is the negative value of Head Select bits in Drive/Head register. This bit is set to “0” when Slave drive is active and selected. This bit is set to “0” when Master drive is active and selected. function This bit is set when the card internal operation is executing. When this bit is set to “1”, other bits in this register are invalid. DRDY indicates whether the card is capable of performing card operations. This bit, if set, indicates a write fault has occurred. This bit is set when the drive seek complete. This bit is set when the information can be transferred between the host and Data register. This bit is set when a correctable data error has been occurred and the data has been corrected. This bit is always set to “0”. This bit is set when the previous command has ended in some type of error. The error information is set in the other Status register bits or Error register. This bit is cleared by the next command. DRDY DWF DSC DRQ CORR IDX ERR Command Register The Command register contains the command code being sent to the device. Command execution begins immediately after this register is written. The Command register is a write only register. D7 D6 D5 D4 D3 Command D2 D1 D0 Device Control Register This register is used to control the card interrupt request and to issue a soft reset to the card. The Device Control register is a write only register. D7 X Field X 1 SRST nIEN 0 D6 X D5 X D4 X D3 1 D2 SRST D1 nIEN D0 0 function don’t care. This bit is set to “1”. This bit is set to “1” in order to force the card to perform a Command Block Reset operation. This does not change the Card Configuration registers as a Hardware Reset does. The card remains in Reset until this bit is reset to “0”. This bit is used for enabling IREQ#. When this bit is set to “0”, IREQ# is enabled. When this bit is set to “1”, IREQ# is disabled. This bit is set to “0”. Drive Address Register This register is provided for compatibility with the AT disk drive interface. MITSUBISHI ELECTRIC 16 1997.Nov. Rev. 1.2 MITSUBISHI STORAGE CARD ATA PC CARDS ATA Command Specifications This table summarizes the ATA command set with the paragraphs. Following shows the support commands and command codes which are written in command registers. Command Check Power Mode Execute Drive Diagnostic Erase Sector(s) Format Track Identify Drive Idle Idle Immediate Initialize Drive Parameters Read Buffer Read Long Sector Read Multiple Read Sector(s) Read Verify Sector(s) Recalibrate Request Sense Seek Set Features Set Multiple mode Set Sleep Mode Standby Standby Immediate Wear Level Write Buffer Write Long Sector Write Multiple Write Multiple without Erase Write Sector(s) Write Sector without Erase Write Verify FR : Feature Register, SN : Sector Number Register, DR Drive bit of Drive/Head Register, Code 98h, E5h 90h C0h 50h ECh 97h, E3h 95h, E1h 91h E4h 22h, 23h C4h 20h, 21h 40h, 41h 1xh 03h 7xh EFh C6h 99h, E6h 96h, E2h 94h, E0h F5h E8h 32h, 33h C5h CDh 30h, 31h 38h 3Ch FR SC SN CY y y y y y y y y y y y y y y y y y y y y y y y DR y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y SC : Sector Count Register, CY : Cylinder Low/High Register, HD : Head No. of Drive/Head Register, HD y y y y y y y y y y y y y y MITSUBISHI ELECTRIC 17 1997.Nov. Rev. 1.2 MITSUBISHI STORAGE CARD ATA PC CARDS Check Power Mode(98h, E5h) This command checks the power mode. Read Verify Sector(s)(40h, 41h) Execute Drive Diagnostic(90h) This command is identical to the Read Sector(s) command, except that DRQ is not asserted, and no data is transferred to the host. This command performs the internal diagnostic tests implemented by the card. Recalibrate(1xh) Erase Sector(s)(C0h) This command is used to pre-erase and condition data sectors in advance of a Write without Erase or Write Multiple without Erase command. Although this command is supported for backward compatibility, it has no actual function. The card will always return good status at the completion of this command. Format Track(50h) Request Sense(03h) This command writes the desired head and cylinder of the selected drive with a FFh pattern. This command requests extended error information for the previous command. Identify Drive(ECh) Seek(7xh) This command enables the host to receive parameter information from the card. (Refer to the Identify Drive Information table.) This command is supported for backward compatibility. Although this command has no actual function, it does perform a range check of valid track, and posts an IDNF error if the Head or Cylinder specified are out of bounds. Idle(97h, E3h) Set Features(EFh) This command causes the card to set BSY, enter the Idle mode, clear BSY and generate an interrupt. If the sector count is non-zero, the automatic power down mode is enabled. If the sector count is zero, the automatic power down mode is disabled. This command is used by the host to establish or select certain features. Set Multiple Mode(C6h) This command causes the card to set BSY, enter the idle mode, clear BSY and generate an interrupt. This command enables the card to perform Read and Write Multiple operations and establishes the block count for these commands. This card supports 1 sector block size. Initialize Drive Parameters(91h) Set Sleep Mode(E6h, 99h) This command allows the host to alter the number of sectors per track and the number of heads per cylinder. This command causes the card to set BSY, enter the Sleep mode, clear BSY and generate an interrupt. Read Buffer(E4h) Standby(96h, E2h) This command enables the host to read the current contents of the card’s sector buffer. This command causes the card to set BSY, enter the Standby mode, clear BSY and generate an interrupt. Read Long Sector(22h, 23h) Standby Immediate(94h, E0h) This command is similar to the Read Sector(s) command except the contents of the Sector Count register are ignored and only one sector is read. The 512 data bytes and 4 ECC bytes are read into the buffer(with no ECC correction) and then transferred to the host. This command causes the card to set BSY, enter the Standby mode, clear BSY and generate an interrupt. Idle Immediate(95h, E1h) Wear Leveling(F5h) Although this command is supported for backward compatibility, it has no actual function. The card will always return good status at the completion of this command. Read Multiple(C4h) This command performs similarly to the Read Sector(s) command. Interrupt are not generated on each sector, but on the transfer of a block which contains the number of sectors defined by a Set Multiple command. Write Buffer(E8h) This command enables the host to overwrite contents of the card’s sector buffer with any data pattern desired. This command has the same protocol as the Write Sector(s) command and transfers 512 bytes. Read Sector(s)(20h, 21h) This command transfers data from the card to the host. Data transfer starts at the sector specified by the Cylinder, Head, and Sector Number registers, and proceeds for the number of sectors specified in the Sector Count register. Write Long Sector(32h, 33h) This command is similar to the Write Sector(s) except the contents of the Sector Count register are ignored and only MITSUBISHI ELECTRIC 18 1997.Nov. Rev. 1.2 MITSUBISHI STORAGE CARD ATA PC CARDS one sector is written. The 512 data bytes and 4 ECC bytes are transferred from the host and then written from the buffer to the flash. Write Multiple(C5h) This command is similar to the Write Sector(s) command. Interrupts are not presented on each sector, but on the transfer of a block which contains the number of sectors defined by Set Multiple command. Write Sector(s)(30h, 31h) This command transfers data from the host to the card. Data transfer starts at the sector specified by the Cylinder, Head, and Sector Number registers, and proceeds for the number of sectors specified in the Sector Count register. Write Verify(3Ch) This command is similar to the Write Sector(s) command, except each sector is verified immediately after being written. MITSUBISHI ELECTRIC 19 1997.Nov. Rev. 1.2 MITSUBISHI STORAGE CARD ATA PC CARDS Identify Drive Information Word Address 0 Data 848Ah 1 2 3 4 5 6 7-8 9 10-19 20 21 22 23-26 27-46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62-255 xxxxh 0000h 000xh 4000h 0200h 0020h xxxxh, xxxxh 0000h 2020h 0001h 0001h 0004h xxxxh xxxxh 0001h 0000h 0200h 0000h 0100h 0000h 0001h xxxxh xxxxh xxxxh xxxxh 0000h 010xh xxxxh xxxxh 0000h Description General configuration bit-significant information 15 1 Non-rotating disk drive 14 0 Format speed tolerance gap not required 13 0 Track offset option not available 12 0 Data strobe offset option not available 11 0 Rotational speed tolerance is < 0.5% 10 1 Disk transfer rate > 10Mbs 9 0 10Mbs <= Disk transfer rate > 5Mbs 8 0 Disk transfer rate <= 5Mbs 7 1 Removable cartridge drive 6 0 Not a fixed drive 5 0 Spindle motor control option not implemented 4 0 Head switch time > 15us 3 1 Not MFM encoded 2 0 Not soft sectored 1 1 Hard sectored 0 0 Reserved Number of Cylinders Reserved Number of Heads Number of unformatted bytes per track Number of unformatted bytes per sector Number of sectors per track Number of sectors per card (word 7 = MSW, word 8 = LSW) Reserved Reserved Buffer type: Single ported, single-sector, w/read cache Buffer size, in 512 byte increments ECC length used on Read and Write Long command Firmware revision, 8 ASCII chars Model number, 40 ASCII chars. Maximum Block Count=1 for Read/write Multiple commands Cannot perform doubleword I/O Capabilities: LBA supported, DMA not supported Reserved PIO timing cycle timing mode 1 DMA transfer not supported Words 54-58 are valid Number of Current Cylinders Number of Current Heads Number of Current Sectors per Track LSW of the Current Capacity in Sectors MSW of the Current Capacity in Sectors Current Setting for Block Count for R/W Multiple commands LSW of the total number of user addressable LBA mode MSW of the total number of user addressable LBA mode Reserved MITSUBISHI ELECTRIC 20 1997.Nov. Rev. 1.2 MITSUBISHI STORAGE CARD ATA PC CARDS ABSOLUTE MAXIMUM RATINGS Symbol VCC Vi Vo Pd Topr Tstg Parameter Supply voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions Ratings -0.3~7.0 -0.3~VCC+0.3 -0.3~VCC+0.3 1.2 0~60 -10~80 With respect to GND Ta = 25 °C Unit V V V W °C °C RECOMMENDED OPERATING CONDITIONS Parameter Symbol VCC(5V) VCC(3.3V) GND VIH VIL Limits Typ. 5.0 3.3 0 Min. 4.5 3.135 VCC Supply voltage VCC Supply voltage System ground High input voltage Low input voltage 0.7VCC 0 Unit Max. 5.5 3.465 V V V V V VCC 0.8 DC ELECTRICAL CHARACTERISTICS (Ta=0~60°C, VCC=5V±10% or VCC=3.3V±5%, unless otherwise noted) Symbol VOH VOL IOZ ICCR ICCW ICCS Parameter High output voltage Low output voltage Output current in off state Active supply current (Read) Active supply current (Write) Standby current (Auto power down) Test Condition IOH=2.0mA (3.135V) 4.0mA (4.5V) IOL=-4.0mA (3.465V) -7.0mA (5.5V) READY, INPACK#, BVD1, BVD2 the other outputs READY, INPACK#, BVD1, BVD2 the other outputs CE1# = CE2# = VIH D15-D0 IOH=3.5mA (3.135V) 7.0mA (4.5V) IOL=-2.5mA (3.465V) -4.0mA (5.5V) Output open CE1# = CE2# = VIH Min. 3.135V 4.5V Limits Typ. Max. 3.465V 5.5V Unit 0.8 VCC - V - 0.4 V - ±5 µA 70 mA 100 mA 5 mA MITSUBISHI ELECTRIC 21 1997.Nov. Rev. 1.2 MITSUBISHI STORAGE CARD ATA PC CARDS Symbol IIH Parameter High input current Test Condition VIN=VCC VIN=GND IIL Low input current PC card mode VIN=GND IDE mode CE1#,CE2#, OE#,WE#, IORD#,IOWR#, REG#, CSEL,RESET, D15-D0, A10-A0 BVD1,BVD2 CE1#,CE2#, OE#,WE#, REG#, IORD#,IOWR# RESET A10-A0, CSEL D15-D0 CE1#,CE2#, IORD#,IOWR#, A10-A0,RESET D15-D0 OE#,WE#, REG#, BVD1,BVD2 CSEL Min. 3.135V 4.5V Limits Typ. Max. 3.465V 5.5V Unit -1 1 µA -5 5 -14 -7 -20 -90 -10 -45 -140 -70 -1 -5 1 5 -1 1 -5 µA 5 -14 -20 -90 -140 -7 -10 -45 -70 CAPACITANCE Symbol Parameter Test conditions CI Input capacitance V I =GND, Vi=25mVrms, f=1 MH Z , T a = 2 5 ° C CO Output capacitance V O =GND, Vo=25mVrms, f=1 MH Z , T a = 2 5 ° C Note : These parameters are not 100% tested. Min. Limits T y p . Max. 45 45 Unit pF MITSUBISHI ELECTRIC 22 1997.Nov. Rev. 1.2 MITSUBISHI STORAGE CARD ATA PC CARDS AC ELECTRICAL CHARACTERISTICS MEMORY TIMING Read Cycle[Attribute] (Ta=0~60°C, VCC=5V±10% or VCC=3.3V±5% unless otherwise noted) Parameter Symbol Min. Limits Typ. Max. 300 Unit tCR Read cycle time ta(A) Address access time 300 ns ns ta(CE) Card enable access time 300 ns ta(OE) Output enable access time 150 ns tdis(CE) Output disable time (from CE) 100 ns tdis(OE) Output disable time (from OE) 100 ns ten(CE) Output enable time (from CE) 5 ns ten(OE) Output enable time (from OE) 5 ns tV(A) Data valid time (after address change) 0 ns Read Cycle[Common] (Ta=0~60°C, VCC=5V±10% or VCC=3.3V±5% unless otherwise noted) Symbol tCR ta(A) ta(CE) ta(OE) tdis(CE) tdis(OE) ten(CE) ten(OE) tV(A) Parameter Min. Read cycle time Address access time Card enable access time Output enable access time Output disable time (from CE) Output disable time (from OE) Output enable time (from CE) Output enable time (from OE) Data valid time after address change Limits Typ. Max. 250 250 250 125 100 100 5 5 0 Unit ns ns ns ns ns ns ns ns ns MITSUBISHI ELECTRIC 23 1997.Nov. Rev. 1.2 MITSUBISHI STORAGE CARD ATA PC CARDS Write Cycle[Attribute and Common] (Ta=0~60°C, VCC=5V±10% or VCC=3.3V±5% unless otherwise noted) Symbol tCW tw(WE) tsu(A) tsu(A-WEH) tsu(CE-WEH) tsu(D-WEH) th(D) trec(WE) tdis(WE) tdis(OE) ten(WE) ten(OE) tsu(OE-WE) th(OE-WE) Parameter Min. Write cycle time Write pulse width Address setup time Address setup time with respect to WE high Card enable setup time with respect to WE high Data setup time with respect to WE high Data hold time Write recovery time Output disable time (from WE) Output disable time (from OE) Output enable time (from WE) Output enable time (from OE) OE set up time with respect to WE low OE hold time with respect to WE high Limits Typ. Max. 250 150 30 180 180 80 30 30 100 100 5 5 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns MITSUBISHI ELECTRIC 24 1997.Nov. Rev. 1.2 MITSUBISHI STORAGE CARD ATA PC CARDS MEMORY TIMING DIAGRAM Read Cycle tCR VIH An, REG# VIL ta(A) ta(CE) VIH tV(A) CE# VIL tdis(CE) ten(CE) ta(OE) VIH OE# VIL ten(OE) VOH Dm (DOUT) VOL Hi-Z tdis(OE) OUTPUT VALID WE#=“H” level Note 5 : Indicates the don’t care input Write Cycle tCW VIH An, REG# VIL tSU(CE-WEH) VIH CE# VIL tSU(A-WEH) VIH OE# VIL tW(WE) tSU(A) trec(WE) VIH WE# VIL tSU(OE-WE) Dm (DIN) tSU(D-WEH) VIH Hi-Z th(D) th(OE-WE) DATA INPUT STABLE VIL tdis(WE) tdis(OE) VOH Dm (DOUT) VOL Hi-Z ten(OE) ten(WE) MITSUBISHI ELECTRIC 25 1997.Nov. Rev. 1.2 MITSUBISHI STORAGE CARD ATA PC CARDS I/O READ (INPUT) TIMING Limit Symbol Parameter Min t d (IORD) Data Delay after I O R D # t h (IORD) Data Hold following I O R D # 0 t w IORD I O R D # Width Time 165 t s u A(IORD) Address Setup before IORD# 70 t h A(IORD) Address Hold following I O R D # 20 t s u CE(IORD) CE# Setup before IORD# 5 th CE(IORD) C E # Hold following I O R D # 20 t s u REG(IORD) REG# Setup before IORD# 5 t h REG(IORD) R E G # Hold following I O R D # 0 t d f INPACK(IORD) I N P A C K # Delay Falling from I O R D # 0 t d r INPACK(IORD) I N P A C K # Delay Rising from I O R D # t d f IOIS16(ADR) I O I S 1 6 # Delay Falling from Address t d r IOIS16(ADR) I O I S 1 6 # Delay Rising from Address tdf WT(IORD) W A I T # Delay Falling from I O R D # tdr(WT) Data Delay from W A I T # Rising tw(WT) W A I T # Width Time The maximum load on WAIT#, INPACK# and IOIS16# are 1 LSTTL with 50 pF total load. Max 100 45 45 35 35 35 0 350 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns I/O WRITE (OUTPUT) TIMING Limit Symbol Parameter Min td(IOWR) Data Setup before I O W R # 60 th(IOWR) Data Hold following I O W R # 30 twIOWR I O W R # Width Time 165 t s u A((IOWR) Address Setup before IOWR# 70 t h A((IOWR) Address Hold following I O W R # 20 t s u CE((IOWR) CE# Setup before IOWR# 5 th CE((IOWR) C E # Hold following I O W R # 20 tsu REG(IOWR) REG# Setup before IOWR# 5 th REG((IOWR) R E G # Hold following I O W R # 0 t d f IOIS16(ADR) I O I S 1 6 # Delay Falling from Address r d r IOIS16(ADR) I O I S 1 6 # Delay Rising from Address tdf WT(IOWR) W A I T # Delay Falling from I O W R # tw(WT) W A I T # Width Time tdr IOWR(WT) I O W R # high from W A I T # High 0 The maximum load on WAIT#, INPACK# and IOIS16# are 1 LSTTL with 50 pF total load. Max 35 35 35 350 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns MITSUBISHI ELECTRIC 26 1997.Nov. Rev. 1.2 MITSUBISHI STORAGE CARD ATA PC CARDS I/O READ (INPUT) TIMING DIAGRAM A[10::0] th A(IORD) tsu REG(IORD) th REG(IORD) tsu CE(IORD) th CE(IODR) REG# CE# tw(IORD) IORD# tdr INPACK(ADR) tsu A(IODR) INPACK# tdf INPACK(IORD) tdr IOIS16(ADR) IOIS16# tdf IOIS16(ADR) td (IORD) tdr(WT) WAIT# tdf WT(IORD) tw(WT) th (IORD) D[15::0] MITSUBISHI ELECTRIC 27 1997.Nov. Rev. 1.2 MITSUBISHI STORAGE CARD ATA PC CARDS I/O WRITE (OUTPUT) TIMING DIAGRAM A[10::0] th A(IOWR) tsu REG(IOWR) th REG(IOWR) tsu CE(IOWR) th CE(IOWR) REG# CE# tw(IOWR) IOWR# tsu A(IOWR) tdr IOIS16(ADR) IOIS16# tdf IOIS16(ADR) tdf WT(IOWR) tdr IOWR(WT) WAIT# tw(WT) th (IOWR) D[15::0] tsu(IOWR) MITSUBISHI ELECTRIC 28 1997.Nov. Rev. 1.2 MITSUBISHI STORAGE CARD ATA PC CARDS RECOMMENDED POWER UP/DOWN CONDITIONS (Ta=0~60°C, unless otherwise noted) Symbol Parameter Vi(CE) CE input voltage tsu(Vcc) t s u (RESET) trec(Vcc) tpr CE setup time RESET setup time CE recover time Vcc rising time tpf V C C falling time tw(RESET) th(Hi-zRESET) ts(Hi-zRESET) RESET width Conditions Min. 0 V C C -0.1 V IH 20 20 1 0.1 0V≤ V C C <2V 2V≤ V C C <V IH V IH ≤ V C C 10%à90% of Vcc 90% of Vccà10% 3 Limits Typ. VC C Max. VC C V C C +0.1 V C C +0.1 Unit 100 V V V ms ms µs ms 300 ms 10 1 0 µs ms ms POWER UP/DOWN TIMING DIAGRAM tsu(VCC) tpr VCC VCC @ 90% tsu(RESET) tsu (RESET) VIH VCC @ 10% 2V CE1#, CE2# th (Hi-z RESET) tw (RESET) Hi-z RESET tw (RESET) tpf VCC VCC @ 90% trec(VCC) VIH 2V VCC @ 10% CE1#, CE2# ts(Hi-z RESET) RESET Hi-z MITSUBISHI ELECTRIC 29 1997.Nov. Rev. 1.2