ETC2 N572F065 32-bit multi-algorithm voice processor Datasheet

N572F065
Data Sheet
32-BIT MULTI-ALGORITHM VOICE PROCESSOR
(NuVoice™)
Release Date: Jan 2012
Version 1.7
-1-
N572F065 Data Sheet
Table of Content
1.
General Description ......................................................................................................3
2.
Features .........................................................................................................................3
3.
Functional Block Diagram ............................................................................................6
4.
Pin Configuration ..........................................................................................................7
4.1 Pin Diagram.................................................................................................................7
4.2 Pad Description ...........................................................................................................8
4.3 Alternate Function List of GPIO .................................................................................10
5.
Typical Application Circuit .........................................................................................12
5.1 Recording and Playback............................................................................................12
5.2 Dual microphones for sound direction detection and motor control ...........................13
5.3 USB updateable program and data ...........................................................................14
6.
Software and Development Environment .................................................................14
7.
DC Electrical Characteristics .....................................................................................15
7.1 DC Electrical Characteristics .....................................................................................15
7.2 AC Electrical Characteristics .....................................................................................16
7.2.1 Internal 24MHz RC Oscillator ........................................................................................ 16
7.3 Analog Characteristics ..............................................................................................16
7.3.1 12-bit SAR ADC ............................................................................................................. 16
7.3.2 Voice Recorder .............................................................................................................. 17
7.3.3 2.4V LDO for Internal Core ............................................................................................ 17
7.3.4 Voutx for External Driving .............................................................................................. 17
7.3.5 Low Voltage Reset ......................................................................................................... 18
7.3.6 Voltage Detector ............................................................................................................ 18
7.3.7 Power-On Reset (5V) ..................................................................................................... 18
7.3.8 Power Amplifier and DAC .............................................................................................. 18
7.3.9 PLL ................................................................................................................................. 19
7.3.10 USB PHY ....................................................................................................................... 19
8.
Package Information...................................................................................................21
9.
Ordering Information ..................................................................................................22
10. Revision History..........................................................................................................22
Release Date: Jan 2012
Version 1.7
-2-
N572F065 Data Sheet
1. General Description
The N572 is the first Cortex™-M0 based processor for voice process applications, running up
to 48MHz and equipped with 64KB flash and 8KB SRAM for high performance process of audio
and voice algorithms. Integrating rich analog peripherals, like pre-amplifier, ADC, DAC, hardware
mixer, and PA, this chip saves a lot of system design effort and cost. An USB device and flash
work together to provide updatable content and scenario downloaded from internet via a PC.
To utilize the high performance M0 and high density of SRAM, advanced algorithms are
designed, optimized, and tested in N572 chip. These algorithms include watermark, voice
changer, NuSound, NuOne, beat detection, and more in developing. In additional to algorithms
developed by ourselves, Nuvoton also seeks third parties for more interesting software to enrich
the applications on N572. Additionally, the new designed NVIC in M0, the latency of interrupt and
response to external events are faster. Multiple algorithms could be run together smoothly and
naturally.
The development tools are based on Keil™ MDK using C/C++ for programming language.
This is a robust and easy to use environment for development and debug.
Following is table of Part No. of N572F065:
Part No.
N572F065
Program
64KB Flash
SRAM
8KB
CPU freq
48MHz
USB
FS/12Mbps
2. Features

Core
– ARM® Cortex™-M0 core runs up to 48MHz
– Support low power sleep mode
– Single-cycle 32-bit hardware multiplier
– NVIC for the 16 interrupt inputs, each with 4-levels of priority
– Serial Wire Debug supports with 2 watchpoints/4 breakpoints

Widely operating voltage range from 2.4V to 5.5V

Flash EPROM Memory
– 64KB Flash EPROM
– Support ISP for Flash update
– 512 bytes page erase for Flash
– Support 2-wire ICP update from ICE interface
– Support fast parallel programming mode by external programmer
– Security Lock preventing content in Flash access from external interface

SRAM Memory
– 8KB embedded SRAM

Clock Control
– Flexible selection for different applications
Release Date: Jan 2012
Version 1.7
-3-
N572F065 Data Sheet
–
–
–
–
Support PLL, up to 48MHz, for high performance system operation
External 12MHz(or 6MHz) crystal input for USB and precise timing operating mode
External 32KHz crystal input for RTC function and system clock
Internal 24MHz RC oscillator

GPIO
– Four I/O modes:

Quasi bi-direction

Push-Pull output

Open-Drain output

Input only with high impendence
– TTL/Schmitt trigger input selectable
– I/O pin can be configured as interrupt source with edge/level setting
– High driver and high sink IO mode support

Timers
– 3 sets of the timer with 8-bit pre-scaler and 16-bit timer.
– Counter auto reload.
– IR carrier generator
– One fixed frequency timer

Watch Dog Timer
– Default ON/OFF by configuration setting
– Multiple clock sources
– 8 selectable time out period from 6ms ~ 3.0sec (depends on clock source)
– Able to wake up power down/sleep
– Interrupt or reset selectable on watchdog time-out

RTC
– Support time out interrupt
– Support wake up function

PWM/Capture/Compare Timer
– one 16-bit timer and four 16-bit comparators
– Four clock selectors
– One 8-bit pre-scaler and one clock divider
– Two Dead-Zone generators
– Programmable duty control of output waveform
– Auto reload mode or one-shot pulse mode
– Capture and compare function

SPI
– Two sets of SPI device
– Master mode up to 24MHz on system runs on 48MHz
– Support MICROWIRE/SPI master mode (SSP)
– Full duplex synchronous serial data transfer
– Variable length of transfer data from 1 to 32 bits
– MSB or LSB first data transfer
– Rx and Tx on both rising or falling edge of serial clock independently
– 2 slave/device select lines
– Two 32-bit buffers

USB 2.0 Full-Speed Device
– One set of USB 2.0 FS Device 12Mbps
– On-chip USB Transceiver
Release Date: Jan 2012
Version 1.7
-4-
N572F065 Data Sheet
–
–
–
–
–
–
Provide 1 interrupt source with 4 interrupt events
Support Control, Bulk In/Out, Interrupt and Isochronous transfers
Auto suspend function when no bus signaling for 3 ms
Provide 6 programmable endpoints
Include 512 Bytes internal SRAM as USB buffer
Provide remote wakeup capability

ADC
– 8-ch 12-bit with 200Ksps
– Single scan/single cycle scan/continuous scan
– 8 channels share 8 result registers
– Programmable channel scan sequence
– Threshold voltage detection
– Conversion start by S/W, external pins
– Programmable gain control for sound record

APU
– 13-bit DAC
– H/W mixer with 2 channel PCM input
– Embedded power amplifier
– 7-level volume control

Voltage detector
– with 2 levels: 3.0V/2.7V

LDO
– Built-in 2.4V LDO for internal core
– Built-in 3.3V LDO for USB

Voltage Output
– Built-in power supply Voutx for driving external spi-flash

Low Voltage Reset

Operating Temperature: -20℃~85℃

Packages:
– All Green package (RoHS)
– 7mmx7mm LQFP 64-pin
Release Date: Jan 2012
Version 1.7
-5-
N572F065 Data Sheet
3. Functional Block Diagram
CLK_CTL
24MHz
Rosc
Ext. 32K X’tal
PLL
Cortex-M0
48MHz
Ext. 6M/12M X’tal
AHB
LDO 2.4V
Flash
64K Byte
SRAM
8KB
APB Bridge
GPIO
A,B
APB
ADC
LDO 3.3V
Voutx 3.0V
ADC, 8ch/12bit
@ 400ksps
PGC
RTC
APU
WDT
DAC ( 13-b)
Speaker PA
Timer_0,1,2,F
SPI 0,1 (Master)
POR/LVD/LVR
PWM Timer
PWM_0/C&C
PWM_1,2,3
USB F.S.
USB_PHY
Release Date: Jan 2012
Version 1.7
-6-
N572F065 Data Sheet
4. Pin Configuration
GPA8/ADC0
GPA9/ADC1
GPA10/ADC2
GPA11/ADC3
GPA12/ADC4
GPA13/ADC5
GPA14/ADC6
GPA15/ADC7
AVSS
ICE_CLK
ICE_DAT
VMID
SPKVSS1
SPK-
SPKVDD
SPK+
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
4.1 Pin Diagram
Vref
49
32
SPKVSS0
AVDD
50
31
GPB15/TM2
STADC/GPA7
51
30
GPB14/TM1
INT0/GPA6
52
29
GPB13/IROUT
TM0/GPA5
53
28
GPB12/CPR0
VSSIO2
54
27
GPB11/PWM3
VDDIO2
55
26
GPB10/PWM2
RSTB
56
N572F064 (without USB)
N572F065 (support USB)
25
GPB9/PWM1
24
GPB8/PWM0
23
LDO24
16
MOSI1/GPB4
15
MISO1/GPB3
Voutx
14
17
SPCK1/GPB2
64
13
DP
SSB10/GPB1
VDDIO4
12
18
SSB11/GPB0
63
11
VPP
VDDIO3
VSSIO4
10
19
VSSIO1
62
9
PLLC
VDDIO1
GPB5
8
20
SSB01/GPA0
61
7
PLVSS
SSB00/GPA1
GPB6
6
21
SPCK0/GPA2
60
5
X32O
MISO0/GPA3
GPB7
4
22
MOSI0/GPA4
59
3
X32I
VDDU
VPP(63) is for test only
2
58
LDO33U
XOUT
1
57
DM
XIN
DP/DM/LDO33U/VDDU (64/1/2/3) are for USB
Note1: VPP is for embedded flash test, keep it no connection in general application.
Release Date: Jan 2012
Version 1.7
-7-
N572F065 Data Sheet
4.2 Pad Description
Name
Type
Description
1. GPIO
GPA0
GPA15
~
I/O
Bidirectional general purpose I/O ports. Most of these pins have
alternate function, refer to section 4.3 for detail.
GPB0
GPB15
~
I/O
Bidirectional general purpose I/O ports. Most of these pins have
alternate function, refer to section 4.3 for detail.
X32I
I
32KHz crystal input
X32O
O
32KHz crystal output
XIN
I
6MHz or 12MHz crystal input
XOUT
O
6MHz or 12MHz crystal output
PLVSS
P
PLL ground
PLLC
A
Capacitor connection for built-in PLL1
DP
I/O
USB data pin, DP.
DM
I/O
USB data pin, DM.
LDO33U
P
3.3V LDO output for USB
VDDU
P
USB bus power supply, floating detect input
VDDA
P
Analog power supply
VSSA
P
Analog ground.
Vref
A
Reference voltage input
2. Oscillator
3. USB
4. ADC
5. Speaker Driver
SPK+/DAC
O
Speaker positive output pin, or current type DAC output.
SPK-
O
Speaker negative output pin.
SPKVDD
P
Analog power supply
SPKVSS1
P
Analog ground.
SPKVSS0
P
Analog ground.
VMID
A
Connect a capacitor to SPKVSS
Release Date: Jan 2012
Version 1.7
-8-
N572F065 Data Sheet
6. Power
VDDIO4
P
Power supply for I/O port, and source of LDO for logic circuit.
VSSIO4
P
Ground pin, connect to 0V.
VDDIO2
P
Power supply for I/O port, and source of oscillator.
VSSIO2
P
Ground pin, connect to 0V.
VDDIO1
P
Power supply for I/O port.
VSSIO1
P
Ground pin, connect to 0V.
VDDIO3
P
Power supply for I/O port.
LDO24
P
2.4V LDO output
Voutx
P
3.0V output for driving out
VPP
P
For embedded flash test, keep it no connection in general
application.
ICE_CLK
I
Serial Wired Debugger Clock pin
ICE_DAT
I/O
Serial Wired Debugger Data pin
I
Reset input pin, low active. Internal pull-high.
7. SWD
8. Other
RSTB
Release Date: Jan 2012
Version 1.7
-9-
N572F065 Data Sheet
4.3 Alternate Function List of GPIO
GPIO
Power
Alternate
I/O of
Alternate
Function Description
GPA0
VDDIO1
SSB01
O
SPI0 2nd chip select pin
GPA1
VDDIO1
SSB00
O
SPI0 1st chip select pin
GPA2
VDDIO1
SPCK0
O
SPI0 serial clock output
GPA3
VDDIO1
MISO0
I
SPI0 master data input
GPA4
VDDIO1
MOSI0
O
SPI0 master data output
GPA5
VDDIO2
TM0
I
Timer0 counter external input
GPA6
VDDIO2
INT0
I
External interrupt input pin
GPA7
VDDIO2
STADC
I
ADC external trigger input
GPA8
VDDIO2
ADC0
A
ADC analog input 0
GPA9
VDDIO2
ADC1
A
ADC analog input 1
GPA10
VDDIO2
ADC2
A
ADC analog input 2
GPA11
VDDIO2
ADC3
A
ADC analog input 3
GPA12
VDDIO2
ADC4
A
ADC analog input 4
GPA13
VDDIO2
ADC5
A
ADC analog input 5
GPA14
VDDIO2
ADC6
A
ADC analog input 6
GPA15
VDDIO2
ADC7
A
ADC analog input 7
GPB0
VDDIO3
SSB11
O
SPI1 2nd chip select pin
GPB1
VDDIO3
SSB10
O
SPI1 1st chip select pin
GPB2
VDDIO3
SPCK1
O
SPI1 serial clock output
GPB3
VDDIO3
MISO1
I
SPI1 master data input
GPB4
VDDIO3
MOSI1
O
SPI1 master data output
GPB5
VDDIO4
-
GPB6
VDDIO4
-
GPB7
VDDIO4
-
GPB8
VDDIO4
PWM0
O
PWM output pin 0
GPB9
VDDIO4
PWM1
O
PWM output pin 1
Release Date: Jan 2012
Version 1.7
- 10 -
N572F065 Data Sheet
GPB10
VDDIO4
PWM2
O
PWM output pin 2
GPB11
VDDIO4
PWM3
O
PWM output pin 3
GPB12
VDDIO4
CPR0
I
Capture input
GPB13
VDDIO4
IROUT
O
IR carrier output
GPB14
VDDIO4
TM1
I
Timer1 counter external input
GPB15
VDDIO4
TM2
I
Timer2 counter external input
I: Input, O: Output, A: Analog input
Release Date: Jan 2012
Version 1.7
- 11 -
N572F065 Data Sheet
5. Typical Application Circuit
5.1 Recording and Playback
10n
PLVSS
PLLC
22K
X32I
SPK+
SPK-
SPEAKER
20p
GPB4/MOSI1
GPB3/MISO1
GPB2/SPCK1
GPB1/SSB10
32.768K
X32O
20p
DI
DO
CLK
CS\
VDDIO3
Vbias
2
1
33n
0.47u
MICROPHONE
AVDD
0.1u
GPA9
2.2K
VBAT
Vref
GPA8
10
10
VSS
0.1u
SPKVSS0
SPKVSS1
2.2K
V30
SPI
FLASH
V30
SPKVDD
VDD
47u
0.47u
AVSS
VDDIO4
0.1u
FB
VSSIO4
VBAT
VDDIO2
0.1u
RSTB
FB
VSSIO2
VDDU
Voutx
LDO24
10u
VMID
RESET
47u
VDDIO1
LDO33U
0.1u
VSSIO1
FB
V30
0.1u
4.7u
4.7u
Release Date: Jan 2012
Version 1.7
- 12 -
FB
N572F065 Data Sheet
5.2 Dual microphones for sound direction detection and motor
control
VBAT
22K
10n
SPK+
SPEAKER
SPK-
LED X 8
20p
GPB0~7
32.768K
2.2K
1
X32O
20p
GPB8~11
2
1
GPA8
10
33n
SPKVDD
-
0.1u
SPKVSS0
SPKVSS1
GPA9
10
A
VBAT
0.47u
MICROPHONE
2.2K
+
Motor
Driver
0.47u
Vref
AVDD
Vbias
47u
0.1u
AVSS
2.2K
2
1
GPA10
10
33n
VDDIO4
0.47u
MICROPHONE
0.1u
GPA11
10
0.47u
VDDIO2
0.1u
VSSIO2
FB
RSTB
VDDIO1
VDDU
LDO33U
Voutx
10u
LDO24
RESET
VBAT
VDDIO3
VMID
2.2K
FB
VSSIO4
0.1u
FB
VSSIO1
47u
FB
0.1u
4.7u
FB
FB
Release Date: Jan 2012
Version 1.7
- 13 -
2
Vbias
PLLC
X32I
PLVSS
330
MOTOR
N572F065 Data Sheet
5.3 USB updateable program and data
22K
10n
Vbias
PLLC
XIN
PLVSS
VBAT
330
SPK+
SPEAKER
SPK-
20p
LED X 8
12M
2.2K
XOUT
GPB0~7
20p
2
1
GPA8
10
33n
SPKVDD
VBAT
0.47u
0.1u
SPKVSS0
MICROPHONE
GPA9
2.2K
10
SPKVSS1
0.47u
Vref
AVDD
47u
RESET
0.1u
AVSS
RSTB
10u
VDDIO4
0.1u
VSSIO4
USB
Interface
FB
VDDU
USB_5V
DM
DM
DP
VBAT
VDDIO2
VSSIO2
0.1u
DP
FB
GND
VDDIO3
0.1u
47u
Voutx
VMID
LDO33U
LDO24
VDDIO1
0.1u
VSSIO1
FB
0.1u
0.1u
4.7u
6. Software and Development Environment
The Keil™ MDK 4.0 (or above version) including IDE, compiler, linker, and debugger is for
your software development. Debug hardware requires Nu-Link™ and N572 EVB. A Nu-Link driver
is required to add views of peripherals and add-ons within MDK’s IDE. With software library, you
can development and debug in the MDK4.0 environment. Please refer to Programming Guide for
details.
Release Date: Jan 2012
Version 1.7
- 14 -
FB
N572F065 Data Sheet
7. DC Electrical Characteristics
7.1 DC Electrical Characteristics
PARAMETER
SYM
SPECIFICATION
MIN.
Operation voltage
TYP.
TEST CONDITIONS
MAX.
UNIT
5.5
V
VDD
2.4
VSS
AVSS
AVDD
-0.3
0
VDD
V
Analog Reference
Voltage
Vref
0
VDD
V
Operating Current at
Normal Run Mode
IDD1
50
mA
VDD=5.5V@48MHz, enable all IPs
IDD3
42
mA
VDD=3V@48MHz, enable all IPs
Operating Current at Idle
Mode
IIDLE2
17
mA
VDD=5.5V@48MHz, disable all IPs
IIDLE4
15
mA
VDD=3V@48MHz, disable all IP
Operating Current at
Power-down Mode
IPWD1
10
A
VDD = 5.5V, No load, disable LVD
IPWD2
9
A
VDD = 3.3V, No load, disable LVD
Power Ground
Analog Operating Voltage
V
IIN1
-60
-
+15
A
VDD = 5.5V, VIN = 0V or VIN=VDD
IIN2
-55
-45
-30
A
VDD = 5.5V, VIN = 0.45V
Input Leakage Current
GPA/GPB
ILK
-0.1
-
+0.1
A
VDD = 5.5V, 0<VIN<VDD
Input Low Voltage GPIO
(TTL input)
VIL1
-0.3
-
1.0
V
VDD = 4.5V
-0.3
-
0.6
Input High Voltage GPIO
(TTL input)
VIH1
2.2
-
VDD +0.2
1.5
-
VDD +0.2
ISR11
-300
-370
-450
ISR12
-50
-70
-90
ISR13
-40
-60
-80
VDD = 2.5V, VS = 2.0V
ISR21
-20
-24
-28
VDD = 4.5V, VS = 3.0V
ISR22
-4
-6
-8
Input Current GPA/GPB
Input Current at RSTB
[1]
Source Current GPA/GPB
(Quasi-bidirectional
Mode)
Source Current GPA/GPB
(Push-pull Mode)
Sink Current GPA/GPB
(Quasi-bidirectional and
Push-pull Mode)
VDD = 2.4V
V
VDD = 5.5V
VDD = 3.0V
VDD = 4.5V, VS = 2.4V
A
mA
VDD = 2.7V, VS = 2.2V
VDD = 2.7V, VS = 2.2V
ISR23
-3
-5
-7
VDD = 2.5V, VS = 2.0V
ISK1
10
16
20
VDD = 4.5V, VS = 0.45V
ISK2
7
10
13
ISK3
6
9
12
mA
VDD = 2.7V, VS = 0.45V
VDD = 2.5V, VS = 0.45V
Notes: 1. RSTB pin is a Schmitt trigger input.
Release Date: Jan 2012
Version 1.7
- 15 -
N572F065 Data Sheet
7.2 AC Electrical Characteristics
7.2.1 Internal 24MHz RC Oscillator
PARAMETER
CONDITION
Supply voltage VDD
MIN.
TYP.
MAX.
UNIT
2.2
2.4
2.7
V
Center Frequency
Calibrated Internal
Oscillator Frequency
Accuracy of Uncalibrated Internal
Oscillator Frequency
Operating current
24.0
+25C; VDD=2.5V
-20C ~+85C;
VDD=2.2V~2.7V
-20C ~+85C;
VDD=2.2V~2.7V
MHz
-0.6
+0.6
%
-5
+5
%
-20
+20
%
VDD=2.5V
500
uA
7.3 Analog Characteristics
7.3.1 12-bit SAR ADC
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
-
-
-
12
Bit
Differential nonlinearity error
DNL
-
±1
-
LSB
Integral nonlinearity error
INL
-
±1
-
LSB
Offset error
EO
-
±1
-
LSB
Gain error (Transfer gain)
EG
-
1
-
-
Resolution
Monotonic
-
Guaranteed
-
ADC clock frequency
FADC
-
-
5
MHz
Calibration time
TCAL
-
127
-
Clock
TS
-
7
-
Clock
TADC
-
25
-
Clock
FS
-
-
200
Ksps
VDD
-
2.5
-
V
VDDA
3
-
5.5
V
IDD
-
0.5
-
mA
IDDA
-
1.5
-
mA
Sample time
Conversion time
Sample rate
Supply voltage
Supply current (Avg.)
Release Date: Jan 2012
Version 1.7
- 16 -
N572F065 Data Sheet
Reference voltage
VREFP
-
VDDA
-
V
Reference current (Avg.)
IREFP
-
1
-
mA
Input voltage range
VIN
0
-
VREFP
V
Capacitance
CIN
-
5
-
pF
7.3.2 Voice Recorder
Parameter
Sym.
Operation Voltage
VDDA
Operation Current
IDD
Programmable Gain
VOL[4:0]
(Gain1)
Preamp Gain
PAG[1:0]
(Gain2)
Offset Bit
Condition
Min.
Typ.
Max.
Unit
3
5
5.5
V
3.5
5-bit Control
5’b11111→46dB
5’b00001→16dB
5’b00000→0dB
2-bit Control
2’b00: -6dB
2’b01: 0dB
2’b10: 8dB
2’b11: 14dB
OS[4:0]
5-bit Control
16
46
dB
-6
14
dB
-32
32
mV
THD
Gain1=14db,
Gain2=16db
VDDA=4.5V
Input 100mV
SNR
mA
50
dB
43
dB
7.3.3 2.4V LDO for Internal Core
Parameter
Condition
MIN.
TYP.
MAX.
Unit
2.7
5
5.5
V
-10%
2.4
+10%
V
-10%
2.0
+10%
V
Input Voltage
Output Voltage
Power Down
7.3.4 Voutx for External Driving
Parameter
Condition
Input Voltage
Output Voltage
Turn off
Min.
Typ.
Max.
Unit
3.3
5
5.5
V
-10%
3.0
+10%
V
floating
-
V
Release Date: Jan 2012
Version 1.7
- 17 -
N572F065 Data Sheet
I load
30
mA
7.3.5 Low Voltage Reset
PARAMETER
Threshold voltage
CONDITION
MIN.
TYP.
MAX.
UNIT
Temperature=25C
1.7
2.0
2.3
V
MIN.
TYP.
MAX.
7.3.6 Voltage Detector
PARAMETER
CONDITION
Detected Voltage
UNIT
CVDTV=0
2.7
V
CVDTV=1
3.0
V
7.3.7 Power-On Reset (5V)
PARAMETER
CONDITION
MIN.
TYP.
MAX.
UNIT
Temperature
-
-20
25
85
C
Reset voltage
V+
-
2
-
V
Vin>reset voltage
-
1
-
nA
Quiescent current
7.3.8 Power Amplifier and DAC
PARAMETER
Operation voltage
CONDITION
MIN.
TYP.
MAX.
UNIT
SPKVDD
2.4
4.5
5.5
V
0
25
70
C
Temperature
Output Power
SPKVDD=4.5V, 27C, 8Ω
BTL load, 0dB gain
250
mW
Total Harmonic
Distortion
SPKVDD=4.5V, 27C, 8Ω
BTL load, 0dB gain,
250mW
0.5
%
Power Amplifier Gain
DAC output current
-18
0
dB
mA
DACGN=0
2.4
3
3.6
DACGN=1
4.0
5.0
6.0
DAC operation Current
SPKVDD=4.5V
5.5
mA
DAC Quiescent Current
SPKVDD=4.5V
100
A
Release Date: Jan 2012
Version 1.7
- 18 -
N572F065 Data Sheet
Power Amplifier
Quiescent Current
DAC fine-tuned,
SPKVDD=4.5V, 27C
11
mA
Power Down Current
DAC fine-tuned,
SPKVDD=4.5V, 27C
1
A
Operation Current
SPKVDD=4.5V, 27C,
250mW
180
mA
7.3.9 PLL
PARAMETER
SYMBOL
Operating Voltage
Range
VDD
CONDITION
MIN.
TYP.
MAX.
UNIT
2.2
2.4
2.7
V
-20
25
85
C
Temperature
Input Low Voltage
VIL
VDD=2.4V
VSS
--
0.2*VDD
V
Input High Voltage
VIH
VDD=2.4V
0.8*VDD
--
VDD
V
Input Clock
Frequency
Fin1
--
32.768
--
KHz
Fin2
--
6 or 12
--
MHz
Fout
--
48
--
MHz
1
nS
60
%
Output Clock
Frequency
Jitter
--
25C, TT, 2.4V
--
Duty Cycle
--
Fout=48MHz
40
Iop
25C, TT, 2.4V
8
mA
32768Hz to 48MHz
5
mS
Operating Current
Lock Time
50
7.3.10 USB PHY
7.3.10.1 USB DC Electrical Characteristics
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
2.0
UNIT
Input high (driven)
VIH
V
Input low
VIL
Differential input
sensitivity
VDI
|DP-DM|
0.2
Differential commonmode range
VCM
Include VDI range
0.8
2.5
V
Single-ended receiver
threshold
VSE
0.8
2.0
V
0.8
V
V
Release Date: Jan 2012
Version 1.7
- 19 -
N572F065 Data Sheet
Receiver hysteresis
VRH
200
Output low (driven)
VOL
0
0.3
V
Output high (driven)
VOH
2.8
3.6
V
Output signal cross
voltage
VCRS
1.3
2.0
V
Pull-up resistor
RPU
1.425
1.575
KΩ
Pull-down resistor
RPD
14.25
15.75
KΩ
Termination Voltage for
upstream port pull up
(RPU)
VTRM
3.0
3.6
V
Driver output resistance
ZDRV
Transceiver capacitance
CIN
Steady state drive*
Pin to GND
mV
Ω
10
20
pF
*Driver output resistance doesn’t include series resistor resistance.
Release Date: Jan 2012
Version 1.7
- 20 -
N572F065 Data Sheet
8. Package Information
64L LQFP(7x7x1.4mm footprint 2.0mm)
Release Date: Jan 2012
Version 1.7
- 21 -
N572F065 Data Sheet
9. Ordering Information
PART
NUMBER
PACKAGE
SPECIAL
FEATURE
PB FREE +
HALOGEN
FREE (GREEN)
RELEASE
DATE
N572F065
NA (Die Form)
With USB
Yes
Available
N572F065G
LQFP 64pin
7mmx7mm
With USB
Yes
Available
10. Revision History
VERSION
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
DATE
Apr. 2010
May 2010
Jun. 2010
Aug. 2010
Oct. 2010
Dec. 2010
Aug. 2011
Jan. 2012
DESCRIPTIONS
Preliminary draft
With algorithms and partial DC characteristics
Add DC/AC/Analog characteristics
Remove Preliminary, add security lock, add part no.
Adjust the part no.
Fix the typo of LDO 3.3V, add Voutx in Block Diagram
Fix the output value of Voutx in Analog Characteristics (7.3.4).
Sync ADC performance to 200K sps (2 & 7.3.1).
Change LDO30E to Voutx (4.1) and revise AP circuits (5).
Update importance notice.
Add description for VPP & USB related pins/pads (4).
Add Voutx I load information (7.3.4).
Add package information (8).
Release Date: Jan 2012
Version 1.7
- 22 -
N572F065 Data Sheet
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
Release Date: Jan 2012
Version 1.7
- 23 -
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