ETC1 A42MX24-3PL100I 40mx and 42mx fpga family Datasheet

v6.0
40MX and 42MX FPGA Families
Features
HiRel Features
•
High Capacity
•
•
•
•
•
•
Single-Chip ASIC Alternative
3,000 to 54,000 System Gates
Up to 2.5 kbits Configurable Dual-Port SRAM
Fast Wide-Decode Circuitry
Up to 202 User-Programmable I/O Pins
•
•
Commercial, Industrial, Automotive, and Military
Temperature Plastic Packages
Commercial, Military Temperature, and MIL-STD-883
Ceramic Packages
QML Certification
Ceramic Devices Available to DSCC SMD
Ease of Integration
High Performance
•
•
•
•
•
•
•
5.6 ns Clock-to-Out
250 MHz Performance
5 ns Dual-Port SRAM Access
100 MHz FIFOs
7.5 ns 35-Bit Address Decode
•
•
•
•
Mixed-Voltage Operation (5.0V or 3.3V for core and
I/Os), with PCI-Compliant I/Os
Up to 100% Resource Utilization and 100% Pin
Locking
Deterministic, User-Controllable Timing
Unique In-System Diagnostic and Verification
Capability with Silicon Explorer II
Low Power Consumption
IEEE Standard 1149.1 (JTAG) Boundary Scan Testing
Product Profile
Device
A40MX02
A40MX04
A42MX09
A42MX16
A42MX24
A42MX36
Capacity
System Gates
SRAM Bits
3,000
–
6,000
–
14,000
–
24,000
–
36,000
–
54,000
2,560
Logic Modules
Sequential
Combinatorial
Decode
–
295
–
–
547
–
348
336
–
624
608
–
954
912
24
1,230
1,184
24
9.5 ns
9.5 ns
5.6 ns
6.1 ns
6.1 ns
6.3 ns
SRAM Modules
(64x4 or 32x8)
–
–
–
–
–
10
Dedicated Flip-Flops
–
–
348
624
954
1,230
Maximum Flip-Flops
147
273
516
928
1,410
1,822
Clocks
1
1
2
2
2
6
User I/O (maximum)
57
69
104
140
176
202
PCI
–
–
–
–
Yes
Yes
Boundary Scan Test (BST)
–
–
–
–
Yes
Yes
44, 68
100
80
–
–
–
44, 68, 84
100
80
–
–
–
84
100, 160
100
176
–
–
84
100, 160, 208
100
176
–
–
84
160, 208
–
176
–
–
–
208, 240
–
–
208, 256
272
Clock-to-Out
Packages (by pin count)
PLCC
PQFP
VQFP
TQFP
CQFP
PBGA
January 2004
© 2004 Actel Corporation
i
See the Actel website (www.actel.com) for the latest version of this datasheet.
40MX and 42MX FPGA Families
Ordering Information
A42MX16 _
PQ
1
100
ES
Application (Temperature Range)
Blank = Commercial (0 to +70˚C)
I
= Industrial (–40 to +85˚C)
M
= Military (–55 to +125˚C)
B
= MIL-STD-883
A
= Automotive (–40 to +125˚C)
Package Lead Count
Package Type
PL =
Plastic Leaded Chip Carrier
PQ =
Plastic Quad Flat Pack
TQ =
Thin (1.4 mm) Quad Flat Pack
VQ =
Very Thin (1.0 mm) Quad Flat Pack
BG =
Plastic Ball Grid Array
CQ =
Ceramic Quad Flat Pack
Speed Grade
Blank = Standard Speed
–1 =
Approximately 15% Faster than Standard
–2 =
Approximately 25% Faster than Standard
–3 =
Approximately 35% Faster than Standard
–F =
Approximately 40% Slower than Standard
Part Number
A40MX02
=
3,000 System Gates
A40MX04
=
6,000 System Gates
A42MX09
=
14,000 System Gates
A42MX16
=
24,000 System Gates
A42MX24
=
36,000 System Gates
A42MX36
=
54,000 System Gates
Plastic Device Resources
User I/Os
PLCC
44-Pin
PLCC
68-Pin
PLCC
84-Pin
A40MX02
34
57
–
A40MX04
34
57
69
69
–
A42MX09
–
–
72
83
101
A42MX16
–
–
72
83
125
A42MX24
–
–
72
–
A42MX36
–
–
–
–
Device
PQFP
PQFP
PQFP
PQFP
100-Pin 160-Pin 208-Pin 240-Pin
57
–
–
VQFP
80-Pin
VQFP
TQFP
PBGA
100-Pin 176-Pin 272-Pin
–
57
–
–
–
–
–
69
–
–
–
–
–
–
83
104
–
140
–
–
83
140
–
125
176
–
–
–
150
–
–
176
202
–
–
–
202
Note: Package Definitions
PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, VQFP = Very Thin Quad Flat Pack,
PBGA = Plastic Ball Grid Array
ii
v6.0
40MX and 42MX FPGA Families
Ceramic Device Resources
User I/Os
Device
CQFP 208-Pin
CQFP 256-Pin
176
202
A42MX36
Note: Package Definitions
CQFP = Ceramic Quad Flat Pack
Temperature Grade Offerings
Package
A40MX02
A40MX04
PLCC 44
C, I, M
C, I, M
PLCC 68
C, I, A, M
C, I, M
PLCC 84
PQFP 100
C, I, A, M
A42MX09
A42MX16
A42MX24
C, I, A, M
C, I, A, M
C, I, M
C, I, M
C, I, A, M
C, I, A, M
C, I, M
C, I, A, M
C, I, M
C, I, A, M
C, I, A, M
C, I, A, M
PQFP 160
PQFP 208
PQFP 240
VQFP 80
A42MX36
C, I, A, M
C, I, A, M
C, I, A, M
C, I, A, M
VQFP 100
C, I, A, M
C, I, A, M
TQFP 176
C, I, A, M
C, I, A, M
C, I, A, M
PBGA 272
C, I, M
CQFP 208
C, M, B
CQFP 256
C, M, B
Note:
C = Commercial
I = Industrial
A = Automotive
M = Military
B = MIL-STD-883 Class B
Speed Grade Offerings
–F
–1
–2
–3
✓
✓
✓
✓
I
✓
✓
✓
✓
A
✓
M
✓
✓
B
✓
✓
C
✓
Std
Note: Refer to the 40MX and 42MX Automotive Family FPGAs datasheet for details on automotive-grade MX offerings.
Contact your local Actel representative for device availability.
v6.0
iii
40MX and 42MX FPGA Families
Table of Contents
40MX and 42MX FPGA Families
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
MX Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Development Tool Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
5.0V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
5V TTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
3.3V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
3.3V LVTTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
Mixed 5.0V/3.3V Operating Conditions (for 42MX Devices Only) . . . . . . . . . . . . . 1-18
Mixed 5.0V/3.3V Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
Output Drive Characteristics for 5.0V PCI Signaling . . . . . . . . . . . . . . . . . . . . . . . . 1-19
Output Drive Characteristics for 3.3V PCI Signaling . . . . . . . . . . . . . . . . . . . . . . . . 1-20
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23
Parameter Measurement
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25
Sequential Module Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26
Sequential Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27
Decode Module Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28
SRAM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28
Dual-Port SRAM Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28
Predictable Performance: Tight Delay Distributions . . . . . . . . . . . . . . . . . . . . . . . 1-30
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30
Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31
PCI System Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-35
PCI Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-35
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-36
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-77
Package Pin Assignments
44-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
68-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
84-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
v6.0
v
40MX and 42MX FPGA Families
Table of Contents
100-Pin PQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
160-Pin PQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
208-Pin PQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
240-Pin PQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
80-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
100-Pin VQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
176-Pin TQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
208-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
256-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
272-Pin BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
vi
v6.0
40MX and 42MX FPGA Families
40MX and 42MX FPGA Families
General Description
MX Architectural Overview
Actel's 40MX and 42MX families offer a cost-effective
design solution at 5V. The MX devices are single-chip
solutions and provide high performance while
shortening the system design and development cycle.
MX devices can integrate and consolidate logic
implemented in multiple PALs, CPLDs, and FPGAs.
Example applications include high-speed controllers and
address decoding, peripheral bus interfaces, DSP, and coprocessor functions.
The MX devices are composed of fine-grained building
blocks that enable fast, efficient logic designs. All devices
within these families are composed of logic modules, I/O
modules, routing resources and clock networks, which
are the building blocks for fast logic designs. In addition,
the A42MX36 device contains embedded dual-port
SRAM modules, which are optimized for high-speed
datapath functions such as FIFOs, LIFOs and scratchpad
memory. A42MX24 and A42MX36 also contain widedecode modules.
The MX device architecture is based on Actel’s patented
antifuse technology implemented in a 0.45µm triplemetal CMOS process. With capacities ranging from 3,000
to 54,000 system gates, the MX devices provide
performance up to 250 MHz, are live on power-up and
have one-fifth the standby power consumption of
comparable FPGAs. Actel’s MX FPGAs provide up to 202
user I/Os and are available in a wide variety of packages
and speed grades.
Logic Modules
The 40MX logic module is an eight-input, one-output
logic circuit designed to implement a wide range of logic
functions with efficient use of interconnect routing
resources (Figure 1-1).
The logic module can implement the four basic logic
functions (NAND, AND, OR and NOR) in gates of two,
three, or four inputs. The logic module can also
implement a variety of D-latches, exclusivity functions,
AND-ORs and OR-ANDs. No dedicated hard-wired latches
or flip-flops are required in the array; latches and flipflops can be constructed from logic modules whenever
required in the application.
Actel’s A42MX24 and A42MX36 devices also feature
MultiPlex I/Os, which support mixed-voltage systems,
enable programmable PCI, deliver high-performance
operation at both 5.0V and 3.3V, and provide a lowpower mode. The devices are fully compliant with the
PCI Local Bus Specification (version 2.1). They deliver
200 MHz on-chip operation and 6.1 ns clock-to-output
performance.
The 42MX24 and 42MX36 devices include system-level
features such as IEEE Standard 1149.1 (JTAG) Boundary
Scan Testing and fast wide-decode modules. In addition,
the A42MX36 device offers dual-port SRAM for
implementing fast FIFOs, LIFOs, and temporary data
storage. The storage elements can efficiently address
applications requiring wide datapath manipulation and
can perform transformation functions such as those
required for telecommunications, networking, and DSP.
All MX devices are fully tested over automotive and
military temperature ranges. In addition, the largest
member of the family, the A42MX36, is available in both
CQ208 and CQ256 ceramic packages screened to MILSTD-883 levels. For easy prototyping and conversion from
plastic to ceramic, the CQ208 and PQ208 devices are pincompatible.
Figure 1-1 • 40MX Logic Module
v6.0
1-1
40MX and 42MX FPGA Families
The 42MX devices contain three types of logic modules:
combinatorial (C-modules), sequential (S-modules) and
decode
(D-modules).
Figure 1-2
illustrates
the
combinatorial logic module. The S-module, shown in
Figure 1-3, implements the same combinatorial logic
function as the C-module while adding a sequential
element. The sequential element can be configured as
either a D-flip-flop or a transparent latch. The S-module
register can be bypassed so that it implements purely
combinatorial logic.
A0
B0
S0
D00
D01
Y
D10
D11
S1
A1
B1
Figure 1-2 • 42MX C-Module Implementation
D00
D01
D00
D01
Y
D10
D
S0
D11
S1
Q
OUT
Y
D10
D11
S1
CLR
Up to 7-Input Function Plus D-Type Flip-Flop with Clear
S0
D
Q
GATE
Up to 7-Input Function Plus Latch
D00
D0
D01
Y
D1
S
D
Q
OUT
D11
S1
GATE
CLR
OUT
S0
Up to 8-Input Function (Same as C-Module)
Up to 4-Input Function Plus Latch with Clear
Figure 1-3 • 42MX S-Module Implementation
1 -2
Y
D10
v6.0
OUT
40MX and 42MX FPGA Families
A42MX24 and A42MX36 devices contain D-modules,
which are arranged around the periphery of the device.
D-modules contain wide-decode circuitry, providing a
fast, wide-input AND function similar to that found in
CPLD architectures (Figure 1-4). The D-module allows
A42MX24 and A42MX36 devices to perform widedecode functions at speeds comparable to CPLDs and
PALs. The output of the D-module has a programmable
inverter for active HIGH or LOW assertion. The D-module
output is hardwired to an output pin, and can also be
fed back into the array to be incorporated into other
logic.
highest order address bits (RDAD5 and WRAD5) are not
used. The read and write ports of the SRAM block
contain independent clocks (RCLK and WCLK) with
programmable polarities offering active HIGH or LOW
implementation. The SRAM block contains eight data
inputs (WD[7:0]), and eight outputs (RD[7:0]), which are
connected to segmented vertical routing tracks.
The A42MX36 dual-port SRAM blocks provide an optimal
solution for high-speed buffered applications requiring
FIFO and LIFO queues. The ACTgen Macro Builder within
Actel's Designer software provides capability to quickly
design memory functions with the SRAM blocks. Unused
SRAM blocks can be used to implement registers for
other user logic within the design.
Dual-Port SRAM Modules
The A42MX36 device contains dual-port SRAM modules
that have been optimized for synchronous or
asynchronous applications. The SRAM modules are
arranged in 256-bit blocks that can be configured as 32x8
or 64x4. SRAM modules can be cascaded together to
form memory spaces of user-definable width and depth.
A block diagram of the A42MX36 dual-port SRAM block
is shown in Figure 1-5.
7 Inputs
Hard-Wire to I/O
Programmable
Inverter
The A42MX36 SRAM modules are true dual-port
structures containing independent read and write ports.
Each SRAM module contains six bits of read and write
addressing (RDAD[5:0] and WRAD[5:0], respectively) for
64x4-bit blocks. When configured in byte mode, the
WD[7:0]
Feedback to Array
Figure 1-4 • A42MX24 and A42MX36 D-Module
Implementation
Latches
[7:0]
WRAD[5:0]
MODE
BLKEN
WEN
[5:0]
Write
Port
Logic
SRAM Module
32 x 8 or 64 x 4
(256 Bits)
WCLK
Latches
Read
Logic
Latches
Write
Logic
[5:0]
Read
Port
Logic
RD[7:0]
RDAD[5:0]
REN
RCLK
Routing Tracks
Figure 1-5 • A42MX36 Dual-Port SRAM Block
v6.0
1-3
40MX and 42MX FPGA Families
Routing Structure
Segmented
Horizontal
Routing
The MX architecture uses vertical and horizontal routing
tracks to interconnect the various logic and I/O modules.
These routing tracks are metal interconnects that may be
continuous or split into segments. Varying segment
lengths allow the interconnect of over 90% of design
tracks to occur with only two antifuse connections.
Segments can be joined together at the ends using
antifuses to increase their lengths up to the full length of
the track. All interconnects can be accomplished with a
maximum of four antifuses.
Horizontal Routing
Horizontal routing tracks span the whole row length or
are divided into multiple segments and are located in
between the rows of modules. Any segment that spans
more than one-third of the row length is considered a
long horizontal segment. A typical channel is shown in
Figure 1-6. Within horizontal routing, dedicated routing
tracks are used for global clock networks and for power
and ground tie-off tracks. Non-dedicated tracks are used
for signal nets.
Vertical Routing
Another set of routing tracks run vertically through the
module. There are three types of vertical tracks: input,
output, and long. Long tracks span the column length of
the module, and can be divided into multiple segments.
Each segment in an input track is dedicated to the input
of a particular module; each segment in an output track
is dedicated to the output of a particular module. Long
segments are uncommitted and can be assigned during
routing. Each output segment spans four channels (two
above and two below), except near the top and bottom
of the array, where edge effects occur. Long vertical
tracks contain either one or two segments. An example
of vertical routing tracks and segments is shown in
Figure 1-6.
Antifuse Structures
An antifuse is a "normally open" structure. The use of
antifuses to implement a programmable logic device
results in highly testable structures as well as efficient
programming algorithms. There are no pre-existing
connections; temporary connections can be made using
pass transistors. These temporary connections can isolate
individual antifuses to be programmed and individual
circuit structures to be tested, which can be done before
and after programming. For instance, all metal tracks can
be tested for continuity and shorts between adjacent
tracks, and the functionality of all logic modules can be
verified.
1 -4
v6.0
Logic
Modules
Antifuses
Vertical Routing Tracks
Figure 1-6 • MX Routing Structure
Clock Networks
The 40MX devices have one global clock distribution
network (CLK). A signal can be put on the CLK network
by being routed through the CLKBUF buffer.
In 42MX devices, there are two low-skew, high-fanout
clock distribution networks, referred to as CLKA and
CLKB. Each network has a clock module (CLKMOD) that
can select the source of the clock signal from any of the
following (Figure 1-7 on page 1-5):
•
Externally from the CLKA pad, using CLKBUF
buffer
•
Externally from the CLKB pad, using CLKBUF
buffer
•
Internally from the CLKINTA input, using CLKINT
buffer
•
Internally from the CLKINTB input, using CLKINT
buffer
The clock modules are located in the top row of I/O
modules. Clock drivers and a dedicated horizontal clock
track are located in each horizontal routing channel.
Clock input pads in both 40MX and 42MX devices can
also be used as normal I/Os, bypassing the clock
networks.
The A42MX36 device has four additional register control
resources, called quadrant clock networks (Figure 1-8 on
page 1-5). Each quadrant clock provides a local, highfanout resource to the contiguous logic modules within
its quadrant of the device. Quadrant clock signals can
originate from specific I/O pins or from the internal array
and can be used as a secondary register clock, register
clear, or output enable.
40MX and 42MX FPGA Families
CLKB
CLKINB
CLKA
From
Pads
CLKINA
CLKMOD
S0
S1
Internal
Signal
CLKO(17)
Clock
Drivers
CLKO(16)
CLKO(15)
CLKO(2)
CLKO(1)
Clock Tracks
Figure 1-7 • Clock Networks of 42MX Devices
QCLKA
QCLKB
QCLKC
Quad
Clock
Modul
QCLK1
QCLK3
Quad
Clock
Modul
*QCLK1IN
QCLKD
*QCLK3IN
S0 S1
Quad
Clock
Modul
S1 S0
QCLK2
QCLK4
Quad
Clock
Modul
*QCLK2IN
*QCLK4IN
S0 S1
S1 S0
Note: *QCLK1IN, QCLK2IN, QCLK3IN, and QCLK4IN are internally-generated signals.
Figure 1-8 • Quadrant Clock Network of A42MX36 Devices
v6.0
1-5
40MX and 42MX FPGA Families
MultiPlex I/O Modules
STD
42MX devices feature Multiplex I/Os and support 5.0V,
3.3V, and mixed 3.3V/5.0V operations.
The MultiPlex I/O modules provide the interface between
the device pins and the logic array. Figure 1-9 is a block
diagram of the 42MX I/O module. A variety of user
functions, determined by a library macro selection, can
be implemented in the module. (Refer to the Antifuse
Macro Library Guide for more information.) All 42MX I/O
modules contain tristate buffers, with input and output
latches that can be configured for input, output, or
bidirectional operation.
All 42MX devices contain flexible I/O structures, where
each output pin has a dedicated output-enable control
(Figure 1-9). The I/O module can be used to latch input or
output data, or both, providing fast set-up time. In
addition, the Actel Designer software tools can build a Dtype flip-flop using a C-module combined with an I/O
module to register input and output signals. Refer to the
Antifuse Macro Library Guide for more details.
A42MX24 and A42MX36 devices also offer selectable PCI
output drives, enabling 100% compliance with version
2.1 of the PCI specification. For low-power systems, all
inputs and outputs are turned off to reduce current
consumption to below 500µA.
To achieve 5.0V or 3.3V PCI-compliant output drives on
A42MX24 and A42MX36 devices, a chip-wide PCI fuse is
programmed via the Device Selection Wizard in the
Designer software (Figure 1-10). When the PCI fuse is not
programmed, the output drive is standard.
Actel's Designer software development tools provide a
design library of I/O macro functions that can implement
all I/O configurations supported by the MX FPGAs.
EN
Q
D
PAD
From Array
Q
D
G/CLK*
Note: *Can be configured as a Latch or D Flip-Flop (Using
C-Module)
PCI
Drive
PCI Enable
Fuse
Figure 1-10 • PCI Output Structure of A42MX24 and
A42MX36 Devices
Other Architectural Features
Performance
MX devices can operate with internal clock frequencies
of 250 MHz, enabling fast execution of complex logic
functions. MX devices are live on power-up and do not
require auxiliary configuration devices and thus are an
optimal platform to integrate the functionality
contained in multiple programmable logic devices. In
addition, designs that previously would have required a
gate array to meet performance can be integrated into
an MX device with improvements in cost and time-tomarket. Using timing-driven place-and-route (TDPR)
tools, designers can achieve highly deterministic device
performance.
User Security
The Actel FuseLock provides robust security against
design theft. Special security fuses are hidden in the
fabric of the device and prevent unauthorized users from
accessing the programming and/or probe interfaces. It is
virtually impossible to identify or bypass these fuses
without damaging the device, making Actel antifuse
FPGAs immune to both invasive and noninvasive attacks.
Look for this symbol to ensure your valuable IP is secure.
For more information, refer to Actel's Implementation of
Security in Actel Antifuse FPGAs application note.
Figure 1-9 • 42MX I/O Module
1 -6
Output
Special security fuses in 40MX devices include the Probe
Fuse and Program Fuse. The former disables the probing
circuitry while the latter prohibits further programming
of all fuses, including the Probe Fuse. In 42MX devices,
there is the Security Fuse which, when programmed,
both disables the probing circuitry and prohibits further
programming of the device.
G/CLK*
To Array
Signal
v6.0
40MX and 42MX FPGA Families
nonprogrammed), Silicon Sculptor II also allows self-test
to verify its own hardware extensively.
™
The procedure for programming an MX device using
Silicon Sculptor II is as follows:
1. Load the .AFM file
u e
Figure 1-11 • Fuselock
2. Select the device to be programmed
3. Begin programming
Programming
When the design is ready to go to production, Actel
offers device volume-programming services either
through distribution partners or via In-House
Programming from the factory.
Device programming is supported through the Silicon
Sculptor series of programmers. Silicon Sculptor II is a
compact, robust, single-site and multi-site device
programmer for the PC. With standalone software,
Silicon Sculptor II is designed to allow concurrent
programming of multiple units from the same PC.
For more details on programming MX devices, please
refer to the Programming Antifuse Devices and the
Silicon Sculptor II user's guides.
Silicon Sculptor II programs devices independently to
achieve the fastest programming times possible. After
being programmed, each fuse is verified to insure that it
has been programmed correctly. Furthermore, at the end
of programming, there are integrity tests that are run to
ensure no extra fuses have been programmed. Not only
does
it
test
fuses
(both
programmed
and
Table 1 •
Power Supply
MX devices are designed to operate in both 5.0V and
3.3V environments. In particular, 42MX devices can
operate in mixed 5.0V/3.3V systems. Table 1 describes the
voltage support of MX devices.
Voltage Support of MX Devices
Device
VCC
VCCA
VCCI
Maximum Input Tolerance
Nominal Output Voltage
40MX
5.0V
–
–
5.5V
5.0V
3.3V
–
–
3.6V
3.3V
–
5.0V
5.0V
5.5V
5.0V
–
3.3V
3.3V
3.6V
3.3V
–
5.0V
3.3V
5.5V
3.3V
42MX
Power-Up/Down in Mixed-Voltage Mode
Low Power Mode
When powering up 42MX in mixed voltage mode
(VCCA = 5.0V and VCCI = 3.3V), VCCA must be greater than
or equal to VCCI throughout the power-up sequence. If
VCCI exceeds VCCA during power up, either the I/Os' input
protection junction on the I/Os will be forward-biased or
the I/Os will be at logical HIGH, and ICC rises to high
levels. For power-down, any sequence with VCCA and
VCCI can be implemented.
42MX devices have been designed with a Low Power
Mode. This feature, activated with setting the special LP
pin to HIGH for a period longer than 800 ns, is
particularly useful for battery-operated systems where
battery life is a primary concern. In this mode, the core of
the device is turned off and the device consumes minimal
power with low standby current. In addition, all input
buffers are turned off, and all outputs and bidirectional
buffers are tristated. Since the core of the device is
turned off, the states of the registers are lost. The device
must be re-initialized when exiting Low Power Mode. I/
Os can be driven during LP mode, and clock pins should
be driven HIGH or LOW and should not float to avoid
drawing current. To exit LP mode, the LP pin must be
pulled LOW for over 200 µs to allow for charge pumps to
power up, and device initialization will begin.
v6.0
1-7
40MX and 42MX FPGA Families
Power Dissipation
The power dissipated by a CMOS circuit can be expressed
by the equation:
The general power consumption of MX devices is made
up of static and dynamic power and can be expressed
with the following equation:
Power (µW) = CEQ * VCCA2 * F(1)
where:
CEQ =Equivalent capacitance expressed in picofarads (pF)
General Power Equation
VCCA =Power supply in volts (V)
F =Switching frequency in megahertz (MHz)
P = [ICCstandby + ICCactive] * VCCI + IOL* VOL* N
+ IOH * (VCCI – VOH) * M
Equivalent Capacitance
where:
ICCstandby is the current flowing when no inputs or
outputs are changing.
ICCactive is the current flowing due to CMOS
switching.
IOL, IOH are TTL sink/source currents.
VOL, VOH are TTL level output voltages.
N equals the number of outputs driving TTL loads to
VOL.
M equals the number of outputs driving TTL loads to
VOH.
Accurate values for N and M are difficult to determine
because they depend on the family type, on design
details, and on the system I/O. The power can be divided
into two components: static and active.
Static Power Component
The static power due to standby current is typically a
small component of the overall power consumption.
Standby power is calculated for commercial, worst-case
conditions. The static power dissipation by TTL loads
depends on the number of outputs driving, and on the
DC load current. For instance, a 32-bit bus sinking 4mA at
0.33V will generate 42mW with all outputs driving LOW,
and 140mW with all outputs driving HIGH. The actual
dissipation will average somewhere in between, as I/Os
switch states with time.
Equivalent capacitance is calculated by measuring
ICCactive at a specified frequency and voltage for each
circuit component of interest. Measurements have been
made over a range of frequencies at a fixed value of VCC.
Equivalent capacitance is frequency-independent, so the
results can be used over a wide range of operating
conditions. Equivalent capacitance values are shown
below.
CEQ Values for Actel MX FPGAs
Modules (CEQM)3.5
Input Buffers (CEQI)6.9
Output Buffers (CEQO)18.2
Routed Array Clock Buffer Loads (CEQCR)1.4
To calculate the active power dissipated from the
complete design, the switching frequency of each part of
the logic must be known. The equation below shows a
piece-wise linear summation over all components.
Power = VCCA2 * [(m x CEQM * fm)Modules +
(n * CEQI * fn)Inputs + (p * (CEQO + CL) *
fp)outputs +
0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 *
fq1)routed_Clk1 +
0.5 * (q2 * CEQCR * fq2)routed_Clk2 + (r2 *
fq2)routed_Clk2 (2)
where:
m
= Number of
frequency fm
logic
modules
switching
at
n
= Number of
frequency fn
input
buffers
switching
at
p
= Number of
frequency fp
output
buffers
switching
at
q1
= Number of clock loads on the first routed array
clock
q2
= Number of clock loads on the second routed
array clock
r1
= Fixed capacitance due to first routed array
clock
r2
= Fixed capacitance due to second routed array
clock
Active Power Component
Power dissipation in CMOS devices is usually dominated
by the dynamic power dissipation. Dynamic power
consumption is frequency-dependent and is a function of
the logic and the external I/O. Active power dissipation
results from charging internal chip capacitances of the
interconnect, unprogrammed antifuses, module inputs,
and module outputs, plus external capacitances due to
PC board traces and load device inputs. An additional
component of the active power dissipation is the totem
pole current in the CMOS transistor pairs. The net effect
can be associated with an equivalent capacitance that
can be combined with frequency and voltage to
represent active power dissipation.
1 -8
v6.0
40MX and 42MX FPGA Families
resources. Silicon Explorer II's noninvasive method does
not alter timing or loading effects, thus shortening the
debug cycle and providing a true representation of the
device under actual functional situations.
CEQM = Equivalent capacitance of logic modules in pF
CEQI = Equivalent capacitance of input buffers in pF
CEQO = Equivalent capacitance of output buffers in pF
CEQCR = Equivalent capacitance of routed array clock in
pF
CL
= Output load capacitance in pF
fm
= Average logic module switching rate in MHz
fn
= Average input buffer switching rate in MHz
fp
= Average output buffer switching rate in MHz
fq1
= Average first routed array clock rate in MHz
fq2
= Average second routed array clock rate in MHz
Silicon Explorer II samples data at 100 MHz
(asynchronous) or 66 MHz (synchronous). Silicon Explorer
II attaches to a PC's standard COM port, turning the PC
into a fully functional 18-channel logic analyzer. Silicon
Explorer II allows designers to complete the design
verification process at their desks and reduces
verification time from several hours per cycle to a few
seconds.
Silicon Explorer II is used to control the MODE, DCLK, SDI
and SDO pins in MX devices to select the desired nets for
debugging. The user simply assigns the selected internal
nets in the Silicon Explorer II software to the PRA/PRB
output pins for observation. Probing functionality is
activated when the MODE pin is held HIGH.
Fixed Capacitance Values for MX FPGAs (pF)
Device Type
A40MX02
A40MX04
A42MX09
A42MX16
A42MX24
A42MX36
r2
routed_Clk2
N/A
N/A
118
165
185
220
r1
routed_Clk1
41.4
68.6
118
165
185
220
Figure 1-12 illustrates the interconnection between
Silicon Explorer II and 40MX devices, while Figure 1-13
on page 1-10 illustrates the interconnection between
Silicon Explorer II and 42MX devices
To allow for probing capabilities, the security fuses must
not be programmed. (Refer to <zBlue>“User Security”
section on page 6 for the security fuses of 40MX and
42MX devices). Table 2 on page 1-10 summarizes the
possible device configurations for probing.
Test Circuitry and Silicon Explorer II Probe
MX devices contain probing circuitry that provides builtin access to every node in a design, via the use of Silicon
Explorer II. Silicon Explorer II is an integrated hardware
and software solution that, in conjunction with the
Designer software, allow users to examine any of the
internal nets of the device while it is operating in a
prototyping or a production system. The user can probe
into an MX device without changing the placement and
routing of the design and without using any additional
PRA and PRB pins are dual-purpose pins. When the
"Reserve
Probe
Pin"
is
checked
in
the
Designer software, PRA and PRB pins are reserved as
dedicated outputs for probing. If PRA and PRB pins are
required as user I/Os to achieve successful layout and
"Reserve Probe Pin" is checked, the layout tool will
override the option and place user I/Os on PRA and PRB
pins.
16 Logic Analyzer Channels
Serial Connection
to Windows PC
40MX
MODE
SDI
DCLK
Silicon
Explorer II
SDO
PRB
PRA
Figure 1-12 • Silicon Explorer II Setup with 40MX
v6.0
1-9
40MX and 42MX FPGA Families
16 Logic Analyzer Channels
42MX
Serial Connection
to Windows PC
MODE
SDI
DCLK
Silicon
Explorer II
SDO
PRB
PRA
Figure 1-13 • Silicon Explorer II Setup with 42MX
Table 2 •
Device Configuration Options for Probe Capability
Security Fuse(s)
Programmed
MODE
PRA, PRB1
SDI, SDO, DCLK1
No
LOW
User I/Os2
User I/Os2
No
HIGH
Probe Circuit Outputs
Probe Circuit Inputs
Yes
–
Probe Circuit Secured
Probe Circuit Secured
Notes:
1. Avoid using SDI, SDO, DCLK, PRA and PRB pins as input or bidirectional ports. Since these pins are active during probing, input
signals will not pass through these pins and may cause contention.
2. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. See the <zBlue>“Pin Descriptions” section
on page 77 for information on unused I/O pins.
Design Consideration
It is recommended to use a series 70Ω termination
resistor on every probe connector (SDI, SDO, MODE,
DCLK, PRA and PRB). The 70Ω series termination is used
to prevent data transmission corruption during probing
and reading back the checksum.
IEEE Standard 1149.1 Boundary Scan Test
(BST) Circuitry
42MX24 and 42MX36 devices are compatible with IEEE
Standard 1149.1 (informally known as Joint Testing
Action Group Standard or JTAG), which defines a set of
hardware architecture and mechanisms for cost-effective
board-level testing. The basic MX boundary-scan logic
circuit is composed of the TAP (test access port), TAP
controller, test data registers and instruction register
(Figure 1-14 on page 1-11). This circuit supports all
mandatory IEEE 1149.1 instructions (EXTEST, SAMPLE/
PRELOAD and BYPASS) and some optional instructions.
Table 3 on page 1-11 describes the ports that control
JTAG testing, while Table 4 on page 1-11 describes the
test instructions supported by these MX devices.
1 -1 0
v6.0
Each test section is accessed through the TAP, which has
four associated pins: TCK (test clock input), TDI and TDO
(test data input and output), and TMS (test mode
selector).
The TAP controller is a four-bit state machine. The '1's
and '0's represent the values that must be present at TMS
at a rising edge of TCK for the given state transition to
occur. IR and DR indicate that the instruction register or
the data register is operating in that state.
The TAP controller receives two control inputs (TMS and
TCK) and generates control and clock signals for the rest
of the test logic architecture. On power-up, the TAP
controller enters the Test-Logic-Reset state. To guarantee
a reset of the controller from any of the possible states,
TMS must remain high for five TCK cycles.
42MX24 and 42MX36 devices support three types of test
data registers: bypass, device identification, and
boundary scan. The bypass register is selected when no
other register needs to be accessed in a device. This
speeds up test data transfer to other devices in a test
data path. The 32-bit device identification register is a
shift register with four fields (lowest significant byte
(LSB), ID number, part number and version). The
boundary-scan register observes and controls the state of
each I/O pin.
40MX and 42MX FPGA Families
Each I/O cell has three boundary-scan register cells, each
with a serial-in, serial-out, parallel-in, and parallel-out
pin. The serial pins are used to serially connect all the
boundary-scan register cells in a device into a boundaryscan register chain, which starts at the TDI pin and ends
at the TDO pin. The parallel ports are connected to the
internal core logic tile and the input, output and control
ports of an I/O buffer to capture and load data into the
register to control or observe the logic state of each I/O.
Boundary Scan Register
Output
MUX
TDO
Bypass
Register
Control Logic
JTAG
TMS
TAP Controller
TCK
Instruction
Decode
JTAG
Instruction
Register
TDI
Figure 1-14 • 42MX IEEE 1149.1 Boundary Scan Circuitry
Table 3 •
Test Access Port Descriptions
Port
Description
TMS
(Test
Select)
Mode Serial input for the test logic control bits. Data is captured on the rising edge of the test logic clock (TCK).
TCK (Test Clock Input) Dedicated test logic clock used serially to shift test instruction, test data, and control inputs on the rising edge
of the clock, and serially to shift the output data on the falling edge of the clock. The maximum clock frequency
for TCK is 20 MHz.
TDI (Test Data Input)
TDO
(Test
Output)
Table 4 •
Serial input for instruction and test data. Data is captured on the rising edge of the test logic clock.
Data Serial output for test instruction and data from the test logic. TDO is set to an Inactive Drive state (high
impedance) when data scanning is not in progress.
Supported BST Public Instructions
Instruction
IR Code (IR2.IR0)
Instruction Type
Description
EXTEST
000
Mandatory
Allows the external circuitry and board-level interconnections to
be tested by forcing a test pattern at the output pins and
capturing test results at the input pins.
SAMPLE/PRELOAD
001
Mandatory
Allows a snapshot of the signals at the device pins to be
captured and examined during operation
HIGH Z
101
Optional
Tristates all I/Os to allow external signals to drive pins. Please
refer to the IEEE Standard 1149.1 specification.
CLAMP
110
Optional
Allows state of signals driven from component pins to be
determined from the Boundary-Scan Register. Please refer to
the IEEE Standard 1149.1 specification for details.
BYPASS
111
Mandatory
Enables the bypass register between the TDI and TDO pins. The
test data passes through the selected device to adjacent devices
in the test chain.
v6.0
1-11
40MX and 42MX FPGA Families
JTAG Mode Activation
The JTAG test logic circuit is activated in the Designer
software by selecting Tools -> Device Selection. This
brings up the Device Selection dialog box as shown in
Figure 1-15. The JTAG test logic circuit can be enabled by
clicking the "Reserve JTAG Pins" check box. Table 5
explains the pins' behavior in either mode.
Figure 1-15 • Device Selection Wizard
Table 5 •
Boundary Scan Pin Configuration and Functionality
Reserve JTAG
Checked
Unchecked
TCK
BST input; must be terminated to logical HIGH or LOW to avoid floating
User I/O
TDI, TMS
BST input; may float or be tied to HIGH
User I/O
TDO
BST output; may float or be connected to TDI of another device
User I/O
TRST Pin and TAP Controller Reset
An active reset (TRST) pin is not supported; however, MX
devices contain power-on circuitry that resets the
boundary scan circuitry upon power-up. Also, the TMS
pin is equipped with an internal pull-up resistor. This
allows the TAP controller to remain in or return to the
Test-Logic-Reset state when there is no input or when a
logical 1 is on the TMS pin. To reset the controller, TMS
must be HIGH for at least five TCK cycles.
Boundary Scan Description Language
(BSDL) File
Conforming to the IEEE Standard 1149.1 requires that
the operation of the various JTAG components be
documented. The BSDL file provides the standard format
to describe the JTAG components that can be used by
automatic test equipment software. The file includes the
instructions that are supported, instruction bit pattern,
and the boundary-scan chain order. For an in-depth
discussion on BSDL files, please refer to Actel BSDL Files
Format Description application note.
Actel BSDL files are grouped into two categories generic and device-specific. The generic files assign all
user I/Os as inouts. Device-specific files assign user I/Os as
inputs, outputs or inouts.
Generic files for MX devices are available on Actel's website
at http://www.actel.com/techdocs/models/bsdl.html.
1 -1 2
v6.0
40MX and 42MX FPGA Families
Development Tool Support
Related Documents
The MX family of FPGAs is fully supported by both Actel's
Libero™ Integrated Design Environment and Designer
FPGA Development software. Actel Libero IDE is a design
management environment that streamlines the design
flow. Libero IDE provides an integrated design manager
that seamlessly integrates design tools while guiding the
user through the design flow, managing all design and
log files, and passing necessary design data among tools.
Additionally, Libero IDE allows users to integrate both
schematic and HDL synthesis into a single flow and verify
the entire design in a single environment. Libero IDE
includes Synplify® for Actel from Synplicity®, ViewDraw
for Actel from Mentor Graphics, ModelSim™ HDL
Simulator from Mentor Graphics®, WaveFormer Lite™
from SynaptiCAD™, and Designer software from Actel.
Refer to the Libero IDE flow (located on Actel’s website)
diagram for more information.
Application Notes
Actel BSDL Files Format Description
www.actel.com/documents/BSDLformat_AN.pdf
Programming Antifuse Devices
http://www.actel.com/documents/
AntifuseProgram_AN.pdf
Actel's Implementation of Security in Actel Antifuse
FPGAs
www.actel.com/documents/Antifuse_Security_AN.pdf
User’s Guides and Manuals
Antifuse Macro Library Guide
www.actel.com/documents/libguide_UG.pdf
Actel's Designer software is a place-and-route tool and
provides a comprehensive suite of backend support tools
for FPGA development. The Designer software includes
timing-driven place-and-route, and a world-class
integrated static timing analyzer and constraints editor.
With the Designer software, a user can lock his/her
design pins before layout while minimally impacting the
results of place-and-route. Additionally, the backannotation flow is compatible with all the major
simulators and the simulation results can be cross-probed
with Silicon Explorer II, Actel’s integrated verification
and logic analysis tool. Another tool included in the
Designer software is the ACTgen macro builder, which
easily creates popular and commonly used logic
functions for implementation into your schematic or HDL
design. Actel's Designer software is compatible with the
most popular FPGA design entry and verification tools
from companies such as Mentor Graphics, Synplicity,
Synopsys, and Cadence Design Systems. The Designer
software is available for both the Windows and UNIX
operating systems.
Silicon Sculptor II
www.actel.com/techdocs/manuals/default.asp#programmers
Miscellaneous
Libero IDE Flow Diagram
www.actel.com/products/tools/libero/flow.html
Actel's Designer software is compatible with the most
popular FPGA design entry and verification tools from
companies such as Mentor Graphics, Synplicity, Synopsys,
and Cadence Design Systems. The Designer software is
available for both the Windows and UNIX operating
systems.
v6.0
1-13
40MX and 42MX FPGA Families
5.0V Operating Conditions
Table 6 •
Absolute Maximum Ratings for 40MX Devices*
Symbol
Parameter
Limits
Units
–0.5 to +7.0
V
VCC
DC Supply Voltage
VI
Input Voltage
–0.5 to VCC+0.5
V
VO
Output Voltage
–0.5 to VCC+0.5
V
tSTG
Storage Temperature
–65 to +150
°C
Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to
absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the
Recommended Operating Conditions.
Table 7 •
Absolute Maximum Ratings for 42MX Devices*
Symbol
Parameter
Limits
Units
VCCI
DC Supply Voltage for I/Os
–0.5 to +7.0
V
VCCA
DC Supply Voltage for Array
–0.5 to +7.0
V
VI
Input Voltage
–0.5 to VCCI+0.5
V
VO
Output Voltage
–0.5 to VCCI+0.5
V
tSTG
Storage Temperature
–65 to +150
°C
Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to
absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the
Recommended Operating Conditions.
Table 8 •
Recommended Operating Conditions
Parameter
Commercial
Industrial
Military
Units
0 to +70
-40 to +85
–55 to +125
°C
VCC (40MX)
4.75 to 5.25
4.5 to 5.5
4.5 to 5.5
V
VCCA (42MX)
4.75 to 5.25
4.5 to 5.5
4.5 to 5.5
V
VCCI (42MX)
4.75 to 5.25
4.5 to 5.5
4.5 to 5.5
V
Temperature Range*
Note: *Ambient temperature (TA) is used for commercial and industrial grades; case temperature (TC) is used for military grades.
1 -1 4
v6.0
40MX and 42MX FPGA Families
5V TTL Electrical Specifications
Table 9 •
5V TTL Electrical Specifications
Commercial
Symbol
Parameter
Min.
VOH1
IOH = -10mA
2.4
Max.
Commercial -F
Min.
Max.
Min.
Max.
Military
Min.
0.5
Units
V
3.7
IOL = 10mA
Max.
2.4
IOH = -4mA
VOL1
Industrial
3.7
V
0.5
V
IOL = 6mA
0.4
0.4
V
VIL
-0.3
0.8
-0.3
0.8
-0.3
0.8
-0.3
0.8
V
VIH (40MX)
2.0
VCC+0.3
2.0
VCC+0.3
2.0
VCC+0.3
2.0
VCC+0.3
V
VIH (42MX)
2.0
VCCI+0.3
2.0
VCCI+0.3
2.0
VCCI+0.3
2.0
VCCI+0.3
V
IIL
VIN = 0.5V
-10
-10
-10
-10
µA
IIH
VIN = 2.7V
-10
-10
-10
-10
µA
Input
Transition
Time, TR and TF
500
500
500
500
ns
CIO I/O Capacitance
10
10
10
10
pF
A40MX02,
A40MX04
3
25
10
25
mA
A42MX09
5
25
25
25
mA
A42MX16
6
25
25
25
mA
A42MX24,
A42MX36
20
25
25
25
mA
42MX devices
only
0.5
ICC - 5.0
ICC - 5.0
ICC - 5.0
mA
Standby
ICC2
Current,
Low-Power
Mode
Standby Current
IIO, I/O source sink Can be derived from the IBIS model (http://www.actel.com/techdocs/models/ibis.html)
current
Notes:
1. Only one output tested at a time. VCC/VCCI = min.
2. All outputs unloaded. All inputs = VCC/VCCI or GND.
v6.0
1-15
40MX and 42MX FPGA Families
3.3V Operating Conditions
Table 10 •
Absolute Maximum Ratings for 40MX Devices*
Symbol
Parameter
Limits
Units
–0.5 to +7.0
V
VCC
DC Supply Voltage
VI
Input Voltage
–0.5 to VCC+0.5
V
VO
Output Voltage
–0.5 to VCC+0.5
V
tSTG
Storage Temperature
–65 to +150
°C
Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to
absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the
Recommended Operating Conditions.
Table 11 •
Absolute Maximum Ratings for 42MX Devices*
Symbol
Parameter
Limits
Units
VCCI
DC Supply Voltage for I/Os
–0.5 to +7.0
V
VCCA
DC Supply Voltage for Array
–0.5 to +7.0
V
VI
Input Voltage
–0.5 to VCCI+0.5
V
VO
Output Voltage
–0.5 to VCCI+0.5
V
tSTG
Storage Temperature
–65 to +150
°C
Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to
absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the
Recommended Operating Conditions.
Table 12 •
Recommended Operating Conditions
Parameter
Commercial
Industrial
Military
Units
Temperature Range*
0 to +70
–40 to +85
–55 to +125
°C
VCC (40MX)
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
V
VCCA (42MX)
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
V
VCCI (42MX)
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
V
Note: *Ambient temperature (TA) is used for commercial and industrial grades; case temperature (TC) is used for military grades.
1 -1 6
v6.0
40MX and 42MX FPGA Families
3.3V LVTTL Electrical Specifications
Table 13 •
3.3V LVTTL Electrical Specifications
Commercial
Symbol
Parameter
Min.
VOH1
IOH = –4mA
2.15
VOL1
IOL = 6mA
Max.
Commercial -F
Min.
Max.
2.15
0.4
Industrial
Min.
Max.
2.4
0.4
Military
Min.
Max.
2.4
0.48
Units
V
0.48
V
VIL
–0.3
0.8
–0.3
0.8
–0.3
0.8
–0.3
0.8
V
VIH (40MX)
2.0
VCC+0.3
2.0
VCC+0.3
2.0
VCC+0.3
2.0
VCC+0.3
V
VIH (42MX)
2.0
VCCI+0.3
2.0
VCCI+0.3
2.0
VCCI+0.3
2.0
VCCI+0.3
V
IIL
–10
–10
–10
–10
µA
IIH
–10
–10
–10
–10
µA
Input Transition Time,
TR and TF
500
500
500
500
ns
CIO I/O Capacitance
10
10
10
10
pF
A40MX02,
A40MX04
3
25
10
25
mA
A42MX09
5
25
25
25
mA
A42MX16
6
25
25
25
mA
A42MX24,
A42MX36
15
25
25
25
mA
42MX
devices only
0.5
ICC - 5.0
ICC - 5.0
ICC - 5.0
mA
Standby Current,
ICC2
Low-Power
Mode
Standby Current
IIO, I/O
current
source
sink Can be derived from the IBIS model (http://www.actel.com/techdocs/models/ibis.html)
Notes:
1. Only one output tested at a time. VCC/VCCI = min.
2. All outputs unloaded. All inputs = VCC/VCCI or GND.
v6.0
1-17
40MX and 42MX FPGA Families
Mixed 5.0V/3.3V Operating Conditions (for 42MX Devices Only)
Table 14 •
Absolute Maximum Ratings*
Symbol
Parameter
Limits
Units
VCCI
DC Supply Voltage for I/Os
–0.5 to +7.0
V
VCCA
DC Supply Voltage for Array
–0.5 to +7.0
V
VI
Input Voltage
–0.5 to VCCI+0.5
V
VO
Output Voltage
–0.5 to VCCI+0.5
V
tSTG
Storage Temperature
–65 to +150
°C
Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to
absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the
Recommended Operating Conditions.
Table 15 •
Recommended Operating Conditions
Parameter
Commercial
Industrial
Military
Units
0 to +70
-40 to +85
–55 to +125
°C
VCCA
4.75 to 5.25
4.5 to 5.5
4.5 to 5.5
V
VCCI
3.14 to 3.47
3.0 to 3.6
3.0 to 3.6
V
Temperature Range*
Note: *Ambient temperature (TA) is used for commercial and industrial grades; case temperature (TC) is used for military grades.
Mixed 5.0V/3.3V Electrical Specifications
Table 16 •
Mixed 5.0V/3.3V Electrical Specifications
Symbol
VOH1
Commercial
Commercial '-F
Parameter
Min.
Min.
IOH = –10mA
2.4
Max.
Max.
Min.
Max.
Min.
Max.
0.5
Units
V
3.7
IOL = 10mA
Military
2.4
IOH = –4mA
VOL1
'Industrial
3.7
V
0.5
V
IOL = 6mA
0.4
0.4
V
VIL
–0.3
0.8
–0.3
0.8
–0.3
0.8
–0.3
0.8
V
VIH
2.0
VCCI+0.3
2.0
VCCI+0.3
2.0
VCCI+0.3
2.0
VCCI+0.3
V
IL
VIN = 0.5V
–10
–10
–10
–10
µA
IH
VIN = 2.7V
–10
–10
–10
–10
µA
Input Transition Time, TR and TF
500
500
500
500
ns
CIO I/O Capacitance
10
10
10
10
pF
A42MX09
5
25
25
25
mA
A42MX16
6
25
25
25
mA
A42MX24, A42MX36
20
25
25
25
mA
0.5
ICC - 5.0
ICC - 5.0
ICC - 5.0
mA
Standby Current,
ICC2
Low-Power Mode Standby Current
IIO I/O source sink current
Can be derived from the IBIS model (http://www.actel.com/techdocs/models/ibis.html)
Notes:
1. Only one output tested at a time. VCCI = min.
2. All outputs unloaded. All inputs = VCCI or GND.
1 -1 8
v6.0
40MX and 42MX FPGA Families
Output Drive Characteristics for 5.0V PCI Signaling
MX PCI device I/O drivers were designed specifically for high-performance PCI systems. Figure 1-16 on page 1-21 shows
the typical output drive characteristics of the MX devices. MX output drivers are compliant with the PCI Local Bus
Specification.
Table 17 •
DC Specification (5.0V PCI Signaling)1
PCI
Symbol
Parameter
Condition
MX
Min.
Max.
Min.
Max.
Units
VCCI
Supply Voltage for I/Os
4.75
5.25
4.75
5.252
V
VIH
Input High Voltage
2.0
VCC + 0.5
2.0
VCCI + 0.3
V
VIL
Input Low Voltage
–0.5
0.8
–0.3
0.8
V
IIH
Input High Leakage Current
VIN = 2.7V
70
—
10
µA
IIL
Input Low Leakage Current
VIN=0.5V
–70
—
–10
µA
Output High Voltage
IOUT = –2 mA
VOH
2.4
V
IOUT = –6 mA
VOL
Output Low Voltage
CIN
Input Pin Capacitance
CCLK
CLK Pin Capacitance
LPIN
3.84
IOUT = 3 mA,
6 mA
0.55
—
0.33
V
10
—
10
pF
12
—
10
pF
5
Pin Inductance
20
—
<8
nH3
nH
Notes:
1. PCI Local Bus Specification, Version 2.1, Section 4.2.1.1.
2. Maximum rating for VCCI –0.5V to 7.0V.
3. Dependent upon the chosen package. PCI recommends QFP and BGA packaging to reduce pin inductance and capacitance.
Table 18 •
AC Specifications (5.0V PCI Signaling)*
PCI
Symbol
Parameter
Condition
Min.
Low Clamp Current
–5 < VIN ≤ –1
–25 + (VIN +1)
/0.015
Slew (r)
Output Rise Slew Rate
0.4V to 2.4V load
1
Slew (f)
Output Fall Slew Rate
2.4V to 0.4V load
1
ICL
MX
Max.
Min.
Max.
Units
–60
–10
mA
5
1.8
2.8
V/ns
5
2.8
4.3
V/ns
Note: *PCI Local Bus Specification, Version 2.1, Section 4.2.1.2.
v6.0
1-19
40MX and 42MX FPGA Families
Output Drive Characteristics for 3.3V PCI Signaling
Table 19 •
DC Specification (3.3V PCI Signaling)1
PCI
Symbol
Parameter
Condition
MX
Min.
Max.
Min.
Max.
Units
VCCI
Supply Voltage for I/Os
3.0
3.6
3.0
3.6
V
VIH
Input High Voltage
0.5
VCC + 0.5
0.5
VCCI + 0.3
V
VIL
Input Low Voltage
–0.5
0.8
–0.3
0.8
V
IIH
Input High Leakage Current
70
10
µA
IIL
Input Leakage Current
–70
–10
µA
VIN = 2.7V
VOH
Output High Voltage
IOUT = –2 mA
VOL
Output Low Voltage
IOUT = 3 mA,
6 mA
CIN
Input Pin Capacitance
CCLK
CLK Pin Capacitance
LPIN
0.9
3.3
5
Pin Inductance
V
0.1
0.1 VCCI
V
10
10
pF
12
10
pF
20
<8
nH3
nH
Notes:
1. PCI Local Bus Specification, Version 2.1, Section 4.2.2.1.
2. Maximum rating for VCCI –0.5V to 7.0V.
3. Dependent upon the chosen package. PCI recommends QFP and BGA packaging to reduce pin inductance and capacitance.
Table 20 •
AC Specifications for (3.3V PCI Signaling)*
PCI
Symbol
Parameter
Condition
Min.
Low Clamp Current
–5 < VIN ≤ –1
–25 + (VIN +1)
/0.015
Slew (r)
Output Rise Slew Rate
0.2V to 0.6V load
1
Slew (f)
Output Fall Slew Rate
0.6V to 0.2V load
1
ICL
Note: *PCI Local Bus Specification, Version 2.1, Section 4.2.2.2.
1 -2 0
v6.0
MX
Max.
Min.
Max.
Units
–60
–10
mA
4
1.8
2.8
V/ns
4
2.8
4.0
V/ns
40MX and 42MX FPGA Families
0.50
0.45
0.40
PCI I OL Maximum
0.35
0.30
0.25
Current (A)
0.20
MX PCI I OL
0.15
0.10
PCI I OL Minimum
0.05
0.00
0
–0.05
1
2
3
4
PCI I OH Maximum
5
6
MX PCI I OH
–0.10
–0.15
PCI I OH Minimum
–0.20
Voltage Out (V)
Figure 1-16 • Typical Output Drive Characteristics (Based Upon Measured Data)
v6.0
1-21
40MX and 42MX FPGA Families
Junction Temperature (TJ)
P = Power
θja = Junction to ambient of package. θja numbers are
The temperature variable in the Designer software refers
to the junction temperature, not the ambient
temperature. This is an important distinction because the
heat generated from dynamic power consumption is
usually hotter than the ambient temperature. EQ 1-1,
shown below, can be used to calculate junction
temperature.
located in the Package Thermal Characteristics table
below.
Package Thermal Characteristics
The device junction-to-case thermal characteristic is θjc,
and the junction-to-ambient air characteristic is θja. The
thermal characteristics for θja are shown with two
different air flow rates.
EQ 1-1
Junction Temperature = ∆T + Ta(1)
Where:
The maximum junction temperature is 150°C.
Ta = Ambient Temperature
Maximum power dissipation for commercialindustrial-grade devices is a function of θja.
∆T = Temperature gradient between junction (silicon)
and ambient
and
A sample calculation of the absolute maximum power
dissipation allowed for a TQFP 176-pin package at
commercial temperature and still air is as follow:
∆T = θja * P(2)
Max. junction temp. (°C) – Max. ambient temp. (°C) 150°C – 70°C
Maximum Power Allowed = --------------------------------------------------------------------------------------------------------------------------------- = ----------------------------------- = 2.86W
28°C/W
θ ja (°C/W)
The maximum power dissipation for military-grade devices is a function of θjc. A sample calculation of the absolute
maximum power dissipation allowed for CQFP 208-pin package at military temperature and still air is as follows:
Max. junction temp. (°C) – Max. ambient temp. (°C) 150°C – 125°C
Maximum Power Allowed = --------------------------------------------------------------------------------------------------------------------------------- = -------------------------------------- = 3.97W
θ jc (°C/W)
6.3°C/W
Table 21 •
Package Thermal Characteristics
θja
1.0 m/s
2.5 m/s
200 ft/min. 500 ft/min.
Pin Count
θjc
Still Air
Plastic Quad Flat Pack
100
12.0
27.8
23.4
21.2
°C/W
Plastic Quad Flat Pack
160
10.0
26.2
22.8
21.1
°C/W
Plastic Quad Flat Pack
208
8.0
26.1
22.5
20.8
°C/W
Plastic Quad Flat Pack
240
8.5
25.6
22.3
20.8
°C/W
Plastic Leaded Chip Carrier
44
16.0
20.0
24.5
22.0
°C/W
Plastic Leaded Chip Carrier
68
13.0
25.0
21.0
19.4
°C/W
Plastic Leaded Chip Carrier
84
12.0
22.5
18.9
17.6
°C/W
Thin Plastic Quad Flat Pack
176
11.0
24.7
19.9
18.0
°C/W
Very Thin Plastic Quad Flat Pack
80
12.0
38.2
31.9
29.4
°C/W
Very Thin Plastic Quad Flat Pack
100
10.0
35.3
29.4
27.1
°C/W
Plastic Ball Grid Array
272
3.0
18.3
14.9
13.9
°C/W
Ceramic Quad Flat Pack
208
2.0
22.0
19.8
18.0
°C/W
Ceramic Quad Flat Pack
256
2.0
20.0
16.5
15.0
°C/W
Plastic Packages
Units
Ceramic Packages
1 -2 2
v6.0
40MX and 42MX FPGA Families
Timing Models
Input Delay
Internal Delays
I/O Module
tINYL=0.62 ns t
IRD2=2.59 ns
Predicted
Routing
Delays
Output Delay
I/O Module
Logic Module
tIRD1=2.09 ns
tIRD4=3.64 ns
tIRD8=5.73 ns
Array
Clock
tCKH=4.55 ns
FMAX=180 MHz
tPD=1.24 ns
tCO=1.24 ns
tDLH=3.32 ns
tENHZ=7.92 ns
tRD1=1.28 ns
tRD2=1.80 ns
tRD4=2.33 ns
tRD8=4.93 ns
FO=128
Note:
* Values are shown for 40MX ‘–3’ speed devices at 5.0V worst-case commercial conditions.
Figure 1-17 • 40MX Timing Model*
Input Delays
I/O Module
tINYL=0.8 ns
Internal Delays
t
Predicted
Routing
Delays
IRD1=2.0 ns †
Output Delays
I/O Module
Combinatorial
Logic Module
D
PD=1.2 ns
tDLH=2.5 ns
Sequential
Logic Module
tINH=0.0 ns
t
INSU=0.3 ns
tINGL=1.3 ns
Combin
-atoria l
D
Q
tRD1=0.70 ns
Logic
tSUD=0.3 ns
t
HD=0.00 ns
tCKH=2.70 ns
MAX=296 MHz
D
Q
t
ENHZ=4.9 ns
G
include
F
DLH=2.5 ns
I/O Module
G
Array
Clocks
t
tRD1=0.7 ns
tRD2=1.9 ns
tRD4=1.4 ns
t
RD8=2.3 ns
t
Q
t
CO=1.3 ns
tOUTH=0.00 ns
t
OUTSU=0.3 ns
tGLH=2.6 ns
FO = 32
tLCO=5.2 ns (light loads, pad-to-pad)
Notes: *Values are shown for A42MX09 ‘–3’ at 5.0V worst-case commercial conditions.
† Input module predicted routing delay.
Figure 1-18 • 42MX Timing Model*
v6.0
1-23
40MX and 42MX FPGA Families
Input Delays
I/O Module
tINYL=0.8 ns
Internal Delays
tIRD1=2.0 ns †
Predicted
Routing
Delays
Output Delays
I/O Module
Combinatorial
Logic Module
D
tDLH=2.5 ns
tRD1=0.7 ns
t
RD2=1.9 ns
tRD4=1.4 ns
tRD8=2.3 ns
tPD=1.2 ns
Q
I/O Module
G
tDLH=2.5 ns
Sequential
Logic Module
tINH=0.0 ns
t
INSU=0.3 ns
tINGL=1.3 ns
Combin
-atoria l
D
Q
D
tRD1=0.70 ns
t
Logic
tSUD=0.3 ns
tHD=0.00 ns
t
CKH=2.70 ns
FMAX=296 MHz
ENHZ=4.9 ns
G
include
Array
Clocks
Q
tOUTH=0.00 ns
tOUTSU=0.3 ns
tGLH=2.6 ns
tCO=1.3 ns
FO = 32
t
LCO=5.2 ns (light loads, pad-to-pad)
Notes: * Values are shown for A42MX36 ‘–3’ at 5.0V worst-case commercial conditions.
** Load-dependent
Figure 1-19 • 42MX Timing Model (Logic Functions Using Quadrant Clocks)
Input Delays
I/O Module
tINPY=1.0ns
D
tIRD1=2.0ns
Q
G
tINSU=0.5ns
tINH=0.0ns
tINGO=1.4ns
Predicted
Routing
Delays
WD [7:0]
WRAD [5:0]
RD [7:0]
RDAD [5:0]
Array
Clocks
tADSU=1.6ns
tADH=0.0ns
tWENSU=2.7ns
tBENS=2.8ns
tRD1=0.9ns
REN
BLKEN
WEN
WCLK
RCLK
tADSU=1.6ns
tADH=0.0ns
tRENSU=0.6ns
tRCO=3.4ns
FMAX =167 MHz
Note: *Values are shown for A42MX36 ‘–3 at 5.0V worst-case commercial conditions.
Figure 1-20 • 42MX Timing Model (SRAM Functions)
1 -2 4
I/O Module
tDLH=2.6ns
v6.0
D
Q
G
tGHL=2.9ns
tLSU=0.5ns
tLH=0.0ns
40MX and 42MX FPGA Families
Parameter Measurement
E
D
In
50% 50%
VOH
1.5V
PAD
1.5V
VOL
tDHL
tDLH
TRIBUFF
PAD To AC test loads (shown below)
E
50% 50%
VCCI
1.5V
PAD
10%
VOL
tENZL
tENLZ
E
50% 50%
VOH
PAD
90%
1.5V
GND
tENHZ
tENZH
Figure 1-21 • Output Buffer Delays
Load 1
(Used to measure propagation delay)
Load 2
(Used to measure rising/falling edges)
VC CI
To the output under test
GND
R to VCCI for tPLZ/tPZL
R to GND for tPHZ/tPZH
R=1k Ω
35 pF
To the output under test
35 pF
Figure 1-22 • AC Test Loads
INBUF
PAD
S
A
B
Y
Y
S, A or B 50% 50%
PAD
Y
GND
3V
1.5V 1.5V
VCCI
50%
tINYH
Y
0V
50%
Y
tPLH
50%
tPHL
tINYL
50%
50%
PHL
50%
tPLH
Figure 1-24 • Module Delays
Figure 1-23 • Input Buffer Delays
v6.0
1-25
40MX and 42MX FPGA Families
Sequential Module Timing Characteristics
D
E
CLK
PRE
Y
CLR
(Positive Edge-Triggered)
tHD
D*
tSUD
tA
t
WCLKA
G, CLK
tWCLKI
tSUENA
tHENA
E
tCO
Q
tRS
PRE, CLR
tWASYN
Note: *D represents all data functions involving A, B, and S for multiplexed flip-flops.
Figure 1-25 • Flip-Flops and Latches
1 -2 6
v6.0
40MX and 42MX FPGA Families
Sequential Timing Characteristics
PAD
DATA
IBDL
G
CLK
PAD
DATA
tINH
G
tINSU
tH EXT
CLK
tSU EXT
Figure 1-26 • Input Buffer Latches
D
PAD
OBDLHS
G
D
tOUTSU
G
tOUTH
Figure 1-27 • Output Buffer Latches
v6.0
1-27
40MX and 42MX FPGA Families
Decode Module Timing
A
B
C
D
E
F
G
Y
H
A–G, H
50%
Y
tPHL
tPLH
Figure 1-28 • Decode Module Timing
SRAM Timing Characteristics
Read Port
Write Port
WRAD [5:0]
BLKEN
WEN
RDAD [5:0]
RAM Array
LEW
3 2x8 or 64x4
REN
(2 56 Bits)
WCLK
RCLK
WD [7:0]
RD [7:0]
Figure 1-29 • SRAM Timing Characteristics
Dual-Port SRAM Timing Waveforms
t RCKHL
WCLK
t ADSU
WD[7:0]
WRAD[5:0]
tADH
Valid
t WENSU
t WENH
t BENSU
t BENH
WEN
BLKEN
Valid
Note: Identical timing for falling edge clock.
Figure 1-30 • 42MX SRAM Write Operation
1 -2 8
v6.0
t RCKHL
40MX and 42MX FPGA Families
tCKHL
tRCKHL
RCLK
tRENSU
tRENH
REN
tADSU
tADH
Valid
RDAD[5:0]
tRCO
tDOH
New Data
Old Data
RD[7:0]
Note: Identical timing for falling edge clock.
Figure 1-31 • 42MX SRAM Synchronous Read Operation
t
RDAD[5:0]
RDADV
ADDR1
ADDR2
t RPD
t DOH
Data 1
RD[7:0]
Data 2
Figure 1-32 • 42MX SRAM Asynchronous Read Operation—Type 1 (Read Address Controlled)
WEN
WD[7:0]
WRAD[5:0]
BLKEN
tWENH
tWENSU
Valid
tADH
tADSU
WCLK
tRPD
tDOH
RD[7:0]
Old Data
New Data
Figure 1-33 • 42MX SRAM Asynchronous Read Operation—Type 2 (Write Address Controlled)
v6.0
1-29
40MX and 42MX FPGA Families
Predictable Performance: Tight Delay Distributions
Propagation delay between logic modules depends on
the resistive and capacitive loading of the routing tracks,
the interconnect elements, and the module inputs being
driven. Propagation delay increases as the length of
routing tracks, the number of interconnect elements, or
the number of inputs increases.
From a design perspective, the propagation delay can be
statistically correlated or modeled by the fanout
(number of loads) driven by a module. Higher fanout
usually requires some paths to have longer routing
tracks.
The MX FPGAs deliver a tight fanout delay distribution,
which is achieved in two ways: by decreasing the delay of
the interconnect elements and by decreasing the number
of interconnect elements per path.
Actel’s patented antifuse offers a very low resistive/
capacitive interconnect. The antifuses, fabricated in
0.45 µm lithography, offer nominal levels of 100Ω
resistance and 7.0fF capacitance per antifuse.
MX fanout distribution is also tight due to the low
number of antifuses required for each interconnect path.
The proprietary architecture limits the number of
antifuses per path to a maximum of four, with
90 percent of interconnects using only two antifuses.
Timing Characteristics
Device timing characteristics fall into three categories:
family-dependent, device-dependent, and designdependent. The input and output buffer characteristics
are common to all MX devices. Internal routing delays
are device-dependent; actual delays are not determined
until after place-and-route of the user's design is
complete. Delay values may then be determined by using
the Designer software utility or by performing
simulation with post-layout delays.
1 -3 0
v6.0
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets,
which are used for initial design performance evaluation.
Critical net delays can then be applied to the most timing
critical paths. Critical nets are determined by net
property assignment in Actel's Designer software prior to
placement and routing. Up to 6% of the nets in a design
may be designated as critical.
Long Tracks
Some nets in the design use long tracks, which are
special routing resources that span multiple rows,
columns, or modules. Long tracks employ three and
sometimes four antifuse connections, which increase
capacitance and resistance, resulting in longer net delays
for macros connected to long tracks. Typically, up to
6 percent of nets in a fully utilized device require long
tracks. Long tracks add approximately a 3 ns to a 6 ns
delay, which is represented statistically in higher fanout
(FO=8) routing delays in the data sheet specifications
section, shown in Table 28 on page 1-36.
Timing Derating
MX devices are manufactured with a CMOS process.
Therefore, device performance varies according to
temperature, voltage, and process changes. Minimum
timing parameters reflect maximum operating voltage,
minimum operating temperature and best-case
processing. Maximum timing parameters reflect
minimum operating voltage, maximum operating
temperature and worst-case processing.
40MX and 42MX FPGA Families
Temperature and Voltage Derating Factors
Table 22 •
42MX Temperature and Voltage Derating Factors
(Normalized to TJ = 25°C, VCCA = 5.0V)
Temperature
42MX Voltage
–55°C
–40°C
0°C
25°C
70°C
85°C
125°C
4.50
0.93
0.95
1.05
1.09
1.25
1.29
1.41
4.75
0.88
0.90
1.00
1.03
1.18
1.22
1.34
5.00
0.85
0.87
0.96
1.00
1.15
1.18
1.29
5.25
0.84
0.86
0.95
0.97
1.12
1.14
1.28
5.50
0.83
0.85
0.94
0.96
1.10
1.13
1.26
1.50
1.40
Factor
1.30
–55˚C
1.20
–40˚C
Derating
1.10
0˚C
1.00
25˚C
0.90
70˚C
0.80
85˚C
0.70
125˚C
0.60
4.50
4.75
5.00
Voltage
5.25
5.50
(V)
Note: This derating factor applies to all routing and propagation delays.
Figure 1-34 • 42MX Junction Temperature and Voltage Derating Curves
(Normalized to TJ = 25°C, VCCA = 5.0V)
v6.0
1-31
40MX and 42MX FPGA Families
Table 23 •
40MX Temperature and Voltage Derating Factors
(Normalized to TJ = 25°C, VCC = 5.0V)
Temperature
40MX Voltage
–55°C
–40°C
0°C
25°C
70°C
85°C
125°C
4.50
0.89
0.93
1.02
1.09
1.25
1.31
1.45
4.75
0.84
0.88
0.97
1.03
1.18
1.24
1.37
5.00
0.82
0.85
0.94
1.00
1.15
1.20
1.33
5.25
0.80
0.82
0.91
0.97
1.12
1.16
1.29
5.50
0.79
0.82
0.90
0.96
1.10
1.15
1.28
1.50
1.40
Derating
Factor
1.30
–55˚C
1.20
–40˚C
1.10
0˚C
1.00
25˚C
0.90
70˚C
0.80
85˚C
0.70
125˚C
0.60
4.50
4.75
5.00
Voltage
5.25
(V)
Note: This derating factor applies to all routing and propagation delays.
Figure 1-35 • 40MX Junction Temperature and Voltage Derating Curves
(Normalized to TJ = 25°C, VCC = 5.0V)
1 -3 2
v6.0
5.50
40MX and 42MX FPGA Families
Table 24 •
42MX Temperature and Voltage Derating Factors
(Normalized to TJ = 25°C, VCCA = 3.3V)
Temperature
42MX Voltage
–55°C
–40°C
0°C
25°C
70°C
85°C
125°C
3.00
0.97
1.00
1.10
1.15
1.32
1.36
1.45
3.30
0.84
0.87
0.96
1.00
1.15
1.18
1.26
3.60
0.81
0.84
0.92
0.96
1.10
1.13
1.21
1.60
1.50
Derating Factor
1.40
1.30
55˚C
1.20
40˚C
1.10
0˚C
1.00
25˚C
0.90
70˚C
0.80
85˚C
0.70
125˚C
0.60
0.50
0.40
3.00
3.30
3.60
Voltage (V)
(V)
Note: This derating factor applies to all routing and propagation delays.
Figure 1-36 • 42MX Junction Temperature and Voltage Derating Curves
(Normalized to TJ = 25°C, VCCA = 3.3V)
v6.0
1-33
40MX and 42MX FPGA Families
Table 25 •
40MX Temperature and Voltage Derating Factors
(Normalized to TJ = 25°C, VCC = 3.3V)
Temperature
40MX Voltage
–55°C
–40°C
0°C
25°C
70°C
85°C
125°C
3.00
1.08
1.12
1.21
1.26
1.50
1.64
2.00
3.30
0.86
0.89
0.96
1.00
1.19
1.30
1.59
3.60
0.83
0.85
0.92
0.96
1.14
1.25
1.53
2.20
2.00
55˚C
Derating Factor
1.80
40˚C
0˚C
1.60
25˚C
1.40
70˚C
1.20
85˚C
1.00
125˚C
0.80
0.60
3.00
3.30
Voltage (V)
Note: This derating factor applies to all routing and propagation delays.
Figure 1-37 • 40MX Junction Temperature and Voltage Derating Curves
(Normalized to TJ = 25°C, VCC = 3.3V)
1 -3 4
v6.0
3.60
40MX and 42MX FPGA Families
PCI System Timing Specification
PCI Models
Table 26 and Table 27 list the critical PCI timing
parameters and the corresponding timing parameters
for the MX PCI-compliant devices.
Actel provides synthesizable VHDL and Verilog-HDL
models for a PCI Target interface, a PCI Target and
Target+DMA Master interface. Contact your Actel sales
representative for more details.
Table 26 •
Clock Specification for 33 MHz PCI
PCI
Symbol
Parameter
tCYC
A42MX24
A42MX36
Min.
Max.
Min.
Max.
Min.
Max.
Units
CLK Cycle Time
30
–
4.0
–
4.0
–
ns
tHIGH
CLK High Time
11
–
1.9
–
1.9
–
ns
tLOW
CLK Low Time
11
–
1.9
–
1.9
–
ns
Table 27 •
Timing Parameters for 33 MHz PCI
PCI
Symbol
Parameter
tVAL
CLK to Signal Valid—Bused Signals
A42MX24
A42MX36
Min.
Max.
Min.
Max.
Min.
Max.
Units
2
11
2.0
9.0
2.0
9.0
ns
12
2.0
9.0
2.0
9.0
ns
2
tVAL(PTP)
CLK to Signal Valid—Point-to-Point
tON
Float to Active
2
–
2.0
4.0
2.0
4.0
ns
tOFF
Active to Float
–
28
–
8.31
–
8.31
ns
tSU
Input Set-Up Time to CLK—Bused Signals
7
–
1.5
–
1.5
–
ns
–
1.5
–
1.5
–
ns
–
0
–
0
–
ns
tSU(PTP)
Input Set-Up Time to CLK—Point-to-Point
tH
Input Hold to CLK
2
10, 12
0
2
Notes:
1. TOFF is system dependent. MX PCI devices have 7.4 ns turn-off time, reflection is typically an additional 10 ns.
2. REQ# and GNT# are point-to-point signals and have different output valid delay and input setup times than do bussed signals.
GNT# has a setup of 10; REW# has a setup of 12.
v6.0
1-35
40MX and 42MX FPGA Families
Timing Characteristics
Table 28 •
A40MX02 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, VCC = 4.75V, TJ = 70°C)
‘–3’ Speed
Parameter Description
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Propagation Delays
tPD1
Single Module
1.2
1.4
1.6
1.9
2.7
ns
tPD2
Dual-Module Macros
2.7
3.1
3.5
4.1
5.7
ns
tCO
Sequential Clock-to-Q
1.2
1.4
1.6
1.9
2.7
ns
tGO
Latch G-to-Q
1.2
1.4
1.6
1.9
2.7
ns
tRS
Flip-Flop (Latch) Reset-to-Q
1.2
1.4
1.6
1.9
2.7
ns
Logic Module Predicted Routing
Delays1
tRD1
FO=1 Routing Delay
1.3
1.5
1.7
2.0
2.8
ns
tRD2
FO=2 Routing Delay
1.8
2.1
2.4
2.8
3.9
ns
tRD3
FO=3 Routing Delay
2.3
2.7
3.0
3.6
5.0
ns
tRD4
FO=4 Routing Delay
2.9
3.3
3.7
4.4
6.1
ns
tRD8
FO=8 Routing Delay
4.9
5.7
6.5
7.6
10.6
ns
Logic Module Sequential Timing2
tSUD
Flip-Flop (Latch) Data Input Set-Up
3.1
3.5
4.0
4.7
6.6
ns
tHD3
Flip-Flop (Latch) Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
3.1
3.5
4.0
4.7
6.6
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch)
Clock Active Pulse Width
3.3
3.8
4.3
5.0
7.0
ns
tWASYN
Flip-Flop (Latch)
Asynchronous Pulse Width
3.3
3.8
4.3
5.0
7.0
ns
tA
Flip-Flop Clock Input Period
4.8
5.6
6.3
7.5
10.4
ns
fMAX
Flip-Flop (Latch) Clock
Frequency (FO = 128)
181
168
154
134
80
MHz
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
0.7
0.8
0.9
1.1
1.5
ns
tINYL
Pad-to-Y LOW
0.6
0.7
0.8
1.0
1.3
ns
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold
time for this macro.
4. Delays based on 35pF loading.
1 -3 6
v6.0
40MX and 42MX FPGA Families
Table 28 •
A40MX02 Timing Characteristics (Nominal 5.0V Operation) (Continued)
(Worst-Case Commercial Conditions, VCC = 4.75V, TJ = 70°C)
‘–3’ Speed
Parameter Description
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Module Predicted Routing Delays
1
tIRD1
FO=1 Routing Delay
2.1
2.4
2.2
3.2
4.5
ns
tIRD2
FO=2 Routing Delay
2.6
3.0
3.4
4.0
5.6
ns
tIRD3
FO=3 Routing Delay
3.1
3.6
4.1
4.8
6.7
ns
tIRD4
FO=4 Routing Delay
3.6
4.2
4.8
5.6
7.8
ns
tIRD8
FO=8 Routing Delay
5.7
6.6
7.5
8.8
12.4
ns
Global Clock Network
tCKH
Input Low to HIGH
FO = 16
FO = 128
4.6
4.6
5.3
5.3
6.0
6.0
7.0
7.0
9.8
9.8
ns
tCKL
Input High to LOW
FO = 16
FO = 128
4.8
4.8
5.6
5.6
6.3
6.3
7.4
7.4
10.4
10.4
ns
tPWH
Minimum Pulse
Width HIGH
FO = 16
FO = 128
2.2
2.4
2.6
2.7
2.9
3.1
3.4
3.6
4.8
5.1
ns
tPWL
Minimum Pulse
Width LOW
FO = 16
FO = 128
2.2
2.4
2.6
2.7
2.9
3.01
3.4
3.6
4.8
5.1
ns
tCKSW
Maximum Skew
FO = 16
FO = 128
tP
Minimum Period
FO = 16
FO = 128
fMAX
Maximum
Frequency
FO = 16
FO = 128
0.4
0.5
4.7
4.8
0.5
0.6
5.4
5.6
188
181
0.5
0.7
6.1
6.3
175
168
0.6
0.8
7.2
7.5
160
154
0.8
1.2
10.0
10.4
139
134
ns
ns
83
80
MHz
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold
time for this macro.
4. Delays based on 35pF loading.
v6.0
1-37
40MX and 42MX FPGA Families
Table 28 •
A40MX02 Timing Characteristics (Nominal 5.0V Operation) (Continued)
(Worst-Case Commercial Conditions, VCC = 4.75V, TJ = 70°C)
‘–3’ Speed
Parameter Description
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
TTL Output Module Timing
4
tDLH
Data-to-Pad HIGH
3.3
3.8
4.3
5.1
7.2
ns
tDHL
Data-to-Pad LOW
4.0
4.6
5.2
6.1
8.6
ns
tENZH
Enable
HIGH
Pad
Z
to
3.7
4.3
4.9
5.8
8.0
ns
tENZL
Enable
LOW
Pad
Z
to
4.7
5.4
6.1
7.2
10.1
ns
tENHZ
Enable Pad HIGH to
Z
7.9
9.1
10.4
12.2
17.1
ns
tENLZ
Enable Pad LOW to
Z
5.9
6.8
7.7
9.0
12.6
ns
dTLH
Delta LOW to HIGH
0.02
0.02
0.03
0.03
0.04
ns/pF
dTHL
Delta HIGH to LOW
0.03
0.03
0.03
0.04
0.06
ns/pF
CMOS Output Module Timing4
tDLH
Data-to-Pad HIGH
3.9
4.5
5.1
6.05
8.5
ns
tDHL
Data-to-Pad LOW
3.4
3.9
4.4
5.2
7.3
ns
tENZH
Enable
HIGH
Pad
Z
to
3.4
3.9
4.4
5.2
7.3
ns
tENZL
Enable
LOW
Pad
Z
to
4.9
5.6
6.4
7.5
10.5
ns
tENHZ
Enable Pad HIGH to
Z
7.9
9.1
10.4
12.2
17.0
ns
tENLZ
Enable Pad LOW to
Z
5.9
6.8
7.7
9.0
12.6
ns
dTLH
Delta LOW to HIGH
0.03
0.04
0.04
0.05
0.07
ns/pF
dTHL
Delta HIGH to LOW
0.02
0.02
0.03
0.03
0.04
ns/pF
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold
time for this macro.
4. Delays based on 35pF loading.
1 -3 8
v6.0
40MX and 42MX FPGA Families
Table 29 •
A40MX02 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions, VCC = 3.0V, TJ = 70°C)
‘–3’ Speed
Parameter Description
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Propagation Delays
tPD1
Single Module
1.7
2.0
2.3
2.7
3.7
ns
tPD2
Dual-Module Macros
3.7
4.3
4.9
5.7
8.0
ns
tCO
Sequential Clock-to-Q
1.7
2.0
2.3
2.7
3.7
ns
tGO
Latch G-to-Q
1.7
2.0
2.3
2.7
3.7
ns
tRS
Flip-Flop (Latch) Reset-to-Q
1.7
2.0
2.3
2.7
3.7
ns
1
Logic Module Predicted Routing Delays
tRD1
FO=1 Routing Delay
2.0
2.2
2.5
3.0
4.2
ns
tRD2
FO=2 Routing Delay
2.7
3.1
3.5
4.1
5.7
ns
tRD3
FO=3 Routing Delay
3.4
3.9
4.4
5.2
7.3
ns
tRD4
FO=4 Routing Delay
4.2
4.8
5.4
6.3
8.9
ns
tRD8
FO=8 Routing Delay
7.1
8.2
9.2
10.9
15.2
ns
2
Logic Module Sequential Timing
tSUD
Flip-Flop (Latch) Data Input Set-Up
4.3
4.9
5.6
6.6
9.2
ns
tHD3
Flip-Flop (Latch) Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
4.3
4.9
5.6
6.6
9.2
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active
Pulse Width
4.6
5.3
6.0
7.0
9.8
ns
tWASYN
Flip-Flop (Latch)
Asynchronous Pulse Width
4.6
5.3
6.0
7.0
9.8
ns
tA
Flip-Flop Clock Input Period
6.8
7.8
8.9
10.4
14.6
ns
fMAX
Flip-Flop (Latch) Clock
Frequency (FO = 128)
109
101
92
80
48
MHz
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
1.0
1.1
1.3
1.5
2.1
ns
tINYL
Pad-to-Y LOW
0.9
1.0
1.1
1.3
1.9
ns
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold
time for this macro.
4. Delays based on 35 pF loading.
v6.0
1-39
40MX and 42MX FPGA Families
Table 29 •
A40MX02 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, VCC = 3.0V, TJ = 70°C)
‘–3’ Speed
Parameter Description
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Module Predicted Routing Delays
1
tIRD1
FO=1 Routing Delay
2.9
3.4
3.8
4.5
6.3
ns
tIRD2
FO=2 Routing Delay
3.6
4.2
4.8
5.6
7.8
ns
tIRD3
FO=3 Routing Delay
4.4
5.0
5.7
6.7
9.4
ns
tIRD4
FO=4 Routing Delay
5.1
5.9
6.7
7.8
11.0
ns
tIRD8
FO=8 Routing Delay
8.0
9.26
10.5
12.6
17.3
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO = 16
FO = 128
6.4
6.4
7.4
7.4
8.3
8.3
9.8
9.8
13.7
13.7
ns
tCKL
Input HIGH to LOW
FO = 16
FO = 128
6.7
6.7
7.8
7.8
8.8
8.8
10.4
10.4
14.5
14.5
ns
tPWH
Minimum Pulse
Width HIGH
FO = 16
FO = 128
3.1
3.3
3.6
3.8
4.1
4.3
4.8
5.1
6.7
7.1
ns
tPWL
Minimum Pulse
Width LOW
FO = 16
FO = 128
3.1
3.3
3.6
3.8
4.1
4.3
4.8
5.1
6.7
7.1
ns
tCKSW
Maximum Skew
FO = 16
FO = 128
tP
Minimum Period
FO = 16
FO = 128
fMAX
Maximum Frequency FO = 16
FO = 128
0.6
0.8
6.5
6.8
0.6
0.9
7.5
7.8
0.7
1.0
8.5
8.9
0.8
1.2
10.1
10.4
1.2
1.6
14.1
14.6
ns
ns
113
109
105
101
96
92
83
80
50
48
MHz
TTL Output Module Timing4
tDLH
Data-to-Pad HIGH
4.7
5.4
6.1
7.2
10.0
ns
tDHL
Data-to-Pad LOW
5.6
6.4
7.3
8.6
12.0
ns
tENZH
Enable Pad Z to HIGH
5.2
6.0
6.8
8.1
11.3
ns
tENZL
Enable Pad Z to LOW
6.6
7.6
8.6
10.1
14.1
ns
tENHZ
Enable Pad HIGH to Z
11.1
12.8
14.5
17.1
23.9
ns
tENLZ
Enable Pad LOW to Z
8.2
9.5
10.7
12.6
17.7
ns
dTLH
Delta LOW to HIGH
0.03
0.03
0.04
0.04
0.06
ns/pF
dTHL
Delta HIGH to LOW
0.04
0.04
0.05
0.06
0.08
ns/pF
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold
time for this macro.
4. Delays based on 35 pF loading.
1 -4 0
v6.0
40MX and 42MX FPGA Families
Table 29 •
A40MX02 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, VCC = 3.0V, TJ = 70°C)
‘–3’ Speed
Parameter Description
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
4
CMOS Output Module Timing
tDLH
Data-to-Pad HIGH
5.5
6.4
7.2
8.5
11.9
ns
tDHL
Data-to-Pad LOW
4.8
5.5
6.2
7.3
10.2
ns
tENZH
Enable Pad Z to HIGH
4.7
5.5
6.2
7.3
10.2
ns
tENZL
Enable Pad Z to LOW
6.8
7.9
8.9
10.5
14.7
ns
tENHZ
Enable Pad HIGH to Z
11.1
12.8
14.5
17.1
23.9
ns
tENLZ
Enable Pad LOW to Z
8.2
9.5
10.7
12.6
17.7
ns
dTLH
Delta LOW to HIGH
0.05
0.05
0.06
0.07
0.10
ns/pF
dTHL
Delta HIGH to LOW
0.03
0.03
0.04
0.04
0.06
ns/pF
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold
time for this macro.
4. Delays based on 35 pF loading.
v6.0
1-41
40MX and 42MX FPGA Families
Table 30 •
A40MX04 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, VCC = 4.75V, TJ = 70°C)
‘–3’ Speed
Parameter Description
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Propagation Delays
tPD1
Single Module
1.2
1.4
1.6
1.9
2.7
ns
tPD2
Dual-Module Macros
2.3
3.1
3.5
4.1
5.7
ns
tCO
Sequential Clock-to-Q
1.2
1.4
1.6
1.9
2.7
ns
tGO
Latch G-to-Q
1.2
1.4
1.6
1.9
2.7
ns
tRS
Flip-Flop (Latch) Reset-to-Q
1.2
1.4
1.6
1.9
2.7
ns
1
Logic Module Predicted Routing Delays
tRD1
FO=1 Routing Delay
1.2
1.6
1.8
2.1
3.0
ns
tRD2
FO=2 Routing Delay
1.9
2.2
2.5
2.9
4.1
ns
tRD3
FO=3 Routing Delay
2.4
2.8
3.2
3.7
5.2
ns
tRD4
FO=4 Routing Delay
2.9
3.4
3.9
4.5
6.3
ns
tRD8
FO=8 Routing Delay
5.0
5.8
6.6
7.8
10.9
ns
2
Logic Module Sequential Timing
tSUD
Flip-Flop (Latch) Data Input Set-Up
3.1
3.5
4.0
4.7
6.6
ns
tHD3
Flip-Flop (Latch) Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
3.1
3.5
4.0
4.7
6.6
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active
Pulse Width
3.3
3.8
4.3
5.0
7.0
ns
tWASYN
Flip-Flop (Latch)
Asynchronous Pulse Width
3.3
3.8
4.3
5.0
7.0
ns
tA
Flip-Flop Clock Input Period
4.8
5.6
6.3
7.5
10.4
ns
fMAX
Flip-Flop (Latch) Clock Frequency
(FO = 128)
181
167
154
134
80
MHz
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
0.7
0.8
0.9
1.1
1.5
ns
tINYL
Pad-to-Y LOW
0.6
0.7
0.8
1.0
1.3
ns
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer utility from the Designer software to check the hold
time for this macro.
4. Delays based on 35 pF loading.
1 -4 2
v6.0
40MX and 42MX FPGA Families
Table 30 •
A40MX04 Timing Characteristics (Nominal 5.0V Operation) (Continued)
(Worst-Case Commercial Conditions, VCC = 4.75V, TJ = 70°C)
‘–3’ Speed
Parameter Description
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Module Predicted Routing Delays
1
tIRD1
FO=1 Routing Delay
2.1
2.4
2.2
3.2
4.5
ns
tIRD2
FO=2 Routing Delay
2.6
3.0
3.4
4.0
5.6
ns
tIRD3
FO=3 Routing Delay
3.1
3.6
4.1
4.8
6.7
ns
tIRD4
FO=4 Routing Delay
3.6
4.2
4.8
5.6
7.8
ns
tIRD8
FO=8 Routing Delay
5.7
6.6
7.5
8.8
12.4
ns
Global Clock Network
tCKH
Input Low to HIGH
FO = 16
FO = 128
4.6
4.6
5.3
5.3
6.0
6.0
7.0
7.0
9.8
9.8
ns
tCKL
Input High to LOW
FO = 16
FO = 128
4.8
4.8
5.6
5.6
6.3
6.3
7.4
7.4
10.4
10.4
ns
tPWH
Minimum
Width HIGH
Pulse FO = 16
FO = 128
2.2
2.4
2.6
2.7
2.9
3.1
3.4
3.6
4.8
5.1
ns
tPWL
Minimum
Width LOW
Pulse FO = 16
FO = 128
2.2
2.4
2.6
2.7
2.9
3.01
3.4
3.6
4.8
5.1
ns
tCKSW
Maximum Skew
FO = 16
FO = 128
tP
Minimum Period
FO = 16
FO = 128
fMAX
Maximum
Frequency
FO = 16
FO = 128
0.4
0.5
4.7
4.8
0.5
0.6
5.4
5.6
0.5
0.7
6.1
6.3
0.6
0.8
7.2
7.5
0.8
1.2
10.0
10.4
188
181
175
168
160
154
139
134
ns
ns
83
80
MHz
TTL Output Module Timing4
tDLH
Data-to-Pad HIGH
3.3
3.8
4.3
5.1
7.2
ns
tDHL
Data-to-Pad LOW
4.0
4.6
5.2
6.1
8.6
ns
tENZH
Enable Pad Z to HIGH
3.7
4.3
4.9
5.8
8.0
ns
tENZL
Enable Pad Z to LOW
4.7
5.4
6.1
7.2
10.1
ns
tENHZ
Enable Pad HIGH to Z
7.9
9.1
10.4
12.2
17.1
ns
tENLZ
Enable Pad LOW to Z
5.9
6.8
7.7
9.0
12.6
ns
dTLH
Delta LOW to HIGH
0.02
0.02
0.03
0.03
0.04
ns/pF
dTHL
Delta HIGH to LOW
0.03
0.03
0.03
0.04
0.06
ns/pF
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer utility from the Designer software to check the hold
time for this macro.
4. Delays based on 35 pF loading.
v6.0
1-43
40MX and 42MX FPGA Families
Table 30 •
A40MX04 Timing Characteristics (Nominal 5.0V Operation) (Continued)
(Worst-Case Commercial Conditions, VCC = 4.75V, TJ = 70°C)
‘–3’ Speed
Parameter Description
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
1
CMOS Output Module Timing
tDLH
Data-to-Pad HIGH
3.9
4.5
5.1
6.05
8.5
ns
tDHL
Data-to-Pad LOW
3.4
3.9
4.4
5.2
7.3
ns
tENZH
Enable Pad Z to HIGH
3.4
3.9
4.4
5.2
7.3
ns
tENZL
Enable Pad Z to LOW
4.9
5.6
6.4
7.5
10.5
ns
tENHZ
Enable Pad HIGH to Z
7.9
9.1
10.4
12.2
17.0
ns
tENLZ
Enable Pad LOW to Z
5.9
6.8
7.7
9.0
12.6
ns
dTLH
Delta LOW to HIGH
0.03
0.04
0.04
0.05
0.07
ns/pF
dTHL
Delta HIGH to LOW
0.02
0.02
0.03
0.03
0.04
ns/pF
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer utility from the Designer software to check the hold
time for this macro.
4. Delays based on 35 pF loading.
1 -4 4
v6.0
40MX and 42MX FPGA Families
Table 31 •
A40MX04 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions, VCC = 3.0V, TJ = 70°C)
‘–3’ Speed
Parameter Description
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Propagation Delays
tPD1
Single Module
1.7
2.0
2.3
2.7
3.7
ns
tPD2
Dual-Module Macros
3.7
4.3
4.9
5.7
8.0
ns
tCO
Sequential Clock-to-Q
1.7
2.0
2.3
2.7
3.7
ns
tGO
Latch G-to-Q
1.7
2.0
2.3
2.7
3.7
ns
tRS
Flip-Flop (Latch) Reset-to-Q
1.7
2.0
2.3
2.7
3.7
ns
1
Logic Module Predicted Routing Delays
tRD1
FO=1 Routing Delay
1.9
2.2
2.5
3.0
4.2
ns
tRD2
FO=2 Routing Delay
2.7
3.1
3.5
4.1
5.7
ns
tRD3
FO=3 Routing Delay
3.4
3.9
4.4
5.2
7.3
ns
tRD4
FO=4 Routing Delay
4.1
4.8
5.4
6.3
8.9
ns
tRD8
FO=8 Routing Delay
7.1
8.1
9.2
10.9
15.2
ns
2
Logic Module Sequential Timing
tSUD
Flip-Flop (Latch) Data Input Set-Up
4.3
5.0
5.6
6.6
9.2
ns
tHD3
Flip-Flop (Latch) Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
4.3
5.0
5.6
6.6
9.2
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active
Pulse Width
4.6
5.3
5.6
7.0
9.8
ns
tWASYN
Flip-Flop (Latch)
Asynchronous Pulse Width
4.6
5.3
5.6
7.0
9.8
ns
tA
Flip-Flop Clock Input Period
6.8
7.8
8.9
10.4
14.6
ns
fMAX
Flip-Flop (Latch) Clock Frequency
(FO = 128)
109
101
92
80
48
MHz
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
1.0
1.1
1.3
1.5
2.1
ns
tINYL
Pad-to-Y LOW
0.9
1.0
1.1
1.3
1.9
ns
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold
time for this macro.
4. Delays based on 35 pF loading.
v6.0
1-45
40MX and 42MX FPGA Families
Table 31 •
A40MX04 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, VCC = 3.0V, TJ = 70°C)
‘–3’ Speed
Parameter Description
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Module Predicted Routing Delays
1
tIRD1
FO=1 Routing Delay
2.9
3.3
3.8
4.5
6.3
ns
tIRD2
FO=2 Routing Delay
3.6
4.2
4.8
5.6
7.8
ns
tIRD3
FO=3 Routing Delay
4.4
5.0
5.7
6.7
9.4
ns
tIRD4
FO=4 Routing Delay
5.1
5.9
6.7
7.8
11.0
ns
tIRD8
FO=8 Routing Delay
8.0
9.3
10.5
12.4
17.2
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO = 16
FO = 128
6.4
6.4
7.4
7.4
8.4
8.4
9.9
9.9
13.8
13.8
ns
tCKL
Input HIGH to LOW
FO = 16
FO = 128
6.8
6.8
7.8
7.8
8.9
8.9
10.4
10.4
14.6
14.6
ns
tPWH
Minimum Pulse
Width HIGH
FO = 16
FO = 128
3.1
3.3
3.6
3.8
4.1
4.3
4.8
5.1
6.7
7.1
ns
tPWL
Minimum Pulse
Width LOW
FO = 16
FO = 128
3.1
3.3
3.6
3.8
4.1
4.3
4.8
5.1
6.7
7.1
ns
tCKSW
Maximum Skew
FO = 16
FO = 128
tP
Minimum Period
FO = 16
FO = 128
fMAX
Maximum Frequency FO = 16
FO = 128
0.6
0.8
6.5
6.8
0.6
0.9
7.5
7.8
0.7
1.0
8.5
8.9
0.8
1.2
10.1
10.4
1.2
1.6
14.1
14.6
ns
ns
113
109
105
101
96
92
83
80
50
48
MHz
TTL Output Module Timing4
tDLH
Data-to-Pad HIGH
4.7
5.4
6.1
7.2
10.0
ns
tDHL
Data-to-Pad LOW
5.6
6.4
7.3
8.6
12.0
ns
tENZH
Enable Pad Z to HIGH
5.2
6.0
6.9
8.1
11.3
ns
tENZL
Enable Pad Z to LOW
6.6
7.6
8.6
10.1
14.1
ns
tENHZ
Enable Pad HIGH to Z
11.1
12.8
14.5
17.1
23.9
ns
tENLZ
Enable Pad LOW to Z
8.2
9.5
10.7
12.6
17.7
ns
dTLH
Delta LOW to HIGH
0.03
0.03
0.04
0.04
0.06
ns/pF
dTHL
Delta HIGH to LOW
0.04
0.04
0.05
0.06
0.08
ns/pF
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold
time for this macro.
4. Delays based on 35 pF loading.
1 -4 6
v6.0
40MX and 42MX FPGA Families
Table 31 •
A40MX04 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, VCC = 3.0V, TJ = 70°C)
‘–3’ Speed
Parameter Description
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
4
CMOS Output Module Timing
tDLH
Data-to-Pad HIGH
5.5
6.4
7.2
8.5
11.9
ns
tDHL
Data-to-Pad LOW
4.8
5.5
6.2
7.3
10.2
ns
tENZH
Enable Pad Z to HIGH
4.7
5.5
6.2
7.3
10.2
ns
tENZL
Enable Pad Z to LOW
6.8
7.9
8.9
10.5
14.7
ns
tENHZ
Enable Pad HIGH to Z
11.1
12.8
14.5
17.1
23.9
ns
tENLZ
Enable Pad LOW to Z
8.2
9.5
10.7
12.6
17.7
ns
dTLH
Delta LOW to HIGH
0.05
0.05
0.06
0.07
0.10
ns/pF
dTHL
Delta HIGH to LOW
0.03
0.03
0.04
0.04
0.06
ns/pF
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold
time for this macro.
4. Delays based on 35 pF loading.
v6.0
1-47
40MX and 42MX FPGA Families
Table 32 •
A42MX09 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75V, TJ = 70°C)
‘–3’ Speed
Parameter Description
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Propagation
Delays1
tPD1
Single Module
1.2
1.3
1.5
1.8
2.5
ns
tCO
Sequential Clock-to-Q
1.3
1.4
1.6
1.9
2.7
ns
tGO
Latch G-to-Q
1.2
1.4
1.6
1.8
2.6
ns
tRS
Flip-Flop (Latch) Reset-to-Q
1.2
1.6
1.8
2.1
2.9
ns
Logic Module Predicted Routing Delays2
tRD1
FO=1 Routing Delay
0.7
0.8
0.9
1.0
1.4
ns
tRD2
FO=2 Routing Delay
0.9
1.0
1.2
1.4
1.9
ns
tRD3
FO=3 Routing Delay
1.2
1.3
1.5
1.7
2.4
ns
tRD4
FO=4 Routing Delay
1.4
1.5
1.7
2.0
2.9
ns
tRD8
FO=8 Routing Delay
2.3
2.6
2.9
3.4
4.8
ns
Logic Module Sequential
Timing3, 4
tSUD
Flip-Flop (Latch) Data Input Set-Up
0.3
0.4
0.4
0.5
0.7
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
0.4
0.5
0.5
0.6
0.8
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active
Pulse Width
3.4
3.8
4.3
5.0
7.0
ns
tWASYN
Flip-Flop (Latch) Asynchronous
Pulse Width
4.5
4.9
5.6
6.6
9.2
ns
tA
Flip-Flop Clock Input Period
3.5
3.8
4.3
5.1
7.1
ns
tINH
Input Buffer Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tINSU
Input Buffer Latch Set-Up
0.3
0.3
0.4
0.4
0.6
ns
tOUTH
Output Buffer Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tOUTSU
Output Buffer Latch Set-Up
0.3
0.3
0.4
0.4
0.6
ns
fMAX
Flip-Flop (Latch) Clock Frequency
268
244
224
195
117
MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1 -4 8
v6.0
40MX and 42MX FPGA Families
Table 32 •
A42MX09 Timing Characteristics (Nominal 5.0V Operation) (Continued)
(Worst-Case Commercial Conditions, VCCA = 4.75V, TJ = 70°C)
‘–3’ Speed
Parameter Description
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
1.0
1.2
1.3
1.6
2.2
ns
tINYL
Pad-to-Y LOW
0.8
0.9
1.0
1.2
1.7
ns
tINGH
G to Y HIGH
1.3
1.4
1.6
1.9
2.7
ns
tINGL
G to Y LOW
1.3
1.4
1.6
1.9
2.7
ns
Input Module Predicted Routing Delays2
tIRD1
FO=1 Routing Delay
2.0
2.2
2.5
3.0
4.2
ns
tIRD2
FO=2 Routing Delay
2.3
2.5
2.9
3.4
4.7
ns
tIRD3
FO=3 Routing Delay
2.5
2.8
3.2
3.7
5.2
ns
tIRD4
FO=4 Routing Delay
2.8
3.1
3.5
4.1
5.7
ns
tIRD8
FO=8 Routing Delay
3.7
4.1
4.7
5.5
7.7
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO = 32
FO = 256
2.4
2.7
2.7
3.0
3.0
3.4
3.6
4.0
5.0
5.5
ns
ns
tCKL
Input HIGH to LOW
FO = 32
FO = 256
3.5
3.9
3.9
4.3
4.4
4.9
5.2
5.7
7.3
8.0
ns
ns
tPWH
Minimum Pulse
Width HIGH
FO = 32
FO = 256
1.2
1.3
1.4
1.5
1.5
1.7
1.8
2.0
2.5
2.7
ns
ns
tPWL
Minimum Pulse
Width LOW
FO = 32
FO = 256
1.2
1.3
1.4
1.5
1.5
1.7
1.8
2.0
2.5
2.7
ns
ns
tCKSW
Maximum Skew
FO = 32
FO = 256
tSUEXT
Input Latch External FO = 32
Set-Up
FO = 256
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
tHEXT
Input Latch External FO = 32
Hold
FO = 256
2.3
2.2
2.6
2.4
3.0
3.3
3.5
3.9
4.9
5.5
ns
ns
tP
Minimum Period
3.4
3.7
3.7
4.1
4.0
4.5
4.7
5.2
7.8
8.6
ns
ns
fMAX
Maximum Frequency FO = 32
FO = 256
FO = 32
FO = 256
0.3
0.3
0.3
0.3
296
268
269
244
0.4
0.4
247
224
0.5
0.5
215
195
0.6
0.6
129
117
ns
ns
MHz
MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
v6.0
1-49
40MX and 42MX FPGA Families
Table 32 •
A42MX09 Timing Characteristics (Nominal 5.0V Operation) (Continued)
(Worst-Case Commercial Conditions, VCCA = 4.75V, TJ = 70°C)
‘–3’ Speed
Parameter Description
TTL Output Module Timing
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
5
tDLH
Data-to-Pad HIGH
2.5
2.7
3.1
3.6
5.1
ns
tDHL
Data-to-Pad LOW
2.9
3.2
3.6
4.3
6.0
ns
tENZH
Enable Pad Z to HIGH
2.6
2.9
3.3
3.9
5.5
ns
tENZL
Enable Pad Z to LOW
2.9
3.2
3.7
4.3
6.1
ns
tENHZ
Enable Pad HIGH to Z
4.9
5.4
6.2
7.3
10.2
ns
tENLZ
Enable Pad LOW to Z
5.3
5.9
6.7
7.9
11.1
ns
tGLH
G-to-Pad HIGH
2.6
2.9
3.3
3.8
5.3
ns
tGHL
G-to-Pad LOW
2.6
2.9
3.3
3.8
5.3
ns
tLSU
I/O Latch Set-Up
0.5
0.5
0.6
0.7
1.0
ns
tLH
I/O Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-toPad), 64 Clock Loading
5.2
5.8
6.6
7.7
10.8
ns
tACO
Array Clock-to-Out (Pad-to-Pad),
64 Clock Loading
7.4
8.2
9.3
10.9
15.3
ns
dTLH
Capacity Loading, LOW to HIGH
0.03
0.03
0.03
0.04
0.06
ns/pF
dTHL
Capacity Loading, HIGH to LOW
0.04
0.04
0.04
0.05
0.07
ns/pF
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1 -5 0
v6.0
40MX and 42MX FPGA Families
Table 32 •
A42MX09 Timing Characteristics (Nominal 5.0V Operation) (Continued)
(Worst-Case Commercial Conditions, VCCA = 4.75V, TJ = 70°C)
‘–3’ Speed
Parameter Description
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
5
CMOS Output Module Timing
tDLH
Data-to-Pad HIGH
2.4
2.7
3.1
3.6
5.1
ns
tDHL
Data-to-Pad LOW
2.9
3.2
3.6
4.3
6.0
ns
tENZH
Enable Pad Z to HIGH
2.7
2.9
3.3
3.9
5.5
ns
tENZL
Enable Pad Z to LOW
2.9
3.2
3.7
4.3
6.1
ns
tENHZ
Enable Pad HIGH to Z
4.9
5.4
6.2
7.3
10.2
ns
tENLZ
Enable Pad LOW to Z
5.3
5.9
6.7
7.9
11.1
ns
tGLH
G-to-Pad HIGH
4.2
4.6
5.2
6.1
8.6
ns
tGHL
G-to-Pad LOW
4.2
4.6
5.2
6.1
8.6
ns
tLSU
I/O Latch Set-Up
0.5
0.5
0.6
0.7
1.0
ns
tLH
I/O Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-toPad), 64 Clock Loading
5.2
5.8
6.6
7.7
10.8
ns
tACO
Array Clock-to-Out (Pad-to-Pad),
64 Clock Loading
7.4
8.2
9.3
10.9
15.3
ns
dTLH
Capacity Loading, LOW to HIGH
0.03
0.03
0.03
0.04
0.06
ns/pF
dTHL
Capacity Loading, HIGH to LOW
0.04
0.04
0.04
0.05
0.07
ns/pF
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
v6.0
1-51
40MX and 42MX FPGA Families
Table 33 •
A42MX09 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions, VCCA = 3.0V, TJ = 70°C)
‘–3’ Speed
Parameter Description
Logic Module Propagation
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Delays1
tPD1
Single Module
1.6
1.8
2.1
2.5
3.5
ns
tCO
Sequential Clock-to-Q
1.8
2.0
2.3
2.7
3.8
ns
tGO
Latch G-to-Q
1.7
1.9
2.1
2.5
3.5
ns
tRS
Flip-Flop (Latch) Reset-to-Q
2.0
2.2
2.5
2.9
4.1
ns
Logic Module Predicted Routing Delays2
tRD1
FO=1 Routing Delay
1.0
1.1
1.2
1.4
2.0
ns
tRD2
FO=2 Routing Delay
1.3
1.4
1.6
1.9
2.7
ns
tRD3
FO=3 Routing Delay
1.6
1.8
2.0
2.4
3.3
ns
tRD4
FO=4 Routing Delay
1.9
2.1
2.4
2.9
4.0
ns
tRD8
FO=8 Routing Delay
3.2
3.6
4.1
4.8
6.7
ns
Logic Module Sequential Timing
3, 4
tSUD
Flip-Flop (Latch) Data Input Set-Up
0.5
0.5
0.6
0.7
0.9
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
0.6
0.6
0.7
0.8
1.2
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active
Pulse Width
4.7
5.3
6.0
7.0
9.8
ns
tWASYN
Flip-Flop (Latch) Asynchronous
Pulse Width
6.2
6.9
7.8
9.2
12.9
ns
tA
Flip-Flop Clock Input Period
5.0
5.6
6.2
7.1
9.9
ns
tINH
Input Buffer Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tINSU
Input Buffer Latch Set-Up
0.3
0.3
0.3
0.4
0.6
ns
tOUTH
Output Buffer Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tOUTSU
Output Buffer Latch Set-Up
0.3
0.3
0.3
0.4
0.6
ns
fMAX
Flip-Flop (Latch) Clock
Frequency
161
146
135
117
70
MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1 -5 2
v6.0
40MX and 42MX FPGA Families
Table 33 •
A42MX09 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, VCCA = 3.0V, TJ = 70°C)
‘–3’ Speed
Parameter Description
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
1.5
1.6
1.8
2.17
3.0
ns
tINYL
Pad-to-Y LOW
1.2
1.3
1.4
1.7
2.4
ns
tINGH
G to Y HIGH
1.8
2.0
2.3
2.7
3.7
ns
tINGL
G to Y LOW
1.8
2.0
2.3
2.7
3.7
ns
Input Module Predicted Routing Delays2
tIRD1
FO=1 Routing Delay
2.8
3.2
3.6
4.2
5.9
ns
tIRD2
FO=2 Routing Delay
3.2
3.5
4.0
4.7
6.6
ns
tIRD3
FO=3 Routing Delay
3.5
3.9
4.4
5.2
7.3
ns
tIRD4
FO=4 Routing Delay
3.9
4.3
4.9
5.7
8.0
ns
tIRD8
FO=8 Routing Delay
5.2
5.8
6.6
7.7
10.8
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO = 32
FO = 256
4.1
4.5
4.5
5.0
5.1
5.6
6.0
6.7
8.4
9.3
ns
ns
tCKL
Input HIGH to LOW
FO = 32
FO = 256
5.0
5.4
5.5
6.0
6.2
6.8
7.3
8.0
10.2
11.2
ns
ns
tPWH
Minimum
Width HIGH
Pulse FO = 32
FO = 256
1.7
1.9
1.9
2.1
2.1
2.3
2.5
2.7
3.5
3.8
ns
ns
tPWL
Minimum
Width LOW
Pulse FO = 32
FO = 256
1.7
1.9
1.9
2.1
2.1
2.3
2.5
2.7
3.5
3.8
ns
ns
tCKSW
Maximum Skew
tSUEXT
Input Latch External FO = 32
Set-Up
FO = 256
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
tHEXT
Input Latch External FO = 32
Hold
FO = 256
3.3
3.7
3.7
4.1
4.2
4.6
4.9
5.5
6.9
7.6
ns
ns
tP
Minimum Period
FO = 32
FO = 256
5.6
6.1
6.2
6.8
6.7
7.4
7.8
8.5
12.9
14.2
ns
ns
fMAX
Maximum
Frequency
FO = 32
FO = 256
FO = 32
FO = 256
0.4
0.4
0.5
0.5
177
161
161
146
0.5
0.5
148
135
0.6
0.6
129
117
0.9
0.9
77
70
ns
ns
MHz
MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
v6.0
1-53
40MX and 42MX FPGA Families
Table 33 •
A42MX09 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, VCCA = 3.0V, TJ = 70°C)
‘–3’ Speed
Parameter Description
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
TTL Output Module Timing
5
tDLH
Data-to-Pad HIGH
3.4
3.8
4.3
5.1
7.1
ns
tDHL
Data-to-Pad LOW
4.0
4.5
5.1
6.1
8.3
ns
tENZH
Enable
HIGH
Pad
Z
to
3.7
4.1
4.6
5.5
7.6
ns
tENZL
Enable
LOW
Pad
Z
to
4.1
4.5
5.1
6.1
8.5
ns
tENHZ
Enable Pad HIGH to
Z
6.9
7.6
8.6
10.2
14.2
ns
tENLZ
Enable Pad LOW to
Z
7.5
8.3
9.4
11.1
15.5
ns
tGLH
G-to-Pad HIGH
5.8
6.5
7.3
8.6
12.0
ns
tGHL
G-to-Pad LOW
5.8
6.5
7.3
8.6
12.0
ns
tLSU
I/O Latch Set-Up
0.7
0.8
0.9
1.0
1.4
ns
tLH
I/O Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-toOut (Pad-to-Pad),
64 Clock Loading
8.7
9.7
10.9
12.9
18.0
ns
tACO
Array Clock-to-Out
(Pad-to-Pad),
64 Clock Loading
12.2
13.5
15.4
18.1
25.3
ns
dTLH
Capacity Loading,
LOW to HIGH
0.00
0.00
0.00
0.10
0.01
ns/pF
dTHL
Capacity Loading,
HIGH to LOW
0.09
0.10
0.10
0.10
0.10
ns/pF
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1 -5 4
v6.0
40MX and 42MX FPGA Families
Table 33 •
A42MX09 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, VCCA = 3.0V, TJ = 70°C)
‘–3’ Speed
Parameter Description
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
5
CMOS Output Module Timing
tDLH
Data-to-Pad HIGH
3.4
3.8
5.5
6.4
9.0
ns
tDHL
Data-to-Pad LOW
4.1
4.5
4.2
5.0
7.0
ns
tENZH
Enable Pad Z to HIGH
3.7
4.1
4.6
5.5
7.6
ns
tENZL
Enable Pad Z to LOW
4.1
4.5
5.1
6.1
8.5
ns
tENHZ
Enable Pad HIGH to Z
6.9
7.6
8.6
10.2
14.2
ns
tENLZ
Enable Pad LOW to Z
7.5
8.3
9.4
11.1
15.5
ns
tGLH
G-to-Pad HIGH
5.8
6.5
7.3
8.6
12.0
ns
tGHL
G-to-Pad LOW
5.8
6.5
7.3
8.6
12.0
ns
tLSU
I/O Latch Set-Up
0.7
0.8
0.9
1.0
1.4
ns
tLH
I/O Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-toPad), 64 Clock Loading
8.7
9.7
10.9
12.9
18.0
ns
tACO
Array Clock-to-Out (Pad-to-Pad),
64 Clock Loading
12.2
13.5
15.4
18.1
25.3
ns
dTLH
Capacity Loading, LOW to HIGH
0.04
0.04
0.05
0.06
0.08
ns/pF
dTHL
Capacity Loading, HIGH to LOW
0.05
0.05
0.06
0.07
0.10
ns/pF
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
v6.0
1-55
40MX and 42MX FPGA Families
Table 34 •
A42MX16 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, V CCA = 4.75V, T J = 70°C)
‘–3’ Speed
Parameter Description
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
1
Logic Module Propagation Delays
tPD1
Single Module
1.4
1.5
1.7
2.0
2.8
ns
tCO
Sequential Clock-to-Q
1.4
1.6
1.8
2.1
3.0
ns
tGO
Latch G-to-Q
1.4
1.5
1.7
2.0
2.8
ns
tRS
Flip-Flop (Latch) Reset-to-Q
1.6
1.7
2.0
2.3
3.3
ns
Logic Module Predicted Routing Delays2
tRD1
FO=1 Routing Delay
0.8
0.9
1.0
1.2
1.6
ns
tRD2
FO=2 Routing Delay
1.0
1.2
1.3
1.5
2.1
ns
tRD3
FO=3 Routing Delay
1.3
1.4
1.6
1.9
2.7
ns
tRD4
FO=4 Routing Delay
1.6
1.7
2.0
2.3
3.2
ns
tRD8
FO=8 Routing Delay
2.6
2.9
3.2
3.8
5.3
ns
Logic Module Sequential
Timing3,4
tSUD
Flip-Flop (Latch) Data Input Set-Up
0.3
0.4
0.4
0.5
0.7
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
0.7
0.8
0.9
1.0
1.4
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active
Pulse Width
3.4
3.8
4.3
5.0
7.1
ns
tWASYN
Flip-Flop (Latch) Asynchronous
Pulse Width
4.5
5.0
5.6
6.6
9.2
ns
tA
Flip-Flop Clock Input Period
6.8
7.6
8.6
10.1
14.1
ns
tINH
Input Buffer Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tINSU
Input Buffer Latch Set-Up
0.5
0.5
0.6
0.7
1.0
ns
tOUTH
Output Buffer Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tOUTSU
Output Buffer Latch Set-Up
0.5
0.5
0.6
0.7
1.0
ns
fMAX
Flip-Flop (Latch) Clock Frequency
215
195
179
156
94
MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, point and position whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1 -5 6
v6.0
40MX and 42MX FPGA Families
Table 34 •
A42MX16 Timing Characteristics (Nominal 5.0V Operation) (Continued)
(Worst-Case Commercial Conditions, V CCA = 4.75V, T J = 70°C)
‘–3’ Speed
Parameter Description
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
1.1
1.2
1.3
1.6
2.2
ns
tINYL
Pad-to-Y LOW
0.8
0.9
1.0
1.2
1.7
ns
tINGH
G to Y HIGH
1.4
1.6
1.8
2.1
2.9
ns
tINGL
G to Y LOW
1.4
1.6
1.8
2.1
2.9
ns
Input Module Predicted Routing Delays2
tIRD1
FO=1 Routing Delay
1.8
2.0
2.3
2.7
4.0
ns
tIRD2
FO=2 Routing Delay
2.1
2.3
2.6
3.1
4.3
ns
tIRD3
FO=3 Routing Delay
2.3
2.6
3.0
3.5
4.9
ns
tIRD4
FO=4 Routing Delay
2.6
3.0
3.3
3.9
5.4
ns
tIRD8
FO=8 Routing Delay
3.6
4.0
4.6
5.4
7.5
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO = 32
FO = 384
2.6
2.9
2.9
3.2
3.3
3.6
3.9
4.3
5.4
6.0
ns
ns
tCKL
Input HIGH to LOW
FO = 32
FO = 384
3.8
4.5
4.2
5.0
4.8
5.6
5.6
6.6
7.8
9.2
ns
ns
tPWH
Minimum
Width HIGH
Pulse FO = 32
FO = 384
3.2
3.7
3.5
4.1
4.0
4.6
4.7
5.4
6.6
7.6
ns
ns
tPWL
Minimum
Width LOW
Pulse FO = 32
FO = 384
3.2
3.7
3.5
4.1
4.0
4.6
4.7
5.4
6.6
7.6
ns
ns
tCKSW
Maximum Skew
tSUEXT
Input Latch External FO = 32
Set-Up
FO = 384
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
tHEXT
Input Latch External FO = 32
Hold
FO = 384
2.8
3.2
3.1
3.5
5.5
4.0
4.1
4.7
5.7
6.6
ns
ns
tP
Minimum Period
FO = 32
FO = 384
4.2
4.6
4.67
5.1
5.1
5.6
5.8
6.4
9.7
10.7
ns
ns
fMAX
Maximum
Frequency
FO = 32
FO = 384
FO = 32
FO = 384
0.3
0.3
0.4
0.4
237
215
215
195
0.4
0.4
198
179
0.5
0.5
172
156
0.7
0.7
103
94
ns
ns
MHz
MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, point and position whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
v6.0
1-57
40MX and 42MX FPGA Families
Table 34 •
A42MX16 Timing Characteristics (Nominal 5.0V Operation) (Continued)
(Worst-Case Commercial Conditions, V CCA = 4.75V, T J = 70°C)
‘–3’ Speed
Parameter Description
TTL Output Module
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Timing5
tDLH
Data-to-Pad HIGH
2.5
2.8
3.2
3.7
5.2
ns
tDHL
Data-to-Pad LOW
3.0
3.3
3.7
4.4
6.1
ns
tENZH
Enable Pad Z to HIGH
2.7
3.0
3.4
4.0
5.6
ns
tENZL
Enable Pad Z to LOW
3.0
3.3
3.8
4.4
6.2
ns
tENHZ
Enable Pad HIGH to Z
5.4
6.0
6.8
8.0
11.2
ns
tENLZ
Enable Pad LOW to Z
5.0
5.6
6.3
7.4
10.4
ns
tGLH
G-to-Pad HIGH
2.9
3.2
3.6
4.3
6.0
ns
tGHL
G-to-Pad LOW
2.9
3.2
3.6
4.3
6.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-toPad), 64 Clock Loading
5.7
6.3
7.1
8.4
11.9
ns
tACO
Array Clock-to-Out (Pad-to-Pad),
64 Clock Loading
8.0
8.9
10.1
11.9
16.7
ns
dTLH
Capacitive Loading, LOW to HIGH
0.03
0.03
0.03
0.04
0.06
ns/pF
dTHL
Capacitive Loading, HIGH to LOW
0.04
0.04
0.04
0.05
0.07
ns/pF
5
CMOS Output Module Timing
tDLH
Data-to-Pad HIGH
3.2
3.6
4.0
4.7
6.6
ns
tDHL
Data-to-Pad LOW
2.5
2.7
3.1
3.6
5.1
ns
tENZH
Enable Pad Z to HIGH
2.7
3.0
3.4
4.0
5.6
ns
tENZL
Enable Pad Z to LOW
3.0
3.3
3.8
4.4
6.2
ns
tENHZ
Enable Pad HIGH to Z
5.4
6.0
6.8
8.0
11.2
ns
tENLZ
Enable Pad LOW to Z
5.0
5.6
6.3
7.4
10.4
ns
tGLH
G-to-Pad HIGH
5.1
5.6
6.4
7.5
10.5
ns
tGHL
G-to-Pad LOW
5.1
5.6
6.4
7.5
10.5
ns
tLCO
I/O Latch Clock-to-Out (Pad-toPad), 64 Clock Loading
5.7
6.3
7.1
8.4
11.9
ns
tACO
Array Clock-to-Out (Pad-to-Pad),
64 Clock Loading
8.0
8.9
10.1
11.9
16.7
ns
dTLH
Capacitive Loading, LOW to HIGH
0.03
0.03
0.03
0.04
0.06
ns/pF
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, point and position whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1 -5 8
v6.0
40MX and 42MX FPGA Families
Table 35 •
A42MX16 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions, V CCA = 3.0V, T J = 70°C)
‘–3’ Speed
Parameter Description
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Propagation
Delays1
tPD1
Single Module
1.9
2.1
2.4
2.8
4.0
ns
tCO
Sequential Clock-to-Q
2.0
2.2
2.5
3.0
4.2
ns
tGO
Latch G-to-Q
1.9
2.1
2.4
2.8
4.0
ns
tRS
Flip-Flop (Latch) Reset-to-Q
2.2
2.4
2.8
3.3
4.6
ns
Logic Module Predicted Routing
Delays2
tRD1
FO=1 Routing Delay
1.1
1.2
1.4
1.6
2.3
ns
tRD2
FO=2 Routing Delay
1.5
1.6
1.8
2.1
3.0
ns
tRD3
FO=3 Routing Delay
1.8
2.0
2.3
2.7
3.8
ns
tRD4
FO=4 Routing Delay
2.2
2.4
2.7
3.2
4.5
ns
tRD8
FO=8 Routing Delay
3.6
4.0
4.5
5.3
7.5
ns
Logic Module Sequential
Timing3, 4
tSUD
Flip-Flop (Latch) Data Input Set-Up
0.5
0.5
0.6
0.7
0.9
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
1.0
1.1
1.2
1.4
2.0
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active
Pulse Width
4.8
5.3
6.0
7.1
9.9
ns
tWASYN
Flip-Flop (Latch) Asynchronous
Pulse Width
6.2
6.9
7.9
9.2
12.9
ns
tA
Flip-Flop Clock Input Period
9.5
10.6
12.0
14.1
19.8
ns
tINH
Input Buffer Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tINSU
Input Buffer Latch Set-Up
0.7
0.8
0.9
1.01
1.4
ns
tOUTH
Output Buffer Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tOUTSU
Output Buffer Latch Set-Up
0.7
0.8
0.89
1.01
1.4
ns
fMAX
Flip-Flop (Latch) Clock Frequency
129
117
108
94
56
MHz
Notes:
1. For dual-module macros use tPD1 + tRD1 + taped, to + tRD1 + taped, or tPD1 + tRD1 + tusk, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
v6.0
1-59
40MX and 42MX FPGA Families
Table 35 •
A42MX16 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, V CCA = 3.0V, T J = 70°C)
‘–3’ Speed
Parameter Description
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
1.5
1.6
1.9
2.2
3.1
ns
tINYL
Pad-to-Y LOW
1.1
1.3
1.4
1.7
2.4
ns
tINGH
G to Y HIGH
2.0
2.2
2.5
2.9
4.1
ns
tINGL
G to Y LOW
2.0
2.2
2.5
2.9
4.1
ns
Input Module Predicted Routing
Delays2
tIRD1
FO=1 Routing Delay
2.6
2.9
3.2
3.8
5.3
ns
tIRD2
FO=2 Routing Delay
2.9
3.2
3.7
4.3
6.1
ns
tIRD3
FO=3 Routing Delay
3.3
3.6
4.1
4.9
6.8
ns
tIRD4
FO=4 Routing Delay
3.6
4.0
4.6
5.4
7.6
ns
tIRD8
FO=8 Routing Delay
5.1
5.6
6.4
7.5
10.5
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO = 32
FO = 384
4.4
4.8
4.8
5.3
5.5
6.0
6.5
7.1
9.0
9.9
ns
ns
tCKL
Input HIGH to LOW
FO = 32
FO = 384
5.3
6.2
5.9
6.9
6.7
7.9
7.8
9.2
11.0
12.9
ns
ns
tPWH
Minimum Pulse
Width HIGH
FO = 32
FO = 384
5.7
6.6
6.3
7.4
7.1
8.3
8.4
9.8
11.8
13.7
ns
ns
tPWL
Minimum Pulse
Width LOW
FO = 32
FO = 384
5.3
6.2
5.9
6.9
6.7
7.9
7.8
9.2
11.0
12.9
ns
ns
tCKSW
Maximum Skew
FO = 32
FO = 384
tSUEXT
Input Latch External FO = 32
Set-Up
FO = 384
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
tHEXT
Input Latch External FO = 32
Hold
FO = 384
3.9
4.5
4.3
4.9
4.9
5.6
5.7
6.6
8.0
9.2
ns
ns
tP
Minimum Period
7.0
7.7
7.8
8.6
8.4
9.3
9.7
10.7
16.2
17.8
ns
ns
fMAX
Maximum Frequency FO = 32
FO = 384
FO = 32
FO = 384
0.5
2.2
0.5
2.4
142
129
129
117
0.6
2.7
119
108
0.7
3.2
103
94
1.0
4.5
62
56
ns
ns
MHz
MHz
Notes:
1. For dual-module macros use tPD1 + tRD1 + taped, to + tRD1 + taped, or tPD1 + tRD1 + tusk, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1 -6 0
v6.0
40MX and 42MX FPGA Families
Table 35 •
A42MX16 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, V CCA = 3.0V, T J = 70°C)
‘–3’ Speed
Parameter Description
TTL Output Module
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Timing5
tDLH
Data-to-Pad HIGH
3.5
3.9
4.4
5.2
7.3
ns
tDHL
Data-to-Pad LOW
4.1
4.6
5.2
6.1
8.6
ns
tENZH
Enable Pad Z to HIGH
3.8
4.2
4.8
5.6
7.8
ns
tENZL
Enable Pad Z to LOW
4.2
4.6
5.3
6.2
8.7
ns
tENHZ
Enable Pad HIGH to Z
7.6
8.4
9.5
11.2
15.7
ns
tENLZ
Enable Pad LOW to Z
7.0
7.8
8.8
10.4
14.5
ns
tGLH
G-to-Pad HIGH
4.8
5.3
6.0
7.2
10.0
ns
tGHL
G-to-Pad LOW
4.8
5.3
6.0
7.2
10.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-toPad), 64 Clock Loading
8.0
8.9
10.1
11.9
16.7
ns
tACO
Array Clock-to-Out (Pad-to-Pad),
64 Clock Loading
11.3
12.5
14.2
16.7
23.3
ns
dTLH
Capacitive Loading, LOW to HIGH
0.04
0.04
0.05
0.06
0.08
ns/pF
dTHL
Capacitive Loading, HIGH to LOW
0.05
0.05
0.06
0.07
0.10
ns/pF
CMOS Output Module Timing5
tDLH
Data-to-Pad HIGH
4.5
5.0
5.6
6.6
9.3
ns
tDHL
Data-to-Pad LOW
3.4
3.8
4.3
5.1
7.1
ns
tENZH
Enable Pad Z to HIGH
3.8
4.2
4.8
5.6
7.8
ns
tENZL
Enable Pad Z to LOW
4.2
4.6
5.3
6.2
8.7
ns
tENHZ
Enable Pad HIGH to Z
7.6
8.4
9.5
11.2
15.7
ns
tENLZ
Enable Pad LOW to Z
7.0
7.8
8.8
10.4
14.5
ns
tGLH
G-to-Pad HIGH
7.1
7.9
8.9
10.5
14.7
ns
tGHL
G-to-Pad LOW
7.1
7.9
8.9
10.5
14.7
ns
tLCO
I/O Latch Clock-to-Out (Pad-toPad), 64 Clock Loading
8.0
8.9
10.1
11.9
16.7
ns
tACO
Array Clock-to-Out (Pad-to-Pad),
64 Clock Loading
11.3
12.5
14.2
16.7
23.3
ns
dTLH
Capacitive Loading, LOW to HIGH
0.04
0.04
0.05
0.06
0.08
ns/pF
dTHL
Capacitive Loading, HIGH to LOW
0.05
0.05
0.06
0.07
0.10
ns/pF
Notes:
1. For dual-module macros use tPD1 + tRD1 + taped, to + tRD1 + taped, or tPD1 + tRD1 + tusk, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
v6.0
1-61
40MX and 42MX FPGA Families
Table 36 •
A42MX24 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, V CCA = 4.75V, T J = 70°C)
‘–3’ Speed
Parameter Description
Logic Module Combinatorial
‘–2’Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Functions1
tPD
Internal Array Module Delay
tPDD
Internal Decode Module Delay
1.2
1.3
1.5
1.8
2.5
ns
1.4
1.6
1.8
2.1
3.0
ns
2
Logic Module Predicted Routing Delays
tRD1
FO=1 Routing Delay
0.8
0.9
1.0
1.2
1.7
ns
tRD2
FO=2 Routing Delay
1.0
1.2
1.3
1.5
2.1
ns
tRD3
FO=3 Routing Delay
1.3
1.4
1.6
1.9
2.6
ns
tRD4
FO=4 Routing Delay
1.5
1.7
1.9
2.2
3.1
ns
tRD5
FO=8 Routing Delay
2.4
2.7
3.0
3.6
5.0
ns
Logic Module Sequential Timing3, 4
tCO
Flip-Flop Clock-to-Output
1.3
1.4
1.6
1.9
2.7
ns
tGO
Latch Gate-to-Output
1.2
1.3
1.5
1.8
2.5
ns
tSUD
Flip-Flop (Latch) Set-Up Time
0.3
0.4
0.4
0.5
0.7
ns
tHD
Flip-Flop (Latch) Hold Time
0.0
0.0
0.0
0.0
0.0
ns
tRO
Flip-Flop (Latch) Reset-to-Output
tSUENA
Flip-Flop (Latch) Enable Set-Up
0.4
0.5
0.5
0.6
0.8
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active
Pulse Width
3.3
3.7
4.2
4.9
6.9
ns
tWASYN
Flip-Flop (Latch) Asynchronous
Pulse Width
4.4
4.8
5.3
6.5
9.0
1.4
1.6
1.8
2.1
2.9
ns
ns
Input Module Propagation Delays
tINPY
Input Data Pad-to-Y
1.0
1.1
1.3
1.5
2.1
ns
tINGO
Input Latch Gate-to-Output
1.3
1.4
1.6
1.9
2.6
ns
tINH
Input Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tINSU
Input Latch Set-Up
0.5
0.5
0.6
0.7
1.0
ns
tILA
Latch Active Pulse Width
4.7
5.2
5.9
6.9
9.7
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1 -6 2
v6.0
40MX and 42MX FPGA Families
Table 36 •
A42MX24 Timing Characteristics (Nominal 5.0V Operation) (Continued)
(Worst-Case Commercial Conditions, V CCA = 4.75V, T J = 70°C)
‘–3’ Speed
Parameter Description
‘–2’Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Module Predicted Routing Delays
2
tIRD1
FO=1 Routing Delay
1.8
2.0
2.3
2.7
3.8
ns
tIRD2
FO=2 Routing Delay
2.1
2.3
2.6
3.1
4.3
ns
tIRD3
FO=3 Routing Delay
2.3
2.5
2.9
3.4
4.8
ns
tIRD4
FO=4 Routing Delay
2.5
2.8
3.2
3.7
5.2
ns
tIRD8
FO=8 Routing Delay
3.4
3.8
4.3
5.1
7.1
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO=32
FO=486
2.6
2.9
2.9
3.2
3.3
3.6
3.9
4.3
5.4
5.9
ns
ns
tCKL
Input HIGH to LOW
FO=32
FO=486
3.7
4.3
4.1
4.7
4.6
5.4
5.4
6.3
7.6
8.8
ns
ns
tPWH
Minimum Pulse
Width HIGH
FO=32
FO=486
2.2
2.4
2.4
2.6
2.7
3.0
3.2
3.5
4.5
4.9
ns
ns
tPWL
Minimum Pulse
Width LOW
FO=32
FO=486
2.2
2.4
2.4
2.6
2.7
3.0
3.2
3.5
4.5
4.9
ns
ns
tCKSW
Maximum Skew
FO=32
FO=486
tSUEXT
Input Latch External FO=32
Set-Up
FO=486
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
tHEXT
Input Latch External FO=32
Hold
FO=486
2.8
3.3
3.1
3.7
3.5
4.2
4.1
4.9
5.7
6.9
ns
ns
tP
Minimum Period
(1/fMAX)
4.7
5.1
5.2
5.7
5.7
6.2
6.5
7.1
10.9
11.9
ns
ns
FO=32
FO=486
0.5
0.5
0.6
0.6
0.7
0.7
0.8
0.8
1.1
1.1
ns
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
v6.0
1-63
40MX and 42MX FPGA Families
Table 36 •
A42MX24 Timing Characteristics (Nominal 5.0V Operation) (Continued)
(Worst-Case Commercial Conditions, V CCA = 4.75V, T J = 70°C)
‘–3’ Speed
Parameter Description
TTL Output Module Timing
‘–2’Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
5
tDLH
Data-to-Pad HIGH
2.4
2.7
3.1
3.6
5.1
ns
tDHL
Data-to-Pad LOW
2.8
3.2
3.6
4.2
5.9
ns
tENZH
Enable Pad Z to HIGH
2.5
2.8
3.2
3.8
5.3
ns
tENZL
Enable Pad Z to LOW
2.8
3.1
3.5
4.2
5.9
ns
tENHZ
Enable Pad HIGH to Z
5.2
5.7
6.5
7.6
10.7
ns
tENLZ
Enable Pad LOW to Z
4.8
5.3
6.0
7.1
9.9
ns
tGLH
G-to-Pad HIGH
2.9
3.2
3.6
4.3
6.0
ns
tGHL
G-to-Pad LOW
2.9
3.2
3.6
4.3
6.0
ns
tLSU
I/O Latch Output Set-Up
0.5
0.5
0.6
0.7
1.0
ns
tLH
I/O Latch Output Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
5.6
6.1
6.9
8.1
11.4
ns
tACO
Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
10.6
11.8
13.4
15.7
22.0
ns
dTLH
Capacitive Loading, LOW to HIGH
0.04
0.04
0.04
0.05
0.07
ns/pF
dTHL
Capacitive Loading, HIGH to LOW
0.03
0.03
0.03
0.04
0.06
ns/pF
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1 -6 4
v6.0
40MX and 42MX FPGA Families
Table 36 •
A42MX24 Timing Characteristics (Nominal 5.0V Operation) (Continued)
(Worst-Case Commercial Conditions, V CCA = 4.75V, T J = 70°C)
‘–3’ Speed
Parameter Description
‘–2’Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
5
CMOS Output Module Timing
tDLH
Data-to-Pad HIGH
3.1
3.5
3.9
4.6
6.4
ns
tDHL
Data-to-Pad LOW
2.4
2.6
3.0
3.5
4.9
ns
tENZH
Enable Pad Z to HIGH
2.5
2.8
3.2
3.8
5.3
ns
tENZL
Enable Pad Z to LOW
2.8
3.1
3.5
4.2
5.8
ns
tENHZ
Enable Pad HIGH to Z
5.2
5.7
6.5
7.6
10.7
ns
tENLZ
Enable Pad LOW to Z
4.8
5.3
6.0
7.1
9.9
ns
tGLH
G-to-Pad HIGH
4.9
5.4
6.2
7.2
10.1
ns
tGHL
G-to-Pad LOW
4.9
5.4
6.2
7.2
10.1
ns
tLSU
I/O Latch Set-Up
0.5
0.5
0.6
0.7
1.0
ns
tLH
I/O Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-toPad) 32 I/O
5.5
6.1
6.9
8.1
11.3
ns
tACO
Array Latch Clock-to-Out (Padto-Pad) 32 I/O
10.6
11.8
13.4
15.7
22.0
ns
dTLH
Capacitive Loading, LOW to HIGH
0.04
0.04
0.04
0.05
0.07
ns/pF
dTHL
Capacitive Loading, HIGH to LOW
0.03
0.03
0.03
0.04
0.06
ns/pF
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
v6.0
1-65
40MX and 42MX FPGA Families
Table 37 •
A42MX24 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions, V CCA = 3.0V, T J = 70°C)
‘–3’ Speed
Parameter Description
Logic Module Combinatorial
‘–2’Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Functions1
tPD
Internal Array Module Delay
tPDD
Internal Decode Module Delay
2.0
1.8
2.1
2.5
3.4
ns
1.1
2.2
2.5
3.0
4.2
ns
2
Logic Module Predicted Routing Delays
tRD1
FO=1 Routing Delay
1.7
1.3
1.4
1.7
2.3
ns
tRD2
FO=2 Routing Delay
2.0
1.6
1.8
2.1
3.0
ns
tRD3
FO=3 Routing Delay
1.1
2.0
2.2
2.6
3.7
ns
tRD4
FO=4 Routing Delay
1.5
2.3
2.6
3.1
4.3
ns
tRD5
FO=8 Routing Delay
1.8
3.7
4.2
5.0
7.0
ns
Logic Module Sequential Timing3, 4
tCO
Flip-Flop Clock-to-Output
2.1
2.0
2.3
2.7
3.7
ns
tGO
Latch Gate-to-Output
3.4
1.9
2.1
2.5
3.4
ns
tSUD
Flip-Flop (Latch) Set-Up Time
0.4
0.5
0.6
0.7
0.9
ns
tHD
Flip-Flop (Latch) Hold Time
0.0
0.0
0.0
0.0
0.0
ns
tRO
Flip-Flop (Latch) Reset-to-Output
tSUENA
Flip-Flop (Latch) Enable Set-Up
0.6
0.6
0.7
0.8
1.2
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active
Pulse Width
4.6
5.2
5.8
6.9
9.6
ns
tWASYN
Flip-Flop (Latch) Asynchronous
Pulse Width
6.1
6.8
7.7
9.0
12.6
2.0
2.2
2.5
2.9
4.1
ns
ns
Input Module Propagation Delays
tINPY
Input Data Pad-to-Y
1.4
1.6
1.8
2.2
3.0
ns
tINGO
Input Latch Gate-toOutput
1.8
1.9
2.2
2.6
3.6
ns
tINH
Input Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tINSU
Input Latch Set-Up
0.7
0.7
0.8
1.0
1.4
ns
tILA
Latch Active Pulse Width
6.5
7.3
8.2
9.7
13.5
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1 -6 6
v6.0
40MX and 42MX FPGA Families
Table 37 •
A42MX24 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, V CCA = 3.0V, T J = 70°C)
‘–3’ Speed
Parameter Description
‘–2’Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Module Predicted Routing Delays
2
tIRD1
FO=1 Routing Delay
2.6
2.9
3.2
3.8
5.3
ns
tIRD2
FO=2 Routing Delay
2.9
3.2
3.6
4.3
6.0
ns
tIRD3
FO=3 Routing Delay
3.2
3.6
4.0
4.8
6.6
ns
tIRD4
FO=4 Routing Delay
3.5
3.9
4.4
5.2
7.3
ns
tIRD8
FO=8 Routing Delay
4.8
5.3
6.1
7.1
10.0
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO=32
FO=486
4.4
4.8
4.8
5.3
5.5
6.0
6.5
7.1
9.1
10.0
ns
ns
tCKL
Input HIGH to LOW
FO=32
FO=486
5.1
6.0
5.7
6.6
6.4
7.5
7.6
8.8
10.6
12.4
ns
ns
tPWH
Minimum Pulse
Width HIGH
FO=32
FO=486
3.0
3.3
3.3
3.7
3.8
4.2
4.5
4.9
6.3
6.9
ns
ns
tPWL
Minimum Pulse
Width LOW
FO=32
FO=486
3.0
3.3
3.4
3.7
3.8
4.2
4.5
4.9
6.3
6.9
ns
ns
tCKSW
Maximum Skew
FO=32
FO=486
tSUEXT
Input Latch External FO=32
Set-Up
FO=486
0.8
0.8
0.0
0.0
0.8
0.8
0.0
0.0
1.0
1.0
0.0
0.0
1.1
1.1
0.0
0.0
1.6
1.6
0.0
0.0
ns
ns
ns
ns
TTL Output Module Timing5
tDLH
Data-to-Pad HIGH
3.4
3.8
4.3
5.0
7.1
ns
tDHL
Data-to-Pad LOW
4.0
4.4
5.0
5.9
8.3
ns
tENZH
Enable Pad Z to HIGH
3.6
4.0
4.5
5.3
7.4
ns
tENZL
Enable Pad Z to LOW
3.9
4.4
5.0
5.8
8.2
ns
tENHZ
Enable Pad HIGH to Z
7.2
8.0
9.1
10.7
14.9
ns
tENLZ
Enable Pad LOW to Z
6.7
7.5
8.5
9.9
13.9
ns
tGLH
G-to-Pad HIGH
4.8
5.3
6.0
7.2
10.0
ns
tGHL
G-to-Pad LOW
4.8
5.3
6.0
7.2
10.0
ns
tLSU
I/O Latch Output Set-Up
0.7
0.7
0.8
1.0
1.4
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
v6.0
1-67
40MX and 42MX FPGA Families
Table 37 •
A42MX24 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, V CCA = 3.0V, T J = 70°C)
‘–3’ Speed
Parameter Description
‘–2’Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
5
TTL Output Module Timing (Continued)
tLH
I/O Latch Output Hold
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
7.7
8.5
9.6
11.3
15.9
ns
tACO
Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
14.8
16.5
18.7
22.0
30.8
ns
dTLH
Capacitive Loading, LOW to HIGH
0.05
0.05
0.06
0.07
0.10
ns/pF
dTHL
Capacitive Loading, HIGH to LOW
0.04
0.04
0.05
0.06
0.08
ns/pF
CMOS Output Module
0.0
0.0
0.0
0.0
0.0
ns
Timing5
tDLH
Data-to-Pad HIGH
4.8
5.3
5.5
6.4
9.0
ns
tDHL
Data-to-Pad LOW
3.5
3.9
4.1
4.9
6.8
ns
tENZH
Enable Pad Z to HIGH
3.6
4.0
4.5
5.3
7.4
ns
tENZL
Enable Pad Z to LOW
3.4
4.0
5.0
5.8
8.2
ns
tENHZ
Enable Pad HIGH to Z
7.2
8.0
9.0
10.7
14.9
ns
tENLZ
Enable Pad LOW to Z
6.7
7.5
8.5
9.9
13.9
ns
tGLH
G-to-Pad HIGH
6.8
7.6
8.6
10.1
14.2
ns
tGHL
G-to-Pad LOW
6.8
7.6
8.6
10.1
14.2
ns
tLSU
I/O Latch Set-Up
0.7
0.7
0.8
1.0
1.4
ns
tLH
I/O Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
7.7
8.5
9.6
11.3
15.9
ns
tACO
Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
14.8
16.5
18.7
22.0
30.8
ns
dTLH
Capacitive Loading, LOW to HIGH
0.05
0.05
0.06
0.07
0.10
ns/pF
dTHL
Capacitive Loading, HIGH to LOW
0.04
0.04
0.05
0.06
0.08
ns/pF
tHEXT
Input Latch External FO=32
Hold
FO=486
3.9
4.6
4.3
5.2
4.9
5.8
5.7
6.9
8.1
9.6
ns
ns
tP
Minimum Period
(1/fMAX)
FO=32
FO=486
7.8
8.6
8.7
9.5
9.5
10.4
10.8
11.9
18.2
19.9
ns
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1 -6 8
v6.0
40MX and 42MX FPGA Families
Table 38 •
A42MX36 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, V CCA = 4.75V, T J = 70°C)
‘–3’ Speed
Parameter Description
Logic Module Combinatorial
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Functions1
tPD
Internal Array Module Delay
1.3
1.5
1.7
2.0
2.7
ns
tPDD
Internal Decode Module Delay
1.6
1.8
2.0
2.4
3.3
ns
Delays2
Logic Module Predicted Routing
tRD1
FO=1 Routing Delay
0.9
1.0
1.2
1.4
2.0
ns
tRD2
FO=2 Routing Delay
1.3
1.4
1.6
1.9
2.7
ns
tRD3
FO=3 Routing Delay
1.6
1.8
2.0
2.4
3.4
ns
tRD4
FO=4 Routing Delay
2.0
2.2
2.5
2.9
4.1
ns
tRD5
FO=8 Routing Delay
3.3
3.7
4.2
4.9
6.9
ns
tRDD
Decode-to-Output Routing Delay
0.3
0.4
0.4
0.5
0.7
ns
3, 4
Logic Module Sequential Timing
tCO
Flip-Flop Clock-to-Output
1.3
1.4
1.6
1.9
2.7
ns
tGO
Latch Gate-to-Output
1.3
1.4
1.6
1.9
2.7
ns
tSUD
Flip-Flop (Latch) Set-Up Time
0.3
0.3
0.4
0.5
0.7
ns
tHD
Flip-Flop (Latch) Hold Time
0.0
0.0
0.0
0.0
0.0
ns
tRO
Flip-Flop (Latch) Reset-to-Output
tSUENA
Flip-Flop (Latch) Enable Set-Up
0.7
0.8
0.9
1.0
1.4
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active
Pulse Width
3.3
3.7
4.2
4.9
6.9
ns
tWASYN
Flip-Flop (Latch) Asynchronous
Pulse Width
4.4
4.8
5.5
6.4
9.0
1.6
1.7
2.0
2.3
3.2
ns
ns
Synchronous SRAM Operations
tRC
Read Cycle Time
6.8
7.5
8.5
10.0
14.0
ns
tWC
Write Cycle Time
6.8
7.5
8.5
10.0
14.0
ns
tRCKHL
Clock HIGH/LOW Time
3.4
3.8
4.3
5.0
7.0
ns
tRCO
Data Valid After Clock HIGH/LOW
tADSU
Address/Data Set-Up Time
3.4
1.6
3.8
1.8
4.3
2.0
5.0
2.4
7.0
3.4
ns
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
v6.0
1-69
40MX and 42MX FPGA Families
Table 38 •
A42MX36 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, V CCA = 4.75V, T J = 70°C)
‘–3’ Speed
Parameter Description
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Synchronous SRAM Operations (Continued)
tADH
Address/Data Hold Time
0.0
0.0
0.0
0.0
0.0
ns
tRENSU
Read Enable Set-Up
0.6
0.7
0.8
0.9
1.3
ns
tRENH
Read Enable Hold
3.4
3.8
4.3
5.0
7.0
ns
tWENSU
Write Enable Set-Up
2.7
3.0
3.4
4.0
5.6
ns
tWENH
Write Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tBENS
Block Enable Set-Up
2.8
3.1
3.5
4.1
5.7
ns
tBENH
Block Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
Asynchronous SRAM Operations
tRPD
Asynchronous Access Time
tRDADV
Read Address Valid
8.8
9.8
11.1
13.0
18.2
ns
tADSU
Address/Data Set-Up Time
1.6
1.8
2.0
2.4
3.4
ns
tADH
Address/Data Hold Time
0.0
0.0
0.0
0.0
0.0
ns
tRENSUA
Read Enable Set-Up to Address
Valid
0.6
0.7
0.8
0.9
1.3
ns
tRENHA
Read Enable Hold
3.4
3.8
4.3
5.0
7.0
ns
tWENSU
Write Enable Set-Up
2.7
3.0
3.4
4.0
5.6
ns
tWENH
Write Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tDOH
Data Out Hold Time
8.1
9.0
10.2
12.0
16.8
ns
1.2
1.3
1.5
1.8
2.5
ns
Input Module Propagation Delays
tINPY
Input Data Pad-to-Y
1.0
1.1
1.3
1.5
2.1
ns
tINGO
Input Latch Gate-to-Output
1.4
1.6
1.8
2.1
2.9
ns
tINH
Input Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tINSU
Input Latch Set-Up
0.5
0.5
0.6
0.7
1.0
ns
tILA
Latch Active Pulse Width
4.7
5.2
5.9
6.9
9.7
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1 -7 0
v6.0
40MX and 42MX FPGA Families
Table 38 •
A42MX36 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, V CCA = 4.75V, T J = 70°C)
‘–3’ Speed
Parameter Description
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Module Predicted Routing
Delays2
tIRD1
FO=1 Routing Delay
2.0
2.2
2.5
2.9
4.1
ns
tIRD2
FO=2 Routing Delay
2.3
2.6
2.9
3.4
4.8
ns
tIRD3
FO=3 Routing Delay
2.6
2.9
3.3
3.9
5.5
ns
tIRD4
FO=4 Routing Delay
3.0
3.3
3.8
4.4
6.2
ns
tIRD8
FO=8 Routing Delay
4.3
4.8
5.5
6.4
9.0
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO=32
FO=635
2.7
3.0
3.0
3.3
3.4
3.8
4.0
4.4
5.6
6.2
ns
ns
tCKL
Input HIGH to LOW
FO=32
FO=635
3.8
4.9
4.2
5.4
4.8
6.1
5.6
7.2
7.8
10.1
ns
ns
tPWH
Minimum Pulse
Width HIGH
FO=32
FO=635
1.8
2.0
2.0
2.2
2.2
2.5
2.6
2.9
3.6
4.1
ns
ns
tPWL
Minimum Pulse
Width LOW
FO=32
FO=635
1.8
2.0
2.0
2.2
2.2
2.5
2.6
2.9
3.6
4.1
ns
ns
tCKSW
Maximum Skew
FO=32
FO=635
tSUEXT
Input Latch External FO=32
Set-Up
FO=635
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
tHEXT
Input Latch External FO=32
Hold
FO=635
2.8
3.3
3.2
3.7
3.6
4.2
4.2
4.9
5.9
6.9
ns
ns
tP
Minimum Period
(1/fMAX)
FO=32
FO=635
5.5
6.0
6.1
6.6
6.6
7.2
7.6
8.3
12.7
13.8
ns
ns
fMAX
Maximum Datapath FO=32
Frequency
FO=635
0.8
0.8
0.8
0.8
0.9
0.9
1.0
1.0
1.4
1.4
ns
ns
180
166
164
151
151
139
131
121
79
73
MHz
MHz
TTL Output Module Timing5
tDLH
Data-to-Pad HIGH
2.6
2.8
3.2
3.8
5.3
ns
tDHL
Data-to-Pad LOW
3.0
3.3
3.7
4.4
6.2
ns
tENZH
Enable Pad Z to HIGH
2.7
3.0
3.3
3.9
5.5
ns
tENZL
Enable Pad Z to LOW
3.0
3.3
3.7
4.3
6.1
ns
tENHZ
Enable Pad HIGH to Z
5.3
5.8
6.6
7.8
10.9
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
v6.0
1-71
40MX and 42MX FPGA Families
Table 38 •
A42MX36 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, V CCA = 4.75V, T J = 70°C)
‘–3’ Speed
Parameter Description
TTL Output Module
Timing5
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
(Continued)
tENLZ
Enable Pad LOW to Z
4.9
5.5
6.2
7.3
10.2
ns
tGLH
G-to-Pad HIGH
2.9
3.3
3.7
4.4
6.1
ns
tGHL
G-to-Pad LOW
2.9
3.3
3.7
4.4
6.1
ns
tLSU
I/O Latch Output Set-Up
0.5
0.5
0.6
0.7
1.0
ns
tLH
I/O Latch Output Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-toPad) 32 I/O
5.7
6.3
7.1
8.4
11.8
ns
tACO
Array Latch Clock-to-Out (Padto-Pad) 32 I/O
7.8
8.6
9.8
11.5
16.1
ns
dTLH
Capacitive Loading, LOW to HIGH
0.07
0.08
0.09
0.10
0.14
ns/pF
dTHL
Capacitive Loading, HIGH to LOW
0.07
0.08
0.09
0.10
0.14
ns/pF
CMOS Output Module Timing5
tDLH
Data-to-Pad HIGH
3.5
3.9
4.5
5.2
7.3
ns
tDHL
Data-to-Pad LOW
2.5
2.7
3.1
3.6
5.1
ns
tENZH
Enable Pad Z to HIGH
2.7
3.0
3.3
3.9
5.5
ns
tENZL
Enable Pad Z to LOW
2.9
3.3
3.7
4.3
6.1
ns
tENHZ
Enable Pad HIGH to Z
5.3
5.8
6.6
7.8
10.9
ns
tENLZ
Enable Pad LOW to Z
4.9
5.5
6.2
7.3
10.2
ns
tGLH
G-to-Pad HIGH
5.0
5.6
6.3
7.5
10.4
ns
tGHL
G-to-Pad LOW
5.0
5.6
6.3
7.5
10.4
ns
tLSU
I/O Latch Set-Up
0.5
0.5
0.6
0.7
1.0
ns
tLH
I/O Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-toPad) 32 I/O
5.7
6.3
7.1
8.4
11.8
ns
tACO
Array Latch Clock-to-Out (Padto-Pad) 32 I/O
7.8
8.6
9.8
11.5
16.1
ns
dTLH
Capacitive Loading, LOW to HIGH
0.07
0.08
0.09
0.10
0.14
ns/pF
dTHL
Capacitive Loading, HIGH to LOW
0.07
0.08
0.09
0.10
0.14
ns/pF
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1 -7 2
v6.0
40MX and 42MX FPGA Families
Table 39 •
A42MX36 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions, V CCA = 3.0V, T J = 70°C)
‘–3’ Speed
Parameter Description
Logic Module Combinatorial
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Functions1
tPD
Internal Array Module Delay
1.9
2.1
2.3
2.7
3.8
ns
tPDD
Internal Decode Module Delay
2.2
2.5
2.8
3.3
4.7
ns
Delays2
Logic Module Predicted Routing
tRD1
FO=1 Routing Delay
1.3
1.5
1.7
2.0
2.7
ns
tRD2
FO=2 Routing Delay
1.8
2.0
2.3
2.7
3.7
ns
tRD3
FO=3 Routing Delay
2.3
2.5
2.8
3.4
4.7
ns
tRD4
FO=4 Routing Delay
2.8
3.1
3.5
4.1
5.7
ns
tRD5
FO=8 Routing Delay
4.6
5.2
5.8
6.9
9.6
ns
tRDD
Decode-to-Output Routing Delay
0.5
0.5
0.6
0.7
1.0
ns
3, 4
Logic Module Sequential Timing
tCO
Flip-Flop Clock-to-Output
1.8
2.0
2.3
2.7
3.7
ns
tGO
Latch Gate-to-Output
1.8
2.0
2.3
2.7
3.7
ns
tSUD
Flip-Flop (Latch) Set-Up Time
0.4
0.5
0.6
0.7
0.9
ns
tHD
Flip-Flop (Latch) Hold Time
0.0
0.0
0.0
0.0
0.0
ns
tRO
Flip-Flop (Latch) Reset-to-Output
tSUENA
Flip-Flop (Latch) Enable Set-Up
1.0
1.1
1.2
1.4
2.0
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active
Pulse Width
4.6
5.2
5.8
6.9
9.6
ns
tWASYN
Flip-Flop (Latch) Asynchronous
Pulse Width
6.1
6.8
7.7
9.0
12.6
ns
2.2
2.4
2.7
3.2
4.5
ns
Synchronous SRAM Operations
tRC
Read Cycle Time
9.5
10.5
11.9
14.0
19.6
ns
tWC
Write Cycle Time
9.5
10.5
11.9
14.0
19.6
ns
tRCKHL
Clock HIGH/LOW Time
4.8
5.3
6.0
7.0
9.8
ns
tRCO
Data Valid After Clock HIGH/LOW
tADSU
Address/Data Set-Up Time
4.8
2.3
5.3
2.5
6.0
2.8
7.0
3.4
9.8
4.8
ns
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
v6.0
1-73
40MX and 42MX FPGA Families
Table 39 •
A42MX36 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, V CCA = 3.0V, T J = 70°C)
‘–3’ Speed
Parameter Description
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Synchronous SRAM Operations (Continued)
tADH
Address/Data Hold Time
0.0
0.0
0.0
0.0
0.0
ns
tRENSU
Read Enable Set-Up
0.9
1.0
1.1
1.3
1.8
ns
tRENH
Read Enable Hold
4.8
5.3
6.0
7.0
9.8
ns
tWENSU
Write Enable Set-Up
3.8
4.2
4.8
5.6
7.8
ns
tWENH
Write Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tBENS
Block Enable Set-Up
3.9
4.3
4.9
5.7
8.0
ns
tBENH
Block Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
Asynchronous SRAM Operations
tRPD
Asynchronous Access Time
tRDADV
Read Address Valid
12.3
13.7
15.5
18.2
25.5
ns
tADSU
Address/Data Set-Up Time
2.3
2.5
2.8
3.4
4.8
ns
tADH
Address/Data Hold Time
0.0
0.0
0.0
0.0
0.0
ns
tRENSUA
Read Enable Set-Up to Address
Valid
0.9
1.0
1.1
1.3
1.8
ns
tRENHA
Read Enable Hold
4.8
5.3
6.0
7.0
9.8
ns
tWENSU
Write Enable Set-Up
3.8
4.2
4.8
5.6
7.8
ns
tWENH
Write Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tDOH
Data Out Hold Time
11.3
12.6
14.3
16.8
23.5
ns
1.8
2.0
2.1
2.5
3.5
ns
Input Module Propagation Delays
tINPY
Input Data Pad-to-Y
1.4
1.6
1.8
2.1
3.0
ns
tINGO
Input Latch Gate-toOutput
2.0
2.2
2.5
2.9
4.1
ns
tINH
Input Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tINSU
Input Latch Set-Up
0.7
0.7
0.8
1.0
1.4
ns
tILA
Latch Active Pulse Width
6.5
7.3
8.2
9.7
13.5
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1 -7 4
v6.0
40MX and 42MX FPGA Families
Table 39 •
A42MX36 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, V CCA = 3.0V, T J = 70°C)
‘–3’ Speed
Parameter Description
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Module Predicted Routing
Delays2
tIRD1
FO=1 Routing Delay
2.8
3.1
3.5
4.1
5.7
ns
tIRD2
FO=2 Routing Delay
3.2
3.5
4.1
4.8
6.7
ns
tIRD3
FO=3 Routing Delay
3.7
4.1
4.7
5.5
7.7
ns
tIRD4
FO=4 Routing Delay
4.2
4.6
5.3
6.2
8.7
ns
tIRD8
FO=8 Routing Delay
6.1
6.8
7.7
9.0
12.6
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO=32
FO=635
4.6
5.0
5.1
5.6
5.7
6.3
6.7
7.4
9.3
10.3
ns
ns
tCKL
Input HIGH to LOW
FO=32
FO=635
5.3
6.8
5.9
7.6
6.7
8.6
7.8
10.1
11.0
14.1
ns
ns
tPWH
Minimum Pulse
Width HIGH
FO=32
FO=635
2.5
2.8
2.7
3.1
3.1
3.5
3.6
4.1
5.1
5.7
ns
ns
tPWL
Minimum Pulse
Width LOW
FO=32
FO=635
2.5
2.8
2.7
3.1
3.1
3.5
3.6
4.1
5.1
5.7
ns
ns
tCKSW
Maximum Skew
FO=32
FO=635
tSUEXT
Input Latch
External Set-Up
FO=32
FO=635
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
tHEXT
Input Latch
External Hold
FO=32
FO=635
4.0
4.6
4.4
5.2
5.0
5.9
5.9
6.9
8.2
9.6
ns
ns
tP
Minimum Period
(1/fMAX)
FO=32
FO=635
9.2
9.9
10.2
11.0
11.1
12.0
12.7
13.8
21.2
23.0
ns
ns
fMAX
Maximum Datapath FO=32
Frequency
FO=635
1.0
1.0
1.2
1.2
1.3
1.3
1.5
1.5
2.2
2.2
ns
ns
108
100
98
91
90
83
79
73
47
44
MHz
MHz
TTL Output Module Timing5
tDLH
Data-to-Pad HIGH
3.6
4.0
4.5
5.3
7.4
ns
tDHL
Data-to-Pad LOW
4.2
4.6
5.2
6.2
8.6
ns
tENZH
Enable Pad Z to HIGH
3.7
4.2
4.7
5.5
7.7
ns
tENZL
Enable Pad Z to LOW
4.1
4.6
5.2
6.1
8.5
ns
tENHZ
Enable Pad HIGH to Z
7.34
8.2
9.3
10.9
15.3
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
v6.0
1-75
40MX and 42MX FPGA Families
Table 39 •
A42MX36 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, V CCA = 3.0V, T J = 70°C)
‘–3’ Speed
Parameter Description
TTL Output Module
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Timing5
tENLZ
Enable Pad LOW to Z
6.9
7.6
8.7
10.2
14.3
ns
tGLH
G-to-Pad HIGH
4.9
5.5
6.2
7.3
10.2
ns
tGHL
G-to-Pad LOW
4.9
5.5
6.2
7.3
10.2
ns
tLSU
I/O Latch Output Set-Up
0.7
0.7
0.8
1.0
1.4
ns
tLH
I/O Latch Output Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-toPad) 32 I/O
7.9
8.8
10.0
11.8
16.5
ns
tACO
Array Latch Clock-to-Out (Padto-Pad) 32 I/O
10.9
12.1
13.7
16.1
22.5
ns
dTLH
Capacitive Loading, LOW to HIGH
0.10
0.11
0.12
0.14
0.20
ns/pF
dTHL
Capacitive Loading, HIGH to LOW
0.10
0.11
0.12
0.14
0.20
ns/pF
CMOS Output Module Timing5
tDLH
Data-to-Pad HIGH
4.9
5.5
6.2
7.3
10.3
ns
tDHL
Data-to-Pad LOW
3.4
3.8
4.3
5.1
7.1
ns
tENZH
Enable Pad Z to HIGH
3.7
4.1
4.7
5.5
7.7
ns
tENZL
Enable Pad Z to LOW
4.1
4.6
5.2
6.1
8.5
ns
tENHZ
Enable Pad HIGH to Z
7.4
8.2
9.3
10.9
15.3
ns
tENLZ
Enable Pad LOW to Z
6.9
7.6
8.7
10.2
14.3
ns
tGLH
G-to-Pad HIGH
7.0
7.8
8.9
10.4
14.6
ns
tGHL
G-to-Pad LOW
7.0
7.8
8.9
10.4
14.6
ns
tLSU
I/O Latch Set-Up
0.7
0.7
0.8
1.0
1.4
ns
tLH
I/O Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-toPad) 32 I/O
7.9
8.8
10.0
11.8
16.5
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1 -7 6
v6.0
40MX and 42MX FPGA Families
Pin Descriptions
CLK/A/B, I/O
Global Clock
PRA, I/O
Clock inputs for clock distribution networks. CLK is for
40MX while CLKA and CLKB are for 42MX devices. The
clock input is buffered prior to clocking the logic
modules. This pin can also be used as an I/O.
DCLK, I/O
PRB, I/O
The Probe pin is used to output data from any userdefined design node within the device. Each diagnostic
pin can be used in conjunction with the other probe pin
to allow real-time diagnostic output of any signal path
within the device. The Probe pin can be used as a userdefined I/O when verification has been completed. The
pin's probe capabilities can be permanently disabled to
protect programmed design confidentiality. The Probe
pin is accessible when the MODE pin is HIGH. This pin
functions as an I/O when the MODE pin is LOW.
Diagnostic Clock
Clock input for diagnostic probe and device
programming. DCLK is active when the MODE pin is
HIGH. This pin functions as an I/O when the MODE pin is
LOW.
GND
Probe A/B
Ground
Input LOW supply voltage.
QCLKA/B/C/D, I/O
I/O
Quadrant clock inputs for A42MX36 devices. When not
used as a register control signal, these pins can function
as user I/Os.
Input/Output
Input, output, tristate or bi-directional buffer. Input and
output levels are compatible with standard TTL and
CMOS specifications. Unused I/Os pins are configured by
the Designer software as shown in Table 40.
Table 40 •
SDI, I/O
Configuration
A40MX02, A40MX04
Pulled LOW
A42MX09, A42MX16
Pulled LOW
A42MX24, A42MX36
Tristated
Serial Data Input
Serial data input for diagnostic probe and device
programming. SDI is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
Configuration of Unused I/Os
Device
Quadrant Clock
SDO, I/O
Serial Data Output
Serial data output for diagnostic probe and device
programming. SDO is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
SDO is available for 42MX devices only.
In all cases, it is recommended to tie all unused MX I/O
pins to LOW on the board. This applies to all dualpurpose pins when configured as I/Os as well.
When Silicon Explorer II is being used, SDO will act as an
output while the "checksum" command is run. It will
return to user I/O when "checksum" is complete.
LP
TCK, I/O
Low Power Mode
Controls the low power mode of all 42MX devices. The
device is placed in the low power mode by connecting
the LP pin to logic HIGH. In low power mode, all I/Os are
tristated, all input buffers are turned OFF, and the core
of the device is turned OFF. To exit the low power mode,
the LP pin must be set LOW. The device enters the low
power mode 800ns after the LP pin is driven to a logic
HIGH. It will resume normal operation in 200µs after the
LP pin is driven to a logic LOW.
MODE
Clock signal to shift the Boundary Scan Test (BST) data
into the device. This pin functions as an I/O when
"Reserve JTAG" is not checked in the Designer Software.
BST pins are only available in A42MX24 and A42MX36
devices.
TDI, I/O
Test Data In
Serial data input for BST instructions and data. Data is
shifted in on the rising edge of TCK. This pin functions as
an I/O when "Reserve JTAG" is not checked in the
Designer Software. BST pins are only available in
A42MX24 and A42MX36 devices.
Mode
Controls the use of multifunction pins (DCLK, PRA, PRB,
SDI, TDO). The MODE pin is held HIGH to provide
verification capability. The MODE pin should be
terminated to GND through a 10kΩ resistor so that the
MODE pin can be pulled HIGH when required.
NC
Test Clock
TDO, I/O
Test Data Out
Serial data output for BST instructions and test data. This
pin functions as an I/O when "Reserve JTAG" is not
checked in the Designer Software. BST pins are only
available in A42MX24 and A42MX36 devices.
No Connection
This pin is not connected to circuitry within the device.
These pins can be driven to any voltage or can be left
floating with no effect on the operation of the device.
v6.0
1-77
40MX and 42MX FPGA Families
TMS, I/O
Test Mode Select
VCC
The TMS pin controls the use of the IEEE 1149.1
Boundary Scan pins (TCK, TDI, TDO). In flexible mode
when the TMS pin is set LOW, the TCK, TDI and TDO pins
are boundary scan pins. Once the boundary scan pins are
in test mode, they will remain in that mode until the
internal boundary scan state machine reaches the "logic
reset" state. At this point, the boundary scan pins will be
released and will function as regular I/O pins. The "logic
reset" state is reached 5 TCK cycles after the TMS pin is
set HIGH. In dedicated test mode, TMS functions as
specified in the IEEE 1149.1 specifications. IEEE JTAG
specification recommends a 10kΩ pull-up resistor on the
pin. BST pins are only available in A42MX24 and
A42MX36 devices.
1 -7 8
v6.0
Supply Voltage
Input supply voltage for 40MX devices
VCCA
Supply Voltage
Supply voltage for array in 42MX devices
VCCI
Supply Voltage
Supply voltage for I/Os in 42MX devices
WD, I/O
Wide Decode Output
When a wide decode module is used in a 42MX device
this pin can be used as a dedicated output from the wide
decode module. This direct connection eliminates
additional interconnect delays associated with regular
logic modules. To implement the direct I/O connection,
connect an output buffer of any type to the output of
the wide decode macro and place this output on one of
the reserved WD pins.
40MX and 42MX FPGA Families
Package Pin Assignments
44-Pin PLCC
1 44
44-Pin
PLCC
Figure 2-1 • 44-Pin PLCC
44-pin PLCC
44-pin PLCC
Pin Number
Pin Number
A40MX02 Function A40MX04 Function
A40MX02 Function A40MX04 Function
1
I/O
I/O
23
I/O
I/O
2
I/O
I/O
24
I/O
I/O
3
VCC
VCC
25
VCC
VCC
4
I/O
I/O
26
I/O
I/O
5
I/O
I/O
27
I/O
I/O
6
I/O
I/O
28
I/O
I/O
7
I/O
I/O
29
I/O
I/O
8
I/O
I/O
30
I/O
I/O
9
I/O
I/O
31
I/O
I/O
10
GND
GND
32
GND
GND
11
I/O
I/O
33
CLK, I/O
CLK, I/O
12
I/O
I/O
34
MODE
MODE
13
I/O
I/O
35
VCC
VCC
14
VCC
VCC
36
SDI, I/O
SDI, I/O
15
I/O
I/O
37
DCLK, I/O
DCLK, I/O
16
VCC
VCC
38
PRA, I/O
PRA, I/O
17
I/O
I/O
39
PRB, I/O
PRB, I/O
18
I/O
I/O
40
I/O
I/O
19
I/O
I/O
41
I/O
I/O
20
I/O
I/O
42
I/O
I/O
21
GND
GND
43
GND
GND
22
I/O
I/O
44
I/O
I/O
v6.0
2-1
40MX and 42MX FPGA Families
68-Pin PLCC
1 68
68-Pin
PLCC
Figure 2-2 • 68-Pin PLCC
44-pin PLCC
44-pin PLCC
44-pin PLCC
Pin
Number
A40MX02
Function
A40MX04
Function
Pin
Number
A40MX02
Function
A40MX04
Function
Pin
Number
A40MX02
Function
A40MX04
Function
1
I/O
I/O
24
I/O
I/O
47
I/O
I/O
2
I/O
I/O
25
VCC
VCC
48
I/O
I/O
3
I/O
I/O
26
I/O
I/O
49
GND
GND
4
VCC
VCC
27
I/O
I/O
50
I/O
I/O
5
I/O
I/O
28
I/O
I/O
51
I/O
I/O
6
I/O
I/O
29
I/O
I/O
52
CLK, I/O
CLK, I/O
7
I/O
I/O
30
I/O
I/O
53
I/O
I/O
8
I/O
I/O
31
I/O
I/O
54
MODE
MODE
9
I/O
I/O
32
GND
GND
55
VCC
VCC
10
I/O
I/O
33
I/O
I/O
56
SDI, I/O
SDI, I/O
11
I/O
I/O
34
I/O
I/O
57
DCLK, I/O
DCLK, I/O
12
I/O
I/O
35
I/O
I/O
58
PRA, I/O
PRA, I/O
13
I/O
I/O
36
I/O
I/O
59
PRB, I/O
PRB, I/O
14
GND
GND
37
I/O
I/O
60
I/O
I/O
15
GND
GND
38
VCC
VCC
61
I/O
I/O
16
I/O
I/O
39
I/O
I/O
62
I/O
I/O
17
I/O
I/O
40
I/O
I/O
63
I/O
I/O
18
I/O
I/O
41
I/O
I/O
64
I/O
I/O
19
I/O
I/O
42
I/O
I/O
65
I/O
I/O
20
I/O
I/O
43
I/O
I/O
66
GND
GND
21
VCC
VCC
44
I/O
I/O
67
I/O
I/O
22
I/O
I/O
45
I/O
I/O
68
I/O
I/O
23
I/O
I/O
46
I/O
I/O
2 -2
v6.0
40MX and 42MX FPGA Families
84-Pin PLCC
1 84
84-Pin
PLCC
Figure 2-3 • 84-Pin PLCC
v6.0
2-3
40MX and 42MX FPGA Families
84-Pin PLCC
84-Pin PLCC
Pin
Number
2 -4
Pin
Number
A40MX04 A42MX09 A42MX16 A42MX24
Function Function Function Function
A40MX04 A42MX09 A42MX16 A42MX24
Function Function Function Function
1
I/O
I/O
I/O
I/O
36
I/O
I/O
I/O
WD, I/O
2
I/O
CLKB, I/O
CLKB, I/O
CLKB, I/O
37
I/O
I/O
I/O
I/O
3
I/O
I/O
I/O
I/O
38
I/O
I/O
I/O
WD, I/O
4
VCC
PRB, I/O
PRB, I/O
PRB, I/O
39
I/O
I/O
I/O
WD, I/O
5
I/O
I/O
I/O
WD, I/O
40
GND
I/O
I/O
I/O
6
I/O
GND
GND
GND
41
I/O
I/O
I/O
I/O
7
I/O
I/O
I/O
I/O
42
I/O
I/O
I/O
I/O
8
I/O
I/O
I/O
WD, I/O
43
I/O
VCCA
VCCA
VCCA
9
I/O
I/O
I/O
WD, I/O
44
I/O
I/O
I/O
WD, I/O
10
I/O
DCLK, I/O
DCLK, I/O
DCLK, I/O
45
I/O
I/O
I/O
WD, I/O
11
I/O
I/O
I/O
I/O
46
VCC
I/O
I/O
WD, I/O
12
NC
MODE
MODE
MODE
47
I/O
I/O
I/O
WD, I/O
13
I/O
I/O
I/O
I/O
48
I/O
I/O
I/O
I/O
14
I/O
I/O
I/O
I/O
49
I/O
GND
GND
GND
15
I/O
I/O
I/O
I/O
50
I/O
I/O
I/O
WD, I/O
16
I/O
I/O
I/O
I/O
51
I/O
I/O
I/O
WD, I/O
17
I/O
I/O
I/O
I/O
52
I/O
SDO, I/O
SDO, I/O
SDO, TDO, I/O
18
GND
I/O
I/O
I/O
53
I/O
I/O
I/O
I/O
19
GND
I/O
I/O
I/O
54
I/O
I/O
I/O
I/O
20
I/O
I/O
I/O
I/O
55
I/O
I/O
I/O
I/O
21
I/O
I/O
I/O
I/O
56
I/O
I/O
I/O
I/O
22
I/O
VCCA
VCCI
VCCI
57
I/O
I/O
I/O
I/O
23
I/O
VCCI
VCCA
VCCA
58
I/O
I/O
I/O
I/O
24
I/O
I/O
I/O
I/O
59
I/O
I/O
I/O
I/O
25
VCC
I/O
I/O
I/O
60
GND
I/O
I/O
I/O
26
VCC
I/O
I/O
I/O
61
GND
I/O
I/O
I/O
27
I/O
I/O
I/O
I/O
62
I/O
I/O
I/O
TCK, I/O
28
I/O
GND
GND
GND
63
I/O
LP
LP
LP
29
I/O
I/O
I/O
I/O
64
CLK, I/O
VCCA
VCCA
VCCA
30
I/O
I/O
I/O
I/O
65
I/O
VCCI
VCCI
VCCI
31
I/O
I/O
I/O
I/O
66
MODE
I/O
I/O
I/O
32
I/O
I/O
I/O
I/O
67
VCC
I/O
I/O
I/O
33
VCC
I/O
I/O
I/O
68
VCC
I/O
I/O
I/O
34
I/O
I/O
I/O
TMS, I/O
69
I/O
I/O
I/O
I/O
35
I/O
I/O
I/O
TDI, I/O
70
I/O
GND
GND
GND
v6.0
40MX and 42MX FPGA Families
84-Pin PLCC
84-Pin PLCC
Pin
Number
Pin
Number
A40MX04 A42MX09 A42MX16 A42MX24
Function Function Function Function
A40MX04 A42MX09 A42MX16 A42MX24
Function Function Function Function
71
I/O
I/O
I/O
I/O
78
I/O
I/O
I/O
WD, I/O
72
SDI, I/O
I/O
I/O
I/O
79
I/O
I/O
I/O
WD, I/O
73
DCLK, I/O
I/O
I/O
I/O
80
I/O
I/O
I/O
WD, I/O
74
PRA, I/O
I/O
I/O
I/O
81
I/O
PRA, I/O
PRA, I/O
PRA, I/O
75
PRB, I/O
I/O
I/O
I/O
82
GND
I/O
I/O
I/O
76
I/O
SDI, I/O
SDI, I/O
SDI, I/O
83
I/O
CLKA, I/O
CLKA, I/O
CLKA, I/O
77
I/O
I/O
I/O
I/O
84
I/O
VCCA
VCCA
VCCA
v6.0
2-5
40MX and 42MX FPGA Families
100-Pin PQFP Package
100-Pin
PQFP
100
1
Figure 2-4 • 100-Pin PQFP Package (Top View)
2 -6
v6.0
40MX and 42MX FPGA Families
100-Pin PQFP
100-Pin PQFP
Pin
Number
Pin
Number
A40MX02 A40MX04 A42MX09 A42MX16
Function Function Function Function
A40MX02 A40MX04 A42MX09 A42MX16
Function Function Function Function
1
NC
NC
I/O
I/O
36
GND
GND
I/O
I/O
2
NC
NC
DCLK, I/O
DCLK, I/O
37
GND
GND
I/O
I/O
3
NC
NC
I/O
I/O
38
I/O
I/O
I/O
I/O
4
NC
NC
MODE
MODE
39
I/O
I/O
I/O
I/O
5
NC
NC
I/O
I/O
40
I/O
I/O
VCCA
VCCA
6
PRB, I/O
PRB, I/O
I/O
I/O
41
I/O
I/O
I/O
I/O
7
I/O
I/O
I/O
I/O
42
I/O
I/O
I/O
I/O
8
I/O
I/O
I/O
I/O
43
VCC
VCC
I/O
I/O
9
I/O
I/O
GND
GND
44
VCC
VCC
I/O
I/O
10
I/O
I/O
I/O
I/O
45
I/O
I/O
I/O
I/O
11
I/O
I/O
I/O
I/O
46
I/O
I/O
GND
GND
12
I/O
I/O
I/O
I/O
47
I/O
I/O
I/O
I/O
13
GND
GND
I/O
I/O
48
NC
I/O
I/O
I/O
14
I/O
I/O
I/O
I/O
49
NC
I/O
I/O
I/O
15
I/O
I/O
I/O
I/O
50
NC
I/O
I/O
I/O
16
I/O
I/O
VCCA
VCCA
51
NC
NC
I/O
I/O
17
I/O
I/O
VCCI
VCCA
52
NC
NC
SDO, I/O
SDO, I/O
18
I/O
I/O
I/O
I/O
53
NC
NC
I/O
I/O
19
VCC
VCC
I/O
I/O
54
NC
NC
I/O
I/O
20
I/O
I/O
I/O
I/O
55
NC
NC
I/O
I/O
21
I/O
I/O
I/O
I/O
56
VCC
VCC
I/O
I/O
22
I/O
I/O
GND
GND
57
I/O
I/O
GND
GND
23
I/O
I/O
I/O
I/O
58
I/O
I/O
I/O
I/O
24
I/O
I/O
I/O
I/O
59
I/O
I/O
I/O
I/O
25
I/O
I/O
I/O
I/O
60
I/O
I/O
I/O
I/O
26
I/O
I/O
I/O
I/O
61
I/O
I/O
I/O
I/O
27
NC
NC
I/O
I/O
62
I/O
I/O
I/O
I/O
28
NC
NC
I/O
I/O
63
GND
GND
I/O
I/O
29
NC
NC
I/O
I/O
64
I/O
I/O
LP
LP
30
NC
NC
I/O
I/O
65
I/O
I/O
VCCA
VCCA
31
NC
I/O
I/O
I/O
66
I/O
I/O
VCCI
VCCI
32
NC
I/O
I/O
I/O
67
I/O
I/O
VCCA
VCCA
33
NC
I/O
I/O
I/O
68
I/O
I/O
I/O
I/O
34
I/O
I/O
GND
GND
69
VCC
VCC
I/O
I/O
35
I/O
I/O
I/O
I/O
70
I/O
I/O
I/O
I/O
v6.0
2-7
40MX and 42MX FPGA Families
100-Pin PQFP
100-Pin PQFP
Pin
Number
2 -8
Pin
Number
A40MX02 A40MX04 A42MX09 A42MX16
Function Function Function Function
A40MX02 A40MX04 A42MX09 A42MX16
Function Function Function Function
71
I/O
I/O
I/O
I/O
86
GND
GND
I/O
I/O
72
I/O
I/O
GND
GND
87
GND
GND
PRA, I/O
PRA, I/O
73
I/O
I/O
I/O
I/O
88
I/O
I/O
I/O
I/O
74
I/O
I/O
I/O
I/O
89
I/O
I/O
CLKA, I/O
CLKA, I/O
75
I/O
I/O
I/O
I/O
90
CLK, I/O
CLK, I/O
VCCA
VCCA
76
I/O
I/O
I/O
I/O
91
I/O
I/O
I/O
I/O
77
NC
NC
I/O
I/O
92
MODE
MODE
CLKB, I/O
CLKB, I/O
78
NC
NC
I/O
I/O
93
VCC
VCC
I/O
I/O
79
NC
NC
SDI, I/O
SDI, I/O
94
VCC
VCC
PRB, I/O
PRB, I/O
80
NC
I/O
I/O
I/O
95
NC
I/O
I/O
I/O
81
NC
I/O
I/O
I/O
96
NC
I/O
GND
GND
82
NC
I/O
I/O
I/O
97
NC
I/O
I/O
I/O
83
I/O
I/O
I/O
I/O
98
SDI, I/O
SDI, I/O
I/O
I/O
84
I/O
I/O
GND
GND
99
DCLK, I/O
DCLK, I/O
I/O
I/O
85
I/O
I/O
I/O
I/O
100
PRA, I/O
PRA, I/O
I/O
I/O
v6.0
40MX and 42MX FPGA Families
160-Pin PQFP Package
160
1
160-Pin
PQFP
Figure 2-5 • 160-Pin PQFP Package (Top View)
v6.0
2-9
40MX and 42MX FPGA Families
160-Pin PQFP
160-Pin PQFP
Pin Number
A42MX09
Function
A42MX16
Function
A42MX24
Function
Pin Number
A42MX09
Function
A42MX16
Function
A42MX24
Function
1
I/O
I/O
I/O
36
I/O
I/O
WD, I/O
2
DCLK, I/O
DCLK, I/O
DCLK, I/O
37
I/O
I/O
WD, I/O
3
NC
I/O
I/O
38
SDI, I/O
SDI, I/O
SDI, I/O
4
I/O
I/O
WD, I/O
39
I/O
I/O
I/O
5
I/O
I/O
WD, I/O
40
GND
GND
GND
6
NC
VCCI
VCCI
41
I/O
I/O
I/O
7
I/O
I/O
I/O
42
I/O
I/O
I/O
8
I/O
I/O
I/O
43
I/O
I/O
I/O
9
I/O
I/O
I/O
44
GND
GND
GND
10
NC
I/O
I/O
45
I/O
I/O
I/O
11
GND
GND
GND
46
I/O
I/O
I/O
12
NC
I/O
I/O
47
I/O
I/O
I/O
13
I/O
I/O
WD, I/O
48
I/O
I/O
I/O
14
I/O
I/O
WD, I/O
49
GND
GND
GND
15
I/O
I/O
I/O
50
I/O
I/O
I/O
16
PRB, I/O
PRB, I/O
PRB, I/O
51
I/O
I/O
I/O
17
I/O
I/O
I/O
52
NC
I/O
I/O
18
CLKB, I/O
CLKB, I/O
CLKB, I/O
53
I/O
I/O
I/O
19
I/O
I/O
I/O
54
NC
VCCA
VCCA
20
VCCA
VCCA
VCCA
55
I/O
I/O
I/O
21
CLKA, I/O
CLKA, I/O
CLKA, I/O
56
I/O
I/O
I/O
22
I/O
I/O
I/O
57
VCCA
VCCA
VCCA
23
PRA, I/O
PRA, I/O
PRA, I/O
58
VCCI
VCCI
VCCI
24
NC
I/O
WD, I/O
59
GND
GND
GND
25
I/O
I/O
WD, I/O
60
VCCA
VCCA
VCCA
26
I/O
I/O
I/O
61
LP
LP
LP
27
I/O
I/O
I/O
62
I/O
I/O
TCK, I/O
28
NC
I/O
I/O
63
I/O
I/O
I/O
29
I/O
I/O
WD, I/O
64
GND
GND
GND
30
GND
GND
GND
65
I/O
I/O
I/O
31
NC
I/O
WD, I/O
66
I/O
I/O
I/O
32
I/O
I/O
I/O
67
I/O
I/O
I/O
33
I/O
I/O
I/O
68
I/O
I/O
I/O
34
I/O
I/O
I/O
69
GND
GND
GND
35
NC
VCCI
VCCI
70
NC
I/O
I/O
2 -1 0
v6.0
40MX and 42MX FPGA Families
160-Pin PQFP
160-Pin PQFP
Pin Number
A42MX09
Function
A42MX16
Function
A42MX24
Function
Pin Number
A42MX09
Function
A42MX16
Function
A42MX24
Function
71
I/O
I/O
I/O
106
I/O
I/O
WD, I/O
72
I/O
I/O
I/O
107
I/O
I/O
WD, I/O
73
I/O
I/O
I/O
108
I/O
I/O
I/O
74
I/O
I/O
I/O
109
GND
GND
GND
75
NC
I/O
I/O
110
NC
I/O
I/O
76
I/O
I/O
I/O
111
I/O
I/O
WD, I/O
77
NC
I/O
I/O
112
I/O
I/O
WD, I/O
78
I/O
I/O
I/O
113
I/O
I/O
I/O
79
NC
I/O
I/O
114
NC
VCCI
VCCI
80
GND
GND
GND
115
I/O
I/O
WD, I/O
81
I/O
I/O
I/O
116
NC
I/O
WD, I/O
82
SDO, I/O
SDO, I/O
SDO, TDO, I/O
117
I/O
I/O
I/O
83
I/O
I/O
WD, I/O
118
I/O
I/O
TDI, I/O
84
I/O
I/O
WD, I/O
119
I/O
I/O
TMS, I/O
85
I/O
I/O
I/O
120
GND
GND
GND
86
NC
VCCI
VCCI
121
I/O
I/O
I/O
87
I/O
I/O
I/O
122
I/O
I/O
I/O
88
I/O
I/O
WD, I/O
123
I/O
I/O
I/O
89
GND
GND
GND
124
NC
I/O
I/O
90
NC
I/O
I/O
125
GND
GND
GND
91
I/O
I/O
I/O
126
I/O
I/O
I/O
92
I/O
I/O
I/O
127
I/O
I/O
I/O
93
I/O
I/O
I/O
128
I/O
I/O
I/O
94
I/O
I/O
I/O
129
NC
I/O
I/O
95
I/O
I/O
I/O
130
GND
GND
GND
96
I/O
I/O
WD, I/O
131
I/O
I/O
I/O
97
I/O
I/O
I/O
132
I/O
I/O
I/O
98
VCCA
VCCA
VCCA
133
I/O
I/O
I/O
99
GND
GND
GND
134
I/O
I/O
I/O
100
NC
I/O
I/O
135
NC
VCCA
VCCA
101
I/O
I/O
I/O
136
I/O
I/O
I/O
102
I/O
I/O
I/O
137
I/O
I/O
I/O
103
NC
I/O
I/O
138
NC
VCCA
VCCA
104
I/O
I/O
I/O
139
VCCI
VCCI
VCCI
105
I/O
I/O
I/O
140
GND
GND
GND
v6.0
2-11
40MX and 42MX FPGA Families
160-Pin PQFP
160-Pin PQFP
Pin Number
A42MX09
Function
A42MX16
Function
A42MX24
Function
Pin Number
A42MX09
Function
A42MX16
Function
A42MX24
Function
141
NC
I/O
I/O
151
NC
I/O
I/O
142
I/O
I/O
I/O
152
NC
I/O
I/O
143
I/O
I/O
I/O
153
NC
I/O
I/O
144
I/O
I/O
I/O
154
NC
I/O
I/O
145
GND
GND
GND
155
GND
GND
GND
146
NC
I/O
I/O
156
I/O
I/O
I/O
147
I/O
I/O
I/O
157
I/O
I/O
I/O
148
I/O
I/O
I/O
158
I/O
I/O
I/O
149
I/O
I/O
I/O
159
MODE
MODE
MODE
150
NC
VCCA
VCCA
160
GND
GND
GND
2 -1 2
v6.0
40MX and 42MX FPGA Families
208-Pin PQFP Package
1
208
208-Pin PQFP
Figure 2-6 • 208-Pin PQFP Package (Top View)
v6.0
2-13
40MX and 42MX FPGA Families
208-Pin PQFP
208-Pin PQFP
Pin Number
A42MX16
Function
A42MX24
Function
A42MX36
Function
Pin Number
A42MX16
Function
A42MX24
Function
A42MX36
Function
1
GND
GND
GND
36
I/O
I/O
I/O
2
NC
VCCA
VCCA
37
I/O
I/O
I/O
3
MODE
MODE
MODE
38
I/O
I/O
I/O
4
I/O
I/O
I/O
39
I/O
I/O
I/O
5
I/O
I/O
I/O
40
I/O
I/O
I/O
6
I/O
I/O
I/O
41
NC
I/O
I/O
7
I/O
I/O
I/O
42
NC
I/O
I/O
8
I/O
I/O
I/O
43
NC
I/O
I/O
9
NC
I/O
I/O
44
I/O
I/O
I/O
10
NC
I/O
I/O
45
I/O
I/O
I/O
11
NC
I/O
I/O
46
I/O
I/O
I/O
12
I/O
I/O
I/O
47
I/O
I/O
I/O
13
I/O
I/O
I/O
48
I/O
I/O
I/O
14
I/O
I/O
I/O
49
I/O
I/O
I/O
15
I/O
I/O
I/O
50
NC
I/O
I/O
16
NC
I/O
I/O
51
NC
I/O
I/O
17
VCCA
VCCA
VCCA
52
GND
GND
GND
18
I/O
I/O
I/O
53
GND
GND
GND
19
I/O
I/O
I/O
54
I/O
TMS, I/O
TMS, I/O
20
I/O
I/O
I/O
55
I/O
TDI, I/O
TDI, I/O
21
I/O
I/O
I/O
56
I/O
I/O
I/O
22
GND
GND
GND
57
I/O
WD, I/O
WD, I/O
23
I/O
I/O
I/O
58
I/O
WD, I/O
WD, I/O
24
I/O
I/O
I/O
59
I/O
I/O
I/O
25
I/O
I/O
I/O
60
VCCI
VCCI
VCCI
26
I/O
I/O
I/O
61
NC
I/O
I/O
27
GND
GND
GND
62
NC
I/O
I/O
28
VCCI
VCCI
VCCI
63
I/O
I/O
I/O
29
VCCA
VCCA
VCCA
64
I/O
I/O
I/O
30
I/O
I/O
I/O
65
I/O
I/O
QCLKA, I/O
31
I/O
I/O
I/O
66
I/O
WD, I/O
WD, I/O
32
VCCA
VCCA
VCCA
67
NC
WD, I/O
WD, I/O
33
I/O
I/O
I/O
68
NC
I/O
I/O
34
I/O
I/O
I/O
69
I/O
I/O
I/O
35
I/O
I/O
I/O
70
I/O
WD, I/O
WD, I/O
2 -1 4
v6.0
40MX and 42MX FPGA Families
208-Pin PQFP
208-Pin PQFP
Pin Number
A42MX16
Function
A42MX24
Function
A42MX36
Function
Pin Number
A42MX16
Function
A42MX24
Function
A42MX36
Function
71
I/O
WD, I/O
WD, I/O
106
NC
VCCA
VCCA
72
I/O
I/O
I/O
107
I/O
I/O
I/O
73
I/O
I/O
I/O
108
I/O
I/O
I/O
74
I/O
I/O
I/O
109
I/O
I/O
I/O
75
I/O
I/O
I/O
110
I/O
I/O
I/O
76
I/O
I/O
I/O
111
I/O
I/O
I/O
77
I/O
I/O
I/O
112
NC
I/O
I/O
78
GND
GND
GND
113
NC
I/O
I/O
79
VCCA
VCCA
VCCA
114
NC
I/O
I/O
80
NC
VCCI
VCCI
115
NC
I/O
I/O
81
I/O
I/O
I/O
116
I/O
I/O
I/O
82
I/O
I/O
I/O
117
I/O
I/O
I/O
83
I/O
I/O
I/O
118
I/O
I/O
I/O
84
I/O
I/O
I/O
119
I/O
I/O
I/O
85
I/O
WD, I/O
WD, I/O
120
I/O
I/O
I/O
86
I/O
WD, I/O
WD, I/O
121
I/O
I/O
I/O
87
I/O
I/O
I/O
122
I/O
I/O
I/O
88
I/O
I/O
I/O
123
I/O
I/O
I/O
89
NC
I/O
I/O
124
I/O
I/O
I/O
90
NC
I/O
I/O
125
I/O
I/O
I/O
91
I/O
I/O
QCLKB, I/O
126
GND
GND
GND
92
I/O
I/O
I/O
127
I/O
I/O
I/O
93
I/O
WD, I/O
WD, I/O
128
I/O
TCK, I/O
TCK, I/O
94
I/O
WD, I/O
WD, I/O
129
LP
LP
LP
95
NC
I/O
I/O
130
VCCA
VCCA
VCCA
96
NC
I/O
I/O
131
GND
GND
GND
97
NC
I/O
I/O
132
VCCI
VCCI
VCCI
98
VCCI
VCCI
VCCI
133
VCCA
VCCA
VCCA
99
I/O
I/O
I/O
134
I/O
I/O
I/O
100
I/O
WD, I/O
WD, I/O
135
I/O
I/O
I/O
101
I/O
WD, I/O
WD, I/O
136
VCCA
VCCA
VCCA
102
I/O
I/O
I/O
137
I/O
I/O
I/O
103
SDO, I/O
138
I/O
I/O
I/O
104
I/O
I/O
I/O
139
I/O
I/O
I/O
105
GND
GND
GND
140
I/O
I/O
I/O
SDO, TDO, I/O SDO, TDO, I/O
v6.0
2-15
40MX and 42MX FPGA Families
208-Pin PQFP
208-Pin PQFP
Pin Number
A42MX16
Function
A42MX24
Function
A42MX36
Function
Pin Number
A42MX16
Function
A42MX24
Function
A42MX36
Function
141
NC
I/O
I/O
175
I/O
I/O
I/O
142
I/O
I/O
I/O
176
I/O
WD, I/O
WD, I/O
143
I/O
I/O
I/O
177
I/O
WD, I/O
WD, I/O
144
I/O
I/O
I/O
178
PRA, I/O
PRA, I/O
PRA, I/O
145
I/O
I/O
I/O
179
I/O
I/O
I/O
146
NC
I/O
I/O
180
CLKA, I/O
CLKA, I/O
CLKA, I/O
147
NC
I/O
I/O
181
NC
I/O
I/O
148
NC
I/O
I/O
182
NC
VCCI
VCCI
149
NC
I/O
I/O
183
VCCA
VCCA
VCCA
150
GND
GND
GND
184
GND
GND
GND
151
I/O
I/O
I/O
185
I/O
I/O
I/O
152
I/O
I/O
I/O
186
CLKB, I/O
CLKB, I/O
CLKB, I/O
153
I/O
I/O
I/O
187
I/O
I/O
I/O
154
I/O
I/O
I/O
188
PRB, I/O
PRB, I/O
PRB, I/O
155
I/O
I/O
I/O
189
I/O
I/O
I/O
156
I/O
I/O
I/O
190
I/O
WD, I/O
WD, I/O
157
GND
GND
GND
191
I/O
WD, I/O
WD, I/O
158
I/O
I/O
I/O
192
I/O
I/O
I/O
159
SDI, I/O
SDI, I/O
SDI, I/O
193
NC
I/O
I/O
160
I/O
I/O
I/O
194
NC
WD, I/O
WD, I/O
161
I/O
WD, I/O
WD, I/O
195
NC
WD, I/O
WD, I/O
162
I/O
WD, I/O
WD, I/O
196
I/O
I/O
QCLKC, I/O
163
I/O
I/O
I/O
197
NC
I/O
I/O
164
VCCI
VCCI
VCCI
198
I/O
I/O
I/O
165
NC
I/O
I/O
199
I/O
I/O
I/O
166
NC
I/O
I/O
200
I/O
I/O
I/O
167
I/O
I/O
I/O
201
NC
I/O
I/O
168
I/O
WD, I/O
WD, I/O
202
VCCI
VCCI
VCCI
169
I/O
WD, I/O
WD, I/O
203
I/O
WD, I/O
WD, I/O
170
I/O
I/O
I/O
204
I/O
WD, I/O
WD, I/O
171
NC
I/O
QCLKD, I/O
205
I/O
I/O
I/O
172
I/O
I/O
I/O
206
I/O
I/O
I/O
173
I/O
I/O
I/O
207
DCLK, I/O
DCLK, I/O
DCLK, I/O
174
I/O
I/O
I/O
208
I/O
I/O
I/O
2 -1 6
v6.0
40MX and 42MX FPGA Families
•
•
•
240-Pin PQFP Package
240
1
240-Pin
PQFP
•
•
•
•
•
•
•
•
•
Figure 2-7 • 240-Pin PQFP Package (Top View)
v6.0
2-17
40MX and 42MX FPGA Families
240-Pin PQFP
240-Pin PQFP
240-Pin PQFP
240-Pin PQFP
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
1
I/O
36
I/O
71
VCCI
106
I/O
2
DCLK, I/O
37
WD, I/O
72
I/O
107
I/O
3
I/O
38
WD, I/O
73
I/O
108
VCCI
4
I/O
39
I/O
74
I/O
109
I/O
5
I/O
40
I/O
75
I/O
110
I/O
6
WD, I/O
41
I/O
76
I/O
111
I/O
7
WD, I/O
42
I/O
77
I/O
112
I/O
8
VCCI
43
I/O
78
I/O
113
I/O
9
I/O
44
I/O
79
I/O
114
I/O
10
I/O
45
QCLKD, I/O
80
I/O
115
I/O
11
I/O
46
I/O
81
I/O
116
I/O
12
I/O
47
WD, I/O
82
I/O
117
I/O
13
I/O
48
WD, I/O
83
I/O
118
VCCA
14
I/O
49
I/O
84
I/O
119
GND
15
QCLKC, I/O
50
I/O
85
VCCA
120
GND
16
I/O
51
I/O
86
I/O
121
GND
17
WD, I/O
52
VCCI
87
I/O
122
I/O
18
WD, I/O
53
I/O
88
VCCA
123
SDO, TDO, I/O
19
I/O
54
WD, I/O
89
VCCI
124
I/O
20
I/O
55
WD, I/O
90
VCCA
125
WD, I/O
21
WD, I/O
56
I/O
91
LP
126
WD, I/O
22
WD, I/O
57
SDI, I/O
92
TCK, I/O
127
I/O
23
I/O
58
I/O
93
I/O
128
VCCI
24
PRB, I/O
59
VCCA
94
GND
129
I/O
25
I/O
60
GND
95
I/O
130
I/O
26
CLKB, I/O
61
GND
96
I/O
131
I/O
27
I/O
62
I/O
97
I/O
132
WD, I/O
28
GND
63
I/O
98
I/O
133
WD, I/O
29
VCCA
64
I/O
99
I/O
134
I/O
30
VCCI
65
I/O
100
I/O
135
QCLKB, I/O
31
I/O
66
I/O
101
I/O
136
I/O
32
CLKA, I/O
67
I/O
102
I/O
137
I/O
33
I/O
68
I/O
103
I/O
138
I/O
34
PRA, I/O
69
I/O
104
I/O
139
I/O
35
I/O
70
I/O
105
I/O
140
I/O
2 -1 8
v6.0
40MX and 42MX FPGA Families
240-Pin PQFP
240-Pin PQFP
240-Pin PQFP
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
141
I/O
176
I/O
211
I/O
142
WD, I/O
177
I/O
212
I/O
143
WD, I/O
178
TDI, I/O
213
I/O
144
I/O
179
TMS, I/O
214
I/O
145
I/O
180
GND
215
I/O
146
I/O
181
VCCA
216
I/O
147
I/O
182
GND
217
I/O
148
I/O
183
I/O
218
I/O
149
I/O
184
I/O
219
VCCA
150
VCCI
185
I/O
220
I/O
151
VCCA
186
I/O
221
I/O
152
GND
187
I/O
222
I/O
153
I/O
188
I/O
223
I/O
154
I/O
189
I/O
224
I/O
155
I/O
190
I/O
225
I/O
156
I/O
191
I/O
226
I/O
157
I/O
192
VCCI
227
VCCI
158
I/O
193
I/O
228
I/O
159
WD, I/O
194
I/O
229
I/O
160
WD, I/O
195
I/O
230
I/O
161
I/O
196
I/O
231
I/O
162
I/O
197
I/O
232
I/O
163
WD, I/O
198
I/O
233
I/O
164
WD, I/O
199
I/O
234
I/O
165
I/O
200
I/O
235
I/O
166
QCLKA, I/O
201
I/O
236
I/O
167
I/O
202
I/O
237
GND
168
I/O
203
I/O
238
MODE
169
I/O
204
I/O
239
VCCA
170
I/O
205
I/O
240
GND
171
I/O
206
VCCA
172
VCCI
207
I/O
173
I/O
208
I/O
174
WD, I/O
209
VCCA
175
WD, I/O
210
VCCI
v6.0
2-19
40MX and 42MX FPGA Families
80-Pin VQFP
80
1
80-Pin
VQFP
Figure 2-8 • 80-Pin VQFP
2 -2 0
v6.0
40MX and 42MX FPGA Families
80-Pin VQFP
80-Pin VQFP
80-Pin VQFP
Pin
Number
A40MX02
Function
A40MX04
Function
Pin
Number
A40MX02
Function
A40MX04
Function
Pin
Number
A40MX02
Function
A40MX04
Function
1
I/O
I/O
28
I/O
I/O
55
NC
I/O
2
NC
I/O
29
I/O
I/O
56
NC
I/O
3
NC
I/O
30
I/O
I/O
57
SDI, I/O
SDI, I/O
4
NC
I/O
31
I/O
I/O
58
DCLK, I/O
DCLK, I/O
5
I/O
I/O
32
I/O
I/O
59
PRA, I/O
PRA, I/O
6
I/O
I/O
33
VCC
VCC
60
NC
NC
7
GND
GND
34
I/O
I/O
61
PRB, I/O
PRB, I/O
8
I/O
I/O
35
I/O
I/O
62
I/O
I/O
9
I/O
I/O
36
I/O
I/O
63
I/O
I/O
10
I/O
I/O
37
I/O
I/O
64
I/O
I/O
11
I/O
I/O
38
I/O
I/O
65
I/O
I/O
12
I/O
I/O
39
I/O
I/O
66
I/O
I/O
13
VCC
VCC
40
I/O
I/O
67
I/O
I/O
14
I/O
I/O
41
NC
I/O
68
GND
GND
15
I/O
I/O
42
NC
I/O
69
I/O
I/O
16
I/O
I/O
43
NC
I/O
70
I/O
I/O
17
NC
I/O
44
I/O
I/O
71
I/O
I/O
18
NC
I/O
45
I/O
I/O
72
I/O
I/O
19
NC
I/O
46
I/O
I/O
73
I/O
I/O
20
VCC
VCC
47
GND
GND
74
VCC
VCC
21
I/O
I/O
48
I/O
I/O
75
I/O
I/O
22
I/O
I/O
49
I/O
I/O
76
I/O
I/O
23
I/O
I/O
50
CLK, I/O
CLK, I/O
77
I/O
I/O
24
I/O
I/O
51
I/O
I/O
78
I/O
I/O
25
I/O
I/O
52
MODE
MODE
79
I/O
I/O
26
I/O
I/O
53
VCC
VCC
80
I/O
I/O
27
GND
GND
54
NC
I/O
v6.0
2-21
40MX and 42MX FPGA Families
100-Pin VQFP Package
100
1
100-Pin
VQFP
Figure 2-9 • 100-Pin VQFP Package (Top View)
2 -2 2
v6.0
40MX and 42MX FPGA Families
100-Pin VQFP Package
100-Pin VQFP Package
100-Pin VQFP Package
Pin
Number
A42MX09
Function
A42MX16
Function
Pin
Number
A42MX09
Function
A42MX16
Function
Pin
Number
A42MX09
Function
A42MX16
Function
1
I/O
I/O
36
I/O
I/O
71
I/O
I/O
2
MODE
MODE
37
I/O
I/O
72
I/O
I/O
3
I/O
I/O
38
VCCA
VCCA
73
I/O
I/O
4
I/O
I/O
39
I/O
I/O
74
I/O
I/O
5
I/O
I/O
40
I/O
I/O
75
I/O
I/O
6
I/O
I/O
41
I/O
I/O
76
I/O
I/O
7
GND
GND
42
I/O
I/O
77
SDI, I/O
SDI, I/O
8
I/O
I/O
43
I/O
I/O
78
I/O
I/O
9
I/O
I/O
44
GND
GND
79
I/O
I/O
10
I/O
I/O
45
I/O
I/O
80
I/O
I/O
11
I/O
I/O
46
I/O
I/O
81
I/O
I/O
12
I/O
I/O
47
I/O
I/O
82
GND
GND
13
I/O
I/O
48
I/O
I/O
83
I/O
I/O
14
VCCA
NC
49
I/O
I/O
84
I/O
I/O
15
VCCI
VCCI
50
SDO, I/O
SDO, I/O
85
PRA, I/O
PRA, I/O
16
I/O
I/O
51
I/O
I/O
86
I/O
I/O
17
I/O
I/O
52
I/O
I/O
87
CLKA, I/O
CLKA, I/O
18
I/O
I/O
53
I/O
I/O
88
VCCA
VCCA
19
I/O
I/O
54
I/O
I/O
89
I/O
I/O
20
GND
GND
55
GND
GND
90
CLKB, I/O
CLKB, I/O
21
I/O
I/O
56
I/O
I/O
91
I/O
I/O
22
I/O
I/O
57
I/O
I/O
92
PRB, I/O
PRB, I/O
23
I/O
I/O
58
I/O
I/O
93
I/O
I/O
24
I/O
I/O
59
I/O
I/O
94
GND
GND
25
I/O
I/O
60
I/O
I/O
95
I/O
I/O
26
I/O
I/O
61
I/O
I/O
96
I/O
I/O
27
I/O
I/O
62
LP
LP
97
I/O
I/O
28
I/O
I/O
63
VCCA
VCCA
98
I/O
I/O
29
I/O
I/O
64
VCCI
VCCI
99
I/O
I/O
30
I/O
I/O
65
VCCA
VCCA
100
DCLK, I/O
DCLK, I/O
31
I/O
I/O
66
I/O
I/O
32
GND
GND
67
I/O
I/O
33
I/O
I/O
68
I/O
I/O
34
I/O
I/O
69
I/O
I/O
35
I/O
I/O
70
GND
GND
v6.0
2-23
40MX and 42MX FPGA Families
176-Pin TQFP Package
176
1
176-Pin
TQFP
Figure 2-10 • 176-Pin TQFP Package (Top View)
2 -2 4
v6.0
40MX and 42MX FPGA Families
176-Pin TQFP
176-Pin TQFP
Pin Number
A42MX09
Function
A42MX16
Function
A42MX24
Function
Pin Number
A42MX09
Function
A42MX16
Function
A42MX24
Function
1
GND
GND
GND
36
I/O
I/O
I/O
2
MODE
MODE
MODE
37
NC
I/O
I/O
3
I/O
I/O
I/O
38
NC
NC
I/O
4
I/O
I/O
I/O
39
I/O
I/O
I/O
5
I/O
I/O
I/O
40
I/O
I/O
I/O
6
I/O
I/O
I/O
41
I/O
I/O
I/O
7
I/O
I/O
I/O
42
I/O
I/O
I/O
8
NC
NC
I/O
43
I/O
I/O
I/O
9
I/O
I/O
I/O
44
I/O
I/O
I/O
10
NC
I/O
I/O
45
GND
GND
GND
11
NC
I/O
I/O
46
I/O
I/O
TMS, I/O
12
I/O
I/O
I/O
47
I/O
I/O
TDI, I/O
13
NC
VCCA
VCCA
48
I/O
I/O
I/O
14
I/O
I/O
I/O
49
I/O
I/O
WD, I/O
15
I/O
I/O
I/O
50
I/O
I/O
WD, I/O
16
I/O
I/O
I/O
51
I/O
I/O
I/O
17
I/O
I/O
I/O
52
NC
VCCI
VCCI
18
GND
GND
GND
53
I/O
I/O
I/O
19
NC
I/O
I/O
54
NC
I/O
I/O
20
NC
I/O
I/O
55
NC
I/O
WD, I/O
21
I/O
I/O
I/O
56
I/O
I/O
WD, I/O
22
NC
I/O
I/O
57
NC
NC
I/O
23
GND
GND
GND
58
I/O
I/O
I/O
24
NC
VCCI
VCCI
59
I/O
I/O
WD, I/O
25
VCCA
VCCA
VCCA
60
I/O
I/O
WD, I/O
26
NC
I/O
I/O
61
NC
I/O
I/O
27
NC
I/O
I/O
62
I/O
I/O
I/O
28
VCCI
VCCA
VCCA
63
I/O
I/O
I/O
29
NC
I/O
I/O
64
NC
I/O
I/O
30
I/O
I/O
I/O
65
I/O
I/O
I/O
31
I/O
I/O
I/O
66
NC
I/O
I/O
32
I/O
I/O
I/O
67
GND
GND
GND
33
NC
NC
I/O
68
VCCA
VCCA
VCCA
34
I/O
I/O
I/O
69
I/O
I/O
WD, I/O
35
I/O
I/O
I/O
70
I/O
I/O
WD, I/O
v6.0
2-25
40MX and 42MX FPGA Families
176-Pin TQFP
176-Pin TQFP
Pin Number
A42MX09
Function
A42MX16
Function
A42MX24
Function
Pin Number
A42MX09
Function
A42MX16
Function
A42MX24
Function
71
I/O
I/O
I/O
106
GND
GND
GND
72
I/O
I/O
I/O
107
NC
I/O
I/O
73
I/O
I/O
I/O
108
NC
I/O
TCK, I/O
74
NC
I/O
I/O
109
LP
LP
LP
75
I/O
I/O
I/O
110
VCCA
VCCA
VCCA
76
I/O
I/O
I/O
111
GND
GND
GND
77
NC
NC
WD, I/O
112
VCCI
VCCI
VCCI
78
NC
I/O
WD, I/O
113
VCCA
VCCA
VCCA
79
I/O
I/O
I/O
114
NC
I/O
I/O
80
NC
I/O
I/O
115
NC
I/O
I/O
81
I/O
I/O
I/O
116
NC
VCCA
VCCA
82
NC
VCCI
VCCI
117
I/O
I/O
I/O
83
I/O
I/O
I/O
118
I/O
I/O
I/O
84
I/O
I/O
WD, I/O
119
I/O
I/O
I/O
85
I/O
I/O
WD, I/O
120
I/O
I/O
I/O
86
NC
I/O
I/O
121
NC
NC
I/O
87
SDO, I/O
SDO, I/O
SDO, TDO, I/O
122
I/O
I/O
I/O
88
I/O
I/O
I/O
123
I/O
I/O
I/O
89
GND
GND
GND
124
NC
I/O
I/O
90
I/O
I/O
I/O
125
NC
I/O
I/O
91
I/O
I/O
I/O
126
NC
NC
I/O
92
I/O
I/O
I/O
127
I/O
I/O
I/O
93
I/O
I/O
I/O
128
I/O
I/O
I/O
94
I/O
I/O
I/O
129
I/O
I/O
I/O
95
I/O
I/O
I/O
130
I/O
I/O
I/O
96
NC
I/O
I/O
131
I/O
I/O
I/O
97
NC
I/O
I/O
132
I/O
I/O
I/O
98
I/O
I/O
I/O
133
GND
GND
GND
99
I/O
I/O
I/O
134
I/O
I/O
I/O
100
I/O
I/O
I/O
135
SDI, I/O
SDI, I/O
SDI, I/O
101
NC
NC
I/O
136
NC
I/O
I/O
102
I/O
I/O
I/O
137
I/O
I/O
WD, I/O
103
NC
I/O
I/O
138
I/O
I/O
WD, I/O
104
I/O
I/O
I/O
139
I/O
I/O
I/O
105
I/O
I/O
I/O
140
NC
VCCI
VCCI
2 -2 6
v6.0
40MX and 42MX FPGA Families
176-Pin TQFP
176-Pin TQFP
Pin Number
A42MX09
Function
A42MX16
Function
A42MX24
Function
Pin Number
A42MX09
Function
A42MX16
Function
A42MX24
Function
141
I/O
I/O
I/O
159
I/O
I/O
I/O
142
I/O
I/O
I/O
160
PRB, I/O
PRB, I/O
PRB, I/O
143
NC
I/O
I/O
161
NC
I/O
WD, I/O
144
NC
I/O
WD, I/O
162
I/O
I/O
WD, I/O
145
NC
NC
WD, I/O
163
I/O
I/O
I/O
146
I/O
I/O
I/O
164
I/O
I/O
I/O
147
NC
I/O
I/O
165
NC
NC
WD, I/O
148
I/O
I/O
I/O
166
NC
I/O
WD, I/O
149
I/O
I/O
I/O
167
I/O
I/O
I/O
150
I/O
I/O
WD, I/O
168
NC
I/O
I/O
151
NC
I/O
WD, I/O
169
I/O
I/O
I/O
152
PRA, I/O
PRA, I/O
PRA, I/O
170
NC
VCCI
VCCI
153
I/O
I/O
I/O
171
I/O
I/O
WD, I/O
154
CLKA, I/O
CLKA, I/O
CLKA, I/O
172
I/O
I/O
WD, I/O
155
VCCA
VCCA
VCCA
173
NC
I/O
I/O
156
GND
GND
GND
174
I/O
I/O
I/O
157
I/O
I/O
I/O
175
DCLK, I/O
DCLK, I/O
DCLK, I/O
158
CLKB, I/O
CLKB, I/O
CLKB, I/O
176
I/O
I/O
I/O
v6.0
2-27
40MX and 42MX FPGA Families
208-Pin CQFP
)
208207206205204203202201200
164163162161160159158157
Pin #1
Index
1
2
3
4
5
6
7
8
156
155
154
153
152
151
150
149
A42MX36
208-Pin
CQFP
44
45
46
47
48
49
50
51
52
113
112
111
110
109
108
107
106
105
53 54 55 56 57 58 59 60 61
97 98 99 100101102103104
Figure 2-11 • 208-Pin CQFP (Top View)
2 -2 8
v6.0
40MX and 42MX FPGA Families
208-Pin CQFP
208-Pin CQFP
208-Pin CQFP
208-Pin CQFP
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
1
GND
36
I/O
71
WD, I/O
106
VCCA
2
VCCA
37
I/O
72
I/O
107
I/O
3
MODE
38
I/O
73
I/O
108
I/O
4
I/O
39
I/O
74
I/O
109
I/O
5
I/O
40
I/O
75
I/O
110
I/O
6
I/O
41
I/O
76
I/O
111
I/O
7
I/O
42
I/O
77
I/O
112
I/O
8
I/O
43
I/O
78
GND
113
I/O
9
I/O
44
I/O
79
VCCA
114
I/O
10
I/O
45
I/O
80
VCCI
115
I/O
11
I/O
46
I/O
81
I/O
116
I/O
12
I/O
47
I/O
82
I/O
117
I/O
13
I/O
48
I/O
83
I/O
118
I/O
14
I/O
49
I/O
84
I/O
119
I/O
15
I/O
50
I/O
85
WD, I/O
120
I/O
16
I/O
51
I/O
86
WD, I/O
121
I/O
17
VCCA
52
GND
87
I/O
122
I/O
18
I/O
53
GND
88
I/O
123
I/O
19
I/O
54
TMS, I/O
89
I/O
124
I/O
20
I/O
55
TDI, I/O
90
I/O
125
I/O
21
I/O
56
I/O
91
QCLKB, I/O
126
GND
22
GND
57
WD, I/O
92
I/O
127
I/O
23
I/O
58
WD, I/O
93
WD, I/O
128
TCK, I/O
24
I/O
59
I/O
94
WD, I/O
129
LP
25
I/O
60
VCCI
95
I/O
130
VCCA
26
I/O
61
I/O
96
I/O
131
GND
27
GND
62
I/O
97
I/O
132
VCCI
28
VCCI
63
I/O
98
VCCI
133
VCCA
29
VCCA
64
I/O
99
I/O
134
I/O
30
I/O
65
QCLKA, I/O
100
WD, I/O
135
I/O
31
I/O
66
WD, I/O
101
WD, I/O
136
VCCA
32
VCCA
67
WD, I/O
102
I/O
137
I/O
33
I/O
68
I/O
103
TDO, I/O
138
I/O
34
I/O
69
I/O
104
I/O
139
I/O
35
I/O
70
WD, I/O
105
GND
140
I/O
v6.0
2-29
40MX and 42MX FPGA Families
208-Pin CQFP
208-Pin CQFP
208-Pin CQFP
208-Pin CQFP
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
141
I/O
158
I/O
175
I/O
192
I/O
142
I/O
159
SDI, I/O
176
WD, I/O
193
I/O
143
I/O
160
I/O
177
WD, I/O
194
WD, I/O
144
I/O
161
WD, I/O
178
PRA, I/O
195
WD, I/O
145
I/O
162
WD, I/O
179
I/O
196
QCLKC, I/O
146
I/O
163
I/O
180
CLKA, I/O
197
I/O
147
I/O
164
VCCI
181
I/O
198
I/O
148
I/O
165
I/O
182
VCCI
199
I/O
149
I/O
166
I/O
183
VCCA
200
I/O
150
GND
167
I/O
184
GND
201
I/O
151
I/O
168
WD, I/O
185
I/O
202
VCCI
152
I/O
169
WD, I/O
186
CLKB, I/O
203
WD, I/O
153
I/O
170
I/O
187
I/O
204
WD, I/O
154
I/O
171
QCLKD, I/O
188
PRB, I/O
205
I/O
155
I/O
172
I/O
189
I/O
206
I/O
156
I/O
173
I/O
190
WD, I/O
207
DCLK, I/O
157
GND
174
I/O
191
WD, I/O
208
I/O
2 -3 0
v6.0
40MX and 42MX FPGA Families
256-Pin CQFP
256255254253252251250249248
200199198197196195194193
Pin #1
Index
1
2
3
4
5
6
7
8
192
191
190
189
188
187
186
185
A42MX36
256-Pin
CQFP
56
57
58
59
60
61
62
63
64
137
136
135
134
133
132
131
130
129
65 66 67 68 69 70 71 72 73
121122123124125126127128
Figure 2-12 • 256-Pin CQFP (Top View)
v6.0
2-31
40MX and 42MX FPGA Families
256-Pin CQFP
256-Pin CQFP
256-Pin CQFP
256-Pin CQFP
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
1
NC
36
GND
71
I/O
106
WD, I/O
2
GND
37
I/O
72
VCCI
107
I/O
3
I/O
38
I/O
73
I/O
108
I/O
4
I/O
39
I/O
74
I/O
109
WD, I/O
5
I/O
40
I/O
75
I/O
110
WD, I/O
6
I/O
41
I/O
76
WD, I/O
111
I/O
7
I/O
42
I/O
77
GND
112
QCLKA, I/O
8
I/O
43
I/O
78
WD, I/O
113
I/O
9
I/O
44
I/O
79
I/O
114
GND
10
GND
45
I/O
80
QCLKB, I/O
115
I/O
11
I/O
46
I/O
81
I/O
116
I/O
12
I/O
47
I/O
82
I/O
117
I/O
13
I/O
48
GND
83
I/O
118
I/O
14
I/O
49
I/O
84
I/O
119
VCCI
15
I/O
50
I/O
85
I/O
120
I/O
16
I/O
51
I/O
86
I/O
121
WD, I/O
17
I/O
52
I/O
87
WD, I/O
122
WD, I/O
18
I/O
53
I/O
88
WD, I/O
123
I/O
19
I/O
54
I/O
89
I/O
124
I/O
20
I/O
55
I/O
90
I/O
125
I/O
21
I/O
56
I/O
91
I/O
126
I/O
22
I/O
57
I/O
92
I/O
127
GND
23
I/O
58
I/O
93
I/O
128
NC
24
I/O
59
I/O
94
I/O
129
NC
25
I/O
60
VCCA
95
VCCI
130
NC
26
VCCA
61
GND
96
VCCA
131
GND
27
I/O
62
GND
97
GND
132
I/O
28
I/O
63
NC
98
GND
133
I/O
29
VCCA
64
NC
99
I/O
134
I/O
30
VCCI
65
NC
100
I/O
135
I/O
31
GND
66
I/O
101
I/O
136
I/O
32
VCCA
67
SDO, TDO, I/O
102
I/O
137
I/O
33
LP
68
I/O
103
I/O
138
I/O
34
TCK, I/O
69
WD, I/O
104
I/O
139
GND
35
I/O
70
WD, I/O
105
WD, I/O
140
I/O
2 -3 2
v6.0
40MX and 42MX FPGA Families
256-Pin CQFP
256-Pin CQFP
256-Pin CQFP
256-Pin CQFP
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
141
I/O
176
I/O
211
WD, I/O
246
I/O
142
I/O
177
I/O
212
WD, I/O
247
I/O
143
I/O
178
I/O
213
I/O
248
VCCI
144
I/O
179
I/O
214
I/O
249
I/O
145
I/O
180
GND
215
WD, I/O
250
WD, I/O
146
I/O
181
I/O
216
WD, I/O
251
WD, I/O
147
I/O
182
I/O
217
I/O
252
I/O
148
I/O
183
I/O
218
PRB, I/O
253
SDI, I/O
149
I/O
184
I/O
219
I/O
254
I/O
150
I/O
185
I/O
220
CLKB, I/O
255
GND
151
I/O
186
I/O
221
I/O
256
NC
152
I/O
187
I/O
222
GND
153
I/O
188
MODE
223
GND
154
I/O
189
VCCA
224
VCCA
155
VCCA
190
GND
225
VCCI
156
I/O
191
NC
226
I/O
157
I/O
192
NC
227
CLKA, I/O
158
VCCA
193
NC
228
I/O
159
VCCI
194
I/O
229
PRA, I/O
160
GND
195
DCLK, I/O
230
I/O
161
I/O
196
I/O
231
I/O
162
I/O
197
I/O
232
WD, I/O
163
I/O
198
I/O
233
WD, I/O
164
I/O
199
WD, I/O
234
I/O
165
GND
200
WD, I/O
235
I/O
166
I/O
201
VCCI
236
I/O
167
I/O
202
I/O
237
I/O
168
I/O
203
I/O
238
I/O
169
I/O
204
I/O
239
I/O
170
VCCA
205
I/O
240
QCLKD, I/O
171
I/O
206
GND
241
I/O
172
I/O
207
I/O
242
WD, I/O
173
I/O
208
I/O
243
GND
174
I/O
209
QCLKC, I/O
244
WD, I/O
175
I/O
210
I/O
245
I/O
v6.0
2-33
40MX and 42MX FPGA Families
272-Pin BGA Package
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20
A
B
C
D
E
F
G
272-Pin PBGA
H
J
K
L
M
N
P
R
T
U
V
W
Y
Figure 2-13 • 272-Pin BGA Package (Top View)
2 -3 4
v6.0
40MX and 42MX FPGA Families
272-Pin PBGA
272-Pin PBGA
272-Pin PBGA
272-Pin PBGA
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
A1
GND
B16
I/O
D11
I/O
H2
I/O
A2
GND
B17
WD, I/O
D12
VCCI
H3
I/O
A3
I/O
B18
I/O
D13
I/O
H4
VCCA
A4
WD, I/O
B19
GND
D14
VCCI
H17
I/O
A5
I/O
B20
GND
D15
I/O
H18
I/O
A6
I/O
C1
I/O
D16
VCCA
H19
I/O
A7
WD, I/O
C2
MODE
D17
GND
H20
I/O
A8
WD, I/O
C3
GND
D18
I/O
J1
I/O
A9
I/O
C4
I/O
D19
I/O
J2
I/O
A10
I/O
C5
WD, I/O
D20
I/O
J3
I/O
A11
CLKA
C6
I/O
E1
I/O
J4
VCCI
A12
I/O
C7
QCLKC, I/O
E2
I/O
J9
GND
A13
I/O
C8
I/O
E3
I/O
J10
GND
A14
I/O
C9
I/O
E4
VCCA
J11
GND
A15
I/O
C10
CLKB
E17
VCCI
J12
GND
A16
WD, I/O
C11
PRA, I/O
E18
I/O
J17
VCCA
A17
I/O
C12
WD, I/O
E19
I/O
J18
I/O
A18
I/O
C13
I/O
E20
I/O
J19
I/O
A19
GND
C14
QCLKD, I/O
F1
I/O
J20
I/O
A20
GND
C15
I/O
F2
I/O
K1
I/O
B1
GND
C16
WD, I/O
F3
I/O
K2
I/O
B2
GND
C17
SDI, I/O
F4
VCCI
K3
I/O
B3
DCLK, I/O
C18
I/O
F17
I/O
K4
VCCI
B4
I/O
C19
I/O
F18
I/O
K9
GND
B5
I/O
C20
I/O
F19
I/O
K10
GND
B6
I/O
D1
I/O
F20
I/O
K11
GND
B7
WD, I/O
D2
I/O
G1
I/O
K12
GND
B8
I/O
D3
I/O
G2
I/O
K17
I/O
B9
PRB, I/O
D4
I/O
G3
I/O
K18
VCCA
B10
I/O
D5
VCCI
G4
VCCI
K19
VCCA
B11
I/O
D6
I/O
G17
VCCI
K20
LP
B12
WD, I/O
D7
I/O
G18
I/O
L1
I/O
B13
I/O
D8
VCCA
G19
I/O
L2
I/O
B14
I/O
D9
WD, I/O
G20
I/O
L3
VCCA
B15
WD, I/O
D10
VCCI
H1
I/O
L4
VCCA
v6.0
2-35
40MX and 42MX FPGA Families
272-Pin PBGA
272-Pin PBGA
272-Pin PBGA
272-Pin PBGA
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
L9
GND
P20
I/O
U19
I/O
W13
WD, I/O
L10
GND
R1
I/O
U20
I/O
W14
I/O
L11
GND
R2
I/O
V1
I/O
W15
I/O
L12
GND
R3
I/O
V2
I/O
W16
WD, I/O
L17
VCCI
R4
VCCI
V3
GND
W17
I/O
L18
I/O
R17
VCCI
V4
GND
W18
WD, I/O
L19
I/O
R18
I/O
V5
I/O
W19
GND
L20
TCK, I/O
R19
I/O
V6
I/O
W20
GND
M1
I/O
R20
I/O
V7
I/O
Y1
GND
M2
I/O
T1
I/O
V8
WD, I/O
Y2
GND
M3
I/O
T2
I/O
V9
I/O
Y3
I/O
M4
VCCI
T3
I/O
V10
I/O
Y4
TDI, I/O
M9
GND
T4
I/O
V11
I/O
Y5
WD, I/O
M10
GND
T17
VCCA
V12
I/O
Y6
I/O
M11
GND
T18
I/O
V13
WD, I/O
Y7
QCLKA, I/O
M12
GND
T19
I/O
V14
I/O
Y8
I/O
M17
I/O
T20
I/O
V15
WD, I/O
Y9
I/O
M18
I/O
U1
I/O
V16
I/O
Y10
I/O
M19
I/O
U2
I/O
V17
I/O
Y11
I/O
M20
I/O
U3
I/O
V18
Y12
I/O
N1
I/O
U4
I/O
SDO, TDO,
I/O
Y13
I/O
V19
I/O
Y14
I/O
V20
I/O
Y15
I/O
W1
GND
Y16
I/O
W2
GND
Y17
I/O
W3
I/O
Y18
WD, I/O
W4
TMS, I/O
Y19
GND
W5
I/O
Y20
GND
W6
I/O
W7
I/O
W8
WD, I/O
W9
WD, I/O
W10
I/O
W11
I/O
W12
I/O
N2
N3
N4
N17
N18
N19
N20
2 -3 6
I/O
I/O
VCCI
VCCI
I/O
I/O
I/O
U5
U6
U7
U8
U9
U10
U11
VCCI
WD, I/O
I/O
I/O
WD, I/O
VCCA
VCCI
P1
I/O
U12
I/O
P2
I/O
U13
I/O
P3
I/O
U14
QCLKB, I/O
P4
VCCA
U15
I/O
P17
I/O
U16
VCCI
P18
I/O
U17
I/O
P19
I/O
U18
GND
v6.0
FPGA Families 40MX and 42MX
Datasheet Information
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous version
v5.1
Changes in current version (v 6. 0 )
Page
The "Ease of Integration" section was updated.
1-i
The "Temperature Grade Offerings" section is new.
1-iii
The "Speed Grade Offerings" section is new.
1-iii
The "General Description" section was updated.
1-1
The "MultiPlex I/O Modules" section was updated.
1-6
The "User Security" section was updated.
1-6
Table 1 • Voltage Support of MX Devices was updated.
1-7
The "Power Dissipation" section was updated.
1-8
The "Static Power Component" section was updated.
1-8
The "Equivalent Capacitance" section was updated.
1-8
Figure 1-13 • Silicon Explorer II Setup with 42MX was updated.
1-10
Table 4 • Supported BST Public Instructions was updated.
1-11
Figure 1-14 • 42MX IEEE 1149.1 Boundary Scan Circuitry was updated.
1-11
Table 5 • Boundary Scan Pin Configuration and Functionality was updated.
1-12
The "Development Tool Support" section was updated.
1-13
The Table 7 • Absolute Maximum Ratings for 42MX Devices* and the Table 6 • Absolute 1-14
Maximum Ratings for 40MX Devices* were updated.
The Table 9 • 5V TTL Electrical Specifications was updated.
1-15
The Table 13 • 3.3V LVTTL Electrical Specifications was updated.
1-17
In the "Mixed 5.0V/3.3V Electrical Specifications" section, Table 14 • Absolute Maximum 1-18
Ratings*, Table 15 • Recommended Operating Conditions, and Table 16 • Mixed 5.0V/3.3V
Electrical Specificationswere updated.
The Table 17 • DC Specification (5.0V PCI Signaling)1 was updated.
1
The Table 19 • DC Specification (3.3V PCI Signaling) was updated.
1-19
1-20
The <zBlue>Junction Temperature (TJ) section, "Package Thermal Characteristics" section, and the 1-22
tables were updated.
Figure 1-17 • 40MX Timing Model* was updated.
1-23
Figure 1-19 • 42MX Timing Model (Logic Functions Using Quadrant Clocks)
1-24
The Figure 1-20 • 42MX Timing Model (SRAM Functions) was updated.
1-24
The Figure 1-27 • Output Buffer Latches was updated.
1-27
The Table 22 • 42MX Temperature and Voltage Derating Factors is new.
1-31
The Table 23 • 40MX Temperature and Voltage Derating Factors is new.
1-32
The "Pin Descriptions" section was updated.
1-77
In the 100-Pin PQFP table, the following pins changed:
Pin 64 (42MX09 and 42MX16) has changed to LP
2-7
v6.0
3-1
FPGA Families 40MX and 42MX
Previous version
5.1
v5.0
v4.0.1
Changes in current version (v 6. 0 )
Page
In the 160-Pin PQFP table, the following pins changed:
Pin 61 (42MX09, 42MX16, and 42MX64) has changed to LP
2-10
In the 208-Pin PQFP table, the following pins changed:
Pin 129 (42MX09, 42MX16, and 42MX64) has changed to LP
Pin 198 (42MX09) has changed to I/O
2-14
The n the 240-Pin PQFP table, the following pins changed:
Pin 91 (42MX36) has changed to LP
2-18
In the 100-Pin VQFP Package table, the following pins changed:
Pin 62 (42MX09 and 42MX16) has changed to LP
2-23
In the 176-Pin TQFP table, the following pins changed:
Pin 109 (42MX09 and 42MX16) has changed to LP
2-25
In the 272-Pin PBGA table, the following pins changed:
Pin K20 (42MX36) has changed to LP
2-35
The "Low Power Mode" section was updated.
1-7
Footnote 8 in the Table 9 • 5V TTL Electrical Specifications was updated.
1-15
Footnote 8 in the Table 13 • 3.3V LVTTL Electrical Specifications was updated.
1-17
Because the changes in this data sheet are extensive and technical in nature, this should be viewed ALL
as a new document. Please read it as you would a data sheet that is published for the first time.
Note that the “Package Characteristics and Mechanical Drawings” section has been eliminated
from the data sheet. The mechanical drawings are now contained in a separate document,
“Package Characteristics and Mechanical Drawings,” available on the Actel web site.
Datasheet Categories
In order to provide the latest information to designers, some datasheets are published before data has been fully
characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet
Supplement." The definitions of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advanced or production) containing general product
information. This brief gives an overview of specific device and family information.
Advanced
This datasheet version contains initial estimated information based on simulation, other products, devices, or speed
grades. This information can be used as estimates, but not for production.
Unmarked (production)
This datasheet version contains information that is considered to be final.
Datasheet Supplement
The datasheet supplement gives specific device information for a derivative family that differs from the general family
datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and
for specifications that do not differ between the two families.
3 -2
v6.0
Actel and the Actel logo are registered trademarks of Actel Corporation.
All other trademarks are the property of their owners.
http://www.actel.com
Actel Corporation
Actel Europe Ltd.
Actel Japan
Actel Hong Kong
2061 Stierlin Court
Mountain View, CA
94043-4655 USA
Phone 650.318.4200
Fax 650.318.4600
Dunlop House, Riverside Way
Camberley, Surrey GU15 3YL
United Kingdom
Phone +44 (0)1276.401450
Fax +44 (0)1276.401490
EXOS Ebisu Bldg. 4F
1-24-14 Ebisu Shibuya-ku
Tokyo 150 Japan
Phone +81.03.3445.7671
Fax +81.03.3445.7668
39th Floor, One Pacific Place
88 Queensway, Admiralty
Hong Kong
Phone +852.227.35712
Fax +852.227.35999
5172136-8/01.04
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