CAT93C86 (Rev. C) 16K-Bit Microwire Serial EEPROM FEATURES DESCRIPTION High speed operation: 3 MHz Low power CMOS technology 1.8 to 5.5 volt operation Selectable x8 or x16 memory organization Self-timed write cycle with auto-clear Hardware and software write protection Power-up inadvertant write protection Sequential read Program enable (PE) pin 1,000,000 Program/erase cycles 100 year data retention Commercial, industrial and automotive temperature ranges RoHS-compliant packages The CAT93C86 is a 16K-bit Serial EEPROM memory device which is configured as either registers of 16 bits (ORG pin at VCC) or 8 bits (ORG pin at GND). Each register can be written (or read) serially by using the DI (or DO) pin. The CAT93C86 is manufactured using Catalyst’s advanced CMOS EEPROM floating gate technology. The device is designed to endure 1,000,000 program/erase cycles and has a data retention of 100 years. The device is available in 8-pin DIP, 8-pin SOIC and 8-pad TDFN packages. PIN CONFIGURATION FUNCTIONAL SYMBOL VCC PDIP (L) SOIC (V, X) TDFN (ZD4) SOIC (W) CS 1 8 VCC SK 2 7 PE DI 3 6 ORG DO 4 5 GND PE 1 ORG 8 ORG CS VCC 2 7 GND SK CS 3 6 DO PE SK 4 5 DI DI DO GND PIN FUNCTION (1) Pin Name Function CS Chip Select SK Clock Input DI Serial Data Input DO Serial Data Output VCC Power Supply GND Ground ORG Memory Organization PE Program Enable For Ordering Information details, see page 12. Notes: (1) When the ORG pin is connected to VCC, x16 organization is selected. When it is connected to ground, x8 pin is selected. If the ORG pin is left unconnected, then an internal pull-up device will select the x16 organization. © 2009 SCILLC. All rights reserved Characteristics subject to change without notice 1 Doc. No. MD-1091 Rev. S CAT93C86 (Rev. C) ABSOLUTE MAXIMUM RATINGS (1) Parameters Ratings Units Temperature Under Bias –55 to +125 ºC Storage Temperature –65 to 150 ºC -2.0 to +VCC +2.0 V -2.0 to +7.0 V Package Power Dissipation Capability (TA = 25ºC) 1.0 W Lead Soldering Temperature (10 seconds) 300 ºC 100 mA Voltage on any Pin with Respect to Ground(2) VCC with Respect to Ground Output Short Circuit Current (3) RELIABILITY CHARACTERISTICS Symbol NEND(4) TDR(4) VZAP(4) ILTH(4)(5) Parameter Endurance Data Retention ESD Susceptibility Latch-Up Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17 Min 1,000,000 100 2000 100 Units Cycles/Byte Years V mA D.C. OPERATING CHARACTERISTICS VCC = +1.8 V to +5.5 V unless otherwise specified. Symbol Parameter ICC1 Power Supply Current (Write) ICC2 Max Units fSK = 1 MHz; VCC = 5.0 V 3 mA fSK = 1 MHz; VCC = 5.0 V 500 µA CS = 0 V ORG = GND 10 µA 10 µA VIN = 0 V to VCC 1 µA VOUT = 0 V to VCC, CS = 0 V 1 µA VIL1 Power Supply Current (Read) Power Supply Current (Standby) (x8 Mode) Power Supply Current (Standby) (x16Mode) Input Leakage Current Output Leakage Current (Including ORG pin) Input Low Voltage 4.5 V ≤ VCC < 5.5 V -0.1 0.8 V VIH1 Input High Voltage 4.5 V ≤ VCC < 5.5 V 2 VCC + 1 V VIL2 Input Low Voltage 1.8 V ≤ VCC < 4.5 V 0 VCC x 0.2 V VIH2 Input High Voltage 1.8 V ≤ VCC < 4.5 V VCC x 0.7 VCC + 1 V VOL1 Output Low Voltage 4.5 V ≤ VCC < 5.5 V; IOL = 2.1 mA 0.4 V VOH1 Output High Voltage 4.5 V ≤ VCC < 5.5 V; IOH = -400 µA VOL2 Output Low Voltage 1.8 V ≤ VCC < 4.5 V; IOL = 1 mA VOH2 Output High Voltage 1.8 V ≤ VCC < 4.5 V; IOH = -100 µA ISB1 ISB2 ILI ILO Test Conditions Min Typ 0 CS = 0 V ORG = Float or VCC 2.4 V 0.2 VCC - 0.2 V V Notes: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5 V, which may overshoot to VCC +2.0 V for periods of less than 20 ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) These parameters are tested initially and after a design or process change that affects the parameter. (5) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1 V to VCC +1 V. Doc. No. MD-1091 Rev. S 2 © 2009 SCILLC. All rights reserved Characteristics subject to change without notice CAT93C86 (Rev. C) PIN CAPACITANCE Symbol COUT CIN (1) Test Conditions Output Capacitance (DO) VOUT = 0 V 5 pF VIN = 0 V 5 pF Input Capacitance (CS, SK, DI, ORG) Min Typ Max Units POWER-UP TIMING (1)(2) Symbol tPUR tPUW Parameter Power-up to Read Operation Power-up to Write Operation Max 1 1 Units ms ms A.C. TEST CONDITIONS Input Rise and Fall Times ≤ 50 ns Input Pulse Voltages 0.4 V to 2.4 V 4.5 V ≤ VCC ≤ 5.5 V Timing Reference Voltages 0.8 V, 2.0 V 4.5 V ≤ VCC ≤ 5.5 V Input Pulse Voltages 0.2 x VCC to 0.7 x VCC 1.8 V ≤ VCC ≤ 4.5 V Timing Reference Voltages 0.5 x VCC 1.8 V ≤ VCC ≤ 4.5 V A.C. CHARACTERISTICS Symbol Parameter Test Conditions VCC = 1.8 V - 5.5 V VCC = 2.5 V - 5.5 V VCC = 4.5 V - 5.5 V Min Min Min Max 200 Max 50 Units tCSS CS Setup Time tCSH CS Hold Time 0 0 0 ns tDIS DI Setup Time 200 100 50 ns tDIH DI Hold Time 200 100 50 ns tPD1 Output Delay to 1 tPD0 Output Delay to 0 tHZ(1) Output Delay to High-Z tEW Program/Erase Pulse Width CL = 100 F (3) 100 Max ns 1 0.5 0.15 µs 1 0.5 0.15 µs 400 200 100 ns 5 5 5 ms tCSMIN Minimum CS Low Time 1 0.5 0.15 µs tSKHI Minimum SK High Time 1 0.5 0.15 µs tSKLOW Minimum SK Low Time 1 0.5 0.15 µs tSV Output Delay to Status Valid SKMAX Maximum Clock Frequency 1 DC 500 0.5 DC 1000 DC 0.1 µs 3000 kHz Notes: (1) These parameters are tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. (3) The input levels and timing reference points are shown in the “AC Test Conditions” table. © 2009 SCILLC. All rights reserved Characteristics subject to change without notice 3 Doc. No. MD-1091 Rev. S CAT93C86 (Rev. C) INSTRUCTION SET Address Data Instruction Start Bit Opcode x8 x16 READ 1 10 A10-A0 A9-A0 Read Address AN– A0 ERASE 1 11 A10-A0 A9-A0 Clear Address AN– A0 WRITE 1 01 A10-A0 A9-A0 EWEN 1 00 11XXXXXXXXX 11XXXXXXXX Write Enable EWDS 1 00 00XXXXXXXXX 00XXXXXXXX Write Disable ERAL 1 00 10XXXXXXXXX 10XXXXXXXX Clear All Addresses WRAL 1 00 01XXXXXXXXX 01XXXXXXXX x8 D7-D0 D7-D0 Comments x16 D15-D0 D15-D0 Write Address AN– A0 Write All Addresses DEVICE OPERATION The CAT93C86 is a 16,384-bit nonvolatile memory intended for use with industry standard microprocessors. The CAT93C86 can be organized as either registers of 16 bits or 8 bits. When organized as X16, seven 13-bit instructions control the reading, writing and erase operations of the device. When organized as X8, seven 14-bit instructions control the reading, writing and erase operations of the device. The CAT93C86 operates on a single power supply and will generate on chip, the high voltage required during any write operation. is in Program Enabled mode. For Write Enable and Write Disable instruction PE = don’t care. Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. After the initial data word has been shifted out and CS remains asserted with the SK clock continuing to toggle, the device will automatically increment to the next address and shift out the next data word in a sequential READ mode. As long as CS is continuously asserted and SK continues to toggle, the device will keep incrementing to the next address automatically until it reaches to the end of the address space, then loops back to address 0. In the sequential READ mode, only the initial data word is preceeded by a dummy zero bit. All subsequent data words will follow without a dummy zero bit. Read Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the CAT93C86 will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (MSB first). The output data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay (tPD0 or tPD1). The ready/busy status can be determined after the start of a write operation by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. If necessary, the DO pin may be placed back into a high impedance state during chip select by shifting a dummy “1” into the DI pin. The DO pin will enter the high impedance state on the falling edge of the clock (SK). Placing the DO pin into the high impedance state is recommended in applications where the DI pin and the DO pin are to be tied together to form a common DI/O pin. Write After receiving a WRITE command, address and the data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear and data store cycle of the memory location specified in the instruction. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C86 can be determined by selecting the device and polling the DO pin. Since this device features Auto-Clear before write, it is NOT necessary to erase a memory location before it is written into. The format for all instructions sent to the device is a logical “1” start bit, a 2-bit (or 4-bit) opcode, 10-bit address (an additional bit when organized X8) and for write operations a 16-bit data field (8-bit for X8 organizations). Note: The Write, Erase, Write all and Erase all instructions require PE=1. If PE is left floating, 93C86 Doc. No. MD-1091 Rev. S 4 © 2009 SCILLC. All rights reserved Characteristics subject to change without notice CAT93C86 (Rev. C) tSKLOW tSKHI tCSH SK tDIS tDIH VALID DI VALID tCSS CS tDIS tPD0,tPD1 DO tCSMIN DATA VALID Figure 1. Sychronous Data Timing SK 1 1 1 1 1 AN A-–1 1 1 1 1 1 1 1 1 1 1 CS Don't Care DI 1 1 A0 0 HIGH-Z DO Dummy 0 D15 . . . D0 or D7 . . . D0 Address + 1 D15 . . . D0 or D7 . . . D0 Address + 2 D15 . . . D0 or D7 . . . D0 Address + n D15 . . . or D7 . . . Figure 2. Read Instruction Timing SK tCSMIN AN DI STANDBY STATUS VERIFY CS 1 0 AN-1 A0 DN D0 1 tSV DO tHZ BUSY HIGH-Z READY HIGH-Z tEW Figure 3. Write Instruction Timing © 2009 SCILLC. All rights reserved Characteristics subject to change without notice 5 Doc. No. MD-1091 Rev. S CAT93C86 (Rev. C) Erase Upon receiving an ERASE command and address, the CS (Chip Select) pin must be deasserted for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of the selected memory location. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C86 can be determined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical “1” state. Erase All Upon receiving an ERAL command, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C86 can be determined by selecting the device and polling the DO pin. Once cleared, the contents of all memory bits return to a logical “1” state. Erase/Write Enable and Disable The CAT93C86 powers up in the write disable state. Any writing after power-up or after an EWDS (write disable) instruction must first be preceded by the EWEN (write enable) instruction. Once the write instruction is enabled, it will remain enabled until power to the device is removed, or the EWDS instruction is sent. The EWDS instruction can be used to disable all CAT93C86 write and clear instructions, and will prevent any accidental writing or clearing of the device. Data can be read normally from the device regardless of the write enable/disable status. Write All Upon receiving a WRAL command and data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking data write to all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C86 can be determined by selecting the device and polling the DO pin. It is not necessary for all memory locations to be cleared before the WRAL command is executed. SK STATUS VERIFY CS AN DI DO 1 1 tCS A0 AN-1 STANDBY 1 tSV HIGH-Z tHZ BUSY READY HIGH-Z tEW Figure 4. Erase Instruction Timing Doc. No. MD-1091 Rev. S 6 © 2009 SCILLC. All rights reserved Characteristics subject to change without notice CAT93C86 (Rev. C) PACKAGE OUTLINE DRAWINGS PDIP 8-Lead 300 mils (L) (1)(2) SYMBOL MIN NOM A E1 5.33 A1 0.38 A2 2.92 3.30 4.95 b 0.36 0.46 0.56 b2 1.14 1.52 1.78 c 0.20 0.25 0.36 D 9.02 9.27 10.16 E 7.62 7.87 8.25 e PIN # 1 IDENTIFICATION MAX 2.54 BSC E1 6.10 eB 7.87 L 2.92 6.35 7.11 10.92 3.30 3.80 D TOP VIEW E A2 A A1 c b2 L e eB b SIDE VIEW END VIEW For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC standard MS-001. © 2009 SCILLC. All rights reserved Characteristics subject to change without notice 7 Doc. No. MD-1091 Rev. S CAT93C86 (Rev. C) SOIC 8-Lead 150 mils (V) (1)(2) E1 E SYMBOL MIN A 1.35 A1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 D 4.80 5.00 E 5.80 6.20 E1 3.80 e PIN # 1 IDENTIFICATION NOM MAX 1.75 4.00 1.27 BSC h 0.25 0.50 L 0.40 1.27 θ 0º 8º TOP VIEW D h A1 θ A c e b L SIDE VIEW END VIEW For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC standard MS-012. Doc. No. MD-1091 Rev. S 8 © 2009 SCILLC. All rights reserved Characteristics subject to change without notice CAT93C86 (Rev. C) SOIC 8-Lead EIAJ 208 mils (X) (1)(2) SYMBOL MIN NOM A E1 E MAX 2.03 A1 0.05 0.25 b 0.36 0.48 c 0.19 0.25 D 5.13 5.33 E 7.75 8.26 E1 5.13 5.38 e 1.27 BSC L 0.51 0.76 θ 0º 8º PIN#1 IDENTIFICATION TOP VIEW D A e b θ L A1 SIDE VIEW c END VIEW For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with EIAJ standard EDR-7320. © 2009 SCILLC. All rights reserved Characteristics subject to change without notice 9 Doc. No. MD-1091 Rev. S CAT93C86 (Rev. C) TDFN 8-Pad 3 x 3 mm (ZD4) (1)(2) D A e b L E E2 PIN#1 ID PIN#1 INDEX AREA A1 SIDE VIEW TOP VIEW SYMBOL MIN NOM MAX A 0.70 0.75 0.80 A1 0.00 0.02 0.05 A3 A3 A1 0.23 0.30 0.37 D 2.90 3.00 3.10 D2 2.20 — 2.50 E 2.90 3.00 3.10 E2 1.40 — 1.80 e BOTTOM VIEW A 0.20 REF b L D2 FRONT VIEW 0.65 TYP 0.20 0.30 0.40 For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC standard MO-229. Doc. No. MD-1091 Rev. S 10 © 2009 SCILLC. All rights reserved Characteristics subject to change without notice CAT93C86 (Rev. C) EXAMPLE OF ORDERING INFORMATION (1) Prefix Device # Suffix CAT 93C86 V I -1.8 -G T3 Temperature Range I = Industrial (-40°C to +85°C) E = Extended (-40°C to +125°C) Company ID Rev C (4) Die Revision 93C86: C Product Number 93C86 L V W X ZD4 Package = PDIP = SOIC, JEDEC = SOIC, JEDEC (5) = SOIC, EIAJ = TDFN (3 x 3 mm) Operating Voltage Blank (VCC = 2.5 V to 5.5 V) 1.8 (VCC = 1.8 V to 5.5 V) Tape & Reel T: Tape & Reel 2: 2,000/Reel(5) 3: 3,000/Reel Lead Finish Blank: Matte-Tin G: NiPdAu ORDERING INFORMATION Orderable Part Numbers CAT93C86LI-G CAT93C86VI-GT3 CAT93C86WI-GT3 CAT93C86XI-T2 CAT93C86ZD4I-GT3 CAT93C86VI1.8GT3* CAT93C86LE-G CAT93C86VE-GT3 CAT93C86WE-GT3 CAT93C86XE-T2 CAT93C86ZD4E-GT3 * Part number is not exactly the same as the “Example of Ordering Information” shown above. For part numbers marked with * there are NO hyphens in the orderable part numbers. For Product Top Mark Codes, click here: http://www.catsemi.com/techsupport/producttopmark.asp Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish is NiPdAu. (3) The device used in the above example is a 93C86VI-GT3 (SOIC, Industrial Temperature, 1.8 V to 5.5 V, NiPdAu, Tape & Reel, 3,000/Reel) (4) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWE.) For additional information, please contact your ON Semiconductor sales office. (5) For SOIC, EIAJ (X) package the standard lead finish is Matte-Tin. This package is available in 2,000/Reel, i.e., CAT93C86XI-T2. (6) For additional package and temperature options, please contact your nearest ON Semiconductor sales office. © 2009 SCILLC. All rights reserved Characteristics subject to change without notice 11 Doc. No. MD-1091 Rev. S CAT93C86 (Rev. C) REVISION HISTORY Date Rev. Comments 14-May-04 L New Data Sheet Created From CAT93C46/56/57/66/86. Parts CAT93C56, CAT93C56, CAT93C57, CAT93C66, CAT93C76 and CAT93C86 have been separated into single data sheets Add Die Revision ID Letter Update Features Update Description Update Pin Condition Add Functional Diagram Update Pin Function Update D.C. Operating Characteristics Update Pin Capacitance Update Instruction Set Update Device Operation Update Ordering Information 10-Aug-04 M Added TDFN Package pin out 03-Sep-04 N Minor changes 13-Oct-06 O Update Features Update Pin Configuration Update Pin Functions Update D.C. Operating Characteristics (VCC Range) Update A.C. Characteristics (VCC Range) Update Ordering Information 21-May-08 P Update Package Outline Drawings Add Top Mark Code Link Update Document Layout 29-Oct-08 R Change logo and fine print to ON Semiconductor 13-Jul-09 S Update Ordering Information table Doc. No. MD-1091 Rev. S 12 © 2009 SCILLC. All rights reserved Characteristics subject to change without notice ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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